URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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- This comparison shows the changes necessary to convert path
/versatile_library/trunk
- from Rev 84 to Rev 83
- ↔ Reverse comparison
Rev 84 → Rev 83
/rtl/verilog/wb.v
44,11 → 44,11
// async wb3 - wb3 bridge |
`timescale 1ns/1ns |
`define MODULE wb_adr_inc |
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst); |
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, ack_o, adr_o, clk, rst); |
`undef MODULE |
parameter adr_width = 10; |
parameter max_burst_width = 4; |
input cyc_i, stb_i, we_i; |
input cyc_i, stb_i; |
input [2:0] cti_i; |
input [1:0] bte_i; |
input [adr_width-1:0] adr_i; |
85,9 → 85,7
(cyc_i & !stb_i) ? ws : |
cyc; |
assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0]; |
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] : |
(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : |
adr[max_burst_width-1:0]; |
assign adr_o[max_burst_width-1:0] = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0]; |
assign ack_o = last_cycle == cyc; |
end |
endgenerate |
390,8 → 388,6
// avalon master side |
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst); |
|
parameter linewrapburst = 1'b0; |
|
input [31:0] wbs_dat_i; |
input [31:2] wbs_adr_i; |
input [3:0] wbs_sel_i; |
453,7 → 449,7
end else |
if (wbm_we_o) begin |
if (!waitrequest & !last_cyc & wbm_cyc_o) begin |
counter <= burstcount -4'd1; |
counter <= burstcount -1; |
end else if (waitrequest & !last_cyc & wbm_cyc_o) begin |
counter <= burstcount; |
end else if (!waitrequest & wbm_stb_o) begin |
803,13 → 799,14
wbs_dat_o, wbs_ack_o, wb_clk, wb_rst); |
|
parameter adr_size = 16; |
parameter mem_size = 1<<adr_size; |
parameter adr_lo = 2; |
parameter mem_size = 1<<16; |
parameter dat_size = 32; |
parameter max_burst_width = 4; |
parameter memory_init = 1; |
parameter memory_file = "vl_ram.vmem"; |
|
localparam aw = (adr_size); |
localparam aw = (adr_size - adr_lo); |
localparam dw = dat_size; |
localparam sw = dat_size/8; |
localparam cw = 3; |
824,6 → 821,7
output [dw-1:0] wbs_dat_o; |
output wbs_ack_o; |
input wb_clk, wb_rst; |
reg wbs_ack_o; |
|
wire [aw-1:0] adr; |
|
839,7 → 837,7
.d(wbs_dat_i), |
.adr(adr), |
.be(wbs_sel_i), |
.we(wbs_we_i & wb_ack_o), |
.we(wbs_we_i), |
.q(wbs_dat_o), |
.clk(wb_clk) |
); |
851,7 → 849,6
.cti_i(wbs_cti_i), |
.bte_i(wbs_bte_i), |
.adr_i(wbs_adr_i), |
.we_i(wbs_we_i), |
.ack_o(wbs_ack_o), |
.adr_o(adr), |
.clk(wb_clk), |
/rtl/verilog/memories.v
115,12 → 115,10
output reg [(data_width-1):0] q; |
input clk; |
|
|
//E2_ifdef SYSTEMVERILOG |
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width |
//E2_else |
reg [data_width-1:0] ram [mem_size-1:0]; |
wire [data_width/8-1:0] cke; |
reg [data_width-1:0] ram [mem_size-1:0]; |
//E2_endif |
|
parameter memory_init = 0; |
150,11 → 148,10
|
//E2_else |
|
assign cke = {data_width/8{we}} & be; |
genvar i; |
generate for (i=0;i<data_width/8;i=i+1) begin : be_ram |
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram |
always @ (posedge clk) |
if (cke[i]) |
if (we & be[i]) |
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8]; |
end |
endgenerate |
164,21 → 161,6
|
//E2_endif |
|
// Function to access RAM (for use by Verilator). |
function [31:0] get_mem; |
// verilator public |
input [aw-1:0] addr; |
get_mem = ram[addr]; |
endfunction // get_mem |
|
// Function to write RAM (for use by Verilator). |
function set_mem; |
// verilator public |
input [aw-1:0] addr; |
input [dw-1:0] data; |
ram[addr] = data; |
endfunction // set_mem |
|
endmodule |
`endif |
|