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    /versatile_library/trunk
    from Rev 98 to Rev 97
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Rev 98 → Rev 97

/rtl/verilog/versatile_library.v
10,13 → 10,6
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ACTEL
// ACTEL FPGA should not use logic to handle rw collision
`define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
`else
`define SYN_NO_RW_CHECK
`endif
 
`ifdef ALL
 
`define GBUF
103,6 → 96,18
`endif
`endif
 
`ifdef CDC
`ifndef PULSE2TOGGLE
`define PULSE2TOGGLE
`endif
`ifndef TOGGLE2PULSE
`define TOGGLE2PULSE
`endif
`ifndef SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
 
`ifdef WB_B3_DPRAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
164,10 → 169,7
`ifndef dpram_be_2r2w
`define DPRAM_BE_2R2W
`endif
`ifndef CDC
`define CDC
`endif
`endif
`ifdef MULTS18X18
`ifndef MULTS
280,18 → 282,6
`endif
`endif
 
`ifdef CDC
`ifndef PULSE2TOGGLE
`define PULSE2TOGGLE
`endif
`ifndef TOGGLE2PULSE
`define TOGGLE2PULSE
`endif
`ifndef SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
 
// size to width
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
//////////////////////////////////////////////////////////////////////
1191,12 → 1181,13
`endif
 
`ifdef PULSE2TOGGLE
`define MODULE pulse2toggle
module `BASE`MODULE ( pl, q, clk, rst);
`define MODULE pules2toggle
module `BASE`MODULE ( pl, q, clk, rst)
`undef MODULE
input pl;
output reg q;
output q;
input clk, rst;
input
always @ (posedge clk or posedge rst)
if (rst)
q <= 1'b0;
1206,7 → 1197,7
`endif
 
`ifdef TOGGLE2PULSE
`define MODULE toggle2pulse
`define MODULE toggle2pulse;
module `BASE`MODULE (d, pl, clk, rst);
`undef MODULE
input d;
1218,7 → 1209,7
dff <= 1'b0;
else
dff <= d;
assign pl = d ^ dff;
assign d ^ dff;
endmodule
`endif
 
1277,7 → 1268,7
 
// dst -> src
`define MODULE pulse2toggle
`BASE`MODULE p2t1 (
`BASE`MODULE p2t0 (
`undef MODULE
.pl(take_it_grant_pl),
.q(got_it_tg),
3790,7 → 3781,7
input we;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [mem_size-1:0];
reg [data_width-1:0] ram [mem_szie-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
3895,6 → 3886,13
endmodule
`endif
 
`ifdef ACTEL
// ACTEL FPGA should not use logic to handle rw collision
`define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
`else
`define SYN
`endif
 
`ifdef DPRAM_1R1W
`define MODULE dpram_1r1w
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3909,7 → 3907,7
output [(data_width-1):0] q_b;
input clk_a, clk_b;
reg [(addr_width-1):0] adr_b_reg;
reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
3947,7 → 3945,7
output reg [(data_width-1):0] q_a;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
3988,7 → 3986,7
input we_b;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [mem_size-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
4050,7 → 4048,7
generate
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
 
logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
logic [0:3][7:0] ram [0:mem_size-1];
initial
if (init)
4088,7 → 4086,7
generate
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
 
logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
logic [0:7][7:0] ram [0:mem_size-1];
initial
if (init)
4193,7 → 4191,6
 
`else
// This modules requires SystemVerilog
// at this point anyway
`endif
endmodule
`endif
4649,8 → 4646,8
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg we3_reg;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
always @ (posedge clk or posedge rst)
if (rst)
{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
5845,8 → 5842,8
`ifdef WBB3_WBB4_CACHE
`define MODULE wbb3_wbb4_cache
module `BASE`MODULE (
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
);
`undef MODULE
 
5861,9 → 5858,8
parameter nr_of_ways = 1;
parameter aw_offset = 4; // 4 => 16 words per cache line
parameter aw_slot = 10;
localparam aw_tag = aw_s - aw_slot - aw_offset;
localparam aw_tag = aw_s - aw_tag_mem - aw_offset;
parameter wbm_burst_size = 4; // valid options 4,8,16
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
`define SIZE2WIDTH wbm_burst_size
localparam wbm_burst_width `SIZE2WIDTH_EXPR
`undef SIZE2WIDTH
5873,10 → 5869,10
`undef SIZE2WIDTH
input [dw_s-1:0] wbs_dat_i;
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
input [dw_s/8-1:0] wbs_sel_i;
input [dw_s/8-1:0] wbs-sel_i;
input [2:0] wbs_cti_i;
input [1:0] wbs_bte_i;
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
input wbs_we_i;
output [dw_s-1:0] wbs_dat_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
5886,7 → 5882,6
output [dw_m/8-1:0] wbm_sel_o;
output [2:0] wbm_cti_o;
output [1:0] wbm_bte_o;
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
input [dw_m-1:0] wbm_dat_i;
input wbm_ack_i;
input wbm_stall_i;
5897,8 → 5892,8
wire tag_mem_we;
wire [aw_tag-1:0] wbs_adr_tag;
wire [aw_slot-1:0] wbs_adr_slot;
wire [aw_offset-1:0] wbs_adr_word;
wire [aw_s-1:0] wbs_adr;
wire [aw_offset_1:0] wbs_adr_word;
wire [aw-1:0] wbs_adr;
 
reg [1:0] state;
localparam idle = 2'h0;
5910,29 → 5905,18
// cdc
wire done, mem_alert, mem_done;
 
// wbm side
reg [aw_m-1:0] wbm_radr;
reg [aw_m-1:0] wbm_wadr;
wire [aw_slot+-1:0] wbm_adr;
wire wbm_radr_cke, wbm_wadr_cke;
 
reg [1:0] phase;
localparam wbm_wait = 2'b00;
localparam wbm_rd = 2'b10;
localparam wbm_wr = 2'b11;
 
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
 
`define MODULE ram
`BASE`MODULE
# ( .data_width(aw_tag), .addr_width(aw_slot))
# ( .data_width(aw_tag), .addr_Width(aw_slot))
tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
`undef MODULE
assign valid = wbs_adr_tag == tag;
 
`define MODULE wb_adr_inc
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(max_burst_width)) adr_inc0 (
`BASE`MODULE # ( .adr_width(aw_slot+aw_offset), .max_burst_width(max_burst_width)) adr_inc0 (
.cyc_i(wbs_cyc_i),
.stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
.cti_i(wbs_cti_i),
5947,14 → 5931,14
 
`define MODULE dpram_be_2r2w
`BASE`MODULE
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m) )
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
.d_b(wbm_dat_i), .adr_b(wbm_adr), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
# ( .data_width(aw_tag), .addr_Width(aw_slot+aw_offset))
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr), be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
.d_b(wbm_dat_i), .adr_b(wbm_adr), be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
`undef MODULE
 
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
state <= idle;
case <= idle;
else
case (state)
idle:
5994,53 → 5978,27
end
endgenerate
 
always @ (posedge wbm_clk or posedge wbm_rst)
if (rst)
wbm_burst_adr <= {aw_wbm_burst{1'b0}};
else
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i))
wbm_burst_adr <= wbm_burst_adr + (aw_wbm_burst)'d1
 
// FSM generating a number of burts 4 cycles
// actual number depends on data width ratio
// nr_of_wbm_burst
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt0;
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt1;
reg [wbm_burst_width-1:0] cnt0;
reg [nr_of_wbm_burst_width-1:0] cnt1;
 
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
cnt0 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
{cnt1,cnt0} <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
else
if (wbm_radr_cke)
cnt0 <= cnt0 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
assign wbm_radr_cke = wbm_cyc_o & wbm_stb_o & !wbm_stall_i;
assign wbm_radr = {wbs_adr_tag, tag, cnt0};
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
{cnt1,cnt0} <= (nr_of_wbm_burst_width+wbm_burst_width)1'd1;
 
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
cnt1 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
else
if (wbm_wadr_cke)
cnt1 <= cnt1 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
assign wbm_wadr_cke = wbm_ack_i;
assign wbm_wadr = {wbs_adr_tag, wbs_adr_slot, cnt1};
 
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
phase <= wbm_wait;
else
case (phase)
wbm_wait:
if (mem_alert)
phase <= state;
wbm_wr:
if (&cnt1 & wbm_ack_i)
phase <= wbm_rd;
wbm_rd:
if (&cnt0 & wbm_ack_i)
phase <= idle;
default: phase <= wbm_wait;
endcase
 
assign wbm_adr_o = (phase==wbm_wr) ? {tag, wbs_adr_slot, cnt1} : {wbs_adr_tag, wbs_adr_slot, cnt1};
assign wbm_adr = (phase==wbm_wr) ? {wbs_adr_slot, cnt1} : {wbs_adr_slot, cnt1};
assign wbm_cti_o = (&cnt0 | &cnt1) ? 3'b111 : 3'b010;
assign wbm_bte_o = bte;
assign wbm_we_o = phase==wbm_wr;
 
endmodule
`endif
//////////////////////////////////////////////////////////////////////
/rtl/verilog/versatile_library_actel.v
1,5 → 1,4
// default SYN_KEEP definition
// ACTEL FPGA should not use logic to handle rw collision
// size to width
//////////////////////////////////////////////////////////////////////
//// ////
396,10 → 395,11
assign q = dffs[depth];
assign emptyflag = !(|dffs);
endmodule
module vl_pulse2toggle ( pl, q, clk, rst);
module vl_pules2toggle ( pl, q, clk, rst)
input pl;
output reg q;
output q;
input clk, rst;
input
always @ (posedge clk or posedge rst)
if (rst)
q <= 1'b0;
406,7 → 406,7
else
q <= pl ^ q;
endmodule
module vl_toggle2pulse (d, pl, clk, rst);
module vl_toggle2pulse; (d, pl, clk, rst);
input d;
output pl;
input clk, rst;
416,7 → 416,7
dff <= 1'b0;
else
dff <= d;
assign pl = d ^ dff;
assign d ^ dff;
endmodule
module vl_synchronizer (d, q, clk, rst);
input d;
455,7 → 455,7
.clk(clk_dst),
.rst(rst_dst));
// dst -> src
vl_pulse2toggle p2t1 (
vl_pulse2toggle p2t0 (
.pl(take_it_grant_pl),
.q(got_it_tg),
.clk(clk_dst),
1295,7 → 1295,7
input we;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [mem_size-1:0];
reg [data_width-1:0] ram [mem_szie-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
1378,6 → 1378,7
endfunction // set_mem
`endif
endmodule
// ACTEL FPGA should not use logic to handle rw collision
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
1499,7 → 1500,7
//to model individual bytes within the word
generate
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
logic [0:3][7:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
logic [0:3][7:0] ram [0:mem_size-1];
initial
if (init)
$readmemh(memory_file, ram);
1529,7 → 1530,7
endgenerate
generate
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
logic [0:7][7:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
logic [0:7][7:0] ram [0:mem_size-1];
initial
if (init)
$readmemh(memory_file, ram);
1617,7 → 1618,6
endgenerate
`else
// This modules requires SystemVerilog
// at this point anyway
`endif
endmodule
// FIFO
2794,8 → 2794,8
assign wb_ack_o = wb_ack;
endmodule
module vl_wbb3_wbb4_cache (
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
);
parameter dw_s = 32;
parameter aw_s = 24;
2806,18 → 2806,17
parameter nr_of_ways = 1;
parameter aw_offset = 4; // 4 => 16 words per cache line
parameter aw_slot = 10;
localparam aw_tag = aw_s - aw_slot - aw_offset;
localparam aw_tag = aw_s - aw_tag_mem - aw_offset;
parameter wbm_burst_size = 4; // valid options 4,8,16
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
localparam wbm_burst_width = (wbm_burst_size==4) ? 2 : (wbm_burst_size==8) ? 3 : (wbm_burst_size==16) ? 4 : (wbm_burst_size==32) ? 5 : (wbm_burst_size==64) ? 6 : (wbm_burst_size==128) ? 7 : 8;
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
localparam nr_of_wbm_burst_width = (nr_of_wbm_burst==4) ? 2 : (nr_of_wbm_burst==8) ? 3 : (nr_of_wbm_burst==16) ? 4 : (nr_of_wbm_burst==32) ? 5 : (nr_of_wbm_burst==64) ? 6 : (nr_of_wbm_burst==128) ? 7 : 8;
input [dw_s-1:0] wbs_dat_i;
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
input [dw_s/8-1:0] wbs_sel_i;
input [dw_s/8-1:0] wbs-sel_i;
input [2:0] wbs_cti_i;
input [1:0] wbs_bte_i;
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
input wbs_we_i;
output [dw_s-1:0] wbs_dat_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
2826,7 → 2825,6
output [dw_m/8-1:0] wbm_sel_o;
output [2:0] wbm_cti_o;
output [1:0] wbm_bte_o;
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
input [dw_m-1:0] wbm_dat_i;
input wbm_ack_i;
input wbm_stall_i;
2836,8 → 2834,8
wire tag_mem_we;
wire [aw_tag-1:0] wbs_adr_tag;
wire [aw_slot-1:0] wbs_adr_slot;
wire [aw_offset-1:0] wbs_adr_word;
wire [aw_s-1:0] wbs_adr;
wire [aw_offset_1:0] wbs_adr_word;
wire [aw-1:0] wbs_adr;
reg [1:0] state;
localparam idle = 2'h0;
localparam rdwr = 2'h1;
2846,22 → 2844,13
wire eoc;
// cdc
wire done, mem_alert, mem_done;
// wbm side
reg [aw_m-1:0] wbm_radr;
reg [aw_m-1:0] wbm_wadr;
wire [aw_slot+-1:0] wbm_adr;
wire wbm_radr_cke, wbm_wadr_cke;
reg [1:0] phase;
localparam wbm_wait = 2'b00;
localparam wbm_rd = 2'b10;
localparam wbm_wr = 2'b11;
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
vl_ram
# ( .data_width(aw_tag), .addr_width(aw_slot))
# ( .data_width(aw_tag), .addr_Width(aw_slot))
tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
assign valid = wbs_adr_tag == tag;
vl_wb_adr_inc # ( .adr_width(aw_s), .max_burst_width(max_burst_width)) adr_inc0 (
vl_wb_adr_inc # ( .adr_width(aw_slot+aw_offset), .max_burst_width(max_burst_width)) adr_inc0 (
.cyc_i(wbs_cyc_i),
.stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
.cti_i(wbs_cti_i),
2873,12 → 2862,12
.clk(wbsa_clk),
.rst(wbsa_rst));
vl_dpram_be_2r2w
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m) )
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
.d_b(wbm_dat_i), .adr_b(wbm_adr), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
# ( .data_width(aw_tag), .addr_Width(aw_slot+aw_offset))
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr), be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
.d_b(wbm_dat_i), .adr_b(wbm_adr), be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
state <= idle;
case <= idle;
else
case (state)
idle:
2913,48 → 2902,23
assign done = mem_done;
end
endgenerate
always @ (posedge wbm_clk or posedge wbm_rst)
if (rst)
wbm_burst_adr <= {aw_wbm_burst{1'b0}};
else
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i))
wbm_burst_adr <= wbm_burst_adr + (aw_wbm_burst)'d1
// FSM generating a number of burts 4 cycles
// actual number depends on data width ratio
// nr_of_wbm_burst
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt0;
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt1;
reg [wbm_burst_width-1:0] cnt0;
reg [nr_of_wbm_burst_width-1:0] cnt1;
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
cnt0 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
{cnt1,cnt0} <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
else
if (wbm_radr_cke)
cnt0 <= cnt0 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
assign wbm_radr_cke = wbm_cyc_o & wbm_stb_o & !wbm_stall_i;
assign wbm_radr = {wbs_adr_tag, tag, cnt0};
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
cnt1 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
else
if (wbm_wadr_cke)
cnt1 <= cnt1 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
assign wbm_wadr_cke = wbm_ack_i;
assign wbm_wadr = {wbs_adr_tag, wbs_adr_slot, cnt1};
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
phase <= wbm_wait;
else
case (phase)
wbm_wait:
if (mem_alert)
phase <= state;
wbm_wr:
if (&cnt1 & wbm_ack_i)
phase <= wbm_rd;
wbm_rd:
if (&cnt0 & wbm_ack_i)
phase <= idle;
default: phase <= wbm_wait;
endcase
assign wbm_adr_o = (phase==wbm_wr) ? {tag, wbs_adr_slot, cnt1} : {wbs_adr_tag, wbs_adr_slot, cnt1};
assign wbm_adr = (phase==wbm_wr) ? {wbs_adr_slot, cnt1} : {wbs_adr_slot, cnt1};
assign wbm_cti_o = (&cnt0 | &cnt1) ? 3'b111 : 3'b010;
assign wbm_bte_o = bte;
assign wbm_we_o = phase==wbm_wr;
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
{cnt1,cnt0} <= (nr_of_wbm_burst_width+wbm_burst_width)1'd1;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
/rtl/verilog/wb.v
1142,8 → 1142,8
`ifdef WBB3_WBB4_CACHE
`define MODULE wbb3_wbb4_cache
module `BASE`MODULE (
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
);
`undef MODULE
 
1158,9 → 1158,8
parameter nr_of_ways = 1;
parameter aw_offset = 4; // 4 => 16 words per cache line
parameter aw_slot = 10;
localparam aw_tag = aw_s - aw_slot - aw_offset;
localparam aw_tag = aw_s - aw_tag_mem - aw_offset;
parameter wbm_burst_size = 4; // valid options 4,8,16
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
`define SIZE2WIDTH wbm_burst_size
localparam wbm_burst_width `SIZE2WIDTH_EXPR
`undef SIZE2WIDTH
1170,10 → 1169,10
`undef SIZE2WIDTH
input [dw_s-1:0] wbs_dat_i;
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
input [dw_s/8-1:0] wbs_sel_i;
input [dw_s/8-1:0] wbs-sel_i;
input [2:0] wbs_cti_i;
input [1:0] wbs_bte_i;
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
input wbs_we_i;
output [dw_s-1:0] wbs_dat_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
1183,7 → 1182,6
output [dw_m/8-1:0] wbm_sel_o;
output [2:0] wbm_cti_o;
output [1:0] wbm_bte_o;
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
input [dw_m-1:0] wbm_dat_i;
input wbm_ack_i;
input wbm_stall_i;
1194,8 → 1192,8
wire tag_mem_we;
wire [aw_tag-1:0] wbs_adr_tag;
wire [aw_slot-1:0] wbs_adr_slot;
wire [aw_offset-1:0] wbs_adr_word;
wire [aw_s-1:0] wbs_adr;
wire [aw_offset_1:0] wbs_adr_word;
wire [aw-1:0] wbs_adr;
 
reg [1:0] state;
localparam idle = 2'h0;
1207,29 → 1205,18
// cdc
wire done, mem_alert, mem_done;
 
// wbm side
reg [aw_m-1:0] wbm_radr;
reg [aw_m-1:0] wbm_wadr;
wire [aw_slot+-1:0] wbm_adr;
wire wbm_radr_cke, wbm_wadr_cke;
 
reg [1:0] phase;
localparam wbm_wait = 2'b00;
localparam wbm_rd = 2'b10;
localparam wbm_wr = 2'b11;
 
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
 
`define MODULE ram
`BASE`MODULE
# ( .data_width(aw_tag), .addr_width(aw_slot))
# ( .data_width(aw_tag), .addr_Width(aw_slot))
tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
`undef MODULE
assign valid = wbs_adr_tag == tag;
 
`define MODULE wb_adr_inc
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(max_burst_width)) adr_inc0 (
`BASE`MODULE # ( .adr_width(aw_slot+aw_offset), .max_burst_width(max_burst_width)) adr_inc0 (
.cyc_i(wbs_cyc_i),
.stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
.cti_i(wbs_cti_i),
1244,14 → 1231,14
 
`define MODULE dpram_be_2r2w
`BASE`MODULE
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m) )
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
.d_b(wbm_dat_i), .adr_b(wbm_adr), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
# ( .data_width(aw_tag), .addr_Width(aw_slot+aw_offset))
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr), be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
.d_b(wbm_dat_i), .adr_b(wbm_adr), be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
`undef MODULE
 
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
state <= idle;
case <= idle;
else
case (state)
idle:
1291,52 → 1278,26
end
endgenerate
 
always @ (posedge wbm_clk or posedge wbm_rst)
if (rst)
wbm_burst_adr <= {aw_wbm_burst{1'b0}};
else
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i))
wbm_burst_adr <= wbm_burst_adr + (aw_wbm_burst)'d1
 
// FSM generating a number of burts 4 cycles
// actual number depends on data width ratio
// nr_of_wbm_burst
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt0;
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt1;
reg [wbm_burst_width-1:0] cnt0;
reg [nr_of_wbm_burst_width-1:0] cnt1;
 
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
cnt0 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
{cnt1,cnt0} <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
else
if (wbm_radr_cke)
cnt0 <= cnt0 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
assign wbm_radr_cke = wbm_cyc_o & wbm_stb_o & !wbm_stall_i;
assign wbm_radr = {wbs_adr_tag, tag, cnt0};
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
{cnt1,cnt0} <= (nr_of_wbm_burst_width+wbm_burst_width)1'd1;
 
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
cnt1 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
else
if (wbm_wadr_cke)
cnt1 <= cnt1 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
assign wbm_wadr_cke = wbm_ack_i;
assign wbm_wadr = {wbs_adr_tag, wbs_adr_slot, cnt1};
 
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
phase <= wbm_wait;
else
case (phase)
wbm_wait:
if (mem_alert)
phase <= state;
wbm_wr:
if (&cnt1 & wbm_ack_i)
phase <= wbm_rd;
wbm_rd:
if (&cnt0 & wbm_ack_i)
phase <= idle;
default: phase <= wbm_wait;
endcase
 
assign wbm_adr_o = (phase==wbm_wr) ? {tag, wbs_adr_slot, cnt1} : {wbs_adr_tag, wbs_adr_slot, cnt1};
assign wbm_adr = (phase==wbm_wr) ? {wbs_adr_slot, cnt1} : {wbs_adr_slot, cnt1};
assign wbm_cti_o = (&cnt0 | &cnt1) ? 3'b111 : 3'b010;
assign wbm_bte_o = bte;
assign wbm_we_o = phase==wbm_wr;
 
endmodule
`endif
/rtl/verilog/versatile_library_altera.v
503,10 → 503,11
assign q = dffs[depth];
assign emptyflag = !(|dffs);
endmodule
module vl_pulse2toggle ( pl, q, clk, rst);
module vl_pules2toggle ( pl, q, clk, rst)
input pl;
output reg q;
output q;
input clk, rst;
input
always @ (posedge clk or posedge rst)
if (rst)
q <= 1'b0;
513,7 → 514,7
else
q <= pl ^ q;
endmodule
module vl_toggle2pulse (d, pl, clk, rst);
module vl_toggle2pulse; (d, pl, clk, rst);
input d;
output pl;
input clk, rst;
523,7 → 524,7
dff <= 1'b0;
else
dff <= d;
assign pl = d ^ dff;
assign d ^ dff;
endmodule
module vl_synchronizer (d, q, clk, rst);
input d;
562,7 → 563,7
.clk(clk_dst),
.rst(rst_dst));
// dst -> src
vl_pulse2toggle p2t1 (
vl_pulse2toggle p2t0 (
.pl(take_it_grant_pl),
.q(got_it_tg),
.clk(clk_dst),
1402,7 → 1403,7
input we;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [mem_size-1:0];
reg [data_width-1:0] ram [mem_szie-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
1606,7 → 1607,7
//to model individual bytes within the word
generate
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
logic [0:3][7:0] ram [0:mem_size-1] ;
logic [0:3][7:0] ram [0:mem_size-1];
initial
if (init)
$readmemh(memory_file, ram);
1636,7 → 1637,7
endgenerate
generate
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
logic [0:7][7:0] ram [0:mem_size-1] ;
logic [0:7][7:0] ram [0:mem_size-1];
initial
if (init)
$readmemh(memory_file, ram);
1724,7 → 1725,6
endgenerate
`else
// This modules requires SystemVerilog
// at this point anyway
`endif
endmodule
// FIFO
2899,8 → 2899,8
assign wb_ack_o = wb_ack;
endmodule
module vl_wbb3_wbb4_cache (
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
);
parameter dw_s = 32;
parameter aw_s = 24;
2911,18 → 2911,17
parameter nr_of_ways = 1;
parameter aw_offset = 4; // 4 => 16 words per cache line
parameter aw_slot = 10;
localparam aw_tag = aw_s - aw_slot - aw_offset;
localparam aw_tag = aw_s - aw_tag_mem - aw_offset;
parameter wbm_burst_size = 4; // valid options 4,8,16
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
localparam wbm_burst_width = (wbm_burst_size==4) ? 2 : (wbm_burst_size==8) ? 3 : (wbm_burst_size==16) ? 4 : (wbm_burst_size==32) ? 5 : (wbm_burst_size==64) ? 6 : (wbm_burst_size==128) ? 7 : 8;
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
localparam nr_of_wbm_burst_width = (nr_of_wbm_burst==4) ? 2 : (nr_of_wbm_burst==8) ? 3 : (nr_of_wbm_burst==16) ? 4 : (nr_of_wbm_burst==32) ? 5 : (nr_of_wbm_burst==64) ? 6 : (nr_of_wbm_burst==128) ? 7 : 8;
input [dw_s-1:0] wbs_dat_i;
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
input [dw_s/8-1:0] wbs_sel_i;
input [dw_s/8-1:0] wbs-sel_i;
input [2:0] wbs_cti_i;
input [1:0] wbs_bte_i;
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
input wbs_we_i;
output [dw_s-1:0] wbs_dat_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
2931,7 → 2930,6
output [dw_m/8-1:0] wbm_sel_o;
output [2:0] wbm_cti_o;
output [1:0] wbm_bte_o;
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
input [dw_m-1:0] wbm_dat_i;
input wbm_ack_i;
input wbm_stall_i;
2941,8 → 2939,8
wire tag_mem_we;
wire [aw_tag-1:0] wbs_adr_tag;
wire [aw_slot-1:0] wbs_adr_slot;
wire [aw_offset-1:0] wbs_adr_word;
wire [aw_s-1:0] wbs_adr;
wire [aw_offset_1:0] wbs_adr_word;
wire [aw-1:0] wbs_adr;
reg [1:0] state;
localparam idle = 2'h0;
localparam rdwr = 2'h1;
2951,22 → 2949,13
wire eoc;
// cdc
wire done, mem_alert, mem_done;
// wbm side
reg [aw_m-1:0] wbm_radr;
reg [aw_m-1:0] wbm_wadr;
wire [aw_slot+-1:0] wbm_adr;
wire wbm_radr_cke, wbm_wadr_cke;
reg [1:0] phase;
localparam wbm_wait = 2'b00;
localparam wbm_rd = 2'b10;
localparam wbm_wr = 2'b11;
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
vl_ram
# ( .data_width(aw_tag), .addr_width(aw_slot))
# ( .data_width(aw_tag), .addr_Width(aw_slot))
tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
assign valid = wbs_adr_tag == tag;
vl_wb_adr_inc # ( .adr_width(aw_s), .max_burst_width(max_burst_width)) adr_inc0 (
vl_wb_adr_inc # ( .adr_width(aw_slot+aw_offset), .max_burst_width(max_burst_width)) adr_inc0 (
.cyc_i(wbs_cyc_i),
.stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
.cti_i(wbs_cti_i),
2978,12 → 2967,12
.clk(wbsa_clk),
.rst(wbsa_rst));
vl_dpram_be_2r2w
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m) )
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
.d_b(wbm_dat_i), .adr_b(wbm_adr), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
# ( .data_width(aw_tag), .addr_Width(aw_slot+aw_offset))
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr), be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
.d_b(wbm_dat_i), .adr_b(wbm_adr), be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
state <= idle;
case <= idle;
else
case (state)
idle:
3018,48 → 3007,23
assign done = mem_done;
end
endgenerate
always @ (posedge wbm_clk or posedge wbm_rst)
if (rst)
wbm_burst_adr <= {aw_wbm_burst{1'b0}};
else
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i))
wbm_burst_adr <= wbm_burst_adr + (aw_wbm_burst)'d1
// FSM generating a number of burts 4 cycles
// actual number depends on data width ratio
// nr_of_wbm_burst
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt0;
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt1;
reg [wbm_burst_width-1:0] cnt0;
reg [nr_of_wbm_burst_width-1:0] cnt1;
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
cnt0 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
{cnt1,cnt0} <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
else
if (wbm_radr_cke)
cnt0 <= cnt0 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
assign wbm_radr_cke = wbm_cyc_o & wbm_stb_o & !wbm_stall_i;
assign wbm_radr = {wbs_adr_tag, tag, cnt0};
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
cnt1 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
else
if (wbm_wadr_cke)
cnt1 <= cnt1 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
assign wbm_wadr_cke = wbm_ack_i;
assign wbm_wadr = {wbs_adr_tag, wbs_adr_slot, cnt1};
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
phase <= wbm_wait;
else
case (phase)
wbm_wait:
if (mem_alert)
phase <= state;
wbm_wr:
if (&cnt1 & wbm_ack_i)
phase <= wbm_rd;
wbm_rd:
if (&cnt0 & wbm_ack_i)
phase <= idle;
default: phase <= wbm_wait;
endcase
assign wbm_adr_o = (phase==wbm_wr) ? {tag, wbs_adr_slot, cnt1} : {wbs_adr_tag, wbs_adr_slot, cnt1};
assign wbm_adr = (phase==wbm_wr) ? {wbs_adr_slot, cnt1} : {wbs_adr_slot, cnt1};
assign wbm_cti_o = (&cnt0 | &cnt1) ? 3'b111 : 3'b010;
assign wbm_bte_o = bte;
assign wbm_we_o = phase==wbm_wr;
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
{cnt1,cnt0} <= (nr_of_wbm_burst_width+wbm_burst_width)1'd1;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
/rtl/verilog/defines.v
10,13 → 10,6
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ACTEL
// ACTEL FPGA should not use logic to handle rw collision
`define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
`else
`define SYN_NO_RW_CHECK
`endif
 
`ifdef ALL
 
`define GBUF
103,6 → 96,18
`endif
`endif
 
`ifdef CDC
`ifndef PULSE2TOGGLE
`define PULSE2TOGGLE
`endif
`ifndef TOGGLE2PULSE
`define TOGGLE2PULSE
`endif
`ifndef SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
 
`ifdef WB_B3_DPRAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
164,10 → 169,7
`ifndef dpram_be_2r2w
`define DPRAM_BE_2R2W
`endif
`ifndef CDC
`define CDC
`endif
`endif
`ifdef MULTS18X18
`ifndef MULTS
280,17 → 282,5
`endif
`endif
 
`ifdef CDC
`ifndef PULSE2TOGGLE
`define PULSE2TOGGLE
`endif
`ifndef TOGGLE2PULSE
`define TOGGLE2PULSE
`endif
`ifndef SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
 
// size to width
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
/rtl/verilog/registers.v
476,12 → 476,13
`endif
 
`ifdef PULSE2TOGGLE
`define MODULE pulse2toggle
module `BASE`MODULE ( pl, q, clk, rst);
`define MODULE pules2toggle
module `BASE`MODULE ( pl, q, clk, rst)
`undef MODULE
input pl;
output reg q;
output q;
input clk, rst;
input
always @ (posedge clk or posedge rst)
if (rst)
q <= 1'b0;
491,7 → 492,7
`endif
 
`ifdef TOGGLE2PULSE
`define MODULE toggle2pulse
`define MODULE toggle2pulse;
module `BASE`MODULE (d, pl, clk, rst);
`undef MODULE
input d;
503,7 → 504,7
dff <= 1'b0;
else
dff <= d;
assign pl = d ^ dff;
assign d ^ dff;
endmodule
`endif
 
562,7 → 563,7
 
// dst -> src
`define MODULE pulse2toggle
`BASE`MODULE p2t1 (
`BASE`MODULE p2t0 (
`undef MODULE
.pl(take_it_grant_pl),
.q(got_it_tg),
/rtl/verilog/memories.v
79,7 → 79,7
input we;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [mem_size-1:0];
reg [data_width-1:0] ram [mem_szie-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
184,6 → 184,13
endmodule
`endif
 
`ifdef ACTEL
// ACTEL FPGA should not use logic to handle rw collision
`define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
`else
`define SYN
`endif
 
`ifdef DPRAM_1R1W
`define MODULE dpram_1r1w
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
198,7 → 205,7
output [(data_width-1):0] q_b;
input clk_a, clk_b;
reg [(addr_width-1):0] adr_b_reg;
reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
236,7 → 243,7
output reg [(data_width-1):0] q_a;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
277,7 → 284,7
input we_b;
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram [mem_size-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
339,7 → 346,7
generate
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
 
logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
logic [0:3][7:0] ram [0:mem_size-1];
initial
if (init)
377,7 → 384,7
generate
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
 
logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
logic [0:7][7:0] ram [0:mem_size-1];
initial
if (init)
482,7 → 489,6
 
//E2_else
// This modules requires SystemVerilog
// at this point anyway
//E2_endif
endmodule
`endif
938,8 → 944,8
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg we3_reg;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
always @ (posedge clk or posedge rst)
if (rst)
{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};

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