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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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    /versatile_library
    from Rev 131 to Rev 130
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Rev 131 → Rev 130

/trunk/rtl/verilog/versatile_library.v
6298,16 → 6298,6
end
 
endgenerate
localparam cache_mem_b_aw =
(dw_s==dw_m) ? aw_slot+aw_offset :
(dw_s==dw_m/2) ? aw_slot+aw_offset+1 :
(dw_s==dw_m/4) ? aw_slot+aw_offset+2 :
(dw_s==dw_m/8) ? aw_slot+aw_offset+3 :
(dw_s==dw_m/16) ? aw_slot+aw_offset+4 :
(dw_s==dw_m*2) ? aw_slot+aw_offset-1 :
(dw_s==dw_m*4) ? aw_slot+aw_offset-2 :
(dw_s==dw_m*8) ? aw_slot+aw_offset-3 :
(dw_s==dw_m*16) ? aw_slot+aw_offset-4 : 0;
 
`define MODULE dpram_be_2r2w
`BASE`MODULE
/trunk/rtl/verilog/versatile_library_actel.v
2969,16 → 2969,6
end else if (wbs_mode=="B4") begin : inst_b4
end
endgenerate
localparam cache_mem_b_aw =
(dw_s==dw_m) ? aw_slot+aw_offset :
(dw_s==dw_m/2) ? aw_slot+aw_offset+1 :
(dw_s==dw_m/4) ? aw_slot+aw_offset+2 :
(dw_s==dw_m/8) ? aw_slot+aw_offset+3 :
(dw_s==dw_m/16) ? aw_slot+aw_offset+4 :
(dw_s==dw_m*2) ? aw_slot+aw_offset-1 :
(dw_s==dw_m*4) ? aw_slot+aw_offset-2 :
(dw_s==dw_m*8) ? aw_slot+aw_offset-3 :
(dw_s==dw_m*16) ? aw_slot+aw_offset-4 : 0;
vl_dpram_be_2r2w
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
/trunk/rtl/verilog/wb.v
1380,16 → 1380,6
end
 
endgenerate
localparam cache_mem_b_aw =
(dw_s==dw_m) ? aw_slot+aw_offset :
(dw_s==dw_m/2) ? aw_slot+aw_offset+1 :
(dw_s==dw_m/4) ? aw_slot+aw_offset+2 :
(dw_s==dw_m/8) ? aw_slot+aw_offset+3 :
(dw_s==dw_m/16) ? aw_slot+aw_offset+4 :
(dw_s==dw_m*2) ? aw_slot+aw_offset-1 :
(dw_s==dw_m*4) ? aw_slot+aw_offset-2 :
(dw_s==dw_m*8) ? aw_slot+aw_offset-3 :
(dw_s==dw_m*16) ? aw_slot+aw_offset-4 : 0;
 
`define MODULE dpram_be_2r2w
`BASE`MODULE
/trunk/rtl/verilog/versatile_library_altera.v
3074,16 → 3074,6
end else if (wbs_mode=="B4") begin : inst_b4
end
endgenerate
localparam cache_mem_b_aw =
(dw_s==dw_m) ? aw_slot+aw_offset :
(dw_s==dw_m/2) ? aw_slot+aw_offset+1 :
(dw_s==dw_m/4) ? aw_slot+aw_offset+2 :
(dw_s==dw_m/8) ? aw_slot+aw_offset+3 :
(dw_s==dw_m/16) ? aw_slot+aw_offset+4 :
(dw_s==dw_m*2) ? aw_slot+aw_offset-1 :
(dw_s==dw_m*4) ? aw_slot+aw_offset-2 :
(dw_s==dw_m*8) ? aw_slot+aw_offset-3 :
(dw_s==dw_m*16) ? aw_slot+aw_offset-4 : 0;
vl_dpram_be_2r2w
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),

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