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Rev 26 → Rev 27
/trunk/rtl/verilog/memories.v
310,11 → 310,92
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk)); |
|
vl_cnt_bin_ce_rew_zq_l1 |
# (.length(addr_width+1), .level1_value(1<<add_width)) |
# (.length(addr_width+1), .level1_value(1<<addr_width)) |
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk)); |
|
endmodule |
|
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource |
// RAM is supposed to be larger than the two FIFOs |
// LFSR counters used adr pointers |
module vl_fifo_2r2w_sync_simplex ( |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
a_fill_level, |
// b side |
b_d, b_wr, b_fifo_full, |
b_q, b_rd, b_fifo_empty, |
b_fill_level, |
// common |
clk, rst |
); |
parameter data_width = 8; |
parameter addr_width = 5; |
parameter fifo_full_level = (1<<addr_width)-1; |
|
// a side |
input [data_width-1:0] a_d; |
input a_wr; |
output a_fifo_full; |
output [data_width-1:0] a_q; |
input a_rd; |
output a_fifo_empty; |
output [addr_width-1:0] a_fill_level; |
|
// b side |
input [data_width-1:0] b_d; |
input b_wr; |
output b_fifo_full; |
output [data_width-1:0] b_q; |
input b_rd; |
output b_fifo_empty; |
output [addr_width-1:0] b_fill_level; |
|
input clk; |
input rst; |
|
// adr_gen |
wire [addr_width:1] a_wadr, a_radr; |
wire [addr_width:1] b_wadr, b_radr; |
// dpram |
wire [addr_width:0] a_dpram_adr, b_dpram_adr; |
|
vl_cnt_lfsr_ce |
# ( .length(addr_width)) |
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk)); |
|
vl_cnt_lfsr_ce |
# (.length(addr_width)) |
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk)); |
|
vl_cnt_lfsr_ce |
# ( .length(addr_width)) |
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk)); |
|
vl_cnt_lfsr_ce |
# (.length(addr_width)) |
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk)); |
|
// mux read or write adr to DPRAM |
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr}; |
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr}; |
|
vl_dpram_2r2w |
# (.data_width(data_width), .addr_width(addr_width+1)) |
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk), |
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk)); |
|
vl_cnt_bin_ce_rew_zq_l1 |
# (.length(addr_width+1), .level1_value(fifo_full_level)) |
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk)); |
|
vl_cnt_bin_ce_rew_zq_l1 |
# (.length(addr_width+1), .level1_value(fifo_full_level)) |
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk)); |
|
endmodule |
|
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst ); |
|
parameter addr_width = 4; |
/trunk/rtl/verilog/versatile_library.v
1629,6 → 1629,239
////////////////////////////////////////////////////////////////////// |
|
// LFSR counter |
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk); |
|
parameter length = 4; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
|
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
|
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
|
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10000010000000000000; // 0x82000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
|
assign q = qi; |
|
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
// LFSR counter |
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk); |
|
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
|
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
|
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
|
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10000010000000000000; // 0x82000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
|
assign q = qi; |
|
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
// LFSR counter |
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk); |
|
parameter length = 4; |
2534,11 → 2767,92
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk)); |
|
vl_cnt_bin_ce_rew_zq_l1 |
# (.length(addr_width+1), .level1(1<<add_width)) |
# (.length(addr_width+1), .level1_value(1<<addr_width)) |
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk)); |
|
endmodule |
|
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource |
// RAM is supposed to be larger than the two FIFOs |
// LFSR counters used adr pointers |
module vl_fifo_2r2w_sync_simplex ( |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
a_fill_level, |
// b side |
b_d, b_wr, b_fifo_full, |
b_q, b_rd, b_fifo_empty, |
b_fill_level, |
// common |
clk, rst |
); |
parameter data_width = 8; |
parameter addr_width = 5; |
parameter fifo_full_level = (1<<addr_width)-1; |
|
// a side |
input [data_width-1:0] a_d; |
input a_wr; |
output a_fifo_full; |
output [data_width-1:0] a_q; |
input a_rd; |
output a_fifo_empty; |
output [addr_width-1:0] a_fill_level; |
|
// b side |
input [data_width-1:0] b_d; |
input b_wr; |
output b_fifo_full; |
output [data_width-1:0] b_q; |
input b_rd; |
output b_fifo_empty; |
output [addr_width-1:0] b_fill_level; |
|
input clk; |
input rst; |
|
// adr_gen |
wire [addr_width:1] a_wadr, a_radr; |
wire [addr_width:1] b_wadr, b_radr; |
// dpram |
wire [addr_width:0] a_dpram_adr, b_dpram_adr; |
|
vl_cnt_lfsr_ce |
# ( .length(addr_width)) |
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk)); |
|
vl_cnt_lfsr_ce |
# (.length(addr_width)) |
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk)); |
|
vl_cnt_lfsr_ce |
# ( .length(addr_width)) |
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk)); |
|
vl_cnt_lfsr_ce |
# (.length(addr_width)) |
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk)); |
|
// mux read or write adr to DPRAM |
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr}; |
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr}; |
|
vl_dpram_2r2w |
# (.data_width(data_width), .addr_width(addr_width+1)) |
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk), |
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk)); |
|
vl_cnt_bin_ce_rew_zq_l1 |
# (.length(addr_width+1), .level1_value(fifo_full_level)) |
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk)); |
|
vl_cnt_bin_ce_rew_zq_l1 |
# (.length(addr_width+1), .level1_value(fifo_full_level)) |
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk)); |
|
endmodule |
|
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst ); |
|
parameter addr_width = 4; |
2627,7 → 2941,7
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty)); |
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty)); |
|
endmodule // async_comp |
endmodule // async_compb |
|
module vl_fifo_1r1w_async ( |
d, wr, fifo_full, wr_clk, wr_rst, |
/trunk/rtl/verilog/versatile_library_actel.v
1277,6 → 1277,223
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk); |
parameter length = 4; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10000010000000000000; // 0x82000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk); |
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10000010000000000000; // 0x82000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk); |
parameter length = 4; |
input cke; |
2082,9 → 2299,76
# (.data_width(data_width), .addr_width(addr_width)) |
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk)); |
vl_cnt_bin_ce_rew_zq_l1 |
# (.length(addr_width+1), .level1(1<<add_width)) |
# (.length(addr_width+1), .level1_value(1<<addr_width)) |
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk)); |
endmodule |
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource |
// RAM is supposed to be larger than the two FIFOs |
// LFSR counters used adr pointers |
module vl_fifo_2r2w_sync_simplex ( |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
a_fill_level, |
// b side |
b_d, b_wr, b_fifo_full, |
b_q, b_rd, b_fifo_empty, |
b_fill_level, |
// common |
clk, rst |
); |
parameter data_width = 8; |
parameter addr_width = 5; |
parameter fifo_full_level = (1<<addr_width)-1; |
// a side |
input [data_width-1:0] a_d; |
input a_wr; |
output a_fifo_full; |
output [data_width-1:0] a_q; |
input a_rd; |
output a_fifo_empty; |
output [addr_width-1:0] a_fill_level; |
// b side |
input [data_width-1:0] b_d; |
input b_wr; |
output b_fifo_full; |
output [data_width-1:0] b_q; |
input b_rd; |
output b_fifo_empty; |
output [addr_width-1:0] b_fill_level; |
input clk; |
input rst; |
// adr_gen |
wire [addr_width:1] a_wadr, a_radr; |
wire [addr_width:1] b_wadr, b_radr; |
// dpram |
wire [addr_width:0] a_dpram_adr, b_dpram_adr; |
vl_cnt_lfsr_ce |
# ( .length(addr_width)) |
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk)); |
vl_cnt_lfsr_ce |
# (.length(addr_width)) |
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk)); |
vl_cnt_lfsr_ce |
# ( .length(addr_width)) |
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk)); |
vl_cnt_lfsr_ce |
# (.length(addr_width)) |
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk)); |
// mux read or write adr to DPRAM |
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr}; |
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr}; |
vl_dpram_2r2w |
# (.data_width(data_width), .addr_width(addr_width+1)) |
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk), |
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk)); |
vl_cnt_bin_ce_rew_zq_l1 |
# (.length(addr_width+1), .level1_value(fifo_full_level)) |
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk)); |
vl_cnt_bin_ce_rew_zq_l1 |
# (.length(addr_width+1), .level1_value(fifo_full_level)) |
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk)); |
endmodule |
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst ); |
parameter addr_width = 4; |
parameter N = addr_width-1; |
2145,7 → 2429,7
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */ |
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty)); |
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty)); |
endmodule // async_comp |
endmodule // async_compb |
module vl_fifo_1r1w_async ( |
d, wr, fifo_full, wr_clk, wr_rst, |
q, rd, fifo_empty, rd_clk, rd_rst |
/trunk/rtl/verilog/versatile_library_altera.v
1263,6 → 1263,223
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk); |
parameter length = 4; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10000010000000000000; // 0x82000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk); |
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10000010000000000000; // 0x82000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk); |
parameter length = 4; |
input cke; |
2068,9 → 2285,76
# (.data_width(data_width), .addr_width(addr_width)) |
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk)); |
vl_cnt_bin_ce_rew_zq_l1 |
# (.length(addr_width+1), .level1(1<<add_width)) |
# (.length(addr_width+1), .level1_value(1<<addr_width)) |
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk)); |
endmodule |
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource |
// RAM is supposed to be larger than the two FIFOs |
// LFSR counters used adr pointers |
module vl_fifo_2r2w_sync_simplex ( |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
a_fill_level, |
// b side |
b_d, b_wr, b_fifo_full, |
b_q, b_rd, b_fifo_empty, |
b_fill_level, |
// common |
clk, rst |
); |
parameter data_width = 8; |
parameter addr_width = 5; |
parameter fifo_full_level = (1<<addr_width)-1; |
// a side |
input [data_width-1:0] a_d; |
input a_wr; |
output a_fifo_full; |
output [data_width-1:0] a_q; |
input a_rd; |
output a_fifo_empty; |
output [addr_width-1:0] a_fill_level; |
// b side |
input [data_width-1:0] b_d; |
input b_wr; |
output b_fifo_full; |
output [data_width-1:0] b_q; |
input b_rd; |
output b_fifo_empty; |
output [addr_width-1:0] b_fill_level; |
input clk; |
input rst; |
// adr_gen |
wire [addr_width:1] a_wadr, a_radr; |
wire [addr_width:1] b_wadr, b_radr; |
// dpram |
wire [addr_width:0] a_dpram_adr, b_dpram_adr; |
vl_cnt_lfsr_ce |
# ( .length(addr_width)) |
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk)); |
vl_cnt_lfsr_ce |
# (.length(addr_width)) |
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk)); |
vl_cnt_lfsr_ce |
# ( .length(addr_width)) |
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk)); |
vl_cnt_lfsr_ce |
# (.length(addr_width)) |
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk)); |
// mux read or write adr to DPRAM |
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr}; |
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr}; |
vl_dpram_2r2w |
# (.data_width(data_width), .addr_width(addr_width+1)) |
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk), |
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk)); |
vl_cnt_bin_ce_rew_zq_l1 |
# (.length(addr_width+1), .level1_value(fifo_full_level)) |
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk)); |
vl_cnt_bin_ce_rew_zq_l1 |
# (.length(addr_width+1), .level1_value(fifo_full_level)) |
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk)); |
endmodule |
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst ); |
parameter addr_width = 4; |
parameter N = addr_width-1; |
2131,7 → 2415,7
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */ |
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty)); |
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty)); |
endmodule // async_comp |
endmodule // async_compb |
module vl_fifo_1r1w_async ( |
d, wr, fifo_full, wr_clk, wr_rst, |
q, rd, fifo_empty, rd_clk, rd_rst |