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Rev 29 → Rev 28
/trunk/rtl/verilog/cnt_bin_ce_clear_l1_l2.csv
File deleted
/trunk/rtl/verilog/versatile_library.v
387,47 → 387,6
|
endmodule |
|
module vl_spr ( sp, r, q, clk, rst); |
|
parameter width = 1; |
parameter reset_value = 0; |
|
input sp, r; |
output reg q; |
input clk, rst; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
q <= reset_value; |
else |
if (sp) |
q <= 1'b1; |
else if (r) |
q <= 1'b0; |
|
endmodule |
|
module vl_srp ( s, rp, q, clk, rst); |
|
parameter width = 1; |
parameter reset_value = 0; |
|
input s, rp; |
output reg q; |
input clk, rst; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
q <= reset_value; |
else |
if (rp) |
q <= 1'b0; |
else if (s) |
q <= 1'b1; |
|
endmodule |
|
|
`ifdef ALTERA |
// megafunction wizard: %LPM_FF% |
// GENERATION: STANDARD |
1090,105 → 1049,6
////////////////////////////////////////////////////////////////////// |
|
// binary counter |
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk); |
|
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
output reg level1; |
output reg level2; |
input rst; |
input clk; |
|
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 7; |
parameter level1_value = 15; |
|
wire rew; |
assign rew=1'b0; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
|
assign q = qi; |
|
|
always @ (posedge clk or posedge rst) |
if (rst) |
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
level2 <= 1'b0; |
else |
if (cke) |
if (clear) |
level2 <= 1'b0; |
else if (q_next == level2_value) |
level2 <= 1'b1; |
else if (qi == level2_value & rew) |
level2 <= 1'b0; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
// binary counter |
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk); |
|
parameter length = 4; |
1278,8 → 1138,6
parameter wrap_value = 1; |
parameter level1_value = 15; |
|
wire clear; |
assign clear=1'b0; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = qi + {{length-1{1'b0}},1'b1}; |
1300,9 → 1158,7
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
1365,8 → 1221,6
parameter wrap_value = 1; |
parameter level1_value = 15; |
|
wire clear; |
assign clear=1'b0; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = qi + {{length-1{1'b0}},1'b1}; |
1394,9 → 1248,7
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
1460,8 → 1312,6
parameter wrap_value = 1; |
parameter level1_value = 15; |
|
wire clear; |
assign clear=1'b0; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = qi + {{length-1{1'b0}},1'b1}; |
1490,9 → 1340,7
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
2152,8 → 2000,6
parameter wrap_value = 8; |
parameter level1_value = 15; |
|
wire clear; |
assign clear=1'b0; |
reg [length:1] qi; |
reg lfsr_fb, lfsr_fb_rew; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
2266,9 → 2112,7
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
/trunk/rtl/verilog/versatile_library_actel.v
284,36 → 284,6
else |
q <= d; |
endmodule |
module vl_spr ( sp, r, q, clk, rst); |
parameter width = 1; |
parameter reset_value = 0; |
input sp, r; |
output reg q; |
input clk, rst; |
always @ (posedge clk or posedge rst) |
if (rst) |
q <= reset_value; |
else |
if (sp) |
q <= 1'b1; |
else if (r) |
q <= 1'b0; |
endmodule |
module vl_srp ( s, rp, q, clk, rst); |
parameter width = 1; |
parameter reset_value = 0; |
input s, rp; |
output reg q; |
input clk, rst; |
always @ (posedge clk or posedge rst) |
if (rst) |
q <= reset_value; |
else |
if (rp) |
q <= 1'b0; |
else if (s) |
q <= 1'b1; |
endmodule |
module vl_dff_sr ( aclr, aset, clock, data, q); |
input aclr; |
input aset; |
778,96 → 748,6
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk); |
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
output reg level1; |
output reg level2; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 7; |
parameter level1_value = 15; |
wire rew; |
assign rew=1'b0; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
always @ (posedge clk or posedge rst) |
if (rst) |
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
always @ (posedge clk or posedge rst) |
if (rst) |
level2 <= 1'b0; |
else |
if (cke) |
if (clear) |
level2 <= 1'b0; |
else if (q_next == level2_value) |
level2 <= 1'b1; |
else if (qi == level2_value & rew) |
level2 <= 1'b0; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk); |
parameter length = 4; |
input clear; |
947,8 → 827,6
parameter set_value = 1; |
parameter wrap_value = 1; |
parameter level1_value = 15; |
wire clear; |
assign clear=1'b0; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = qi + {{length-1{1'b0}},1'b1}; |
965,9 → 843,7
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
1026,8 → 902,6
parameter set_value = 1; |
parameter wrap_value = 1; |
parameter level1_value = 15; |
wire clear; |
assign clear=1'b0; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = qi + {{length-1{1'b0}},1'b1}; |
1050,9 → 924,7
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
1112,8 → 984,6
parameter set_value = 1; |
parameter wrap_value = 1; |
parameter level1_value = 15; |
wire clear; |
assign clear=1'b0; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = qi + {{length-1{1'b0}},1'b1}; |
1137,9 → 1007,7
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
1752,8 → 1620,6
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
wire clear; |
assign clear=1'b0; |
reg [length:1] qi; |
reg lfsr_fb, lfsr_fb_rew; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
1861,9 → 1727,7
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
/trunk/rtl/verilog/versatile_library_altera.v
181,36 → 181,6
else |
q <= d; |
endmodule |
module vl_spr ( sp, r, q, clk, rst); |
parameter width = 1; |
parameter reset_value = 0; |
input sp, r; |
output reg q; |
input clk, rst; |
always @ (posedge clk or posedge rst) |
if (rst) |
q <= reset_value; |
else |
if (sp) |
q <= 1'b1; |
else if (r) |
q <= 1'b0; |
endmodule |
module vl_srp ( s, rp, q, clk, rst); |
parameter width = 1; |
parameter reset_value = 0; |
input s, rp; |
output reg q; |
input clk, rst; |
always @ (posedge clk or posedge rst) |
if (rst) |
q <= reset_value; |
else |
if (rp) |
q <= 1'b0; |
else if (s) |
q <= 1'b1; |
endmodule |
// megafunction wizard: %LPM_FF% |
// GENERATION: STANDARD |
// VERSION: WM1.0 |
764,96 → 734,6
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk); |
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
output reg level1; |
output reg level2; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 7; |
parameter level1_value = 15; |
wire rew; |
assign rew=1'b0; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
always @ (posedge clk or posedge rst) |
if (rst) |
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
always @ (posedge clk or posedge rst) |
if (rst) |
level2 <= 1'b0; |
else |
if (cke) |
if (clear) |
level2 <= 1'b0; |
else if (q_next == level2_value) |
level2 <= 1'b1; |
else if (qi == level2_value & rew) |
level2 <= 1'b0; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk); |
parameter length = 4; |
input clear; |
933,8 → 813,6
parameter set_value = 1; |
parameter wrap_value = 1; |
parameter level1_value = 15; |
wire clear; |
assign clear=1'b0; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = qi + {{length-1{1'b0}},1'b1}; |
951,9 → 829,7
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
1012,8 → 888,6
parameter set_value = 1; |
parameter wrap_value = 1; |
parameter level1_value = 15; |
wire clear; |
assign clear=1'b0; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = qi + {{length-1{1'b0}},1'b1}; |
1036,9 → 910,7
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
1098,8 → 970,6
parameter set_value = 1; |
parameter wrap_value = 1; |
parameter level1_value = 15; |
wire clear; |
assign clear=1'b0; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = qi + {{length-1{1'b0}},1'b1}; |
1123,9 → 993,7
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
1738,8 → 1606,6
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
wire clear; |
assign clear=1'b0; |
reg [length:1] qi; |
reg lfsr_fb, lfsr_fb_rew; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
1847,9 → 1713,7
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
/trunk/rtl/verilog/Makefile
6,7 → 6,6
VERILOG_FILES_CNT += vl_cnt_bin_clear.v |
VERILOG_FILES_CNT += vl_cnt_bin_ce.v |
VERILOG_FILES_CNT += vl_cnt_bin_ce_clear.v |
VERILOG_FILES_CNT += vl_cnt_bin_ce_clear_l1_l2.v |
VERILOG_FILES_CNT += vl_cnt_bin_ce_clear_set_rew.v |
VERILOG_FILES_CNT += vl_cnt_bin_ce_rew_l1.v |
VERILOG_FILES_CNT += vl_cnt_bin_ce_rew_zq_l1.v |
41,7 → 40,6
./versatile_counter_generator.php cnt_bin_clear.csv > vl_cnt_bin_clear.v |
./versatile_counter_generator.php cnt_bin_ce.csv > vl_cnt_bin_ce.v |
./versatile_counter_generator.php cnt_bin_ce_clear.csv > vl_cnt_bin_ce_clear.v |
./versatile_counter_generator.php cnt_bin_ce_clear_l1_l2.csv > vl_cnt_bin_ce_clear_l1_l2.v |
./versatile_counter_generator.php cnt_bin_ce_clear_set_rew.csv > vl_cnt_bin_ce_clear_set_rew.v |
./versatile_counter_generator.php cnt_bin_ce_rew_l1.csv > vl_cnt_bin_ce_rew_l1.v |
./versatile_counter_generator.php cnt_bin_ce_rew_zq_l1.csv > vl_cnt_bin_ce_rew_zq_l1.v |
/trunk/rtl/verilog/registers.v
142,47 → 142,6
|
endmodule |
|
module vl_spr ( sp, r, q, clk, rst); |
|
parameter width = 1; |
parameter reset_value = 0; |
|
input sp, r; |
output reg q; |
input clk, rst; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
q <= reset_value; |
else |
if (sp) |
q <= 1'b1; |
else if (r) |
q <= 1'b0; |
|
endmodule |
|
module vl_srp ( s, rp, q, clk, rst); |
|
parameter width = 1; |
parameter reset_value = 0; |
|
input s, rp; |
output reg q; |
input clk, rst; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
q <= reset_value; |
else |
if (rp) |
q <= 1'b0; |
else if (s) |
q <= 1'b1; |
|
endmodule |
|
|
`ifdef ALTERA |
// megafunction wizard: %LPM_FF% |
// GENERATION: STANDARD |