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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path 
    /versatile_library
    from Rev 30 to Rev 29
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  •

Rev 30 → Rev 29

/trunk/rtl/verilog/versatile_library.v
1103,12 → 1103,11
 
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 15;
parameter level1_value = 8;
parameter level2_value = 15;
parameter wrap_value = 7;
parameter level1_value = 15;
 
wire rew;
assign rew = 1'b0;
assign rew=1'b0;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1280,7 → 1279,7
parameter level1_value = 15;
 
wire clear;
assign clear = 1'b0;
assign clear=1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1367,7 → 1366,7
parameter level1_value = 15;
 
wire clear;
assign clear = 1'b0;
assign clear=1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1462,7 → 1461,7
parameter level1_value = 15;
 
wire clear;
assign clear = 1'b0;
assign clear=1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
2154,7 → 2153,7
parameter level1_value = 15;
 
wire clear;
assign clear = 1'b0;
assign clear=1'b0;
reg [length:1] qi;
reg lfsr_fb, lfsr_fb_rew;
wire [length:1] q_next, q_next_fw, q_next_rew;
/trunk/rtl/verilog/versatile_library_actel.v
789,11 → 789,10
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 15;
parameter level1_value = 8;
parameter level2_value = 15;
parameter wrap_value = 7;
parameter level1_value = 15;
wire rew;
assign rew = 1'b0;
assign rew=1'b0;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
949,7 → 948,7
parameter wrap_value = 1;
parameter level1_value = 15;
wire clear;
assign clear = 1'b0;
assign clear=1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1028,7 → 1027,7
parameter wrap_value = 1;
parameter level1_value = 15;
wire clear;
assign clear = 1'b0;
assign clear=1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1114,7 → 1113,7
parameter wrap_value = 1;
parameter level1_value = 15;
wire clear;
assign clear = 1'b0;
assign clear=1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1754,7 → 1753,7
parameter wrap_value = 8;
parameter level1_value = 15;
wire clear;
assign clear = 1'b0;
assign clear=1'b0;
reg [length:1] qi;
reg lfsr_fb, lfsr_fb_rew;
wire [length:1] q_next, q_next_fw, q_next_rew;
/trunk/rtl/verilog/cnt_bin_ce_clear_l1_l2.csv
11,4 → 11,4
0,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,15,8,15
4,0,1,7,15,
/trunk/rtl/verilog/versatile_library_altera.v
775,11 → 775,10
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 15;
parameter level1_value = 8;
parameter level2_value = 15;
parameter wrap_value = 7;
parameter level1_value = 15;
wire rew;
assign rew = 1'b0;
assign rew=1'b0;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
935,7 → 934,7
parameter wrap_value = 1;
parameter level1_value = 15;
wire clear;
assign clear = 1'b0;
assign clear=1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1014,7 → 1013,7
parameter wrap_value = 1;
parameter level1_value = 15;
wire clear;
assign clear = 1'b0;
assign clear=1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1100,7 → 1099,7
parameter wrap_value = 1;
parameter level1_value = 15;
wire clear;
assign clear = 1'b0;
assign clear=1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
1740,7 → 1739,7
parameter wrap_value = 8;
parameter level1_value = 15;
wire clear;
assign clear = 1'b0;
assign clear=1'b0;
reg [length:1] qi;
reg lfsr_fb, lfsr_fb_rew;
wire [length:1] q_next, q_next_fw, q_next_rew;

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