URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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- This comparison shows the changes necessary to convert path
/versatile_library
- from Rev 37 to Rev 38
- ↔ Reverse comparison
Rev 37 → Rev 38
/trunk/rtl/verilog/versatile_library.v
853,11 → 853,14
input [nr_of_ports-1:0] sel; |
output reg [width-1:0] dout; |
|
integer i,j; |
|
always @ (a, sel) |
begin |
dout = a[width-1:0] & {width{sel[0]}}; |
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1) |
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout; |
for (j=0;j<32;j=j+1) |
dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j]; |
end |
|
endmodule |
871,19 → 874,9
output [width-1:0] dout; |
|
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
|
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
|
// or |
assign dout = tmp[1] | tmp[0]; |
*/ |
|
endmodule |
|
module vl_mux3_andor ( a2, a1, a0, sel, dout); |
895,21 → 888,9
output [width-1:0] dout; |
|
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
|
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
|
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
|
// or |
assign dout = tmp[2] | tmp[1] | tmp[0]; |
*/ |
|
endmodule |
|
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout); |
921,21 → 902,9
output [width-1:0] dout; |
|
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
|
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
|
// or |
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
*/ |
endmodule |
|
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout); |
947,22 → 916,9
output [width-1:0] dout; |
|
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
|
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
assign tmp[4] = {width{sel[4]}} & a4; |
|
// or |
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
*/ |
endmodule |
|
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout); |
974,23 → 930,9
output [width-1:0] dout; |
|
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
|
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
assign tmp[4] = {width{sel[4]}} & a4; |
assign tmp[5] = {width{sel[5]}} & a5; |
|
// or |
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
*/ |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
/trunk/rtl/verilog/versatile_library_actel.v
443,11 → 443,13
input [nr_of_ports*width-1:0] a; |
input [nr_of_ports-1:0] sel; |
output reg [width-1:0] dout; |
integer i,j; |
always @ (a, sel) |
begin |
dout = a[width-1:0] & {width{sel[0]}}; |
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1) |
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout; |
for (j=0;j<32;j=j+1) |
dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j]; |
end |
endmodule |
module vl_mux2_andor ( a1, a0, sel, dout); |
457,17 → 459,8
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
// or |
assign dout = tmp[1] | tmp[0]; |
*/ |
endmodule |
module vl_mux3_andor ( a2, a1, a0, sel, dout); |
parameter width = 32; |
476,18 → 469,8
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
// or |
assign dout = tmp[2] | tmp[1] | tmp[0]; |
*/ |
endmodule |
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout); |
parameter width = 32; |
496,19 → 479,8
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
// or |
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
*/ |
endmodule |
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout); |
parameter width = 32; |
517,20 → 489,8
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
assign tmp[4] = {width{sel[4]}} & a4; |
// or |
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
*/ |
endmodule |
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout); |
parameter width = 32; |
539,21 → 499,8
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
assign tmp[4] = {width{sel[4]}} & a4; |
assign tmp[5] = {width{sel[5]}} & a5; |
// or |
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
*/ |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
/trunk/rtl/verilog/versatile_library_altera.v
551,11 → 551,13
input [nr_of_ports*width-1:0] a; |
input [nr_of_ports-1:0] sel; |
output reg [width-1:0] dout; |
integer i,j; |
always @ (a, sel) |
begin |
dout = a[width-1:0] & {width{sel[0]}}; |
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1) |
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout; |
for (j=0;j<32;j=j+1) |
dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j]; |
end |
endmodule |
module vl_mux2_andor ( a1, a0, sel, dout); |
565,17 → 567,8
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
// or |
assign dout = tmp[1] | tmp[0]; |
*/ |
endmodule |
module vl_mux3_andor ( a2, a1, a0, sel, dout); |
parameter width = 32; |
584,18 → 577,8
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
// or |
assign dout = tmp[2] | tmp[1] | tmp[0]; |
*/ |
endmodule |
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout); |
parameter width = 32; |
604,19 → 587,8
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
// or |
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
*/ |
endmodule |
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout); |
parameter width = 32; |
625,20 → 597,8
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
assign tmp[4] = {width{sel[4]}} & a4; |
// or |
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
*/ |
endmodule |
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout); |
parameter width = 32; |
647,21 → 607,8
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
assign tmp[4] = {width{sel[4]}} & a4; |
assign tmp[5] = {width{sel[5]}} & a5; |
// or |
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
*/ |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
/trunk/rtl/verilog/logic.v
48,11 → 48,14
input [nr_of_ports-1:0] sel; |
output reg [width-1:0] dout; |
|
integer i,j; |
|
always @ (a, sel) |
begin |
dout = a[width-1:0] & {width{sel[0]}}; |
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1) |
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout; |
for (j=0;j<32;j=j+1) |
dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j]; |
end |
|
endmodule |
66,19 → 69,9
output [width-1:0] dout; |
|
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
|
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
|
// or |
assign dout = tmp[1] | tmp[0]; |
*/ |
|
endmodule |
|
module vl_mux3_andor ( a2, a1, a0, sel, dout); |
90,21 → 83,9
output [width-1:0] dout; |
|
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
|
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
|
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
|
// or |
assign dout = tmp[2] | tmp[1] | tmp[0]; |
*/ |
|
endmodule |
|
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout); |
116,21 → 97,9
output [width-1:0] dout; |
|
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
|
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
|
// or |
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
*/ |
endmodule |
|
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout); |
142,22 → 111,9
output [width-1:0] dout; |
|
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
|
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
assign tmp[4] = {width{sel[4]}} & a4; |
|
// or |
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
*/ |
endmodule |
|
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout); |
169,21 → 125,7
output [width-1:0] dout; |
|
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports) |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
/* |
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
|
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
assign tmp[4] = {width{sel[4]}} & a4; |
assign tmp[5] = {width{sel[5]}} & a5; |
|
// or |
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
*/ |
endmodule |