OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /versatile_library
    from Rev 87 to Rev 88
    Reverse comparison

Rev 87 → Rev 88

/trunk/testbench/tb_wb_b3_ram_be.v
0,0 → 1,19
module vl_wb_b3_ram_be_tb ();
 
 
 
vl_wb_b3_ram_be dut (
.wbs_dat_i(),
.wbs_adr_i(),
.wbs_cti_i(),
.wbs_bte_i(),
.wbs_sel_i(),
.wbs_we_i(),
.wbs_stb_i(),
.wbs_cyc_i(),
.wbs_dat_o(),
.wbs_ack_o(),
.wb_clk(),
.wb_rst());
endmodule
/trunk/sim/rtl_sim/run/Makefile
1,2 → 1,4
wb_dpram_be:
vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_DPRAM_BE ../../../rt/verilog/versatile_library.v > wb_dp_ram_be.v
VERILOG_FILES = ./../../../rtl/verilog/versatile_library.v
 
wb_b3_ram_be.v:
vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_B3_RAM_BE $(VERILOG_FILES) > wb_b3_ram_be.v

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.