URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl
- from Rev 39 to Rev 40
- ↔ Reverse comparison
Rev 39 → Rev 40
/verilog/cnt_bin_ce_rew_q_zq_l1.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_bin_ce_rew_q_zq_l1,binary,,,, |
cnt_bin_ce_rew_q_zq_l1,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,1,, |
/verilog/cnt_bin_ce_clear.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_bin_ce_clear,binary,,,, |
cnt_bin_ce_clear,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
1,0,1,0,, |
/verilog/versatile_library.v
1,3 → 1,214
`ifndef BASE |
`define BASE vl_ |
`endif |
|
`ifdef ALL |
|
`define GBUF |
`define SYNC_RST |
`define PLL |
|
`define MULTS |
`define MULTS18X18 |
`define MULT |
`define SHIFT_UNIT_32 |
`define LOGIC_UNIT |
|
`define CNT_SHREG_WRAP |
`define CNT_SHREG_CE_WRAP |
`define CNT_SHREG_CE_CLEAR |
`define CNT_SHREG_CE_CLEAR_WRAP |
|
`define MUX_ANDOR |
`define MUX2_ANDOR |
`define MUX3_ANDOR |
`define MUX4_ANDOR |
`define MUX5_ANDOR |
`define MUX6_ANDOR |
|
`define ROM_INIT |
`define RAM |
`define RAM_BE |
`define DPRAM_1R1W |
`define DPRAM_2R1W |
`define DPRAM_2R2W |
`define FIFO_1R1W_FILL_LEVEL_SYNC |
`define FIFO_2R2W_SYNC_SIMPLEX |
`define FIFO_CMP_ASYNC |
`define FIFO_1R1W_ASYNC |
`define FIFO_2R2W_ASYNC |
`define FIFO_2R2W_ASYNC_SIMPLEX |
|
`define DFF |
`define DFF_ARRAY |
`define DFF_CE |
`define DFF_CE_CLEAR |
`define DF_CE_SET |
`define SPR |
`define SRP |
`define DFF_SR |
`define LATCH |
`define SHREG |
`define SHREG_CE |
`define DELAY |
`define DELAY_EMPTYFLAG |
|
`define WB3WB3_BRIDGE |
`define WB3_ARBITER_TYPE1 |
`define WB_BOOT_ROM |
`define WB_DPRAM |
|
`endif |
|
`ifdef PLL |
`ifndef SYNC_RST |
`define SYNC_RST |
`endif |
`endif |
|
`ifdef SYNC_RST |
`ifndef GBUF |
`define GBUF |
`endif |
`endif |
|
`ifdef WB_DPRAM |
`ifndef DPRAM_2R2W |
`define DPRAM_2R2W |
`endif |
`ifndef SPR |
`define SPR |
`endif |
`endif |
|
`ifdef WB3_ARBITER_TYPE1 |
`ifndef MUX_ANDOR |
`define MUX_ANDOR |
`endif |
`endif |
|
`ifdef WB3WB3_BRIDGE |
`ifndef CNT_SHREG_CE_CLEAR |
`define CNT_SHREG_CE_CLEAR |
`endif |
`ifndef DFF |
`define DFF |
`endif |
`ifndef DFF_CE |
`define DFF_CE |
`endif |
`ifndef CNT_SHREG_CE_CLEAR |
`define CNT_SHREG_CE_CLEAR |
`endif |
`ifndef FIFO_2R2W_ASYNC_SIMPLEX |
`define FIFO_2R2W_ASYNC_SIMPLEX |
`endif |
`endif |
|
`ifdef MULTS18X18 |
`ifndef MULTS |
`define MULTS |
`endif |
`endif |
|
`ifdef SHIFT_UNIT_32 |
`ifndef MULTS |
`define MULTS |
`endif |
`endif |
|
`ifdef MUX2_ANDOR |
`ifndef MUX_ANDOR |
`define MUX_ANDOR |
`endif |
`endif |
|
`ifdef MUX3_ANDOR |
`ifndef MUX_ANDOR |
`define MUX_ANDOR |
`endif |
`endif |
|
`ifdef MUX4_ANDOR |
`ifndef MUX_ANDOR |
`define MUX_ANDOR |
`endif |
`endif |
|
`ifdef MUX5_ANDOR |
`ifndef MUX_ANDOR |
`define MUX_ANDOR |
`endif |
`endif |
|
`ifdef MUX6_ANDOR |
`ifndef MUX_ANDOR |
`define MUX_ANDOR |
`endif |
`endif |
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC |
`ifndef CNT_BIN_CE |
`define CNT_BIN_CE |
`endif |
`ifndef DPRAM_1R1W |
`define DPRAM_1R1W |
`endif |
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1 |
`define CNT_BIN_CE_REW_Q_ZQ_L1 |
`endif |
`endif |
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC |
`ifndef CNT_LFSR_CE |
`define CNT_LFSR_CE |
`endif |
`ifndef DPRAM_2R2W |
`define DPRAM_2R2W |
`endif |
`ifndef CNT_BIN_CE_REW_ZQ_L1 |
`define CNT_BIN_CE_REW_ZQ_L1 |
`endif |
`endif |
|
`ifdef FIFO_2R2W_ASYNC_SIMPLEX |
`ifndef CNT_GRAY_CE_BIN |
`define CNT_GRAY_CE_BIN |
`endif |
`ifndef DPRAM_2R2W |
`define DPRAM_2R2W |
`endif |
`ifndef FIFO_CMP_ASYNC |
`define FIFO_CMP_ASYNC |
`endif |
`endif |
|
`ifdef FIFO_2R2W_ASYNC |
`ifndef FIFO_1R1W_ASYNC |
`define FIFO_1R1W_ASYNC |
`endif |
`endif |
|
`ifdef FIFO_1R1W_ASYNC |
`ifndef CNT_GRAY_CE_BIN |
`define CNT_GRAY_CE_BIN |
`endif |
`ifndef DPRAM_1R1W |
`define DPRAM_1R1W |
`endif |
`ifndef FIFO_CMP_ASYNC |
`define FIFO_CMP_ASYNC |
`endif |
`endif |
|
`ifdef FIFO_CMP_ASYNC |
`ifndef DFF_SR |
`define DFF_SR |
`endif |
`ifndef DFF |
`define DFF |
`endif |
`endif |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile library, clock and reset //// |
45,7 → 256,7
// use to enable global buffers for high fan out signals such as clock and reset |
|
`ifdef ACTEL |
|
`ifdef GBUF |
`timescale 1 ns/100 ps |
// Version: 8.4 8.4.0.33 |
module gbuf(GL,CLK); |
60,7 → 271,9
|
endmodule |
`timescale 1 ns/1 ns |
module vl_gbuf ( i, o); |
`define MODULE gbuf |
module `BASE`MODULE ( i, o); |
`undef MODULE |
input i; |
output o; |
`ifdef SIM_GBUF |
69,33 → 282,45
gbuf gbuf_i0 ( .CLK(i), .GL(o)); |
`endif |
endmodule |
`endif |
|
`else |
|
`ifdef ALTERA |
`ifdef ALTERA |
`ifdef GBUF |
//altera |
module vl_gbuf ( i, o); |
`define MODULE gbuf |
module `BASE`MODULE ( i, o); |
`undef MODULE |
input i; |
output o; |
assign o = i; |
endmodule |
`endif |
|
`else |
|
`ifdef GBUF |
`timescale 1 ns/100 ps |
module vl_gbuf ( i, o); |
`define MODULE |
module `BASE`MODULE ( i, o); |
`undef MODULE |
input i; |
output o; |
assign o = i; |
endmodule |
`endif |
`endif // ALTERA |
`endif //ACTEL |
|
`ifdef SYNC_RST |
// sync reset |
// input active lo async reset, normally from external reset generator and/or switch |
// output active high global reset sync with two DFFs |
`timescale 1 ns/100 ps |
module vl_sync_rst ( rst_n_i, rst_o, clk); |
`define MODULE sync_rst |
module `BASE`MODULE ( rst_n_i, rst_o, clk); |
`undef MODULE |
input rst_n_i, clk; |
output rst_o; |
reg [1:0] tmp; |
104,14 → 329,20
tmp <= 2'b11; |
else |
tmp <= {1'b0,tmp[1]}; |
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o)); |
`define MODULE gbuf |
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o)); |
`undef MODULE |
endmodule |
`endif |
|
`ifdef PLL |
// vl_pll |
`ifdef ACTEL |
/////////////////////////////////////////////////////////////////////////////// |
`timescale 1 ps/1 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`define MODULE pll |
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`undef MODULE |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
201,7 → 432,9
|
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i])); |
`define MODULE sync_rst |
`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i])); |
`undef MODULE |
end |
endgenerate |
endmodule |
214,7 → 447,9
`ifdef ALTERA |
|
`timescale 1 ps/1 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`define MODULE pll |
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`undef MODULE |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
339,7 → 574,9
|
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
`define MODULE sync_rst |
`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
`undef MODULE |
end |
endgenerate |
endmodule |
350,7 → 587,9
|
// generic PLL |
`timescale 1 ps/1 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`define MODULE pll |
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`undef MODULE |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
377,7 → 616,9
|
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
`define MODULE sync_rst |
`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
`undef MODULE |
end |
endgenerate |
|
387,7 → 628,8
|
`endif //altera |
`endif //actel |
////////////////////////////////////////////////////////////////////// |
`undef MODULE |
`endif////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile library, registers //// |
//// //// |
429,8 → 671,10
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module vl_dff ( d, q, clk, rst); |
|
`ifdef DFF |
`define MODULE dff |
module `BASE`MODULE ( d, q, clk, rst); |
`undef MODULE |
parameter width = 1; |
parameter reset_value = 0; |
|
445,8 → 689,12
q <= d; |
|
endmodule |
`endif |
|
module vl_dff_array ( d, q, clk, rst); |
`ifdef DFF_ARRAY |
`define MODULE dff_array |
module `BASE`MODULE ( d, q, clk, rst); |
`undef MODULE |
|
parameter width = 1; |
parameter depth = 2; |
470,8 → 718,12
assign q = q_tmp[depth-1]; |
|
endmodule |
`endif |
|
module vl_dff_ce ( d, ce, q, clk, rst); |
`ifdef DFF_CE |
`define MODULE dff_ce |
module `BASE`MODULE ( d, ce, q, clk, rst); |
`undef MODULE |
|
parameter width = 1; |
parameter reset_value = 0; |
488,8 → 740,12
q <= d; |
|
endmodule |
`endif |
|
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst); |
`ifdef DFF_CE_CLEAR |
`define MODULE dff_ce_clear |
module `BASE`MODULE ( d, ce, clear, q, clk, rst); |
`undef MODULE |
|
parameter width = 1; |
parameter reset_value = 0; |
509,8 → 765,12
q <= d; |
|
endmodule |
`endif |
|
module vl_dff_ce_set ( d, ce, set, q, clk, rst); |
`ifdef DF_CE_SET |
`define MODULE dff_ce_set |
module `BASE`MODULE ( d, ce, set, q, clk, rst); |
`undef MODULE |
|
parameter width = 1; |
parameter reset_value = 0; |
530,9 → 790,13
q <= d; |
|
endmodule |
`endif |
|
module vl_spr ( sp, r, q, clk, rst); |
|
`ifdef SPR |
`define MODULE spr |
module `BASE`MODULE ( sp, r, q, clk, rst); |
`undef MODULE |
|
parameter width = 1; |
parameter reset_value = 0; |
|
550,9 → 814,13
q <= 1'b0; |
|
endmodule |
`endif |
|
module vl_srp ( s, rp, q, clk, rst); |
|
`ifdef SRP |
`define MODULE srp |
module `BASE`MODULE ( s, rp, q, clk, rst); |
`undef MODULE |
|
parameter width = 1; |
parameter reset_value = 0; |
|
570,9 → 838,11
q <= 1'b1; |
|
endmodule |
`endif |
|
`ifdef ALTERA |
|
`ifdef ALTERA |
`ifdef DFF_SR |
// megafunction wizard: %LPM_FF% |
// GENERATION: STANDARD |
// VERSION: WM1.0 |
611,7 → 881,10
// synopsys translate_off |
`timescale 1 ps / 1 ps |
// synopsys translate_on |
module vl_dff_sr ( |
`define MODULE dff_sr |
module `BASE`MODULE ( |
`undef MODULE |
|
aclr, |
aset, |
clock, |
691,13 → 964,15
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE |
// Retrieval info: LIB_FILE: lpm |
`endif |
|
|
`else |
|
`ifdef DFF_SR |
`define MODULE dff_sr |
module `BASE`MODULE ( aclr, aset, clock, data, q); |
`undef MODULE |
|
module vl_dff_sr ( aclr, aset, clock, data, q); |
|
input aclr; |
input aset; |
input clock; |
713,6 → 988,7
q <= data; |
|
endmodule |
`endif |
|
`endif |
|
719,14 → 995,24
// LATCH |
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1 |
`ifdef ALTERA |
module vl_latch ( d, le, q, clk); |
|
`ifdef LATCH |
`define MODULE latch |
module `BASE`MODULE ( d, le, q, clk); |
`undef MODULE |
input d, le; |
output q; |
input clk; |
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q)); |
endmodule |
`endif |
|
`else |
module latch ( d, le, q, clk); |
|
`ifdef LATCH |
`define MODULE latch |
module `BASE`MODULE ( d, le, q, clk); |
`undef MODULE |
input d, le; |
output q; |
input clk;/* |
738,7 → 1024,13
endmodule |
`endif |
|
module vl_shreg ( d, q, clk, rst); |
`endif |
|
`ifdef SHREG |
`define MODULE shreg |
module `BASE`MODULE ( d, q, clk, rst); |
`undef MODULE |
|
parameter depth = 10; |
input d; |
output q; |
753,8 → 1045,12
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
`endif |
|
module vl_shreg_ce ( d, ce, q, clk, rst); |
`ifdef SHREG_CE |
`define MODULE shreg_ce |
module `BASE`MODULE ( d, ce, q, clk, rst); |
`undef MODULE |
parameter depth = 10; |
input d, ce; |
output q; |
770,8 → 1066,12
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
`endif |
|
module vl_delay ( d, q, clk, rst); |
`ifdef DELAY |
`define MODULE delay |
module `BASE`MODULE ( d, q, clk, rst); |
`undef MODULE |
parameter depth = 10; |
input d; |
output q; |
786,8 → 1086,12
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
`endif |
|
`ifdef DELAY_EMPTYFLAG |
`define MODULE delay_emptyflag |
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst); |
`undef MODULE |
parameter depth = 10; |
input d; |
output q, emptyflag; |
803,6 → 1107,7
assign q = dffs[depth]; |
assign emptyflag = !(|dffs); |
endmodule |
`endif |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Logic functions //// |
844,7 → 1149,10
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
module vl_mux_andor ( a, sel, dout); |
`ifdef MUX_ANDOR |
`define MODULE mux_andor |
module `BASE`MODULE ( a, sel, dout); |
`undef MODULE |
|
parameter width = 32; |
parameter nr_of_ports = 4; |
864,8 → 1172,12
end |
|
endmodule |
`endif |
|
module vl_mux2_andor ( a1, a0, sel, dout); |
`ifdef MUX2_ANDOR |
`define MODULE mux2_andor |
module `BASE`MODULE ( a1, a0, sel, dout); |
`undef MODULE |
|
parameter width = 32; |
localparam nr_of_ports = 2; |
873,13 → 1185,19
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
vl_mux_andor |
`define MODULE mux_andor |
`BASE`MODULE |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a1,a0}), .sel(sel), .dout(dout)); |
|
`undef MODULE |
|
endmodule |
`endif |
|
module vl_mux3_andor ( a2, a1, a0, sel, dout); |
`ifdef MUX3_ANDOR |
`define MODULE mux3_andor |
module `BASE`MODULE ( a2, a1, a0, sel, dout); |
`undef MODULE |
|
parameter width = 32; |
localparam nr_of_ports = 3; |
887,13 → 1205,18
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
vl_mux_andor |
`define MODULE mux_andor |
`BASE`MODULE |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout)); |
|
`undef MODULE |
endmodule |
`endif |
|
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout); |
`ifdef MUX4_ANDOR |
`define MODULE mux4_andor |
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout); |
`undef MODULE |
|
parameter width = 32; |
localparam nr_of_ports = 4; |
901,13 → 1224,19
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
vl_mux_andor |
`define MODULE mux_andor |
`BASE`MODULE |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
`undef MODULE |
|
endmodule |
`endif |
|
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout); |
`ifdef MUX5_ANDOR |
`define MODULE mux5_andor |
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout); |
`undef MODULE |
|
parameter width = 32; |
localparam nr_of_ports = 5; |
915,13 → 1244,19
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
vl_mux_andor |
`define MODULE mux_andor |
`BASE`MODULE |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
`undef MODULE |
|
endmodule |
`endif |
|
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout); |
`ifdef MUX6_ANDOR |
`define MODULE mux6_andor |
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout); |
`undef MODULE |
|
parameter width = 32; |
localparam nr_of_ports = 6; |
929,11 → 1264,15
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
vl_mux_andor |
`define MODULE mux_andor |
`BASE`MODULE |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
`undef MODULE |
|
endmodule |
`endif |
`ifdef CNT_BIN |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
977,8 → 1316,12
////////////////////////////////////////////////////////////////////// |
|
// binary counter |
module vl_cnt_bin ( q, rst, clk); |
|
`define MODULE cnt_bin |
module `BASE`MODULE ( |
`undef MODULE |
q, rst, clk); |
|
parameter length = 4; |
output [length:1] q; |
input rst; |
1002,6 → 1345,8
assign q = qi; |
|
endmodule |
`endif |
`ifdef CNT_BIN_CLEAR |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
1045,8 → 1390,12
////////////////////////////////////////////////////////////////////// |
|
// binary counter |
module vl_cnt_bin_clear ( clear, q, rst, clk); |
|
`define MODULE cnt_bin_clear |
module `BASE`MODULE ( |
`undef MODULE |
clear, q, rst, clk); |
|
parameter length = 4; |
input clear; |
output [length:1] q; |
1071,6 → 1420,8
assign q = qi; |
|
endmodule |
`endif |
`ifdef CNT_BIN_CE |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
1114,8 → 1465,12
////////////////////////////////////////////////////////////////////// |
|
// binary counter |
module vl_cnt_bin_ce ( cke, q, rst, clk); |
|
`define MODULE cnt_bin_ce |
module `BASE`MODULE ( |
`undef MODULE |
cke, q, rst, clk); |
|
parameter length = 4; |
input cke; |
output [length:1] q; |
1141,6 → 1496,8
assign q = qi; |
|
endmodule |
`endif |
`ifdef CNT_BIN_CE_CLEAR |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
1184,8 → 1541,12
////////////////////////////////////////////////////////////////////// |
|
// binary counter |
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk); |
|
`define MODULE cnt_bin_ce_clear |
module `BASE`MODULE ( |
`undef MODULE |
clear, cke, q, rst, clk); |
|
parameter length = 4; |
input clear; |
input cke; |
1212,6 → 1573,8
assign q = qi; |
|
endmodule |
`endif |
`ifdef CNT_BIN_CE_CLEAR_L1_L2 |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
1255,8 → 1618,12
////////////////////////////////////////////////////////////////////// |
|
// binary counter |
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk); |
|
`define MODULE cnt_bin_ce_clear_l1_l2 |
module `BASE`MODULE ( |
`undef MODULE |
clear, cke, q, level1, level2, rst, clk); |
|
parameter length = 4; |
input clear; |
input cke; |
1312,6 → 1679,8
else if (qi == level2_value & rew) |
level2 <= 1'b0; |
endmodule |
`endif |
`ifdef CNT_BIN_CE_CLEAR_SET_REW |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
1355,8 → 1724,12
////////////////////////////////////////////////////////////////////// |
|
// binary counter |
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk); |
|
`define MODULE cnt_bin_ce_clear_set_rew |
module `BASE`MODULE ( |
`undef MODULE |
clear, set, cke, rew, q, rst, clk); |
|
parameter length = 4; |
input clear; |
input set; |
1387,6 → 1760,8
assign q = qi; |
|
endmodule |
`endif |
`ifdef CNT_BIN_CE_REW_L1 |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
1430,8 → 1805,12
////////////////////////////////////////////////////////////////////// |
|
// binary counter |
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk); |
|
`define MODULE cnt_bin_ce_rew_l1 |
module `BASE`MODULE ( |
`undef MODULE |
cke, rew, level1, rst, clk); |
|
parameter length = 4; |
input cke; |
input rew; |
1473,6 → 1852,8
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
endmodule |
`endif |
`ifdef CNT_BIN_CE_REW_ZQ_L1 |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
1516,8 → 1897,12
////////////////////////////////////////////////////////////////////// |
|
// binary counter |
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk); |
|
`define MODULE cnt_bin_ce_rew_zq_l1 |
module `BASE`MODULE ( |
`undef MODULE |
cke, rew, zq, level1, rst, clk); |
|
parameter length = 4; |
input cke; |
input rew; |
1567,6 → 1952,8
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
endmodule |
`endif |
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1 |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
1610,8 → 1997,12
////////////////////////////////////////////////////////////////////// |
|
// binary counter |
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk); |
|
`define MODULE cnt_bin_ce_rew_q_zq_l1 |
module `BASE`MODULE ( |
`undef MODULE |
cke, rew, q, zq, level1, rst, clk); |
|
parameter length = 4; |
input cke; |
input rew; |
1663,6 → 2054,8
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
endmodule |
`endif |
`ifdef CNT_LFSR_ZQ |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
1706,8 → 2099,12
////////////////////////////////////////////////////////////////////// |
|
// LFSR counter |
module vl_cnt_lfsr_zq ( zq, rst, clk); |
|
`define MODULE cnt_lfsr_zq |
module `BASE`MODULE ( |
`undef MODULE |
zq, rst, clk); |
|
parameter length = 4; |
output reg zq; |
input rst; |
1782,6 → 2179,8
else |
zq <= q_next == {length{1'b0}}; |
endmodule |
`endif |
`ifdef CNT_LFSR_CE_ZQ |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
1825,8 → 2224,12
////////////////////////////////////////////////////////////////////// |
|
// LFSR counter |
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk); |
|
`define MODULE cnt_lfsr_ce_zq |
module `BASE`MODULE ( |
`undef MODULE |
cke, zq, rst, clk); |
|
parameter length = 4; |
input cke; |
output reg zq; |
1904,6 → 2307,8
if (cke) |
zq <= q_next == {length{1'b0}}; |
endmodule |
`endif |
`ifdef CNT_LFSR_CE_Q |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
1947,8 → 2352,12
////////////////////////////////////////////////////////////////////// |
|
// LFSR counter |
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk); |
|
`define MODULE cnt_lfsr_ce_q |
module `BASE`MODULE ( |
`undef MODULE |
cke, q, rst, clk); |
|
parameter length = 4; |
input cke; |
output [length:1] q; |
2020,6 → 2429,8
assign q = qi; |
|
endmodule |
`endif |
`ifdef CNT_LFSR_CE_CLEAR_Q |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
2063,8 → 2474,12
////////////////////////////////////////////////////////////////////// |
|
// LFSR counter |
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk); |
|
`define MODULE cnt_lfsr_ce_clear_q |
module `BASE`MODULE ( |
`undef MODULE |
clear, cke, q, rst, clk); |
|
parameter length = 4; |
input clear; |
input cke; |
2137,6 → 2552,8
assign q = qi; |
|
endmodule |
`endif |
`ifdef CNT_LFSR_CE_Q_ZQ |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
2180,8 → 2597,12
////////////////////////////////////////////////////////////////////// |
|
// LFSR counter |
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk); |
|
`define MODULE cnt_lfsr_ce_q_zq |
module `BASE`MODULE ( |
`undef MODULE |
cke, q, zq, rst, clk); |
|
parameter length = 4; |
input cke; |
output [length:1] q; |
2261,6 → 2682,8
if (cke) |
zq <= q_next == {length{1'b0}}; |
endmodule |
`endif |
`ifdef CNT_LFSR_CE_REW_L1 |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
2304,8 → 2727,12
////////////////////////////////////////////////////////////////////// |
|
// LFSR counter |
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk); |
|
`define MODULE cnt_lfsr_ce_rew_l1 |
module `BASE`MODULE ( |
`undef MODULE |
cke, rew, level1, rst, clk); |
|
parameter length = 4; |
input cke; |
input rew; |
2439,6 → 2866,8
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
endmodule |
`endif |
`ifdef CNT_GRAY |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
2482,8 → 2911,12
////////////////////////////////////////////////////////////////////// |
|
// GRAY counter |
module vl_cnt_gray ( q, rst, clk); |
|
`define MODULE cnt_gray |
module `BASE`MODULE ( |
`undef MODULE |
q, rst, clk); |
|
parameter length = 4; |
output reg [length:1] q; |
input rst; |
2511,6 → 2944,8
q <= (q_next>>1) ^ q_next; |
|
endmodule |
`endif |
`ifdef CNT_GRAY_CE |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
2554,8 → 2989,12
////////////////////////////////////////////////////////////////////// |
|
// GRAY counter |
module vl_cnt_gray_ce ( cke, q, rst, clk); |
|
`define MODULE cnt_gray_ce |
module `BASE`MODULE ( |
`undef MODULE |
cke, q, rst, clk); |
|
parameter length = 4; |
input cke; |
output reg [length:1] q; |
2586,6 → 3025,8
q <= (q_next>>1) ^ q_next; |
|
endmodule |
`endif |
`ifdef CNT_GRAY_CE_BIN |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
2629,8 → 3070,12
////////////////////////////////////////////////////////////////////// |
|
// GRAY counter |
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk); |
|
`define MODULE cnt_gray_ce_bin |
module `BASE`MODULE ( |
`undef MODULE |
cke, q, q_bin, rst, clk); |
|
parameter length = 4; |
input cke; |
output reg [length:1] q; |
2664,6 → 3109,7
assign q_bin = qi; |
|
endmodule |
`endif |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile library, counters //// |
2706,7 → 3152,10
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module vl_cnt_shreg_wrap ( q, rst, clk); |
`ifdef CNT_SHREG_WRAP |
`define MODULE cnt_shreg_wrap |
module `BASE`MODULE ( q, rst, clk); |
`undef MODULE |
|
parameter length = 4; |
output reg [0:length-1] q; |
2720,8 → 3169,12
q <= {q[length-1],q[0:length-2]}; |
|
endmodule |
`endif |
|
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk); |
`ifdef CNT_SHREG_CE_WRAP |
`define MODULE cnt_shreg_ce_wrap |
module `BASE`MODULE ( cke, q, rst, clk); |
`undef MODULE |
|
parameter length = 4; |
input cke; |
2737,8 → 3190,12
q <= {q[length-1],q[0:length-2]}; |
|
endmodule |
`endif |
|
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk); |
`ifdef CNT_SHREG_CE_CLEAR |
`define MODULE cnt_shreg_ce_clear |
module `BASE`MODULE ( cke, clear, q, rst, clk); |
`undef MODULE |
|
parameter length = 4; |
input cke, clear; |
2757,8 → 3214,12
q <= q >> 1; |
|
endmodule |
`endif |
|
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk); |
`ifdef CNT_SHREG_CE_CLEAR_WRAP |
`define MODULE cnt_shreg_ce_clear_wrap |
module `BASE`MODULE ( cke, clear, q, rst, clk); |
`undef MODULE |
|
parameter length = 4; |
input cke, clear; |
2777,6 → 3238,7
q <= {q[length-1],q[0:length-2]}; |
|
endmodule |
`endif |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile library, memories //// |
2819,9 → 3281,12
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`ifdef ROM_INIT |
/// ROM |
`define MODULE rom_init |
module `BASE`MODULE ( adr, q, clk); |
`undef MODULE |
|
module vl_rom_init ( adr, q, clk); |
parameter data_width = 32; |
parameter addr_width = 8; |
input [(addr_width-1):0] adr; |
2838,6 → 3303,7
q <= rom[adr]; |
|
endmodule |
`endif |
|
/* |
module vl_rom ( adr, q, clk); |
2872,9 → 3338,13
|
endmodule |
*/ |
|
`ifdef RAM |
`define MODULE ram |
// Single port RAM |
module `BASE`MODULE ( d, adr, we, q, clk); |
`undef MODULE |
|
module vl_ram ( d, adr, we, q, clk); |
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d; |
2901,8 → 3371,13
end |
|
endmodule |
`endif |
|
module vl_ram_be ( d, adr, be, we, q, clk); |
`ifdef RAM_BE |
`define MODULE ram_be |
module `BASE`MODULE ( d, adr, be, we, q, clk); |
`undef MODULE |
|
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d; |
2936,8 → 3411,8
q <= ram[adr]; |
|
endmodule |
`endif |
|
|
// Dual port RAM |
|
// ACTEL FPGA should not use logic to handle rw collision |
2947,7 → 3422,10
`define SYN |
`endif |
|
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
`ifdef DPRAM_1R1W |
`define MODULE dpram_1r1w |
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
`undef MODULE |
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d_a; |
2975,9 → 3453,15
always @ (posedge clk_b) |
adr_b_reg <= adr_b; |
assign q_b = ram[adr_b_reg]; |
|
endmodule |
`endif |
|
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
`ifdef DPRAM_2R1W |
`define MODULE dpram_2r1w |
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
`undef MODULE |
|
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d_a; |
3009,8 → 3493,13
always @ (posedge clk_b) |
q_b <= ram[adr_b]; |
endmodule |
`endif |
|
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b ); |
`ifdef DPRAM_2R2W |
`define MODULE dpram_2r2w |
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b ); |
`undef MODULE |
|
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d_a; |
3048,11 → 3537,15
ram[adr_b] <= d_b; |
end |
endmodule |
`endif |
|
// Content addresable memory, CAM |
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC |
// FIFO |
module vl_fifo_1r1w_fill_level_sync ( |
`define MODULE fifo_1r1w_fill_level_sync |
module `BASE`MODULE ( |
`undef MODULE |
d, wr, fifo_full, |
q, rd, fifo_empty, |
fill_level, |
3076,28 → 3569,36
|
wire [addr_width:1] wadr, radr; |
|
vl_cnt_bin_ce |
`define MODULE cnt_bin_ce |
`BASE`MODULE |
# ( .length(addr_width)) |
fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk)); |
|
vl_cnt_bin_ce |
`BASE`MODULE |
# (.length(addr_width)) |
fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk)); |
`undef MODULE |
|
vl_dpram_1r1w |
`define MODULE dpram_1r1w |
`BASE`MODULE |
# (.data_width(data_width), .addr_width(addr_width)) |
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk)); |
`undef MODULE |
|
vl_cnt_bin_ce_rew_q_zq_l1 |
`define MODULE cnt_bin_ce_rew_q_zq_l1 |
`BASE`MODULE |
# (.length(addr_width+1), .level1_value(1<<addr_width)) |
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk)); |
|
`undef MODULE |
endmodule |
`endif |
|
`ifdef FIFO_2R2W_SYNC_SIMPLEX |
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource |
// RAM is supposed to be larger than the two FIFOs |
// LFSR counters used adr pointers |
module vl_fifo_2r2w_sync_simplex ( |
`define MODULE fifo_2r2w_sync_simplex |
module `BASE`MODULE ( |
`undef MODULE |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
3140,42 → 3641,52
// dpram |
wire [addr_width:0] a_dpram_adr, b_dpram_adr; |
|
vl_cnt_lfsr_ce |
`define MODULE cnt_lfsr_ce |
`BASE`MODULE |
# ( .length(addr_width)) |
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk)); |
|
vl_cnt_lfsr_ce |
`BASE`MODULE |
# (.length(addr_width)) |
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk)); |
|
vl_cnt_lfsr_ce |
`BASE`MODULE |
# ( .length(addr_width)) |
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk)); |
|
vl_cnt_lfsr_ce |
`BASE`MODULE |
# (.length(addr_width)) |
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk)); |
`undef MODULE |
|
// mux read or write adr to DPRAM |
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr}; |
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr}; |
|
vl_dpram_2r2w |
`define MODULE dpram_2r2w |
`BASE`MODULE |
# (.data_width(data_width), .addr_width(addr_width+1)) |
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk), |
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk)); |
|
vl_cnt_bin_ce_rew_zq_l1 |
`undef MODULE |
|
`define MODULE cnt_bin_ce_rew_zq_l1 |
`BASE`MODULE |
# (.length(addr_width), .level1_value(fifo_full_level)) |
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk)); |
|
vl_cnt_bin_ce_rew_zq_l1 |
`BASE`MODULE |
# (.length(addr_width), .level1_value(fifo_full_level)) |
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk)); |
`undef MODULE |
|
endmodule |
`endif |
|
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst ); |
`ifdef FIFO_CMP_ASYNC |
`define MODULE fifo_cmp_async |
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst ); |
`undef MODULE |
|
parameter addr_width = 4; |
parameter N = addr_width-1; |
3228,8 → 3739,9
default : direction_clr <= 1'b0; |
endcase |
|
`define MODULE dff_sr |
`ifndef GENERATE_DIRECTION_AS_LATCH |
vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction)); |
`BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction)); |
`endif |
|
`ifdef GENERATE_DIRECTION_AS_LATCH |
3243,8 → 3755,9
assign async_empty = (wptr == rptr) && (direction==going_empty); |
assign async_full = (wptr == rptr) && (direction==going_full); |
|
vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2)); |
vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full)); |
`BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2)); |
`BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full)); |
`undef MODULE |
|
/* |
always @ (posedge wclk or posedge rst or posedge async_full) |
3260,12 → 3773,17
{fifo_empty, fifo_empty2} <= 2'b11; |
else |
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */ |
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty)); |
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty)); |
|
`define MODULE dff |
`BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty)); |
`BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty)); |
`undef MODULE |
endmodule // async_compb |
`endif |
|
module vl_fifo_1r1w_async ( |
`ifdef FIFO_1R1W_ASYNC |
`define MODULE fifo_1r1w_async |
module `BASE`MODULE ( |
`undef MODULE |
d, wr, fifo_full, wr_clk, wr_rst, |
q, rd, fifo_empty, rd_clk, rd_rst |
); |
3288,25 → 3806,35
|
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin; |
|
vl_cnt_gray_ce_bin |
`define MODULE cnt_gray_ce_bin |
`BASE`MODULE |
# ( .length(addr_width)) |
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk)); |
|
vl_cnt_gray_ce_bin |
`BASE`MODULE |
# (.length(addr_width)) |
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk)); |
`undef MODULE |
|
vl_dpram_1r1w |
`define MODULE dpram_1r1w |
`BASE`MODULE |
# (.data_width(data_width), .addr_width(addr_width)) |
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk)); |
`undef MODULE |
|
vl_fifo_cmp_async |
`define MODULE fifo_cmp_async |
`BASE`MODULE |
# (.addr_width(addr_width)) |
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) ); |
`undef MODULE |
|
endmodule |
`endif |
|
module vl_fifo_2r2w_async ( |
`ifdef FIFO_2R2W_ASYNC |
`define MODULE fifo_2r2w_async |
module `BASE`MODULE ( |
`undef MODULE |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
3340,21 → 3868,27
input b_clk; |
input b_rst; |
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width)) |
`define MODULE fifo_1r1w_async |
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width)) |
vl_fifo_1r1w_async_a ( |
.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst), |
.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst) |
); |
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width)) |
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width)) |
vl_fifo_1r1w_async_b ( |
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst), |
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst) |
); |
|
`undef MODULE |
|
endmodule |
`endif |
|
module vl_fifo_2r2w_async_simplex ( |
`ifdef FIFO_2R2W_ASYNC_SIMPLEX |
`define MODULE fifo_2r2w_async_simplex |
module `BASE`MODULE ( |
`undef MODULE |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
3394,40 → 3928,47
// dpram |
wire [addr_width:0] a_dpram_adr, b_dpram_adr; |
|
vl_cnt_gray_ce_bin |
`define MODULE cnt_gray_ce_bin |
`BASE`MODULE |
# ( .length(addr_width)) |
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk)); |
|
vl_cnt_gray_ce_bin |
`BASE`MODULE |
# (.length(addr_width)) |
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk)); |
|
vl_cnt_gray_ce_bin |
`BASE`MODULE |
# ( .length(addr_width)) |
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk)); |
|
vl_cnt_gray_ce_bin |
`BASE`MODULE |
# (.length(addr_width)) |
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk)); |
`undef MODULE |
|
// mux read or write adr to DPRAM |
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin}; |
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin}; |
|
vl_dpram_2r2w |
`define MODULE dpram_2r2w |
`BASE`MODULE |
# (.data_width(data_width), .addr_width(addr_width+1)) |
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk), |
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk)); |
`undef MODULE |
|
vl_fifo_cmp_async |
`define MODULE fifo_cmp_async |
`BASE`MODULE |
# (.addr_width(addr_width)) |
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) ); |
|
vl_fifo_cmp_async |
`BASE`MODULE |
# (.addr_width(addr_width)) |
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) ); |
`undef MODULE |
|
endmodule |
`endif |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile library, wishbone stuff //// |
3470,9 → 4011,12
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`ifdef WB3WB3_BRIDGE |
// async wb3 - wb3 bridge |
`timescale 1ns/1ns |
module vl_wb3wb3_bridge ( |
`define MODULE wb3wb3_bridge |
module `BASE`MODULE ( |
`undef MODULE |
// wishbone slave side |
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst, |
// wishbone master side |
3549,7 → 4093,9
else if (wbs_eoc_alert & (a_rd | a_wr)) |
wbs_eoc <= 1'b1; |
|
vl_cnt_shreg_ce_clear # ( .length(16)) |
`define MODULE cnt_shreg_ce_clear |
`BASE`MODULE # ( .length(16)) |
`undef MODULE |
cnt0 ( |
.cke(wbs_ack_o), |
.clear(wbs_eoc), |
3635,12 → 4181,18
1'b0; |
assign b_rd = b_rd_adr | b_rd_data; |
|
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst)); |
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst)); |
`define MODULE dff |
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst)); |
`undef MODULE |
`define MODULE dff_ce |
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst)); |
`undef MODULE |
|
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp; |
|
`define MODULE cnt_shreg_ce_clear |
vl_cnt_shreg_ce_clear # ( .length(16)) |
`undef MODULE |
cnt1 ( |
.cke(wbm_ack_i), |
.clear(wbm_eoc), |
3662,7 → 4214,9
end |
|
//async_fifo_dw_simplex_top |
vl_fifo_2r2w_async_simplex |
`define MODULE fifo_2r2w_async_simplex |
`BASE`MODULE |
`undef MODULE |
# ( .data_width(36), .addr_width(addr_width)) |
fifo ( |
// a side |
3686,8 → 4240,15
); |
|
endmodule |
`undef WE |
`undef BTE |
`undef CTI |
`endif |
|
`ifdef WB3_ARBITER_TYPE1 |
`define MODULE wb3_arbiter_type1 |
module vl_wb3_arbiter_type1 ( |
`undef MODULE |
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, |
wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i, |
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, |
3774,13 → 4335,15
|
assign sel = select | state; |
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i)); |
`define MODULE mux_andor |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i)); |
`undef MODULE |
assign wbs_cyc_i = |sel; |
|
assign wbm_dat_i = {nr_of_ports{wbs_dat_o}}; |
3789,9 → 4352,13
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel; |
|
endmodule |
`endif |
|
`ifdef WB_BOOT_ROM |
// WB ROM |
module vl_wb_boot_rom ( |
`define MODULE wb_boot_rom |
module `BASE`MODULE ( |
`undef MODULE |
wb_adr_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst); |
|
3852,8 → 4419,12
assign wb_ack_o = wb_ack; |
|
endmodule |
`endif |
|
module vl_wb_dpram ( |
`ifdef WB_DPRAM |
`define MODULE wb_dpram |
module `BASE`MODULE ( |
`undef MODULE |
// wishbone slave side a |
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, |
wbsa_clk, wbsa_rst, |
3883,7 → 4454,9
|
wire wbsa_dat_tmp, wbsb_dat_tmp; |
|
vl_dpram_2r2w # ( |
`define MODULE dpram_2r2w |
`BASE`MODULE # ( |
`undef MODULE |
.data_width(data_width), .addr_width(addr_width) ) |
dpram0( |
.d_a(wbsa_dat_i), |
3911,10 → 4484,13
assign wbsb_dat_o = wbsb_dat_tmp; |
endgenerate |
|
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst)); |
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst)); |
`define MODULE spr |
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst)); |
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst)); |
`undef MODULE |
|
endmodule |
`endif |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Arithmetic functions //// |
3957,8 → 4533,11
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`ifdef MULTS |
// signed multiplication |
module vl_mults (a,b,p); |
`define MODULE mults |
module `BASE`MODULE (a,b,p); |
`undef MODULE |
parameter operand_a_width = 18; |
parameter operand_b_width = 18; |
parameter result_hi = 35; |
3976,8 → 4555,11
assign p = result[result_hi:result_lo]; |
|
endmodule |
|
module vl_mults18x18 (a,b,p); |
`endif |
`ifdef MULTS18X18 |
`define MODULE mults18x18 |
module `BASE`MODULE (a,b,p); |
`undef MODULE |
input [17:0] a,b; |
output [35:0] p; |
vl_mult |
3984,9 → 4566,13
# (.operand_a_width(18), .operand_b_width(18)) |
mult0 (.a(a), .b(b), .p(p)); |
endmodule |
`endif |
|
`ifdef MULT |
`define MODULE mult |
// unsigned multiplication |
module vl_mult (a,b,p); |
module `BASE`MODULE (a,b,p); |
`undef MODULE |
parameter operand_a_width = 18; |
parameter operand_b_width = 18; |
parameter result_hi = 35; |
4001,7 → 4587,10
assign p = result[result_hi:result_lo]; |
|
endmodule |
`endif |
|
`ifdef SHIFT_UNIT_32 |
`define MODULE shift_unit_32 |
// shift unit |
// supporting the following shift functions |
// SLL |
4008,7 → 4597,8
// SRL |
// SRA |
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) |
module vl_shift_unit_32( din, s, dout, opcode); |
module `BASE`MODULE( din, s, dout, opcode); |
`undef MODULE |
input [31:0] din; // data in operand |
input [4:0] s; // shift operand |
input [1:0] opcode; |
4049,11 → 4639,12
assign sign[2] = sign[3] & (&din[31:24]); |
assign sign[1] = sign[2] & (&din[23:16]); |
assign sign[0] = sign[1] & (&din[15:8]); |
vl_mults `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3])); |
vl_mults `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2])); |
vl_mults `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1])); |
vl_mults `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0])); |
|
`define MODULE mults |
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3])); |
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2])); |
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1])); |
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0])); |
`undef MODULE |
// second stage is multiplexer based |
// shift on byte level |
|
4089,7 → 4680,9
tmp[3]; |
|
endmodule |
`endif |
|
`ifdef LOGIC_UNIT |
// logic unit |
// supporting the following logic functions |
// a and b |
4096,7 → 4689,9
// a or b |
// a xor b |
// not b |
module vl_logic_unit( a, b, result, opcode); |
`define MODULE logic_unit |
module `BASE`MODULE( a, b, result, opcode); |
`undef MODULE |
parameter width = 32; |
parameter opcode_and = 2'b00; |
parameter opcode_or = 2'b01; |
4126,3 → 4721,4
assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) | |
(~a[width-1] & ~b[width-1] & result[width-1]); |
endmodule |
`endif |
/verilog/versatile_counter_generator.php
0,0 → 1,318
#!/usr/bin/php |
<?php |
|
function __autoload($className) { |
include "$className.class.php"; |
} |
|
if(!isset($argv[1])) { |
?> |
|
Usage: <?php echo basename($argv[0]); ?> <fileName> |
|
<?php |
die(1); |
} |
|
$csv = new CSV($argv[1]); |
|
$counter = $csv->getRow(); |
$csv->parseHeader(); |
$inputs = $csv->getRow(); |
$csv->parseHeader(); |
$outputs = $csv->getRow(); |
$csv->parseHeader(); |
$wrap = $csv->getRow(); |
$csv->parseHeader(); |
$parameters = $csv->getRow(); |
|
$length = $parameters['length']; |
|
# copyright |
echo "`ifdef " . strtoupper($counter['Name']) . PHP_EOL; |
echo "//////////////////////////////////////////////////////////////////////" . PHP_EOL; |
echo "//// ////" . PHP_EOL; |
echo "//// Versatile counter ////" . PHP_EOL; |
echo "//// ////" . PHP_EOL; |
echo "//// Description ////" . PHP_EOL; |
echo "//// Versatile counter, a reconfigurable binary, gray or LFSR ////" . PHP_EOL; |
echo "//// counter ////" . PHP_EOL; |
echo "//// ////" . PHP_EOL; |
echo "//// To Do: ////" . PHP_EOL; |
echo "//// - add LFSR with more taps ////" . PHP_EOL; |
echo "//// ////" . PHP_EOL; |
echo "//// Author(s): ////" . PHP_EOL; |
echo "//// - Michael Unneback, unneback@opencores.org ////" . PHP_EOL; |
echo "//// ORSoC AB ////" . PHP_EOL; |
echo "//// ////" . PHP_EOL; |
echo "//////////////////////////////////////////////////////////////////////" . PHP_EOL; |
echo "//// ////" . PHP_EOL; |
echo "//// Copyright (C) 2009 Authors and OPENCORES.ORG ////" . PHP_EOL; |
echo "//// ////" . PHP_EOL; |
echo "//// This source file may be used and distributed without ////" . PHP_EOL; |
echo "//// restriction provided that this copyright statement is not ////" . PHP_EOL; |
echo "//// removed from the file and that any derivative work contains ////" . PHP_EOL; |
echo "//// the original copyright notice and the associated disclaimer. ////" . PHP_EOL; |
echo "//// ////" . PHP_EOL; |
echo "//// This source file is free software; you can redistribute it ////" . PHP_EOL; |
echo "//// and/or modify it under the terms of the GNU Lesser General ////" . PHP_EOL; |
echo "//// Public License as published by the Free Software Foundation; ////" . PHP_EOL; |
echo "//// either version 2.1 of the License, or (at your option) any ////" . PHP_EOL; |
echo "//// later version. ////" . PHP_EOL; |
echo "//// ////" . PHP_EOL; |
echo "//// This source is distributed in the hope that it will be ////" . PHP_EOL; |
echo "//// useful, but WITHOUT ANY WARRANTY; without even the implied ////" . PHP_EOL; |
echo "//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////" . PHP_EOL; |
echo "//// PURPOSE. See the GNU Lesser General Public License for more ////" . PHP_EOL; |
echo "//// details. ////" . PHP_EOL; |
echo "//// ////" . PHP_EOL; |
echo "//// You should have received a copy of the GNU Lesser General ////" . PHP_EOL; |
echo "//// Public License along with this source; if not, download it ////" . PHP_EOL; |
echo "//// from http://www.opencores.org/lgpl.shtml ////" . PHP_EOL; |
echo "//// ////" . PHP_EOL; |
echo "//////////////////////////////////////////////////////////////////////" . PHP_EOL; |
|
echo PHP_EOL . "// " . $counter['type'] . " counter" . PHP_EOL; |
echo PHP_EOL . "`define MODULE " . $counter['Name'] . PHP_EOL; |
echo "module " . "`BASE`MODULE" . " (" . PHP_EOL; |
echo "`undef MODULE" . PHP_EOL; |
|
if ($inputs['clear']=="1") { echo " clear,"; } |
if ($inputs['set']=="1") { echo " set,"; } |
if ($inputs['cke']=="1") { echo " cke,"; } |
if ($inputs['rew']=="1") { echo " rew,"; } |
|
if ($outputs['q']=="1") { echo " q,"; } |
if ($outputs['q_bin']=="1" and $counter['type']=="GRAY") { echo " q_bin,"; } |
if ($outputs['z']=="1") { echo " z,"; } |
if ($outputs['zq']=="1") { echo " zq,"; } |
if ($outputs['level1']=="1") { echo " level1,"; } |
if ($outputs['level2']=="1") { echo " level2,"; } |
|
echo " rst,"; |
echo " clk);" . PHP_EOL; |
echo PHP_EOL; |
|
echo " parameter length = " . $length . ";" . PHP_EOL; |
|
if ($inputs['clear']=="1") { echo " input " . "clear;" . PHP_EOL; } |
if ($inputs['set']=="1") { echo " input " . "set;" . PHP_EOL; } |
if ($inputs['cke']=="1") { echo " input " . "cke;" . PHP_EOL; } |
if ($inputs['rew']=="1") { echo " input " . "rew;" . PHP_EOL; } |
|
if ($counter['type']=="GRAY") { |
if ($outputs['q']=="1") { echo " output reg [length:1] q;" . PHP_EOL; } |
} else { |
if ($outputs['q']=="1") { echo " output [length:1] q;" . PHP_EOL; } |
} |
if ($outputs['q_bin']=="1" and $counter['type']=="GRAY") { echo " output [length:1] q_bin;" . PHP_EOL; } |
if ($outputs['z']=="1") { echo " output z;" . PHP_EOL; } |
if ($outputs['zq']=="1") { echo " output reg zq;" . PHP_EOL; } |
if ($outputs['level1']=="1") { echo " output reg level1;" . PHP_EOL; } |
if ($outputs['level2']=="1") { echo " output reg level2;" . PHP_EOL; } |
|
echo " input rst;" . PHP_EOL; |
echo " input clk;" . PHP_EOL; |
echo PHP_EOL; |
|
if ($parameters['clear_value']!="") { echo " parameter clear_value = " . $parameters['clear_value'] . ";" . PHP_EOL; } |
if ($parameters['set_value']!="") { echo " parameter set_value = " . $parameters['set_value'] . ";" . PHP_EOL; } |
if ($parameters['wrap_value']!="") { echo " parameter wrap_value = " . $parameters['wrap_value'] . ";" . PHP_EOL; } |
if ($parameters['level1']!="") { echo " parameter level1_value = " . $parameters['level1'] . ";" . PHP_EOL; } |
if ($parameters['level2']!="") { echo " parameter level2_value = " . $parameters['level2'] . ";" . PHP_EOL; } |
|
echo PHP_EOL; |
if ($outputs['level1']=="1" and $inputs['clear']=="0") { echo " wire clear;" . PHP_EOL . " assign clear = 1'b0;" . PHP_EOL; } |
if ($outputs['level1']=="1" and $inputs['rew']=="0") { echo " wire rew;" . PHP_EOL . " assign rew = 1'b0;" . PHP_EOL; } |
|
echo " reg [length:1] qi;" . PHP_EOL; |
if ($counter['type']=="LFSR") { echo " reg lfsr_fb";} |
if ($counter['type']=="LFSR" and $inputs['rew']==1) { echo ", lfsr_fb_rew;" . PHP_EOL; } else { if ($counter['type']=="LFSR") echo ";" . PHP_EOL; } |
if ($inputs['rew']==1) { echo " wire [length:1] q_next, q_next_fw, q_next_rew;" . PHP_EOL; } |
else { echo " wire [length:1] q_next;" . PHP_EOL; } |
if ($counter['type']=="LFSR" and $inputs['rew']==1) { |
echo " reg [32:1] polynom_rew;" . PHP_EOL; |
echo " integer j;" . PHP_EOL; |
} |
|
if ($counter['type']=="LFSR") { |
echo " reg [32:1] polynom;" . PHP_EOL; |
echo " integer i;" . PHP_EOL . PHP_EOL; |
echo " always @ (qi)" . PHP_EOL; |
echo " begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end"; |
echo PHP_EOL; |
} |
|
if ($inputs['rew']!=1) { echo " assign q_next = "; } else { echo " assign q_next_fw = "; } |
if ($inputs['clear']==1) { echo " clear ? {length{1'b0}} :";} |
if ($inputs['set']==1) { echo " set ? set_value :";} |
if ($wrap['wrap']==1) { echo "(qi == wrap_value) ? {length{1'b0}} :";} |
if ($counter['type']=="LFSR") { echo "{qi[length-1:1],lfsr_fb};"; } else { echo "qi + {{length-1{1'b0}},1'b1};"; } |
echo PHP_EOL; |
|
if ($inputs['rew']) { |
if ($counter['type']=="LFSR") { |
echo " always @ (qi)" . PHP_EOL; |
echo " begin |
case (length) |
2: polynom_rew = 32'b11; |
3: polynom_rew = 32'b110; |
4: polynom_rew = 32'b1100; |
5: polynom_rew = 32'b10100; |
6: polynom_rew = 32'b110000; |
7: polynom_rew = 32'b1100000; |
8: polynom_rew = 32'b10111000; |
9: polynom_rew = 32'b100010000; |
10: polynom_rew = 32'b1001000000; |
11: polynom_rew = 32'b10100000000; |
12: polynom_rew = 32'b100000101001; |
13: polynom_rew = 32'b1000000001100; |
14: polynom_rew = 32'b10000000010101; |
15: polynom_rew = 32'b110000000000000; |
16: polynom_rew = 32'b1101000000001000; |
17: polynom_rew = 32'b10010000000000000; |
18: polynom_rew = 32'b100000010000000000; |
19: polynom_rew = 32'b1000000000000100011; |
20: polynom_rew = 32'b10000010000000000000; |
21: polynom_rew = 32'b101000000000000000000; |
22: polynom_rew = 32'b1100000000000000000000; |
23: polynom_rew = 32'b10000100000000000000000; |
24: polynom_rew = 32'b111000010000000000000000; |
25: polynom_rew = 32'b1001000000000000000000000; |
26: polynom_rew = 32'b10000000000000000000100011; |
27: polynom_rew = 32'b100000000000000000000010011; |
28: polynom_rew = 32'b1100100000000000000000000000; |
29: polynom_rew = 32'b10100000000000000000000000000; |
30: polynom_rew = 32'b100000000000000000000000101001; |
31: polynom_rew = 32'b1001000000000000000000000000000; |
32: polynom_rew = 32'b10000000001000000000000000000011; |
default: polynom_rew = 32'b0; |
endcase |
// rotate left |
polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] }; |
lfsr_fb_rew = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom_rew[i]) |
lfsr_fb_rew = lfsr_fb_rew ~^ qi[i]; |
end |
end"; |
echo PHP_EOL; |
|
} |
echo " assign q_next_rew = "; |
if ($inputs['clear']==1) { echo " clear ? clear_value :";} |
if ($inputs['set']==1) { echo " set ? set_value :";} |
if ($wrap['wrap']==1) { echo "(qi == wrap_value) ? {length{1'b0}} :";} |
if ($counter['type']=="LFSR") { echo "{lfsr_fb_rew,qi[length:2]};"; } else { echo "qi - {{length-1{1'b0}},1'b1};"; } |
echo PHP_EOL; |
echo " assign q_next = rew ? q_next_rew : q_next_fw;" . PHP_EOL; |
} |
|
echo " |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else" . PHP_EOL; |
if ($inputs['cke']) { echo " if (cke)" . PHP_EOL;} |
echo " qi <= q_next;" . PHP_EOL; |
echo PHP_EOL; |
|
if ($outputs['q']) { |
if ($counter['type'] == "GRAY" or $counter['type'] == "gray") { |
echo " always @ (posedge clk or posedge rst) |
if (rst) |
q <= {length{1'b0}}; |
else" . PHP_EOL; |
if ($inputs['cke']) { echo " if (cke)" . PHP_EOL; } |
echo " q <= (q_next>>1) ^ q_next;" . PHP_EOL; |
if ($outputs['q_bin']) { echo PHP_EOL . " assign q_bin = qi;" . PHP_EOL; } |
} else { |
echo " assign q = qi;" . PHP_EOL; |
} |
} |
echo PHP_EOL; |
|
if ($outputs['z']) { echo " assign z = (q == {length{1'b0}});" . PHP_EOL; } |
|
if ($outputs['zq']) { |
echo " |
always @ (posedge clk or posedge rst) |
if (rst) |
zq <= 1'b1; |
else" . PHP_EOL; |
if ($inputs['cke']) { echo " if (cke)" . PHP_EOL; } |
echo " zq <= q_next == {length{1'b0}};" . PHP_EOL; |
} |
|
if ($outputs['level1']) { |
echo " |
always @ (posedge clk or posedge rst) |
if (rst) |
level1 <= 1'b0; |
else" . PHP_EOL; |
if ($inputs['cke']) { echo " if (cke)" . PHP_EOL; } |
echo " if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0;" . PHP_EOL; |
} |
|
if ($outputs['level2']) { |
echo " |
always @ (posedge clk or posedge rst) |
if (rst) |
level2 <= 1'b0; |
else" . PHP_EOL; |
if ($inputs['cke']) { echo " if (cke)" . PHP_EOL; } |
echo " if (clear) |
level2 <= 1'b0; |
else if (q_next == level2_value) |
level2 <= 1'b1; |
else if (qi == level2_value & rew) |
level2 <= 1'b0;" . PHP_EOL; |
} |
|
echo "endmodule" . PHP_EOL; |
echo "`endif" . PHP_EOL; |
verilog/versatile_counter_generator.php
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: verilog/cnt_lfsr_ce_q.csv
===================================================================
--- verilog/cnt_lfsr_ce_q.csv (revision 39)
+++ verilog/cnt_lfsr_ce_q.csv (revision 40)
@@ -1,5 +1,5 @@
Name,type,,,,
-vl_cnt_lfsr_ce_q,LFSR,,,,
+cnt_lfsr_ce_q,LFSR,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,0,,
Index: verilog/versatile_library_actel.v
===================================================================
--- verilog/versatile_library_actel.v (revision 39)
+++ verilog/versatile_library_actel.v (revision 40)
@@ -161,7 +161,7 @@
endgenerate // index==0
genvar i;
generate for (i=0;i=1; i=i-1) begin
- if (polynom[i])
- lfsr_fb = lfsr_fb ~^ qi[i];
- end
- end
- assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
- always @ (posedge clk or posedge rst)
- if (rst)
- qi <= {length{1'b0}};
- else
- qi <= q_next;
- always @ (posedge clk or posedge rst)
- if (rst)
- zq <= 1'b1;
- else
- zq <= q_next == {length{1'b0}};
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Versatile counter ////
-//// ////
-//// Description ////
-//// Versatile counter, a reconfigurable binary, gray or LFSR ////
-//// counter ////
-//// ////
-//// To Do: ////
-//// - add LFSR with more taps ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// ORSoC AB ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-// LFSR counter
-module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
- parameter length = 4;
- input cke;
- output reg zq;
- input rst;
- input clk;
- parameter clear_value = 0;
- parameter set_value = 1;
- parameter wrap_value = 8;
- parameter level1_value = 15;
- reg [length:1] qi;
- reg lfsr_fb;
- wire [length:1] q_next;
- reg [32:1] polynom;
- integer i;
- always @ (qi)
- begin
- case (length)
- 2: polynom = 32'b11; // 0x3
- 3: polynom = 32'b110; // 0x6
- 4: polynom = 32'b1100; // 0xC
- 5: polynom = 32'b10100; // 0x14
- 6: polynom = 32'b110000; // 0x30
- 7: polynom = 32'b1100000; // 0x60
- 8: polynom = 32'b10111000; // 0xb8
- 9: polynom = 32'b100010000; // 0x110
- 10: polynom = 32'b1001000000; // 0x240
- 11: polynom = 32'b10100000000; // 0x500
- 12: polynom = 32'b100000101001; // 0x829
- 13: polynom = 32'b1000000001100; // 0x100C
- 14: polynom = 32'b10000000010101; // 0x2015
- 15: polynom = 32'b110000000000000; // 0x6000
- 16: polynom = 32'b1101000000001000; // 0xD008
- 17: polynom = 32'b10010000000000000; // 0x12000
- 18: polynom = 32'b100000010000000000; // 0x20400
- 19: polynom = 32'b1000000000000100011; // 0x40023
- 20: polynom = 32'b10010000000000000000; // 0x90000
- 21: polynom = 32'b101000000000000000000; // 0x140000
- 22: polynom = 32'b1100000000000000000000; // 0x300000
- 23: polynom = 32'b10000100000000000000000; // 0x420000
- 24: polynom = 32'b111000010000000000000000; // 0xE10000
- 25: polynom = 32'b1001000000000000000000000; // 0x1200000
- 26: polynom = 32'b10000000000000000000100011; // 0x2000023
- 27: polynom = 32'b100000000000000000000010011; // 0x4000013
- 28: polynom = 32'b1100100000000000000000000000; // 0xC800000
- 29: polynom = 32'b10100000000000000000000000000; // 0x14000000
- 30: polynom = 32'b100000000000000000000000101001; // 0x20000029
- 31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
- 32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
- default: polynom = 32'b0;
- endcase
- lfsr_fb = qi[length];
- for (i=length-1; i>=1; i=i-1) begin
- if (polynom[i])
- lfsr_fb = lfsr_fb ~^ qi[i];
- end
- end
- assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
- always @ (posedge clk or posedge rst)
- if (rst)
- qi <= {length{1'b0}};
- else
- if (cke)
- qi <= q_next;
- always @ (posedge clk or posedge rst)
- if (rst)
- zq <= 1'b1;
- else
- if (cke)
- zq <= q_next == {length{1'b0}};
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Versatile counter ////
-//// ////
-//// Description ////
-//// Versatile counter, a reconfigurable binary, gray or LFSR ////
-//// counter ////
-//// ////
-//// To Do: ////
-//// - add LFSR with more taps ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// ORSoC AB ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-// LFSR counter
-module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
- parameter length = 4;
- input cke;
- output [length:1] q;
- input rst;
- input clk;
- parameter clear_value = 0;
- parameter set_value = 1;
- parameter wrap_value = 8;
- parameter level1_value = 15;
- reg [length:1] qi;
- reg lfsr_fb;
- wire [length:1] q_next;
- reg [32:1] polynom;
- integer i;
- always @ (qi)
- begin
- case (length)
- 2: polynom = 32'b11; // 0x3
- 3: polynom = 32'b110; // 0x6
- 4: polynom = 32'b1100; // 0xC
- 5: polynom = 32'b10100; // 0x14
- 6: polynom = 32'b110000; // 0x30
- 7: polynom = 32'b1100000; // 0x60
- 8: polynom = 32'b10111000; // 0xb8
- 9: polynom = 32'b100010000; // 0x110
- 10: polynom = 32'b1001000000; // 0x240
- 11: polynom = 32'b10100000000; // 0x500
- 12: polynom = 32'b100000101001; // 0x829
- 13: polynom = 32'b1000000001100; // 0x100C
- 14: polynom = 32'b10000000010101; // 0x2015
- 15: polynom = 32'b110000000000000; // 0x6000
- 16: polynom = 32'b1101000000001000; // 0xD008
- 17: polynom = 32'b10010000000000000; // 0x12000
- 18: polynom = 32'b100000010000000000; // 0x20400
- 19: polynom = 32'b1000000000000100011; // 0x40023
- 20: polynom = 32'b10010000000000000000; // 0x90000
- 21: polynom = 32'b101000000000000000000; // 0x140000
- 22: polynom = 32'b1100000000000000000000; // 0x300000
- 23: polynom = 32'b10000100000000000000000; // 0x420000
- 24: polynom = 32'b111000010000000000000000; // 0xE10000
- 25: polynom = 32'b1001000000000000000000000; // 0x1200000
- 26: polynom = 32'b10000000000000000000100011; // 0x2000023
- 27: polynom = 32'b100000000000000000000010011; // 0x4000013
- 28: polynom = 32'b1100100000000000000000000000; // 0xC800000
- 29: polynom = 32'b10100000000000000000000000000; // 0x14000000
- 30: polynom = 32'b100000000000000000000000101001; // 0x20000029
- 31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
- 32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
- default: polynom = 32'b0;
- endcase
- lfsr_fb = qi[length];
- for (i=length-1; i>=1; i=i-1) begin
- if (polynom[i])
- lfsr_fb = lfsr_fb ~^ qi[i];
- end
- end
- assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
- always @ (posedge clk or posedge rst)
- if (rst)
- qi <= {length{1'b0}};
- else
- if (cke)
- qi <= q_next;
- assign q = qi;
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Versatile counter ////
-//// ////
-//// Description ////
-//// Versatile counter, a reconfigurable binary, gray or LFSR ////
-//// counter ////
-//// ////
-//// To Do: ////
-//// - add LFSR with more taps ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// ORSoC AB ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-// LFSR counter
-module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
- parameter length = 4;
- input clear;
- input cke;
- output [length:1] q;
- input rst;
- input clk;
- parameter clear_value = 0;
- parameter set_value = 1;
- parameter wrap_value = 8;
- parameter level1_value = 15;
- reg [length:1] qi;
- reg lfsr_fb;
- wire [length:1] q_next;
- reg [32:1] polynom;
- integer i;
- always @ (qi)
- begin
- case (length)
- 2: polynom = 32'b11; // 0x3
- 3: polynom = 32'b110; // 0x6
- 4: polynom = 32'b1100; // 0xC
- 5: polynom = 32'b10100; // 0x14
- 6: polynom = 32'b110000; // 0x30
- 7: polynom = 32'b1100000; // 0x60
- 8: polynom = 32'b10111000; // 0xb8
- 9: polynom = 32'b100010000; // 0x110
- 10: polynom = 32'b1001000000; // 0x240
- 11: polynom = 32'b10100000000; // 0x500
- 12: polynom = 32'b100000101001; // 0x829
- 13: polynom = 32'b1000000001100; // 0x100C
- 14: polynom = 32'b10000000010101; // 0x2015
- 15: polynom = 32'b110000000000000; // 0x6000
- 16: polynom = 32'b1101000000001000; // 0xD008
- 17: polynom = 32'b10010000000000000; // 0x12000
- 18: polynom = 32'b100000010000000000; // 0x20400
- 19: polynom = 32'b1000000000000100011; // 0x40023
- 20: polynom = 32'b10010000000000000000; // 0x90000
- 21: polynom = 32'b101000000000000000000; // 0x140000
- 22: polynom = 32'b1100000000000000000000; // 0x300000
- 23: polynom = 32'b10000100000000000000000; // 0x420000
- 24: polynom = 32'b111000010000000000000000; // 0xE10000
- 25: polynom = 32'b1001000000000000000000000; // 0x1200000
- 26: polynom = 32'b10000000000000000000100011; // 0x2000023
- 27: polynom = 32'b100000000000000000000010011; // 0x4000013
- 28: polynom = 32'b1100100000000000000000000000; // 0xC800000
- 29: polynom = 32'b10100000000000000000000000000; // 0x14000000
- 30: polynom = 32'b100000000000000000000000101001; // 0x20000029
- 31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
- 32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
- default: polynom = 32'b0;
- endcase
- lfsr_fb = qi[length];
- for (i=length-1; i>=1; i=i-1) begin
- if (polynom[i])
- lfsr_fb = lfsr_fb ~^ qi[i];
- end
- end
- assign q_next = clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
- always @ (posedge clk or posedge rst)
- if (rst)
- qi <= {length{1'b0}};
- else
- if (cke)
- qi <= q_next;
- assign q = qi;
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Versatile counter ////
-//// ////
-//// Description ////
-//// Versatile counter, a reconfigurable binary, gray or LFSR ////
-//// counter ////
-//// ////
-//// To Do: ////
-//// - add LFSR with more taps ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// ORSoC AB ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-// LFSR counter
-module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
- parameter length = 4;
- input cke;
- output [length:1] q;
- output reg zq;
- input rst;
- input clk;
- parameter clear_value = 0;
- parameter set_value = 1;
- parameter wrap_value = 8;
- parameter level1_value = 15;
- reg [length:1] qi;
- reg lfsr_fb;
- wire [length:1] q_next;
- reg [32:1] polynom;
- integer i;
- always @ (qi)
- begin
- case (length)
- 2: polynom = 32'b11; // 0x3
- 3: polynom = 32'b110; // 0x6
- 4: polynom = 32'b1100; // 0xC
- 5: polynom = 32'b10100; // 0x14
- 6: polynom = 32'b110000; // 0x30
- 7: polynom = 32'b1100000; // 0x60
- 8: polynom = 32'b10111000; // 0xb8
- 9: polynom = 32'b100010000; // 0x110
- 10: polynom = 32'b1001000000; // 0x240
- 11: polynom = 32'b10100000000; // 0x500
- 12: polynom = 32'b100000101001; // 0x829
- 13: polynom = 32'b1000000001100; // 0x100C
- 14: polynom = 32'b10000000010101; // 0x2015
- 15: polynom = 32'b110000000000000; // 0x6000
- 16: polynom = 32'b1101000000001000; // 0xD008
- 17: polynom = 32'b10010000000000000; // 0x12000
- 18: polynom = 32'b100000010000000000; // 0x20400
- 19: polynom = 32'b1000000000000100011; // 0x40023
- 20: polynom = 32'b10010000000000000000; // 0x90000
- 21: polynom = 32'b101000000000000000000; // 0x140000
- 22: polynom = 32'b1100000000000000000000; // 0x300000
- 23: polynom = 32'b10000100000000000000000; // 0x420000
- 24: polynom = 32'b111000010000000000000000; // 0xE10000
- 25: polynom = 32'b1001000000000000000000000; // 0x1200000
- 26: polynom = 32'b10000000000000000000100011; // 0x2000023
- 27: polynom = 32'b100000000000000000000010011; // 0x4000013
- 28: polynom = 32'b1100100000000000000000000000; // 0xC800000
- 29: polynom = 32'b10100000000000000000000000000; // 0x14000000
- 30: polynom = 32'b100000000000000000000000101001; // 0x20000029
- 31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
- 32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
- default: polynom = 32'b0;
- endcase
- lfsr_fb = qi[length];
- for (i=length-1; i>=1; i=i-1) begin
- if (polynom[i])
- lfsr_fb = lfsr_fb ~^ qi[i];
- end
- end
- assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
- always @ (posedge clk or posedge rst)
- if (rst)
- qi <= {length{1'b0}};
- else
- if (cke)
- qi <= q_next;
- assign q = qi;
- always @ (posedge clk or posedge rst)
- if (rst)
- zq <= 1'b1;
- else
- if (cke)
- zq <= q_next == {length{1'b0}};
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Versatile counter ////
-//// ////
-//// Description ////
-//// Versatile counter, a reconfigurable binary, gray or LFSR ////
-//// counter ////
-//// ////
-//// To Do: ////
-//// - add LFSR with more taps ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// ORSoC AB ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-// LFSR counter
-module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
- parameter length = 4;
- input cke;
- input rew;
- output reg level1;
- input rst;
- input clk;
- parameter clear_value = 0;
- parameter set_value = 1;
- parameter wrap_value = 8;
- parameter level1_value = 15;
- wire clear;
- assign clear = 1'b0;
- reg [length:1] qi;
- reg lfsr_fb, lfsr_fb_rew;
- wire [length:1] q_next, q_next_fw, q_next_rew;
- reg [32:1] polynom_rew;
- integer j;
- reg [32:1] polynom;
- integer i;
- always @ (qi)
- begin
- case (length)
- 2: polynom = 32'b11; // 0x3
- 3: polynom = 32'b110; // 0x6
- 4: polynom = 32'b1100; // 0xC
- 5: polynom = 32'b10100; // 0x14
- 6: polynom = 32'b110000; // 0x30
- 7: polynom = 32'b1100000; // 0x60
- 8: polynom = 32'b10111000; // 0xb8
- 9: polynom = 32'b100010000; // 0x110
- 10: polynom = 32'b1001000000; // 0x240
- 11: polynom = 32'b10100000000; // 0x500
- 12: polynom = 32'b100000101001; // 0x829
- 13: polynom = 32'b1000000001100; // 0x100C
- 14: polynom = 32'b10000000010101; // 0x2015
- 15: polynom = 32'b110000000000000; // 0x6000
- 16: polynom = 32'b1101000000001000; // 0xD008
- 17: polynom = 32'b10010000000000000; // 0x12000
- 18: polynom = 32'b100000010000000000; // 0x20400
- 19: polynom = 32'b1000000000000100011; // 0x40023
- 20: polynom = 32'b10010000000000000000; // 0x90000
- 21: polynom = 32'b101000000000000000000; // 0x140000
- 22: polynom = 32'b1100000000000000000000; // 0x300000
- 23: polynom = 32'b10000100000000000000000; // 0x420000
- 24: polynom = 32'b111000010000000000000000; // 0xE10000
- 25: polynom = 32'b1001000000000000000000000; // 0x1200000
- 26: polynom = 32'b10000000000000000000100011; // 0x2000023
- 27: polynom = 32'b100000000000000000000010011; // 0x4000013
- 28: polynom = 32'b1100100000000000000000000000; // 0xC800000
- 29: polynom = 32'b10100000000000000000000000000; // 0x14000000
- 30: polynom = 32'b100000000000000000000000101001; // 0x20000029
- 31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
- 32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
- default: polynom = 32'b0;
- endcase
- lfsr_fb = qi[length];
- for (i=length-1; i>=1; i=i-1) begin
- if (polynom[i])
- lfsr_fb = lfsr_fb ~^ qi[i];
- end
- end
- assign q_next_fw = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
- always @ (qi)
- begin
- case (length)
- 2: polynom_rew = 32'b11;
- 3: polynom_rew = 32'b110;
- 4: polynom_rew = 32'b1100;
- 5: polynom_rew = 32'b10100;
- 6: polynom_rew = 32'b110000;
- 7: polynom_rew = 32'b1100000;
- 8: polynom_rew = 32'b10111000;
- 9: polynom_rew = 32'b100010000;
- 10: polynom_rew = 32'b1001000000;
- 11: polynom_rew = 32'b10100000000;
- 12: polynom_rew = 32'b100000101001;
- 13: polynom_rew = 32'b1000000001100;
- 14: polynom_rew = 32'b10000000010101;
- 15: polynom_rew = 32'b110000000000000;
- 16: polynom_rew = 32'b1101000000001000;
- 17: polynom_rew = 32'b10010000000000000;
- 18: polynom_rew = 32'b100000010000000000;
- 19: polynom_rew = 32'b1000000000000100011;
- 20: polynom_rew = 32'b10000010000000000000;
- 21: polynom_rew = 32'b101000000000000000000;
- 22: polynom_rew = 32'b1100000000000000000000;
- 23: polynom_rew = 32'b10000100000000000000000;
- 24: polynom_rew = 32'b111000010000000000000000;
- 25: polynom_rew = 32'b1001000000000000000000000;
- 26: polynom_rew = 32'b10000000000000000000100011;
- 27: polynom_rew = 32'b100000000000000000000010011;
- 28: polynom_rew = 32'b1100100000000000000000000000;
- 29: polynom_rew = 32'b10100000000000000000000000000;
- 30: polynom_rew = 32'b100000000000000000000000101001;
- 31: polynom_rew = 32'b1001000000000000000000000000000;
- 32: polynom_rew = 32'b10000000001000000000000000000011;
- default: polynom_rew = 32'b0;
- endcase
- // rotate left
- polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
- lfsr_fb_rew = qi[length];
- for (i=length-1; i>=1; i=i-1) begin
- if (polynom_rew[i])
- lfsr_fb_rew = lfsr_fb_rew ~^ qi[i];
- end
- end
- assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
- assign q_next = rew ? q_next_rew : q_next_fw;
- always @ (posedge clk or posedge rst)
- if (rst)
- qi <= {length{1'b0}};
- else
- if (cke)
- qi <= q_next;
- always @ (posedge clk or posedge rst)
- if (rst)
- level1 <= 1'b0;
- else
- if (cke)
- if (clear)
- level1 <= 1'b0;
- else if (q_next == level1_value)
- level1 <= 1'b1;
- else if (qi == level1_value & rew)
- level1 <= 1'b0;
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Versatile counter ////
-//// ////
-//// Description ////
-//// Versatile counter, a reconfigurable binary, gray or LFSR ////
-//// counter ////
-//// ////
-//// To Do: ////
-//// - add LFSR with more taps ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// ORSoC AB ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
// GRAY counter
-module vl_cnt_gray ( q, rst, clk);
+module vl_cnt_gray_ce_bin (
+ cke, q, q_bin, rst, clk);
parameter length = 4;
- output reg [length:1] q;
- input rst;
- input clk;
- parameter clear_value = 0;
- parameter set_value = 1;
- parameter wrap_value = 8;
- parameter level1_value = 15;
- reg [length:1] qi;
- wire [length:1] q_next;
- assign q_next = qi + {{length-1{1'b0}},1'b1};
- always @ (posedge clk or posedge rst)
- if (rst)
- qi <= {length{1'b0}};
- else
- qi <= q_next;
- always @ (posedge clk or posedge rst)
- if (rst)
- q <= {length{1'b0}};
- else
- q <= (q_next>>1) ^ q_next;
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Versatile counter ////
-//// ////
-//// Description ////
-//// Versatile counter, a reconfigurable binary, gray or LFSR ////
-//// counter ////
-//// ////
-//// To Do: ////
-//// - add LFSR with more taps ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// ORSoC AB ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-// GRAY counter
-module vl_cnt_gray_ce ( cke, q, rst, clk);
- parameter length = 4;
input cke;
output reg [length:1] q;
- input rst;
- input clk;
- parameter clear_value = 0;
- parameter set_value = 1;
- parameter wrap_value = 8;
- parameter level1_value = 15;
- reg [length:1] qi;
- wire [length:1] q_next;
- assign q_next = qi + {{length-1{1'b0}},1'b1};
- always @ (posedge clk or posedge rst)
- if (rst)
- qi <= {length{1'b0}};
- else
- if (cke)
- qi <= q_next;
- always @ (posedge clk or posedge rst)
- if (rst)
- q <= {length{1'b0}};
- else
- if (cke)
- q <= (q_next>>1) ^ q_next;
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Versatile counter ////
-//// ////
-//// Description ////
-//// Versatile counter, a reconfigurable binary, gray or LFSR ////
-//// counter ////
-//// ////
-//// To Do: ////
-//// - add LFSR with more taps ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// ORSoC AB ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-// GRAY counter
-module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
- parameter length = 4;
- input cke;
- output reg [length:1] q;
output [length:1] q_bin;
input rst;
input clk;
Index: verilog/cnt_gray_ce_bin.csv
===================================================================
--- verilog/cnt_gray_ce_bin.csv (revision 39)
+++ verilog/cnt_gray_ce_bin.csv (revision 40)
@@ -1,5 +1,5 @@
Name,type,,,,
-vl_cnt_gray_ce_bin,GRAY,,,,
+cnt_gray_ce_bin,GRAY,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,0,,
Index: verilog/cnt_bin_ce_rew_zq_l1.csv
===================================================================
--- verilog/cnt_bin_ce_rew_zq_l1.csv (revision 39)
+++ verilog/cnt_bin_ce_rew_zq_l1.csv (revision 40)
@@ -1,5 +1,5 @@
Name,type,,,,
-vl_cnt_bin_ce_rew_zq_l1,binary,,,,
+cnt_bin_ce_rew_zq_l1,binary,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,1,,
Index: verilog/cnt_gray.csv
===================================================================
--- verilog/cnt_gray.csv (revision 39)
+++ verilog/cnt_gray.csv (revision 40)
@@ -1,5 +1,5 @@
Name,type,,,,
-vl_cnt_gray,GRAY,,,,
+cnt_gray,GRAY,,,,
,,,,,
clear,set,cke,rew,,
0,0,0,0,,
Index: verilog/cnt_lfsr_ce_q_zq.csv
===================================================================
--- verilog/cnt_lfsr_ce_q_zq.csv (revision 39)
+++ verilog/cnt_lfsr_ce_q_zq.csv (revision 40)
@@ -1,5 +1,5 @@
Name,type,,,,
-vl_cnt_lfsr_ce_q_zq,LFSR,,,,
+cnt_lfsr_ce_q_zq,LFSR,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,0,,
Index: verilog/counters.v
===================================================================
--- verilog/counters.v (revision 39)
+++ verilog/counters.v (revision 40)
@@ -40,7 +40,10 @@
//// ////
//////////////////////////////////////////////////////////////////////
-module vl_cnt_shreg_wrap ( q, rst, clk);
+`ifdef CNT_SHREG_WRAP
+`define MODULE cnt_shreg_wrap
+module `BASE`MODULE ( q, rst, clk);
+`undef MODULE
parameter length = 4;
output reg [0:length-1] q;
@@ -54,8 +57,12 @@
q <= {q[length-1],q[0:length-2]};
endmodule
+`endif
-module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
+`ifdef CNT_SHREG_CE_WRAP
+`define MODULE cnt_shreg_ce_wrap
+module `BASE`MODULE ( cke, q, rst, clk);
+`undef MODULE
parameter length = 4;
input cke;
@@ -71,8 +78,12 @@
q <= {q[length-1],q[0:length-2]};
endmodule
+`endif
-module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
+`ifdef CNT_SHREG_CE_CLEAR
+`define MODULE cnt_shreg_ce_clear
+module `BASE`MODULE ( cke, clear, q, rst, clk);
+`undef MODULE
parameter length = 4;
input cke, clear;
@@ -91,8 +102,12 @@
q <= q >> 1;
endmodule
+`endif
-module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
+`ifdef CNT_SHREG_CE_CLEAR_WRAP
+`define MODULE cnt_shreg_ce_clear_wrap
+module `BASE`MODULE ( cke, clear, q, rst, clk);
+`undef MODULE
parameter length = 4;
input cke, clear;
@@ -111,3 +126,4 @@
q <= {q[length-1],q[0:length-2]};
endmodule
+`endif
/verilog/cnt_lfsr_ce.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_lfsr_ce,LFSR,,,, |
cnt_lfsr_ce,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,0,, |
/verilog/cnt_bin_ce_clear_set_rew.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_bin_ce_clear_set_rew,binary,,,, |
cnt_bin_ce_clear_set_rew,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
1,1,1,1,, |
/verilog/wb.v
40,9 → 40,12
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`ifdef WB3WB3_BRIDGE |
// async wb3 - wb3 bridge |
`timescale 1ns/1ns |
module vl_wb3wb3_bridge ( |
`define MODULE wb3wb3_bridge |
module `BASE`MODULE ( |
`undef MODULE |
// wishbone slave side |
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst, |
// wishbone master side |
119,7 → 122,9
else if (wbs_eoc_alert & (a_rd | a_wr)) |
wbs_eoc <= 1'b1; |
|
vl_cnt_shreg_ce_clear # ( .length(16)) |
`define MODULE cnt_shreg_ce_clear |
`BASE`MODULE # ( .length(16)) |
`undef MODULE |
cnt0 ( |
.cke(wbs_ack_o), |
.clear(wbs_eoc), |
205,12 → 210,18
1'b0; |
assign b_rd = b_rd_adr | b_rd_data; |
|
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst)); |
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst)); |
`define MODULE dff |
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst)); |
`undef MODULE |
`define MODULE dff_ce |
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst)); |
`undef MODULE |
|
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp; |
|
`define MODULE cnt_shreg_ce_clear |
vl_cnt_shreg_ce_clear # ( .length(16)) |
`undef MODULE |
cnt1 ( |
.cke(wbm_ack_i), |
.clear(wbm_eoc), |
232,7 → 243,9
end |
|
//async_fifo_dw_simplex_top |
vl_fifo_2r2w_async_simplex |
`define MODULE fifo_2r2w_async_simplex |
`BASE`MODULE |
`undef MODULE |
# ( .data_width(36), .addr_width(addr_width)) |
fifo ( |
// a side |
256,8 → 269,15
); |
|
endmodule |
`undef WE |
`undef BTE |
`undef CTI |
`endif |
|
`ifdef WB3_ARBITER_TYPE1 |
`define MODULE wb3_arbiter_type1 |
module vl_wb3_arbiter_type1 ( |
`undef MODULE |
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, |
wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i, |
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, |
344,13 → 364,15
|
assign sel = select | state; |
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i)); |
`define MODULE mux_andor |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i)); |
`undef MODULE |
assign wbs_cyc_i = |sel; |
|
assign wbm_dat_i = {nr_of_ports{wbs_dat_o}}; |
359,9 → 381,13
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel; |
|
endmodule |
`endif |
|
`ifdef WB_BOOT_ROM |
// WB ROM |
module vl_wb_boot_rom ( |
`define MODULE wb_boot_rom |
module `BASE`MODULE ( |
`undef MODULE |
wb_adr_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst); |
|
422,8 → 448,12
assign wb_ack_o = wb_ack; |
|
endmodule |
`endif |
|
module vl_wb_dpram ( |
`ifdef WB_DPRAM |
`define MODULE wb_dpram |
module `BASE`MODULE ( |
`undef MODULE |
// wishbone slave side a |
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, |
wbsa_clk, wbsa_rst, |
453,7 → 483,9
|
wire wbsa_dat_tmp, wbsb_dat_tmp; |
|
vl_dpram_2r2w # ( |
`define MODULE dpram_2r2w |
`BASE`MODULE # ( |
`undef MODULE |
.data_width(data_width), .addr_width(addr_width) ) |
dpram0( |
.d_a(wbsa_dat_i), |
481,7 → 513,10
assign wbsb_dat_o = wbsb_dat_tmp; |
endgenerate |
|
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst)); |
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst)); |
`define MODULE spr |
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst)); |
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst)); |
`undef MODULE |
|
endmodule |
`endif |
/verilog/cnt_bin_clear.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_bin_clear,binary,,,, |
cnt_bin_clear,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
1,0,0,0,, |
/verilog/cnt_bin_ce.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_bin_ce,binary,,,, |
cnt_bin_ce,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,0,, |
/verilog/Makefile
1,4 → 1,5
VERILOG_FILES = clk_and_reset.v |
VERILOG_FILES = defines.v |
VERILOG_FILES += clk_and_reset.v |
VERILOG_FILES += registers.v |
VERILOG_FILES += logic.v |
|
30,11 → 31,9
VERSATILE_LIBRARIES = versatile_library.v |
VERSATILE_LIBRARIES += versatile_library_actel.v |
VERSATILE_LIBRARIES += versatile_library_altera.v |
OUT_FILE ?= custom.v |
VERSATILE_LIBRARIES += $(OUT_FILE) |
|
svn_export: |
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/versatile_counter_generator.php |
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/CSV.class.php |
|
#.PHONY: $(VERILOG_FILES_CNT) |
$(VERILOG_FILES_CNT): |
./versatile_counter_generator.php cnt_bin.csv > vl_cnt_bin.v |
60,11 → 59,15
cat $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > versatile_library.v |
|
versatile_library_actel.v: $(VERILOG_FILES) |
vppreproc --noline --noblank +define+ACTEL $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > versatile_library_actel.v |
vppreproc --noline --noblank +define+ACTEL +define+ALL $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > versatile_library_actel.v |
|
versatile_library_altera.v: $(VERILOG_FILES) |
vppreproc --noline --noblank +define+ALTERA $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > versatile_library_altera.v |
vppreproc --noline --noblank +define+ALTERA +define+ALL $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > versatile_library_altera.v |
|
$(OUT_FILE): $(VERILOG_FILES) |
vppreproc --noline --noblank $(DEFINE_FILE) $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > $(OUT_FILE) |
|
|
all: $(VERSATILE_LIBRARIES) |
|
clean: |
/verilog/cnt_lfsr_zq.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_lfsr_zq,LFSR,,,, |
cnt_lfsr_zq,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,0,0,, |
/verilog/versatile_library_altera.v
179,7 → 179,7
`endif |
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
end |
endgenerate |
endmodule |
652,131 → 652,9
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin ( q, rst, clk); |
module vl_cnt_bin_ce ( |
cke, q, rst, clk); |
parameter length = 4; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_clear ( clear, q, rst, clk); |
parameter length = 4; |
input clear; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce ( cke, q, rst, clk); |
parameter length = 4; |
input cke; |
output [length:1] q; |
input rst; |
838,311 → 716,11
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk); |
module vl_cnt_bin_ce_rew_zq_l1 ( |
cke, rew, zq, level1, rst, clk); |
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk); |
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
output reg level1; |
output reg level2; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 15; |
parameter level1_value = 8; |
parameter level2_value = 15; |
wire rew; |
assign rew = 1'b0; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
always @ (posedge clk or posedge rst) |
if (rst) |
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
always @ (posedge clk or posedge rst) |
if (rst) |
level2 <= 1'b0; |
else |
if (cke) |
if (clear) |
level2 <= 1'b0; |
else if (q_next == level2_value) |
level2 <= 1'b1; |
else if (qi == level2_value & rew) |
level2 <= 1'b0; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk); |
parameter length = 4; |
input clear; |
input set; |
input cke; |
input rew; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1}; |
assign q_next_rew = clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1}; |
assign q_next = rew ? q_next_rew : q_next_fw; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk); |
parameter length = 4; |
input cke; |
input rew; |
output reg level1; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 1; |
parameter level1_value = 15; |
wire clear; |
assign clear = 1'b0; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = qi + {{length-1{1'b0}},1'b1}; |
assign q_next_rew = qi - {{length-1{1'b0}},1'b1}; |
assign q_next = rew ? q_next_rew : q_next_fw; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk); |
parameter length = 4; |
input cke; |
input rew; |
output reg zq; |
output reg level1; |
input rst; |
1224,7 → 802,8
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk); |
module vl_cnt_bin_ce_rew_q_zq_l1 ( |
cke, rew, q, zq, level1, rst, clk); |
parameter length = 4; |
input cke; |
input rew; |
1310,868 → 889,12
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_zq ( zq, rst, clk); |
parameter length = 4; |
output reg zq; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
zq <= 1'b1; |
else |
zq <= q_next == {length{1'b0}}; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk); |
parameter length = 4; |
input cke; |
output reg zq; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
zq <= 1'b1; |
else |
if (cke) |
zq <= q_next == {length{1'b0}}; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk); |
parameter length = 4; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk); |
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk); |
parameter length = 4; |
input cke; |
output [length:1] q; |
output reg zq; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
always @ (posedge clk or posedge rst) |
if (rst) |
zq <= 1'b1; |
else |
if (cke) |
zq <= q_next == {length{1'b0}}; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk); |
parameter length = 4; |
input cke; |
input rew; |
output reg level1; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
wire clear; |
assign clear = 1'b0; |
reg [length:1] qi; |
reg lfsr_fb, lfsr_fb_rew; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
reg [32:1] polynom_rew; |
integer j; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next_fw = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (qi) |
begin |
case (length) |
2: polynom_rew = 32'b11; |
3: polynom_rew = 32'b110; |
4: polynom_rew = 32'b1100; |
5: polynom_rew = 32'b10100; |
6: polynom_rew = 32'b110000; |
7: polynom_rew = 32'b1100000; |
8: polynom_rew = 32'b10111000; |
9: polynom_rew = 32'b100010000; |
10: polynom_rew = 32'b1001000000; |
11: polynom_rew = 32'b10100000000; |
12: polynom_rew = 32'b100000101001; |
13: polynom_rew = 32'b1000000001100; |
14: polynom_rew = 32'b10000000010101; |
15: polynom_rew = 32'b110000000000000; |
16: polynom_rew = 32'b1101000000001000; |
17: polynom_rew = 32'b10010000000000000; |
18: polynom_rew = 32'b100000010000000000; |
19: polynom_rew = 32'b1000000000000100011; |
20: polynom_rew = 32'b10000010000000000000; |
21: polynom_rew = 32'b101000000000000000000; |
22: polynom_rew = 32'b1100000000000000000000; |
23: polynom_rew = 32'b10000100000000000000000; |
24: polynom_rew = 32'b111000010000000000000000; |
25: polynom_rew = 32'b1001000000000000000000000; |
26: polynom_rew = 32'b10000000000000000000100011; |
27: polynom_rew = 32'b100000000000000000000010011; |
28: polynom_rew = 32'b1100100000000000000000000000; |
29: polynom_rew = 32'b10100000000000000000000000000; |
30: polynom_rew = 32'b100000000000000000000000101001; |
31: polynom_rew = 32'b1001000000000000000000000000000; |
32: polynom_rew = 32'b10000000001000000000000000000011; |
default: polynom_rew = 32'b0; |
endcase |
// rotate left |
polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] }; |
lfsr_fb_rew = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom_rew[i]) |
lfsr_fb_rew = lfsr_fb_rew ~^ qi[i]; |
end |
end |
assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]}; |
assign q_next = rew ? q_next_rew : q_next_fw; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// GRAY counter |
module vl_cnt_gray ( q, rst, clk); |
module vl_cnt_gray_ce_bin ( |
cke, q, q_bin, rst, clk); |
parameter length = 4; |
output reg [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
q <= {length{1'b0}}; |
else |
q <= (q_next>>1) ^ q_next; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// GRAY counter |
module vl_cnt_gray_ce ( cke, q, rst, clk); |
parameter length = 4; |
input cke; |
output reg [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
q <= {length{1'b0}}; |
else |
if (cke) |
q <= (q_next>>1) ^ q_next; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// GRAY counter |
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk); |
parameter length = 4; |
input cke; |
output reg [length:1] q; |
output [length:1] q_bin; |
input rst; |
input clk; |
/verilog/defines.v
0,0 → 1,211
`ifndef BASE |
`define BASE vl_ |
`endif |
|
`ifdef ALL |
|
`define GBUF |
`define SYNC_RST |
`define PLL |
|
`define MULTS |
`define MULTS18X18 |
`define MULT |
`define SHIFT_UNIT_32 |
`define LOGIC_UNIT |
|
`define CNT_SHREG_WRAP |
`define CNT_SHREG_CE_WRAP |
`define CNT_SHREG_CE_CLEAR |
`define CNT_SHREG_CE_CLEAR_WRAP |
|
`define MUX_ANDOR |
`define MUX2_ANDOR |
`define MUX3_ANDOR |
`define MUX4_ANDOR |
`define MUX5_ANDOR |
`define MUX6_ANDOR |
|
`define ROM_INIT |
`define RAM |
`define RAM_BE |
`define DPRAM_1R1W |
`define DPRAM_2R1W |
`define DPRAM_2R2W |
`define FIFO_1R1W_FILL_LEVEL_SYNC |
`define FIFO_2R2W_SYNC_SIMPLEX |
`define FIFO_CMP_ASYNC |
`define FIFO_1R1W_ASYNC |
`define FIFO_2R2W_ASYNC |
`define FIFO_2R2W_ASYNC_SIMPLEX |
|
`define DFF |
`define DFF_ARRAY |
`define DFF_CE |
`define DFF_CE_CLEAR |
`define DF_CE_SET |
`define SPR |
`define SRP |
`define DFF_SR |
`define LATCH |
`define SHREG |
`define SHREG_CE |
`define DELAY |
`define DELAY_EMPTYFLAG |
|
`define WB3WB3_BRIDGE |
`define WB3_ARBITER_TYPE1 |
`define WB_BOOT_ROM |
`define WB_DPRAM |
|
`endif |
|
`ifdef PLL |
`ifndef SYNC_RST |
`define SYNC_RST |
`endif |
`endif |
|
`ifdef SYNC_RST |
`ifndef GBUF |
`define GBUF |
`endif |
`endif |
|
`ifdef WB_DPRAM |
`ifndef DPRAM_2R2W |
`define DPRAM_2R2W |
`endif |
`ifndef SPR |
`define SPR |
`endif |
`endif |
|
`ifdef WB3_ARBITER_TYPE1 |
`ifndef MUX_ANDOR |
`define MUX_ANDOR |
`endif |
`endif |
|
`ifdef WB3WB3_BRIDGE |
`ifndef CNT_SHREG_CE_CLEAR |
`define CNT_SHREG_CE_CLEAR |
`endif |
`ifndef DFF |
`define DFF |
`endif |
`ifndef DFF_CE |
`define DFF_CE |
`endif |
`ifndef CNT_SHREG_CE_CLEAR |
`define CNT_SHREG_CE_CLEAR |
`endif |
`ifndef FIFO_2R2W_ASYNC_SIMPLEX |
`define FIFO_2R2W_ASYNC_SIMPLEX |
`endif |
`endif |
|
`ifdef MULTS18X18 |
`ifndef MULTS |
`define MULTS |
`endif |
`endif |
|
`ifdef SHIFT_UNIT_32 |
`ifndef MULTS |
`define MULTS |
`endif |
`endif |
|
`ifdef MUX2_ANDOR |
`ifndef MUX_ANDOR |
`define MUX_ANDOR |
`endif |
`endif |
|
`ifdef MUX3_ANDOR |
`ifndef MUX_ANDOR |
`define MUX_ANDOR |
`endif |
`endif |
|
`ifdef MUX4_ANDOR |
`ifndef MUX_ANDOR |
`define MUX_ANDOR |
`endif |
`endif |
|
`ifdef MUX5_ANDOR |
`ifndef MUX_ANDOR |
`define MUX_ANDOR |
`endif |
`endif |
|
`ifdef MUX6_ANDOR |
`ifndef MUX_ANDOR |
`define MUX_ANDOR |
`endif |
`endif |
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC |
`ifndef CNT_BIN_CE |
`define CNT_BIN_CE |
`endif |
`ifndef DPRAM_1R1W |
`define DPRAM_1R1W |
`endif |
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1 |
`define CNT_BIN_CE_REW_Q_ZQ_L1 |
`endif |
`endif |
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC |
`ifndef CNT_LFSR_CE |
`define CNT_LFSR_CE |
`endif |
`ifndef DPRAM_2R2W |
`define DPRAM_2R2W |
`endif |
`ifndef CNT_BIN_CE_REW_ZQ_L1 |
`define CNT_BIN_CE_REW_ZQ_L1 |
`endif |
`endif |
|
`ifdef FIFO_2R2W_ASYNC_SIMPLEX |
`ifndef CNT_GRAY_CE_BIN |
`define CNT_GRAY_CE_BIN |
`endif |
`ifndef DPRAM_2R2W |
`define DPRAM_2R2W |
`endif |
`ifndef FIFO_CMP_ASYNC |
`define FIFO_CMP_ASYNC |
`endif |
`endif |
|
`ifdef FIFO_2R2W_ASYNC |
`ifndef FIFO_1R1W_ASYNC |
`define FIFO_1R1W_ASYNC |
`endif |
`endif |
|
`ifdef FIFO_1R1W_ASYNC |
`ifndef CNT_GRAY_CE_BIN |
`define CNT_GRAY_CE_BIN |
`endif |
`ifndef DPRAM_1R1W |
`define DPRAM_1R1W |
`endif |
`ifndef FIFO_CMP_ASYNC |
`define FIFO_CMP_ASYNC |
`endif |
`endif |
|
`ifdef FIFO_CMP_ASYNC |
`ifndef DFF_SR |
`define DFF_SR |
`endif |
`ifndef DFF |
`define DFF |
`endif |
`endif |
/verilog/cnt_lfsr_ce_rew_l1.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_lfsr_ce_rew_l1,LFSR,,,, |
cnt_lfsr_ce_rew_l1,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,1,, |
/verilog/memories.v
40,9 → 40,12
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`ifdef ROM_INIT |
/// ROM |
`define MODULE rom_init |
module `BASE`MODULE ( adr, q, clk); |
`undef MODULE |
|
module vl_rom_init ( adr, q, clk); |
parameter data_width = 32; |
parameter addr_width = 8; |
input [(addr_width-1):0] adr; |
59,6 → 62,7
q <= rom[adr]; |
|
endmodule |
`endif |
|
/* |
module vl_rom ( adr, q, clk); |
93,9 → 97,13
|
endmodule |
*/ |
|
`ifdef RAM |
`define MODULE ram |
// Single port RAM |
module `BASE`MODULE ( d, adr, we, q, clk); |
`undef MODULE |
|
module vl_ram ( d, adr, we, q, clk); |
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d; |
122,8 → 130,13
end |
|
endmodule |
`endif |
|
module vl_ram_be ( d, adr, be, we, q, clk); |
`ifdef RAM_BE |
`define MODULE ram_be |
module `BASE`MODULE ( d, adr, be, we, q, clk); |
`undef MODULE |
|
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d; |
157,8 → 170,8
q <= ram[adr]; |
|
endmodule |
`endif |
|
|
// Dual port RAM |
|
// ACTEL FPGA should not use logic to handle rw collision |
168,7 → 181,10
`define SYN |
`endif |
|
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
`ifdef DPRAM_1R1W |
`define MODULE dpram_1r1w |
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
`undef MODULE |
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d_a; |
196,9 → 212,15
always @ (posedge clk_b) |
adr_b_reg <= adr_b; |
assign q_b = ram[adr_b_reg]; |
|
endmodule |
`endif |
|
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
`ifdef DPRAM_2R1W |
`define MODULE dpram_2r1w |
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
`undef MODULE |
|
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d_a; |
230,8 → 252,13
always @ (posedge clk_b) |
q_b <= ram[adr_b]; |
endmodule |
`endif |
|
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b ); |
`ifdef DPRAM_2R2W |
`define MODULE dpram_2r2w |
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b ); |
`undef MODULE |
|
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d_a; |
269,11 → 296,15
ram[adr_b] <= d_b; |
end |
endmodule |
`endif |
|
// Content addresable memory, CAM |
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC |
// FIFO |
module vl_fifo_1r1w_fill_level_sync ( |
`define MODULE fifo_1r1w_fill_level_sync |
module `BASE`MODULE ( |
`undef MODULE |
d, wr, fifo_full, |
q, rd, fifo_empty, |
fill_level, |
297,28 → 328,36
|
wire [addr_width:1] wadr, radr; |
|
vl_cnt_bin_ce |
`define MODULE cnt_bin_ce |
`BASE`MODULE |
# ( .length(addr_width)) |
fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk)); |
|
vl_cnt_bin_ce |
`BASE`MODULE |
# (.length(addr_width)) |
fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk)); |
`undef MODULE |
|
vl_dpram_1r1w |
`define MODULE dpram_1r1w |
`BASE`MODULE |
# (.data_width(data_width), .addr_width(addr_width)) |
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk)); |
`undef MODULE |
|
vl_cnt_bin_ce_rew_q_zq_l1 |
`define MODULE cnt_bin_ce_rew_q_zq_l1 |
`BASE`MODULE |
# (.length(addr_width+1), .level1_value(1<<addr_width)) |
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk)); |
|
`undef MODULE |
endmodule |
`endif |
|
`ifdef FIFO_2R2W_SYNC_SIMPLEX |
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource |
// RAM is supposed to be larger than the two FIFOs |
// LFSR counters used adr pointers |
module vl_fifo_2r2w_sync_simplex ( |
`define MODULE fifo_2r2w_sync_simplex |
module `BASE`MODULE ( |
`undef MODULE |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
361,42 → 400,52
// dpram |
wire [addr_width:0] a_dpram_adr, b_dpram_adr; |
|
vl_cnt_lfsr_ce |
`define MODULE cnt_lfsr_ce |
`BASE`MODULE |
# ( .length(addr_width)) |
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk)); |
|
vl_cnt_lfsr_ce |
`BASE`MODULE |
# (.length(addr_width)) |
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk)); |
|
vl_cnt_lfsr_ce |
`BASE`MODULE |
# ( .length(addr_width)) |
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk)); |
|
vl_cnt_lfsr_ce |
`BASE`MODULE |
# (.length(addr_width)) |
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk)); |
`undef MODULE |
|
// mux read or write adr to DPRAM |
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr}; |
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr}; |
|
vl_dpram_2r2w |
`define MODULE dpram_2r2w |
`BASE`MODULE |
# (.data_width(data_width), .addr_width(addr_width+1)) |
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk), |
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk)); |
|
vl_cnt_bin_ce_rew_zq_l1 |
`undef MODULE |
|
`define MODULE cnt_bin_ce_rew_zq_l1 |
`BASE`MODULE |
# (.length(addr_width), .level1_value(fifo_full_level)) |
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk)); |
|
vl_cnt_bin_ce_rew_zq_l1 |
`BASE`MODULE |
# (.length(addr_width), .level1_value(fifo_full_level)) |
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk)); |
`undef MODULE |
|
endmodule |
`endif |
|
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst ); |
`ifdef FIFO_CMP_ASYNC |
`define MODULE fifo_cmp_async |
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst ); |
`undef MODULE |
|
parameter addr_width = 4; |
parameter N = addr_width-1; |
449,8 → 498,9
default : direction_clr <= 1'b0; |
endcase |
|
`define MODULE dff_sr |
`ifndef GENERATE_DIRECTION_AS_LATCH |
vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction)); |
`BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction)); |
`endif |
|
`ifdef GENERATE_DIRECTION_AS_LATCH |
464,8 → 514,9
assign async_empty = (wptr == rptr) && (direction==going_empty); |
assign async_full = (wptr == rptr) && (direction==going_full); |
|
vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2)); |
vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full)); |
`BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2)); |
`BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full)); |
`undef MODULE |
|
/* |
always @ (posedge wclk or posedge rst or posedge async_full) |
481,12 → 532,17
{fifo_empty, fifo_empty2} <= 2'b11; |
else |
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */ |
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty)); |
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty)); |
|
`define MODULE dff |
`BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty)); |
`BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty)); |
`undef MODULE |
endmodule // async_compb |
`endif |
|
module vl_fifo_1r1w_async ( |
`ifdef FIFO_1R1W_ASYNC |
`define MODULE fifo_1r1w_async |
module `BASE`MODULE ( |
`undef MODULE |
d, wr, fifo_full, wr_clk, wr_rst, |
q, rd, fifo_empty, rd_clk, rd_rst |
); |
509,25 → 565,35
|
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin; |
|
vl_cnt_gray_ce_bin |
`define MODULE cnt_gray_ce_bin |
`BASE`MODULE |
# ( .length(addr_width)) |
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk)); |
|
vl_cnt_gray_ce_bin |
`BASE`MODULE |
# (.length(addr_width)) |
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk)); |
`undef MODULE |
|
vl_dpram_1r1w |
`define MODULE dpram_1r1w |
`BASE`MODULE |
# (.data_width(data_width), .addr_width(addr_width)) |
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk)); |
`undef MODULE |
|
vl_fifo_cmp_async |
`define MODULE fifo_cmp_async |
`BASE`MODULE |
# (.addr_width(addr_width)) |
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) ); |
`undef MODULE |
|
endmodule |
`endif |
|
module vl_fifo_2r2w_async ( |
`ifdef FIFO_2R2W_ASYNC |
`define MODULE fifo_2r2w_async |
module `BASE`MODULE ( |
`undef MODULE |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
561,21 → 627,27
input b_clk; |
input b_rst; |
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width)) |
`define MODULE fifo_1r1w_async |
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width)) |
vl_fifo_1r1w_async_a ( |
.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst), |
.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst) |
); |
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width)) |
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width)) |
vl_fifo_1r1w_async_b ( |
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst), |
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst) |
); |
|
`undef MODULE |
|
endmodule |
`endif |
|
module vl_fifo_2r2w_async_simplex ( |
`ifdef FIFO_2R2W_ASYNC_SIMPLEX |
`define MODULE fifo_2r2w_async_simplex |
module `BASE`MODULE ( |
`undef MODULE |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
615,37 → 687,44
// dpram |
wire [addr_width:0] a_dpram_adr, b_dpram_adr; |
|
vl_cnt_gray_ce_bin |
`define MODULE cnt_gray_ce_bin |
`BASE`MODULE |
# ( .length(addr_width)) |
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk)); |
|
vl_cnt_gray_ce_bin |
`BASE`MODULE |
# (.length(addr_width)) |
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk)); |
|
vl_cnt_gray_ce_bin |
`BASE`MODULE |
# ( .length(addr_width)) |
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk)); |
|
vl_cnt_gray_ce_bin |
`BASE`MODULE |
# (.length(addr_width)) |
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk)); |
`undef MODULE |
|
// mux read or write adr to DPRAM |
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin}; |
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin}; |
|
vl_dpram_2r2w |
`define MODULE dpram_2r2w |
`BASE`MODULE |
# (.data_width(data_width), .addr_width(addr_width+1)) |
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk), |
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk)); |
`undef MODULE |
|
vl_fifo_cmp_async |
`define MODULE fifo_cmp_async |
`BASE`MODULE |
# (.addr_width(addr_width)) |
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) ); |
|
vl_fifo_cmp_async |
`BASE`MODULE |
# (.addr_width(addr_width)) |
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) ); |
`undef MODULE |
|
endmodule |
`endif |
/verilog/CSV.class.php
0,0 → 1,91
<?php |
|
class CSV { |
|
protected $file = null; |
protected $header = array(); |
|
function __construct($fileName) { |
|
$this->file = fopen($fileName,'r'); |
|
$this->parseHeader(); |
|
} |
|
protected function getLine() { |
|
$line = fgetcsv($this->file); |
|
if($this->isEmpty($line)) { |
return false; |
} else { |
return $line; |
} |
|
} |
|
function parseHeader() { |
|
do { |
|
$this->header = $this->getLine(); |
|
} while($this->header === false and !feof($this->file)); |
|
return (count($this->header) > 0); |
|
} |
|
function getRow() { |
|
$array = $this->getLine(); |
|
if($array === false) { |
|
return false; |
|
} else { |
|
$return = array(); |
|
foreach($array as $key => $val) { |
$return[$this->header[$key]] = $val; |
} |
|
return $return; |
|
} |
|
} |
|
function getRows() { |
|
$return = array(); |
|
while($row = $this->getRow()) { |
$return[] = $row; |
} |
|
return $return; |
|
} |
|
function isEmpty($row) { |
if($row === false or $row === array(null)) { |
return true; |
} else { |
foreach($row as $cur) { |
if(trim($cur) != '') { |
return false; |
} |
} |
return true; |
} |
} |
|
function __destruct() { |
fclose($this->file); |
} |
|
} |
/verilog/cnt_lfsr_ce_zq.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_lfsr_ce_zq,LFSR,,,, |
cnt_lfsr_ce_zq,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,0,, |
/verilog/cnt_bin_ce_rew_l1.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_bin_ce_rew_l1,binary,,,, |
cnt_bin_ce_rew_l1,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,1,, |
/verilog/clk_and_reset.v
45,7 → 45,7
// use to enable global buffers for high fan out signals such as clock and reset |
|
`ifdef ACTEL |
|
`ifdef GBUF |
`timescale 1 ns/100 ps |
// Version: 8.4 8.4.0.33 |
module gbuf(GL,CLK); |
60,7 → 60,9
|
endmodule |
`timescale 1 ns/1 ns |
module vl_gbuf ( i, o); |
`define MODULE gbuf |
module `BASE`MODULE ( i, o); |
`undef MODULE |
input i; |
output o; |
//E2_ifdef SIM_GBUF |
69,33 → 71,45
gbuf gbuf_i0 ( .CLK(i), .GL(o)); |
//E2_endif |
endmodule |
`endif |
|
`else |
|
`ifdef ALTERA |
`ifdef ALTERA |
`ifdef GBUF |
//altera |
module vl_gbuf ( i, o); |
`define MODULE gbuf |
module `BASE`MODULE ( i, o); |
`undef MODULE |
input i; |
output o; |
assign o = i; |
endmodule |
`endif |
|
`else |
|
`ifdef GBUF |
`timescale 1 ns/100 ps |
module vl_gbuf ( i, o); |
`define MODULE |
module `BASE`MODULE ( i, o); |
`undef MODULE |
input i; |
output o; |
assign o = i; |
endmodule |
`endif |
`endif // ALTERA |
`endif //ACTEL |
|
`ifdef SYNC_RST |
// sync reset |
// input active lo async reset, normally from external reset generator and/or switch |
// output active high global reset sync with two DFFs |
`timescale 1 ns/100 ps |
module vl_sync_rst ( rst_n_i, rst_o, clk); |
`define MODULE sync_rst |
module `BASE`MODULE ( rst_n_i, rst_o, clk); |
`undef MODULE |
input rst_n_i, clk; |
output rst_o; |
reg [1:0] tmp; |
104,14 → 118,20
tmp <= 2'b11; |
else |
tmp <= {1'b0,tmp[1]}; |
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o)); |
`define MODULE gbuf |
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o)); |
`undef MODULE |
endmodule |
`endif |
|
`ifdef PLL |
// vl_pll |
`ifdef ACTEL |
/////////////////////////////////////////////////////////////////////////////// |
`timescale 1 ps/1 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`define MODULE pll |
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`undef MODULE |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
201,7 → 221,9
|
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i])); |
`define MODULE sync_rst |
`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i])); |
`undef MODULE |
end |
endgenerate |
endmodule |
214,7 → 236,9
`ifdef ALTERA |
|
`timescale 1 ps/1 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`define MODULE pll |
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`undef MODULE |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
339,7 → 363,9
|
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
`define MODULE sync_rst |
`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
`undef MODULE |
end |
endgenerate |
endmodule |
350,7 → 376,9
|
// generic PLL |
`timescale 1 ps/1 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`define MODULE pll |
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`undef MODULE |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
377,7 → 405,9
|
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
`define MODULE sync_rst |
`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
`undef MODULE |
end |
endgenerate |
|
387,3 → 417,5
|
`endif //altera |
`endif //actel |
`undef MODULE |
`endif |
/verilog/cnt_lfsr_ce_clear_q.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_lfsr_ce_clear_q,LFSR,,,, |
cnt_lfsr_ce_clear_q,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
1,0,1,0,, |
/verilog/logic.v
39,7 → 39,10
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
module vl_mux_andor ( a, sel, dout); |
`ifdef MUX_ANDOR |
`define MODULE mux_andor |
module `BASE`MODULE ( a, sel, dout); |
`undef MODULE |
|
parameter width = 32; |
parameter nr_of_ports = 4; |
59,8 → 62,12
end |
|
endmodule |
`endif |
|
module vl_mux2_andor ( a1, a0, sel, dout); |
`ifdef MUX2_ANDOR |
`define MODULE mux2_andor |
module `BASE`MODULE ( a1, a0, sel, dout); |
`undef MODULE |
|
parameter width = 32; |
localparam nr_of_ports = 2; |
68,13 → 75,19
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
vl_mux_andor |
`define MODULE mux_andor |
`BASE`MODULE |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a1,a0}), .sel(sel), .dout(dout)); |
|
`undef MODULE |
|
endmodule |
`endif |
|
module vl_mux3_andor ( a2, a1, a0, sel, dout); |
`ifdef MUX3_ANDOR |
`define MODULE mux3_andor |
module `BASE`MODULE ( a2, a1, a0, sel, dout); |
`undef MODULE |
|
parameter width = 32; |
localparam nr_of_ports = 3; |
82,13 → 95,18
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
vl_mux_andor |
`define MODULE mux_andor |
`BASE`MODULE |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout)); |
|
`undef MODULE |
endmodule |
`endif |
|
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout); |
`ifdef MUX4_ANDOR |
`define MODULE mux4_andor |
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout); |
`undef MODULE |
|
parameter width = 32; |
localparam nr_of_ports = 4; |
96,13 → 114,19
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
vl_mux_andor |
`define MODULE mux_andor |
`BASE`MODULE |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
`undef MODULE |
|
endmodule |
`endif |
|
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout); |
`ifdef MUX5_ANDOR |
`define MODULE mux5_andor |
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout); |
`undef MODULE |
|
parameter width = 32; |
localparam nr_of_ports = 5; |
110,13 → 134,19
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
vl_mux_andor |
`define MODULE mux_andor |
`BASE`MODULE |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
`undef MODULE |
|
endmodule |
`endif |
|
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout); |
`ifdef MUX6_ANDOR |
`define MODULE mux6_andor |
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout); |
`undef MODULE |
|
parameter width = 32; |
localparam nr_of_ports = 6; |
124,8 → 154,11
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
vl_mux_andor |
`define MODULE mux_andor |
`BASE`MODULE |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
`undef MODULE |
|
endmodule |
`endif |
/verilog/cnt_lfsr.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_lfsr,LFSR,,,, |
cnt_lfsr,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,0,0,, |
/verilog/cnt_bin.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_bin,binary,,,, |
cnt_bin,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,0,0,, |
/verilog/cnt_gray_ce.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_gray_ce,GRAY,,,, |
cnt_gray_ce,GRAY,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,0,, |
/verilog/registers.v
40,8 → 40,10
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module vl_dff ( d, q, clk, rst); |
|
`ifdef DFF |
`define MODULE dff |
module `BASE`MODULE ( d, q, clk, rst); |
`undef MODULE |
parameter width = 1; |
parameter reset_value = 0; |
|
56,8 → 58,12
q <= d; |
|
endmodule |
`endif |
|
module vl_dff_array ( d, q, clk, rst); |
`ifdef DFF_ARRAY |
`define MODULE dff_array |
module `BASE`MODULE ( d, q, clk, rst); |
`undef MODULE |
|
parameter width = 1; |
parameter depth = 2; |
81,8 → 87,12
assign q = q_tmp[depth-1]; |
|
endmodule |
`endif |
|
module vl_dff_ce ( d, ce, q, clk, rst); |
`ifdef DFF_CE |
`define MODULE dff_ce |
module `BASE`MODULE ( d, ce, q, clk, rst); |
`undef MODULE |
|
parameter width = 1; |
parameter reset_value = 0; |
99,8 → 109,12
q <= d; |
|
endmodule |
`endif |
|
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst); |
`ifdef DFF_CE_CLEAR |
`define MODULE dff_ce_clear |
module `BASE`MODULE ( d, ce, clear, q, clk, rst); |
`undef MODULE |
|
parameter width = 1; |
parameter reset_value = 0; |
120,8 → 134,12
q <= d; |
|
endmodule |
`endif |
|
module vl_dff_ce_set ( d, ce, set, q, clk, rst); |
`ifdef DF_CE_SET |
`define MODULE dff_ce_set |
module `BASE`MODULE ( d, ce, set, q, clk, rst); |
`undef MODULE |
|
parameter width = 1; |
parameter reset_value = 0; |
141,9 → 159,13
q <= d; |
|
endmodule |
`endif |
|
module vl_spr ( sp, r, q, clk, rst); |
|
`ifdef SPR |
`define MODULE spr |
module `BASE`MODULE ( sp, r, q, clk, rst); |
`undef MODULE |
|
parameter width = 1; |
parameter reset_value = 0; |
|
161,9 → 183,13
q <= 1'b0; |
|
endmodule |
`endif |
|
module vl_srp ( s, rp, q, clk, rst); |
|
`ifdef SRP |
`define MODULE srp |
module `BASE`MODULE ( s, rp, q, clk, rst); |
`undef MODULE |
|
parameter width = 1; |
parameter reset_value = 0; |
|
181,9 → 207,11
q <= 1'b1; |
|
endmodule |
`endif |
|
`ifdef ALTERA |
|
`ifdef ALTERA |
`ifdef DFF_SR |
// megafunction wizard: %LPM_FF% |
// GENERATION: STANDARD |
// VERSION: WM1.0 |
222,7 → 250,10
// synopsys translate_off |
`timescale 1 ps / 1 ps |
// synopsys translate_on |
module vl_dff_sr ( |
`define MODULE dff_sr |
module `BASE`MODULE ( |
`undef MODULE |
|
aclr, |
aset, |
clock, |
302,13 → 333,15
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE |
// Retrieval info: LIB_FILE: lpm |
`endif |
|
|
`else |
|
`ifdef DFF_SR |
`define MODULE dff_sr |
module `BASE`MODULE ( aclr, aset, clock, data, q); |
`undef MODULE |
|
module vl_dff_sr ( aclr, aset, clock, data, q); |
|
input aclr; |
input aset; |
input clock; |
324,6 → 357,7
q <= data; |
|
endmodule |
`endif |
|
`endif |
|
330,14 → 364,24
// LATCH |
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1 |
`ifdef ALTERA |
module vl_latch ( d, le, q, clk); |
|
`ifdef LATCH |
`define MODULE latch |
module `BASE`MODULE ( d, le, q, clk); |
`undef MODULE |
input d, le; |
output q; |
input clk; |
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q)); |
endmodule |
`endif |
|
`else |
module latch ( d, le, q, clk); |
|
`ifdef LATCH |
`define MODULE latch |
module `BASE`MODULE ( d, le, q, clk); |
`undef MODULE |
input d, le; |
output q; |
input clk;/* |
349,7 → 393,13
endmodule |
`endif |
|
module vl_shreg ( d, q, clk, rst); |
`endif |
|
`ifdef SHREG |
`define MODULE shreg |
module `BASE`MODULE ( d, q, clk, rst); |
`undef MODULE |
|
parameter depth = 10; |
input d; |
output q; |
364,8 → 414,12
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
`endif |
|
module vl_shreg_ce ( d, ce, q, clk, rst); |
`ifdef SHREG_CE |
`define MODULE shreg_ce |
module `BASE`MODULE ( d, ce, q, clk, rst); |
`undef MODULE |
parameter depth = 10; |
input d, ce; |
output q; |
381,8 → 435,12
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
`endif |
|
module vl_delay ( d, q, clk, rst); |
`ifdef DELAY |
`define MODULE delay |
module `BASE`MODULE ( d, q, clk, rst); |
`undef MODULE |
parameter depth = 10; |
input d; |
output q; |
397,8 → 455,12
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
`endif |
|
`ifdef DELAY_EMPTYFLAG |
`define MODULE delay_emptyflag |
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst); |
`undef MODULE |
parameter depth = 10; |
input d; |
output q, emptyflag; |
414,3 → 476,4
assign q = dffs[depth]; |
assign emptyflag = !(|dffs); |
endmodule |
`endif |
/verilog/arith.v
40,8 → 40,11
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`ifdef MULTS |
// signed multiplication |
module vl_mults (a,b,p); |
`define MODULE mults |
module `BASE`MODULE (a,b,p); |
`undef MODULE |
parameter operand_a_width = 18; |
parameter operand_b_width = 18; |
parameter result_hi = 35; |
59,8 → 62,11
assign p = result[result_hi:result_lo]; |
|
endmodule |
|
module vl_mults18x18 (a,b,p); |
`endif |
`ifdef MULTS18X18 |
`define MODULE mults18x18 |
module `BASE`MODULE (a,b,p); |
`undef MODULE |
input [17:0] a,b; |
output [35:0] p; |
vl_mult |
67,9 → 73,13
# (.operand_a_width(18), .operand_b_width(18)) |
mult0 (.a(a), .b(b), .p(p)); |
endmodule |
`endif |
|
`ifdef MULT |
`define MODULE mult |
// unsigned multiplication |
module vl_mult (a,b,p); |
module `BASE`MODULE (a,b,p); |
`undef MODULE |
parameter operand_a_width = 18; |
parameter operand_b_width = 18; |
parameter result_hi = 35; |
84,7 → 94,10
assign p = result[result_hi:result_lo]; |
|
endmodule |
`endif |
|
`ifdef SHIFT_UNIT_32 |
`define MODULE shift_unit_32 |
// shift unit |
// supporting the following shift functions |
// SLL |
91,7 → 104,8
// SRL |
// SRA |
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) |
module vl_shift_unit_32( din, s, dout, opcode); |
module `BASE`MODULE( din, s, dout, opcode); |
`undef MODULE |
input [31:0] din; // data in operand |
input [4:0] s; // shift operand |
input [1:0] opcode; |
132,11 → 146,12
assign sign[2] = sign[3] & (&din[31:24]); |
assign sign[1] = sign[2] & (&din[23:16]); |
assign sign[0] = sign[1] & (&din[15:8]); |
vl_mults `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3])); |
vl_mults `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2])); |
vl_mults `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1])); |
vl_mults `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0])); |
|
`define MODULE mults |
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3])); |
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2])); |
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1])); |
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0])); |
`undef MODULE |
// second stage is multiplexer based |
// shift on byte level |
|
172,7 → 187,9
tmp[3]; |
|
endmodule |
`endif |
|
`ifdef LOGIC_UNIT |
// logic unit |
// supporting the following logic functions |
// a and b |
179,7 → 196,9
// a or b |
// a xor b |
// not b |
module vl_logic_unit( a, b, result, opcode); |
`define MODULE logic_unit |
module `BASE`MODULE( a, b, result, opcode); |
`undef MODULE |
parameter width = 32; |
parameter opcode_and = 2'b00; |
parameter opcode_or = 2'b01; |
209,3 → 228,4
assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) | |
(~a[width-1] & ~b[width-1] & result[width-1]); |
endmodule |
`endif |
/verilog/cnt_bin_ce_clear_l1_l2.csv
1,5 → 1,5
Name,type,,,, |
vl_cnt_bin_ce_clear_l1_l2,binary,,,, |
cnt_bin_ce_clear_l1_l2,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
1,0,1,0,, |