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/rtl/verilog/versatile_library.v
101,6 → 101,7
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// vl_pll |
`ifdef ACTEL |
/////////////////////////////////////////////////////////////////////////////// |
`timescale 1 ps/1 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
parameter index = 0; |
197,13 → 198,157
endgenerate |
endmodule |
`endif |
/////////////////////////////////////////////////////////////////////////////// |
|
`else |
|
/////////////////////////////////////////////////////////////////////////////// |
`ifdef ALTERA |
|
`timescale 1 ps/1 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
parameter period_time_1 = 20000; |
parameter period_time_2 = 20000; |
parameter period_time_3 = 20000; |
parameter period_time_4 = 20000; |
parameter lock_delay = 2000000; |
input clk_i, rst_n_i; |
output lock; |
output reg [0:number_of_clk-1] clk_o; |
output [0:number_of_clk-1] rst_o; |
|
`ifdef SIM_PLL |
|
always |
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0]; |
|
generate if (number_of_clk > 1) |
always |
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1]; |
endgenerate |
|
generate if (number_of_clk > 2) |
always |
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2]; |
endgenerate |
|
always |
#((period_time_3)/2) clk_o[3] <= (!rst_n_i) ? 0 : ~clk_o[3]; |
endgenerate |
|
always |
#((period_time_4)/2) clk_o[4] <= (!rst_n_i) ? 0 : ~clk_o[4]; |
endgenerate |
|
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
end |
endgenerate |
|
assign #lock_delay lock = rst_n_i; |
|
endmodule |
`else |
generate if (number_of_clk==1 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk(clk_i), .locked(lock), .c0(clk_o[0])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==1 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==1 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==1 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0])); |
end |
endgenerate // index==3 |
|
generate if (number_of_clk==2 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==2 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==2 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==2 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); |
end |
endgenerate // index==3 |
|
generate if (number_of_clk==3 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==3 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==3 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==3 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); |
end |
endgenerate // index==3 |
|
generate if (number_of_clk==4 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==4 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==4 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==4 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3])); |
end |
endgenerate // index==3 |
|
generate if (number_of_clk==5 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3], .c4(clk_o[4])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==5 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==5 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==5 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4])); |
end |
endgenerate // index==3 |
|
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i])); |
end |
endgenerate |
endmodule |
`endif |
/////////////////////////////////////////////////////////////////////////////// |
|
`else |
|
// generic PLL |
`timescale 1 ps/1 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
3564,6 → 3709,69
assign wb_ack_o = wb_ack; |
|
endmodule |
|
module vl_wb_dpram ( |
// wishbone slave side a |
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, |
wbsa_clk, wbsa_rst, |
// wishbone slave side a |
wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, |
wbsb_clk, wbsb_rst); |
|
parameter data_width = 32; |
parameter addr_width = 8; |
|
parameter dat_o_mask_a = 1; |
parameter dat_o_mask_b = 1; |
|
input [31:0] wbsa_dat_i; |
input [addr_width-1:2] wbsa_adr_i; |
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i; |
output [31:0] wbsa_dat_o; |
output wbsa_ack_o; |
input wbsa_clk, wbsa_rst; |
|
input [31:0] wbsb_dat_i; |
input [addr_width-1:2] wbsb_adr_i; |
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i; |
output [31:0] wbsb_dat_o; |
output wbsb_ack_o; |
input wbsb_clk, wbsb_rst; |
|
wire wbsa_dat_tmp, wbsb_dat_tmp; |
|
vl_dpram_2r2w # ( |
.data_width(data_width), addr_width(addr_width) ) |
dpram0( |
.d_a(wbsa_dat_i), |
.q_a(wbsa_dat_tmp), |
.adr_a(wbsa_adr_i), |
.we_a(wbsa_we_i), |
.clk_a(wbsa_clk), |
.d_b(wbsb_dat_i), |
.q_b(wbsb_dat_tmp), |
.adr_b(wbsb_adr_i), |
.we_b(wbsb_we_i), |
.clk_b(wbsb_clk) ); |
|
if (dat_o_mask_a==1) generate |
assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}}; |
endgenerate |
if (dat_o_mask_a==0) generate |
assign wbsa_dat_o = wbsa_dat_tmp; |
endgenerate |
|
if (dat_o_mask_b==1) generate |
assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}}; |
endgenerate |
if (dat_o_mask_b==0) generate |
assign wbsb_dat_o = wbsb_dat_tmp; |
endgenerate |
|
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst)); |
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst)); |
|
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Arithmetic functions //// |
/rtl/verilog/versatile_library_actel.v
79,6 → 79,7
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o)); |
endmodule |
// vl_pll |
/////////////////////////////////////////////////////////////////////////////// |
`timescale 1 ps/1 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
parameter index = 0; |
165,6 → 166,7
endgenerate |
endmodule |
`endif |
/////////////////////////////////////////////////////////////////////////////// |
//actel |
////////////////////////////////////////////////////////////////////// |
//// //// |
2960,6 → 2962,58
assign wb_dat_o = wb_dat & {32{wb_ack}}; |
assign wb_ack_o = wb_ack; |
endmodule |
module vl_wb_dpram ( |
// wishbone slave side a |
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, |
wbsa_clk, wbsa_rst, |
// wishbone slave side a |
wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, |
wbsb_clk, wbsb_rst); |
parameter data_width = 32; |
parameter addr_width = 8; |
parameter dat_o_mask_a = 1; |
parameter dat_o_mask_b = 1; |
input [31:0] wbsa_dat_i; |
input [addr_width-1:2] wbsa_adr_i; |
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i; |
output [31:0] wbsa_dat_o; |
output wbsa_ack_o; |
input wbsa_clk, wbsa_rst; |
input [31:0] wbsb_dat_i; |
input [addr_width-1:2] wbsb_adr_i; |
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i; |
output [31:0] wbsb_dat_o; |
output wbsb_ack_o; |
input wbsb_clk, wbsb_rst; |
wire wbsa_dat_tmp, wbsb_dat_tmp; |
vl_dpram_2r2w # ( |
.data_width(data_width), addr_width(addr_width) ) |
dpram0( |
.d_a(wbsa_dat_i), |
.q_a(wbsa_dat_tmp), |
.adr_a(wbsa_adr_i), |
.we_a(wbsa_we_i), |
.clk_a(wbsa_clk), |
.d_b(wbsb_dat_i), |
.q_b(wbsb_dat_tmp), |
.adr_b(wbsb_adr_i), |
.we_b(wbsb_we_i), |
.clk_b(wbsb_clk) ); |
if (dat_o_mask_a==1) generate |
assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}}; |
endgenerate |
if (dat_o_mask_a==0) generate |
assign wbsa_dat_o = wbsa_dat_tmp; |
endgenerate |
if (dat_o_mask_b==1) generate |
assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}}; |
endgenerate |
if (dat_o_mask_b==0) generate |
assign wbsb_dat_o = wbsb_dat_tmp; |
endgenerate |
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst)); |
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst)); |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Arithmetic functions //// |
/rtl/verilog/cnt_lfsr_ce_q_zq.csv
0,0 → 1,14
Name,type,,,, |
vl_cnt_lfsr_ce_q_zq,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,0,, |
,,,,, |
q,q_bin,z,zq,level1,level2 |
1,1,0,1,0,0 |
,,,,, |
wrap,wrap_around,,,, |
1,1,,,, |
,,,,, |
length,clear_value,set_value,wrap_value,level1,level2 |
4,0,1,8,15, |
/rtl/verilog/wb.v
299,3 → 299,66
assign wb_ack_o = wb_ack; |
|
endmodule |
|
module vl_wb_dpram ( |
// wishbone slave side a |
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, |
wbsa_clk, wbsa_rst, |
// wishbone slave side a |
wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, |
wbsb_clk, wbsb_rst); |
|
parameter data_width = 32; |
parameter addr_width = 8; |
|
parameter dat_o_mask_a = 1; |
parameter dat_o_mask_b = 1; |
|
input [31:0] wbsa_dat_i; |
input [addr_width-1:2] wbsa_adr_i; |
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i; |
output [31:0] wbsa_dat_o; |
output wbsa_ack_o; |
input wbsa_clk, wbsa_rst; |
|
input [31:0] wbsb_dat_i; |
input [addr_width-1:2] wbsb_adr_i; |
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i; |
output [31:0] wbsb_dat_o; |
output wbsb_ack_o; |
input wbsb_clk, wbsb_rst; |
|
wire wbsa_dat_tmp, wbsb_dat_tmp; |
|
vl_dpram_2r2w # ( |
.data_width(data_width), addr_width(addr_width) ) |
dpram0( |
.d_a(wbsa_dat_i), |
.q_a(wbsa_dat_tmp), |
.adr_a(wbsa_adr_i), |
.we_a(wbsa_we_i), |
.clk_a(wbsa_clk), |
.d_b(wbsb_dat_i), |
.q_b(wbsb_dat_tmp), |
.adr_b(wbsb_adr_i), |
.we_b(wbsb_we_i), |
.clk_b(wbsb_clk) ); |
|
if (dat_o_mask_a==1) generate |
assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}}; |
endgenerate |
if (dat_o_mask_a==0) generate |
assign wbsa_dat_o = wbsa_dat_tmp; |
endgenerate |
|
if (dat_o_mask_b==1) generate |
assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}}; |
endgenerate |
if (dat_o_mask_b==0) generate |
assign wbsb_dat_o = wbsb_dat_tmp; |
endgenerate |
|
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst)); |
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst)); |
|
endmodule |
/rtl/verilog/versatile_library_altera.v
61,6 → 61,134
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o)); |
endmodule |
// vl_pll |
/////////////////////////////////////////////////////////////////////////////// |
`timescale 1 ps/1 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
parameter period_time_1 = 20000; |
parameter period_time_2 = 20000; |
parameter period_time_3 = 20000; |
parameter period_time_4 = 20000; |
parameter lock_delay = 2000000; |
input clk_i, rst_n_i; |
output lock; |
output reg [0:number_of_clk-1] clk_o; |
output [0:number_of_clk-1] rst_o; |
//E2_ifdef SIM_PLL |
always |
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0]; |
generate if (number_of_clk > 1) |
always |
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1]; |
endgenerate |
generate if (number_of_clk > 2) |
always |
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2]; |
endgenerate |
always |
#((period_time_3)/2) clk_o[3] <= (!rst_n_i) ? 0 : ~clk_o[3]; |
endgenerate |
always |
#((period_time_4)/2) clk_o[4] <= (!rst_n_i) ? 0 : ~clk_o[4]; |
endgenerate |
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
end |
endgenerate |
assign #lock_delay lock = rst_n_i; |
endmodule |
//E2_else |
generate if (number_of_clk==1 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk(clk_i), .locked(lock), .c0(clk_o[0])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==1 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==1 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==1 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0])); |
end |
endgenerate // index==3 |
generate if (number_of_clk==2 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==2 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==2 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==2 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); |
end |
endgenerate // index==3 |
generate if (number_of_clk==3 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==3 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==3 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==3 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); |
end |
endgenerate // index==3 |
generate if (number_of_clk==4 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==4 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==4 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==4 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3])); |
end |
endgenerate // index==3 |
generate if (number_of_clk==5 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3], .c4(clk_o[4])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==5 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==5 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==5 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4])); |
end |
endgenerate // index==3 |
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i])); |
end |
endgenerate |
endmodule |
//E2_endif |
/////////////////////////////////////////////////////////////////////////////// |
//altera |
//actel |
////////////////////////////////////////////////////////////////////// |
2946,6 → 3074,58
assign wb_dat_o = wb_dat & {32{wb_ack}}; |
assign wb_ack_o = wb_ack; |
endmodule |
module vl_wb_dpram ( |
// wishbone slave side a |
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, |
wbsa_clk, wbsa_rst, |
// wishbone slave side a |
wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, |
wbsb_clk, wbsb_rst); |
parameter data_width = 32; |
parameter addr_width = 8; |
parameter dat_o_mask_a = 1; |
parameter dat_o_mask_b = 1; |
input [31:0] wbsa_dat_i; |
input [addr_width-1:2] wbsa_adr_i; |
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i; |
output [31:0] wbsa_dat_o; |
output wbsa_ack_o; |
input wbsa_clk, wbsa_rst; |
input [31:0] wbsb_dat_i; |
input [addr_width-1:2] wbsb_adr_i; |
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i; |
output [31:0] wbsb_dat_o; |
output wbsb_ack_o; |
input wbsb_clk, wbsb_rst; |
wire wbsa_dat_tmp, wbsb_dat_tmp; |
vl_dpram_2r2w # ( |
.data_width(data_width), addr_width(addr_width) ) |
dpram0( |
.d_a(wbsa_dat_i), |
.q_a(wbsa_dat_tmp), |
.adr_a(wbsa_adr_i), |
.we_a(wbsa_we_i), |
.clk_a(wbsa_clk), |
.d_b(wbsb_dat_i), |
.q_b(wbsb_dat_tmp), |
.adr_b(wbsb_adr_i), |
.we_b(wbsb_we_i), |
.clk_b(wbsb_clk) ); |
if (dat_o_mask_a==1) generate |
assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}}; |
endgenerate |
if (dat_o_mask_a==0) generate |
assign wbsa_dat_o = wbsa_dat_tmp; |
endgenerate |
if (dat_o_mask_b==1) generate |
assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}}; |
endgenerate |
if (dat_o_mask_b==0) generate |
assign wbsb_dat_o = wbsb_dat_tmp; |
endgenerate |
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst)); |
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst)); |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Arithmetic functions //// |
/rtl/verilog/clk_and_reset.v
101,6 → 101,7
|
// vl_pll |
`ifdef ACTEL |
/////////////////////////////////////////////////////////////////////////////// |
`timescale 1 ps/1 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
parameter index = 0; |
197,11 → 198,155
endgenerate |
endmodule |
//E2_endif |
/////////////////////////////////////////////////////////////////////////////// |
|
`else |
|
/////////////////////////////////////////////////////////////////////////////// |
`ifdef ALTERA |
|
`timescale 1 ps/1 ps |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
parameter period_time_1 = 20000; |
parameter period_time_2 = 20000; |
parameter period_time_3 = 20000; |
parameter period_time_4 = 20000; |
parameter lock_delay = 2000000; |
input clk_i, rst_n_i; |
output lock; |
output reg [0:number_of_clk-1] clk_o; |
output [0:number_of_clk-1] rst_o; |
|
//E2_ifdef SIM_PLL |
|
always |
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0]; |
|
generate if (number_of_clk > 1) |
always |
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1]; |
endgenerate |
|
generate if (number_of_clk > 2) |
always |
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2]; |
endgenerate |
|
always |
#((period_time_3)/2) clk_o[3] <= (!rst_n_i) ? 0 : ~clk_o[3]; |
endgenerate |
|
always |
#((period_time_4)/2) clk_o[4] <= (!rst_n_i) ? 0 : ~clk_o[4]; |
endgenerate |
|
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
end |
endgenerate |
|
assign #lock_delay lock = rst_n_i; |
|
endmodule |
//E2_else |
generate if (number_of_clk==1 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk(clk_i), .locked(lock), .c0(clk_o[0])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==1 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==1 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==1 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0])); |
end |
endgenerate // index==3 |
|
generate if (number_of_clk==2 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==2 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==2 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==2 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); |
end |
endgenerate // index==3 |
|
generate if (number_of_clk==3 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==3 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==3 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==3 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); |
end |
endgenerate // index==3 |
|
generate if (number_of_clk==4 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==4 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==4 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==4 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3])); |
end |
endgenerate // index==3 |
|
generate if (number_of_clk==5 & index==0) begin |
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3], .c4(clk_o[4])); |
end |
endgenerate // index==0 |
generate if (number_of_clk==5 & index==1) begin |
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4])); |
end |
endgenerate // index==1 |
generate if (number_of_clk==5 & index==2) begin |
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4])); |
end |
endgenerate // index==2 |
generate if (number_of_clk==5 & index==3) begin |
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4])); |
end |
endgenerate // index==3 |
|
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i])); |
end |
endgenerate |
endmodule |
//E2_endif |
/////////////////////////////////////////////////////////////////////////////// |
|
`else |
|
// generic PLL |
/rtl/verilog/logic.v
0,0 → 1,110
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Logic functions //// |
//// //// |
//// Description //// |
//// Logic functions such as multiplexers //// |
//// //// |
//// //// |
//// To Do: //// |
//// - //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout); |
|
parameter width = 32; |
parameter nr_of_ports = 4; |
input [width-1:0] a3, a2, a1, a0; |
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
|
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
|
// or |
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
|
endmodule |
|
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout); |
|
parameter width = 32; |
parameter nr_of_ports = 5; |
input [width-1:0] a4, a3, a2, a1, a0; |
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
|
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
assign tmp[4] = {width{sel[4]}} & a4; |
|
// or |
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
|
endmodule |
|
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout); |
|
parameter width = 32; |
parameter nr_of_ports = 6; |
input [width-1:0] a5, a4, a3, a2, a1, a0; |
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
wire [width-1:0] tmp [nr_of_ports-1:0]; |
integer i; |
|
// and |
assign tmp[0] = {width{sel[0]}} & a0; |
assign tmp[1] = {width{sel[1]}} & a1; |
assign tmp[2] = {width{sel[2]}} & a2; |
assign tmp[3] = {width{sel[3]}} & a3; |
assign tmp[4] = {width{sel[4]}} & a4; |
assign tmp[5] = {width{sel[5]}} & a5; |
|
// or |
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0]; |
|
endmodule |