URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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- This comparison shows the changes necessary to convert path
/versatile_library/trunk
- from Rev 77 to Rev 78
- ↔ Reverse comparison
Rev 77 → Rev 78
/rtl/verilog/versatile_library.v
4743,7 → 4743,7
wbs_eoc <= 1'b0; |
else |
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full) |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111); |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111); |
else if (wbs_eoc_alert & (a_rd | a_wr)) |
wbs_eoc <= 1'b1; |
|
4945,7 → 4945,8
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010; |
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 : |
(wbm_bte_o==2'b10) ? 4'd8 : |
4'd16; |
(wbm_bte_o==2'b11) ? 4'd16: |
4'd1; |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o; |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o; |
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest); |
4968,7 → 4969,7
.wbs_rst(wbs_rst), |
// wishbone master side |
.wbm_dat_o(writedata), |
.wbm_adr_o(adress), |
.wbm_adr_o(address), |
.wbm_sel_o(be), |
.wbm_bte_o(wbm_bte_o), |
.wbm_cti_o(wbm_cti_o), |
/rtl/verilog/versatile_library_actel.v
1991,7 → 1991,7
wbs_eoc <= 1'b0; |
else |
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full) |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111); |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111); |
else if (wbs_eoc_alert & (a_rd | a_wr)) |
wbs_eoc <= 1'b1; |
vl_cnt_shreg_ce_clear # ( .length(16)) |
2155,7 → 2155,8
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010; |
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 : |
(wbm_bte_o==2'b10) ? 4'd8 : |
4'd16; |
(wbm_bte_o==2'b11) ? 4'd16: |
4'd1; |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o; |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o; |
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest); |
2175,7 → 2176,7
.wbs_rst(wbs_rst), |
// wishbone master side |
.wbm_dat_o(writedata), |
.wbm_adr_o(adress), |
.wbm_adr_o(address), |
.wbm_sel_o(be), |
.wbm_bte_o(wbm_bte_o), |
.wbm_cti_o(wbm_cti_o), |
/rtl/verilog/wb.v
148,7 → 148,7
wbs_eoc <= 1'b0; |
else |
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full) |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111); |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111); |
else if (wbs_eoc_alert & (a_rd | a_wr)) |
wbs_eoc <= 1'b1; |
|
350,7 → 350,8
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010; |
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 : |
(wbm_bte_o==2'b10) ? 4'd8 : |
4'd16; |
(wbm_bte_o==2'b11) ? 4'd16: |
4'd1; |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o; |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o; |
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest); |
373,7 → 374,7
.wbs_rst(wbs_rst), |
// wishbone master side |
.wbm_dat_o(writedata), |
.wbm_adr_o(adress), |
.wbm_adr_o(address), |
.wbm_sel_o(be), |
.wbm_bte_o(wbm_bte_o), |
.wbm_cti_o(wbm_cti_o), |
/rtl/verilog/versatile_library_altera.v
2096,7 → 2096,7
wbs_eoc <= 1'b0; |
else |
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full) |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111); |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111); |
else if (wbs_eoc_alert & (a_rd | a_wr)) |
wbs_eoc <= 1'b1; |
vl_cnt_shreg_ce_clear # ( .length(16)) |
2260,7 → 2260,8
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010; |
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 : |
(wbm_bte_o==2'b10) ? 4'd8 : |
4'd16; |
(wbm_bte_o==2'b11) ? 4'd16: |
4'd1; |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o; |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o; |
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest); |
2280,7 → 2281,7
.wbs_rst(wbs_rst), |
// wishbone master side |
.wbm_dat_o(writedata), |
.wbm_adr_o(adress), |
.wbm_adr_o(address), |
.wbm_sel_o(be), |
.wbm_bte_o(wbm_bte_o), |
.wbm_cti_o(wbm_cti_o), |