URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library
- from Rev 146 to Rev 147
- ↔ Reverse comparison
Rev 146 → Rev 147
/trunk/rtl/verilog/versatile_library.v
5005,7 → 5005,7
input [dw-1:0] wd3; |
input we3; |
output [dw-1:0] rd1, rd2; |
input clk; |
input clk, rst; |
wire [dw-1:0] rd1mem, rd2mem; |
reg [dw-1:0] wreg; |
reg sel1, sel2; |
/trunk/rtl/verilog/versatile_library_actel.v
3404,7 → 3404,7
input [dw-1:0] wd3; |
input we3; |
output [dw-1:0] rd1, rd2; |
input clk; |
input clk, rst; |
wire [dw-1:0] rd1mem, rd2mem; |
reg [dw-1:0] wreg; |
reg sel1, sel2; |
/trunk/rtl/verilog/versatile_library_altera.v
3499,7 → 3499,7
input [dw-1:0] wd3; |
input we3; |
output [dw-1:0] rd1, rd2; |
input clk; |
input clk, rst; |
wire [dw-1:0] rd1mem, rd2mem; |
reg [dw-1:0] wreg; |
reg sel1, sel2; |
/trunk/rtl/verilog/memories.v
1095,7 → 1095,7
input [dw-1:0] wd3; |
input we3; |
output [dw-1:0] rd1, rd2; |
input clk; |
input clk, rst; |
wire [dw-1:0] rd1mem, rd2mem; |
reg [dw-1:0] wreg; |
reg sel1, sel2; |