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/rtl/verilog/sdr_sdram_16_ctrl.v

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/doc/src/tRCD.png

doc/src/tRCD.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/src/versatile_mem_ctrl.texi =================================================================== --- doc/src/versatile_mem_ctrl.texi (revision 105) +++ doc/src/versatile_mem_ctrl.texi (revision 106) @@ -60,269 +60,255 @@ This design implements a versatile memory controller. If used in combination with the versitale library, available from OpenCores, different types of system can easily be designed, including use cases where the system bus is in one clock domain and the memory controller in an other. + +@section Dependencies to other IP cores + +This design uses the following IP coreas available from OpenCores project verstile library. +@itemize @bullet +@item vl_cnt_shreg_ce_clear +@item vl_dff_ce_clear +@item vl_cnt_lfsr_zq +@item vl_dff +@item vl_o_dff +@item vl_io_dff_oe +@end itemize + @node Block diagram @chapter Block Diagram @cindex Block diagram -@section Clock domains -@value{DESIGN} contains the following clock domains -@itemize -@item Wishbone slave clock domain -@item Wishbone master clock domain -@item RX GMII clock domain -@item TX GMII clock domain -@end itemize +@section Synchronous design +@image{block-sdram} +Synchronous design where wishbone clock domain is equal to SDRAM and SDRAM controller clock domain. -@node Configuration registers -@chapter Configuration registers +@section Asynchronous design +@image{block-sdram-wbwb} +Asynchronous design where wishbone and SDRAM clock domain are independant. A wishbone rev B3 compatilble bridge +is available in project versatile_library from OpenCores, http://www.opencores.org. -@section Register memory map -@multitable @columnfractions .2 .1 .1 .1 .5 -@headitem Name @tab Address @tab Width @tab Access @tab Description -@item MODER @tab @value{MODER} @tab 32 @tab RW @tab Mode register -@item INT_SOURCE @tab @value{INT_SOURCE} @tab 32 @tab RW @tab Interrupt source register -@item INT_MASK @tab @value{INT_MASK} @tab 32 @tab RW @tab Interrupt mask register -@item TX_BD_NUM @tab @value{TX_BD_NUM} @tab 32 @tab RW @tab Transmit Buffer Descriptor number -@item MIIMODER @tab @value{MIIMODER} @tab 32 @tab RW @tab MII Mode Register -@item MIICOMMAND @tab @value{MIICOMMAND} @tab 32 @tab RW @tab MII Command Register -@item MIIADDRESS @tab @value{MIIADDRESS} @tab 32 @tab RW @tab MII Address Register -@item MIITX_DATA @tab @value{MIITX_DATA} @tab 32 @tab RW @tab MII Transmit Data -@item MIIRX_DATA @tab @value{MIIRX_DATA} @tab 32 @tab RW @tab MII Receive Data -@item MIISTATUS @tab @value{MIISTATUS} @tab 32 @tab RW @tab MII Status Register -@item MAC_ADDR0 @tab @value{MAC_ADDR0} @tab 32 @tab RW @tab MAC address, LSB four bytes -@item MAC_ADDR1 @tab @value{MAC_ADDR1} @tab 32 @tab RW @tab MAC address, MSB two bytes -@end multitable +@section Asynchronous design with multiple wishbone interfaces +@image{block-sdram-wbwb-arbiter} +Asynchronous design where wishbone and SDRAM clock domain are independant. Multiple wishbone port with use of a wishbone arbiter. -@page +@node SDR SDRAM controller +@chapter SDR SDRAM controller -@subsection MODER -@multitable @columnfractions .1 .1 .2 .6 -@headitem Bit @tab Access @tab Description @tab -@item 31-17 @tab @tab Reserved -@item 16 @tab RW @tab RECSMALL @tab Receive small packets -@item 15 @tab RW @tab PAD @tab Padding enabled -@item 14 @tab RW @tab HUGEN @tab Huge Packets Enable -@item 13 @tab RW @tab CRCEN @tab CRC enable -@item 12-8 @tab @tab Reserved -@item 7 @tab RW @tab LOOPBCK @tab Loopback -@item 6 @tab RW @tab Resrved -@item 5 @tab RW @tab PRO @tab Promiscuous -@item 4 @tab @tab Reserved -@item 3 @tab RW @tab BRO @tab Broadcast Address -@item 2 @tab @tab Reserved -@item 1 @tab RW @tab TXEN @tab Transmit Enable -@item 0 @tab RW @tab RXEN @tab Receive Enable +@section Module defines +@multitable @columnfractions .2 .8 +@headitem Name @tab Description +@item NO_BURST @tab Define if burst cycles not used +@item WRAP4 @tab Define to support 4 word wrap burst +@item WRAP8 @tab Define to support 8 word wrap burst +@item WRAP16 @tab Define to support 16 word wrap burst @end multitable -@example -Reset value: -MODER: 0x0000A000 -@end example -@page +@section Module parameters -@subsection INT_SOURCE -@multitable @columnfractions .1 .1 .2 .6 -@headitem Bit @tab Access @tab Description @tab -@item 31-7 @tab @tab Reserved -@item 4 @tab RW @tab BUSY @tab Busy@* This bit indicates that a buffer was received and discarded due to a lack of buffers. It is cleared by writing 1 to it. This bit appears regardless to the IRQ bits in the Receive or Transmit Buffer Descriptors. -@item 3 @tab RW @tab RXE @tab Receive error@* This bit indicates that an error occurred while receiving data. It is cleared by writing 1 to it. This bit appears only when IRQ bit is set in the Receive Buffer Descriptor. -@item 2 @tab RW @tab RXB @tab Receive buffer@* This bit indicates that a frame was received. It is cleared by writing 1 to it. This bit appears only when IRQ bit is set in the Receive Buffer Descriptor. If a control frame is received, then RXC bit is set instead of the RXB bit. -@item 1 @tab RW @tab TXE @tab Transmit error@* This bit indicates that a buffer was not transmitted due to a transmit error. It is cleared by writing 1 to it. This bit appears only when IRQ bit is set in the Receive Buffer Descriptor. This bit appears only when IRQ bit is set in the Transmit Buffer Descriptor. -@item 0 @tab RW @tab TXB @tab Transmit buffer@* This bit indicates that a buffer has been transmitted. It is cleared by writing 1 to it. This bit appears only when IRQ bit is set in the Transmit Buffer Descriptor. +@multitable @columnfractions .2 .1 .7 +@headitem Name @tab Default value @tab Description +@item ba_size @tab 2 @tab Bank adress vector size +@item row_size @tab 13 @tab Row adress vector size +@item col_size @tab 9 @tab Column adress vector size +@item cl @tab 2 @tab CAS latency @end multitable -@example -Reset value: -INT_SOURCE: 0x00000000 -@end example -@page -@subsection INT_MASK -@multitable @columnfractions .1 .1 .2 .6 -@headitem Bit @tab Access @tab Description @tab -@item 31-7 @tab @tab Reserved -@item 4 @tab RW @tab BUSY_M @tab Busy mask@* -@item 3 @tab RW @tab RXE_M @tab Receive error@* Receive error mask -@item 2 @tab RW @tab RXB_M @tab Receive buffer@* Receive buffer mask -@item 1 @tab RW @tab TXE_M @tab Transmit error@* Transmit error mask -@item 0 @tab RW @tab TXB_M @tab Transmit buffer@* Transmit buffer mask -@end multitable -@example -Reset value: -INT_MASK: 0x00000000 -@*@* -0 -> event masked -1 -> event causes an interrupt -@end example +Parameters ba_size, col_size and row_size should be set depending on memory configuration. The following +table holds figures for some SDRAM memories. -@page -@subsection TX_BD_NUM -@multitable @columnfractions .1 .1 .2 .6 -@headitem Bit @tab Access @tab Description @tab -@item 31-8 @tab @tab Reserved -@item 7-0 @tab RW @tab TX_BD_NUM @tab Transmit Buffer Descriptor Number@* Number of the Tx BD. Number of the Rx BD equals to the (0x80 – Tx BD number). Maximum number of the Tx BD is 0x80. Values greater then 0x80 cannot be written to this register (ignored). +@multitable @columnfractions .15 .25 .1 .1 .1 .3 +@headitem Manufacturer @tab Partnumber @tab ba_size @tab row_size @tab col_size @tab Memory size +@item Micron @tab MT48LC4M16 @tab 2 @tab 12 @tab 8 @tab 8Mbyte +@item Micron @tab MT48LC8M16 @tab 2 @tab 12 @tab 9 @tab 16Mbyte +@item Micron @tab MT48LC16M16 @tab 2 @tab 13 @tab 9 @tab 32Mbyte +@item Micron @tab MT48LC32M16 @tab 2 @tab 13 @tab 10 @tab 64Mbyte @end multitable -@example -Reset value: -TX_BD_NUM: 0x00000040 -@end example -@page -@subsection MIIMODER -@multitable @columnfractions .1 .1 .2 .6 -@headitem Bit @tab Access @tab Description @tab -@item 31-9 @tab @tab Reserved -@item 8 @tab RW @tab MIINOPRE @tab No Preamble@* 0 = 32 bit preamble sent@* 1 = No preamble sent -@item 7-0 @tab RW @tab CLKDIV @tab Clock divider The field is a host clock divider factor. The host clock can be divided by an even number, greater then 1. The default value is 0x64 (100). -@end multitable -@example -Reset value: -MIIMODER: 0x00000064 -@end example +Parameter cl should be set to either 2 or 3 depending on SDRAM clock. -@subsection MIICOMMAND -@multitable @columnfractions .1 .1 .2 .6 -@headitem Bit @tab Access @tab Description @tab -@item 31-3 @tab @tab Reserved -@item 2 @tab RW @tab WCTRLDATA @tab Write control data -@item 1 @tab RW @tab RSTAT @tab Read status -@item 0 @tab RW @tab SCANSTAT @tab Scan status +@section Module IO signals +@subsection Wishbone signals +@multitable @columnfractions .2 .1 .1 .6 +@headitem Name @tab Dir @tab Width @tab Description +@item dat_i @tab I @tab 32 @tab Input data vector +@item adr_i @tab I @tab @tab Adress vector +@item sel_i @tab I @tab 4 @tab Byte select signals +@item bte_i @tab I @tab 2 @tab Bus tag identifier +@item we_i @tab I @tab 1 @tab Write enable +@item cyc_i @tab I @tab 1 @tab Active cycle indicator +@item stb_i @tab I @tab 1 @tab Strobe +@item dat_o @tab O @tab 32 @tab Output data vector +@item ack_o @tab O @tab 1 @tab Acknowledge signal @end multitable -@example -Reset value: -MIICOMMAND: 0x00000000 -@end example -@subsection MIIADDRESS -@multitable @columnfractions .1 .1 .2 .6 -@headitem Bit @tab Access @tab Description @tab -@item 31-13 @tab @tab Reserved -@item 12-8 @tab RW @tab RGAD @tab Register address -@item 7-5 @tab RW @tab Reserved @tab -@item 4-0 @tab RW @tab FIAD @tab PHY address +Wishbone signal bte_i is optional and is only used for designs supporting burst transfer. +@subsection SDRAM signals +@multitable @columnfractions .2 .1 .1 .6 +@headitem Name @tab Dir @tab Width @tab Description +@item ba @tab O @tab ba_size @tab Bank adress vector +@item a @tab O @tab 13 @tab Adress vector +@item cmd @tab O @tab 3 @tab SDRAM command, {ras_n, cas_n, we_n} +@item cke @tab O @tab 1 @tab Clock enable +@item cs_n @tab O @tab 1 @tab Chip select, active low +@item dqm @tab O @tab 2 @tab Data mask +@item dq_i @tab I @tab 16 @tab Data input vector +@item dq_o @tab O @tab 16 @tab Data output vector +@item dq_oe @tab O @tab 1 @tab Data output enable @end multitable -@example -Reset value: -MIIADDRESS: 0x00000000 -@end example -@subsection MIITX_DATA -@multitable @columnfractions .1 .1 .2 .6 -@headitem Bit @tab Access @tab Description @tab -@item 31-16 @tab @tab Reserved -@item 15-0 @tab RW @tab CTRLDATA @tab Data to be written to the PHY +@subsection System signals +@multitable @columnfractions .2 .1 .1 .6 +@headitem Name @tab Dir @tab Width @tab Description +@item clk @tab I @tab 1 @tab SDRAM system clock +@item rst @tab I @tab 1 @tab Asynchronous reset, active hig @end multitable -@example -Reset value: -MIITX_DATA: 0x00000000 -@end example -@subsection MIIRX_DATA -@multitable @columnfractions .1 .1 .2 .6 -@headitem Bit @tab Access @tab Description @tab -@item 31-16 @tab @tab Reserved -@item 15-0 @tab R @tab PRSD @tab Data read from the PHY -@end multitable -@example -Reset value: -MIIRX_DATA: 0x00000000 -@end example +@node SDR SDRAM 16 bit data bus controller +@chapter SDR SDRAM 16 bit data bus controller +@cindex SDR SDRAM 16 bit data bus controller -@subsection MIISTATUS -@multitable @columnfractions .1 .1 .2 .6 -@headitem Bit @tab Access @tab Description @tab -@item 31-3 @tab @tab Reserved -@item 2 @tab R @tab NVALID @tab Invalid@* 0 = The data in the MSTATUS register is valid.@* 1 = The data in the MSTATUS register is invalid.@* This bit is only valid when the scan status operation is active. -@item 1 @tab R @tab BUSY @tab 0 = The MII is ready.@* 1 = The MII is busy (operation in progress). -@item 0 @tab R @tab LINKFAIL @tab 0 = The link is OK.@*1 = The link failed.@*The Link fail condition occurred (now the link might be OK). Another status read gets a new status. -@end multitable -@example -Reset value: -MIISTATUS: 0x00000000 -@end example +@section State machine implementation -@page -@subsection MAC_ADDR0 -@multitable @columnfractions .1 .1 .8 -@headitem Bit @tab Access @tab Description @tab -@item 31-24 @tab RW @tab Byte 2 of the Ethernet MAC address -@item 23-16 @tab RW @tab Byte 3 of the Ethernet MAC address -@item 15-8 @tab RW @tab Byte 4 of the Ethernet MAC address -@item 7-0 @tab RW @tab Byte 5 of the Ethernet MAC address -@end multitable -@example -Reset value: -MAC_ADDR0: 0x00000000 -@end example +Design is based on a state machine as described below. -@subsection MAC_ADDR1 -@multitable @columnfractions .1 .1 .8 -@headitem Bit @tab Access @tab Description @tab -@item 31-16 @tab @tab Reserved -@item 15-8 @tab RW @tab Byte 0 of the Ethernet MAC address -@item 7-0 @tab RW @tab Byte 1 of the Ethernet MAC address -@end multitable -@example -Reset value: -MAC_ADDR1: 0x00000000 -@end example +@image{sdr_sdram_16,14cm,16cm,,.png} -@node MDIO -@chapter Management Data Input/Output - -The MDIO interface is implemented by two lines: +A counter is incremented on each cycle the state machine reside in any given state. +When changing state a counter clear is issued. The counter state vector is used for +two things @itemize -@item a MDC clock line -@item an MDIO data line +@item controlling outputs, ie defining cmd and other control signals +@item to make sure timing reqiurements are fulfilled, ie define time from precharge to activate @end itemize -The clock line is driven by the MAC device. The data line is bidirectional: the PHY drives it to provide register data at the end of a read operation. -@*@* -The bus has a single MAC master, but can have up to 32 PHY slaves. -@*@* -The MDC clock can be aperiodic, with a minimum period of 400 ns, which corresponds to a maximal frequency of 2.5 MHz. Newer chips, however, allow faster acesses. -@*@* -The MDIO data line has a pull-up of 1.5 kOhm in the PHY, allowing the MAC to determine if one or more PHYs are attached. The MAC should have a 2 kOhm pull-down on that same line. +@subsection State - init -@section Bus timing -@subsection Read operation -A read operation has the following phases +The init state is responsible to make sure that a proper start-up and initialization of the SDRAM is +performed. The following sequence should be applied: +@enumerate +@item assert CKE low +@item provide stable clock +@item bring CKE high +@item perform PRECHARGE ALL command and wait for tRP +@item issue AUTO RERFESH and wait for tRFC +@item issue AUTO RERFESH and wait for tRFC +@item LOAD MODE REGISTER and wait for tMR +@end enumerate +After this state machine advances to idle state + +@subsection State - idle + +In state idle implementation awaits two different condition, appearing in order of priority +@enumerate +@item refresh request => next state is rfr +@item cyc_i & stb_i => next state is adr +@end enumerate + + +@subsection State - adr + +Depending on status of open bank and open rows choice is taken whether to precharge and activate, activate or go +directly to read write state. Reason for this as a separate state is to be able to have comparison result as a +registered signal to achive an higher clock frequency. + +@subsection State - pch + +Open row in current bank is deactivated. State machine waits in pch state to fulfill tRP. + +@subsection State - act + +Row in current bank is activated. State machine waits in act state to fulfill tRCD. + +@subsection State - rw + +A two word read or write burst is started. If wishbone cycle is of type burst column will get incremented +with possible wrap around and a new burst started for each 32 bit word. + +@section Timing + +The follwoing timing requirements must be fulfilled: + @itemize -@item Preamble with 32 ones -@item Start sequence, 01 -@item Opcode read, 10 -@item PHY adress -@item REG adress -@item Bus turnaround -@item Register data +@item tMR - Load Mode Register period +@item tRCD - Active to read/write delay +@item tRP - Precharge command period +@item tRFC - Auto refresh period +@item tREF - refresh period @end itemize -@image{MDIO_rd,15cm,2.54cm} -@subsection Write operation -A write operation has the following phases +In the SDRAM datasheet the above timing figures will be given in ns and should be +converted to number of clock cycles. All of the above timing figures, except tREF, are implemented as parameters +in the design and should be set depending on SDRAM figures and actual clock period. All +parameters have default values of 2 clock cycles. + +@subsection Bank/Row activation - tRCD + +@image{tRCD,15cm,5cm,,.png} + +Minimum time between activation of and read or write command. +@subsection Auto refresh mode + +@image{aref,15cm,15cm,,.png} + +Minumum time between precharge and auto refresh and active command. + +@subsection Refresh period - tREF + +The auto refresh period, tREF must be met. During auto refresh an internal address counter +is used and adress signals are treated as don't care. During the refresh period each row must +be refreshed. @* +For example consider a SDRAM with tREF = 64 ms and row size of 8K. An auto refresh command +should be issued once every 64 ms / 8192 = 7.813 us.@* +The refresh interval counter is implemented as an LFSR style counter for minimal area and maximum +performance. To accurately set the wrap value for this counter use the application VersatileCounter found +in the versatile library project at opencores. This program gives the wrap value for a given vector length. +Assuming an SDRAM clock frequency of 133 MHz which equals a period time of 7.5 ns we should issue an auto +refresh every 7.813 us / 7.5 ns = 1041 cycle. We need a state vector of 11 bits in the counter.@* +To get the wrap value we use the application@* +@command{./VersatileCounter.php 11 1041@*11111110101} + +@node Example: Timing setup +@chapter Example: Timing setup + +@section Requirements + +SDRAM device to use: @itemize -@item Preamble with 32 ones -@item Start sequence, 01 -@item Opcode read, 01 -@item PHY adress -@item REG adress -@item Bus turnaround -@item Register data +@item Micron MT48LC32M16-7E @end itemize -@image{MDIO_wr,15cm,2.54cm} -@node Ingress and Egress FIFO -@chapter Ingress and Egress FIFO +@multitable @columnfractions .4 .2 .1 .1 .1 .1 +@headitem Parameter @tab Symbol @tab Min @tab Max @tab Unit +@item Auto refresh period @tab tRFC @tab 66 @tab - @tab ns +@item Precharge command period @tab tRP @tab 15 @tab - @tab ns +@item Active to read or write delay @tab tRCD @tab 15 @tab - @tab ns +@item Load mode register command to active or refresh @tab tMRD @tab 2 @tab - @tab tCK +@item Refresh periods (8192 rows) @tab tREF @tab 66 @tab -@tab ms +@end multitable -@section FIFO implementation -Both ingress and egress FIFO implementation uses a generic asynchronous FIFO design -available from OpenCores.@*@* -@uref{http://opencores.org/project,versatile_library} +Intended operating frequency is 75 MHz, tCK = 13.333 ns +@section Parameter settings + +@multitable @columnfractions .2 .8 +@headitem Symbol @tab Value +@item tRFC @tab 5 +@item tRP @tab 2 +@item tRCD @tab 2 +@item tMRD @tab 2 +@end multitable +@* +Refresh rate is 66 ms / 8192 = 8.057 us@* +Number of clock cycles between refresh request 8.057 us / 13.333 ns = 604@* +@* +To get the wrap value we use the application from Versatile Library@* +@command{./VersatileCounter.php 10 604@*0101001110} + + @c **************************************************************************** @c End bits @c **************************************************************************** -@node GNU Free Documentation License +@node GNU Free Documentation License @chapter GNU Free Documentation License @cindex license for @value{DESIGN}

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doc/src/aref.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/src/sdr_sdram_16.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/src/sdr_sdram_16.png =================================================================== --- doc/src/sdr_sdram_16.png (nonexistent) +++ doc/src/sdr_sdram_16.png (revision 106)

doc/src/sdr_sdram_16.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/src/sdr_sdram_16.fsm =================================================================== --- doc/src/sdr_sdram_16.fsm (nonexistent) +++ doc/src/sdr_sdram_16.fsm (revision 106) @@ -0,0 +1,75 @@ + + + + + s_out7,s_out6,s_out5,s_out4,s_out3,s_out2,s_out1,s_out0 + i_7,i_6,i_5,i_4,i_3,i_2,i_1,i_0 + o_7,o_6,o_5,o_4,o_3,o_2,o_1,o_0 + + init + idle + rfr + adr + rw + pch + act + + 0 + 1 + init_done + + + + 1 + 2 + refresh_req + + + + 1 + 3 + cyc&stb + + + + 2 + 1 + tRFC + + + + 3 + 6 + current_bank_closed + + + + 3 + 4 + current_row_open + + + + 3 + + + + + 5 + 6 + tRP + + + + 6 + 4 + tRCD + + + + 1 + end_of_cycle + + + + Index: doc/src/Makefile =================================================================== --- doc/src/Makefile (revision 105) +++ doc/src/Makefile (revision 106) @@ -4,5 +4,6 @@ texinfo: texi2pdf versatile_mem_ctrl.texi + mv versatile_mem_ctrl.pdf ../ all: texinfo

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