URL
https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk
Subversion Repositories vga_lcd
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 45 to Rev 46
- ↔ Reverse comparison
Rev 45 → Rev 46
/trunk/bench/verilog/test_bench_top.v
37,10 → 37,10
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// CVS Log |
// |
// $Id: test_bench_top.v,v 1.5 2003-03-19 12:20:53 rherveille Exp $ |
// $Id: test_bench_top.v,v 1.6 2003-03-19 17:22:19 rherveille Exp $ |
// |
// $Date: 2003-03-19 12:20:53 $ |
// $Revision: 1.5 $ |
// $Date: 2003-03-19 17:22:19 $ |
// $Revision: 1.6 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,10
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2003/03/19 12:20:53 rherveille |
// Changed timing section in VGA core, changed testbench accordingly. |
// Fixed bug in 'timing check' test. |
// |
// Revision 1.4 2002/02/07 05:38:32 rherveille |
// Added wb_ack delay section to testbench |
// |
73,6 → 77,8
wire wb_we_o; |
wire wb_stb_o; |
wire wb_cyc_o; |
wire [2:0] wb_cti_o; |
wire [1:0] wb_bte_o; |
wire wb_ack_i; |
wire wb_err_i; |
wire [31:0] wb_addr_i; |
443,7 → 449,7
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@(posedge pclk); |
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end |
end |
end |
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show_errors; |
463,7 → 469,7
// Sync Monitor |
// |
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sync_check #(PCLK_C) uceck( |
sync_check #(PCLK_C) ucheck( |
.pclk( pclk ), |
.rst( rst ), |
.enable( scen ), |
491,6 → 497,23
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///////////////////////////////////////////////////////////////////// |
// |
// WISHBONE revB.3 checker |
// |
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wb_b3_check u_wb_check ( |
.clk_i ( clk ), |
.cyc_i ( wb_cyc_o ), |
.stb_i ( wb_stb_o ), |
.cti_i ( wb_cti_o ), |
.bte_i ( wb_bte_o ), |
.we_i ( wb_we_i ), |
.ack_i ( wb_ack_i ), |
.err_i ( wb_err_i ), |
.rty_i ( 1'b0 ) ); |
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///////////////////////////////////////////////////////////////////// |
// |
// Watchdog Counter |
// |
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526,13 → 549,12
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///////////////////////////////////////////////////////////////////// |
// |
// WISHBONE DMA IP Core |
// WISHBONE VGA/LCD IP Core |
// |
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// Module Prototype |
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`ifdef USE_VC |
vga_enh_top #(1'b0, LINE_FIFO_AWIDTH) u0 ( |
.wb_clk_i ( clk ), |
.wb_rst_i ( 1'b0 ), |
573,48 → 595,6
.b_pad_o ( blue ) |
); |
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`else |
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VGA u0 ( .CLK_I( clk_v ), |
.RST_I( ~rst ), |
.NRESET( rst ), |
.INTA_O( int ), |
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//-- slave signals |
.ADR_I( wb_addr_i[4:2] ), |
.SDAT_I( wb_data_i ), |
.SDAT_O( wb_data_o ), |
.SEL_I( wb_sel_i ), |
.WE_I( wb_we_i ), |
.STB_I( wb_stb_i ), |
.CYC_I( wb_cyc_i ), |
.ACK_O( wb_ack_o ), |
.ERR_O( wb_err_o ), |
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//-- master signals |
.ADR_O( wb_addr_o[31:2] ), |
.MDAT_I( wbm_data_i ), |
.SEL_O( wb_sel_o ), |
.WE_O( wb_we_o ), |
.STB_O( wb_stb_o ), |
.CYC_O( wb_cyc_o ), |
.CAB_O( ), |
.ACK_I( wb_ack_i ), |
.ERR_I( wb_err_i ), |
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//-- VGA signals |
.PCLK( pclk ), |
.HSYNC( hsync ), |
.VSYNC( vsync ), |
.CSYNC( csync ), |
.BLANK( blanc ), |
.R( red ), |
.G( green ), |
.B( blue ) |
); |
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`endif |
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wb_mast m0( .clk( clk ), |
.rst( rst ), |
.adr( wb_addr_i ), |
/trunk/bench/verilog/wb_b3_check.v
0,0 → 1,124
///////////////////////////////////////////////////////////////////// |
//// //// |
//// WISHBONE revB.3 Registered Feedback Cycle checker //// |
//// //// |
//// //// |
//// Author: Richard Herveille //// |
//// richard@ascis.ws //// |
//// //// |
//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2003 Richard Herveille //// |
//// richard@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
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module wb_b3_check (clk_i, cyc_i, stb_i, we_i, cti_i, bte_i, ack_i, err_i, rty_i); |
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input clk_i; |
input cyc_i; |
input stb_i; |
input [2:0] cti_i; |
input [1:0] bte_i; |
input we_i; |
input ack_i; |
input err_i; |
input rty_i; |
|
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parameter [2:0] cti_classic = 3'b000; |
parameter [2:0] cti_streaming = 3'b001; |
parameter [2:0] cti_inc_burst = 3'b010; |
parameter [2:0] cti_eob = 3'b111; |
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// check CTI, BTE |
reg [2:0] pcti; // previous cti |
reg [1:0] pbte; // previous bte |
reg pwe; // previous we |
reg chk; |
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always @(posedge clk_i) |
if (cyc_i & stb_i & ack_i) |
begin |
pcti <= #1 cti_i; |
pbte <= #1 bte_i; |
end |
|
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always @(posedge clk_i) |
if (cyc_i) |
if (ack_i) |
chk <= #1 1'b1; |
else |
chk <= #1 1'b0; |
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// |
// Check CTI_I |
always @(posedge clk_i) |
if (chk) |
case (cti_i) |
cti_eob: ; // ok |
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default: |
if (cti_i !== pcti) |
$display("\nWISHBONE revB.3 Burst error. CTI change from %0b to %0b not allowed. (%t)\n", |
pcti, cti_i, $time); |
endcase |
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// |
// Check BTE_I |
always @(posedge clk_i) |
if (chk) |
if ((cti_i != cti_classic) && (bte_i !== pbte)) |
$display("\nWISHBONE revB.3 Burst ERROR. BTE change from %0b to %0b not allowed. (%t)\n", |
pbte, bte_i, $time); |
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// |
// Check WE_I |
always @(posedge clk_i) |
if (chk) |
if ((cti_i != cti_classic) && (we_i !== pwe)) |
$display("\nWISHBONE revB.3 Burst ERROR. WE change from %0b to %0b not allowed. (%t)\n", |
pwe, we_i, $time); |
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// |
// Check ACK_I, ERR_I, RTY_I |
always @(posedge clk_i) |
case ({ack_i, err_i, rty_i}) |
3'b000: ; |
3'b001: ; |
3'b010: ; |
3'b100: ; |
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default: |
$display("\n WISHBONE revB.3 ERROR. Either ack(%0b), rty(%0b), or err(%0b) may be asserted. (%t)", |
ack_i, rty_i, err_i, $time); |
endcase |
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endmodule |