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URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

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Rev 59 → Rev 60

/trunk/bench/verilog/wb_mast_model.v
37,18 → 37,24
 
// CVS Log
//
// $Id: wb_mast_model.v,v 1.1 2001-08-21 05:42:32 rudi Exp $
// $Id: wb_mast_model.v,v 1.2 2003-09-23 13:09:25 markom Exp $
//
// $Date: 2001-08-21 05:42:32 $
// $Revision: 1.1 $
// $Author: rudi $
// $Date: 2003-09-23 13:09:25 $
// $Revision: 1.2 $
// $Author: markom $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/21 05:42:32 rudi
//
// - Changed Directory Structure
// - Added verilog Source Code
// - Changed IO pin names and defines statements
//
//
//
//
 
`include "wb_model_defines.v"
105,7 → 111,6
input [31:0] d;
 
begin
 
@(posedge clk);
#1;
adr = a;
/trunk/bench/verilog/test_bench_top.v
37,16 → 37,19
 
// CVS Log
//
// $Id: test_bench_top.v,v 1.9 2003-08-22 07:12:31 rherveille Exp $
// $Id: test_bench_top.v,v 1.10 2003-09-23 13:09:25 markom Exp $
//
// $Date: 2003-08-22 07:12:31 $
// $Revision: 1.9 $
// $Author: rherveille $
// $Date: 2003-09-23 13:09:25 $
// $Revision: 1.10 $
// $Author: markom $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/08/22 07:12:31 rherveille
// Enabled Fifo Underrun test
//
// Revision 1.8 2003/05/07 14:39:19 rherveille
// Added DVI tests
//
100,21 → 103,22
wire wb_err_o;
reg pclk_i;
wire pclk;
wire hsync;
wire hsync;
wire vsync;
wire ihsync;
wire ivsync;
wire csync;
wire blanc;
wire [7:0] red;
wire [7:0] green;
wire [7:0] blue;
wire dvi_pclk_p_o;
wire dvi_pclk_m_o;
wire dvi_hsync_o;
wire dvi_vsync_o;
wire dvi_de_o;
`ifdef VGA_12BIT_DVI
wire [11:0] dvi_d_o;
`else
wire [23:0] dvi_d_o;
`endif
 
 
wire vga_stb_i;
wire clut_stb_i;
 
167,11 → 171,7
 
`define USE_VC 1
 
`ifdef VGA_12BIT_DVI
parameter PCLK_C = 20;
`else
parameter PCLK_C = 30;
`endif
 
/////////////////////////////////////////////////////////////////////
//
214,11 → 214,13
reg_test;
tim_test;
 
`ifdef VGA_24BIT_DVI
dvi_pd_test;
`endif
`ifdef VGA_12BIT_DVI
`else
pd1_test;
pd2_test;
 
`ifdef VGA_12BIT_DVI
dvi_pd_test;
`endif
 
ur_test;
488,7 → 490,7
//
 
`ifdef VGA_12BIT_DVI
sync_check #(PCLK_C*2) ucheck(
sync_check #(PCLK_C) ucheck(
`else
sync_check #(PCLK_C) ucheck(
`endif
564,7 → 566,7
$display("*************************************\n\n\n");
end
 
always #2.5 clk = ~clk;
always #2.4 clk = ~clk;
always #(PCLK_C/2) pclk_i = ~pclk_i;
 
/////////////////////////////////////////////////////////////////////
575,7 → 577,11
 
// Module Prototype
 
`ifdef VGA_12BIT_DVI
vga_dvi_top #(1'b0, LINE_FIFO_AWIDTH) u0 (
`else
vga_enh_top #(1'b0, LINE_FIFO_AWIDTH) u0 (
`endif
.wb_clk_i ( clk ),
.wb_rst_i ( 1'b0 ),
.rst_i ( rst ),
606,17 → 612,16
.wbm_err_i ( wb_err_i ),
 
//-- VGA signals
.clk_p_i ( pclk_i ),
`ifdef VGA_12BIT_DVI
.dvi_pclk_p_o ( dvi_pclk_p_o ),
.dvi_pclk_m_o ( dvi_pclk_m_o ),
.dvi_hsync_o ( dvi_hsync_o ),
.dvi_vsync_o ( dvi_vsync_o ),
.dvi_de_o ( dvi_de_o ),
.dvi_d_o ( dvi_d_o ),
.clk_p_i ( pclk_i )
`ifdef VGA_24BIT_DVI
, .dvi_hsync_o ( ihsync ),
.dvi_vsync_o ( ivsync ),
.dvi_de_o ( dvi_de_o ),
.dvi_d_o ( dvi_d_o )
`endif
.clk_p_o ( pclk ),
.hsync_pad_o ( hsync ),
`ifdef VGA_12BIT_DVI
`else
, .hsync_pad_o ( hsync ),
.vsync_pad_o ( vsync ),
.csync_pad_o ( csync ),
.blank_pad_o ( blanc ),
623,8 → 628,25
.r_pad_o ( red ),
.g_pad_o ( green ),
.b_pad_o ( blue )
`endif
 
`ifdef VGA_BIST
/* BIST signals */
, .scanb_rst(1'b1),
.scanb_clk(1'b0),
.scanb_si (1'b0),
.scanb_en (1'b0),
.scanb_so ()
`endif
);
 
assign pclk = pclk_i;
 
`ifdef VGA_12BIT_DVI
assign hsync = !ihsync;
assign vsync = !ivsync;
`endif
 
wb_mast m0( .clk( clk ),
.rst( rst ),
.adr( wb_addr_i ),
/trunk/bench/verilog/tests.v
37,16 → 37,19
 
// CVS Log
//
// $Id: tests.v,v 1.9 2003-08-22 07:17:21 rherveille Exp $
// $Id: tests.v,v 1.10 2003-09-23 13:09:25 markom Exp $
//
// $Date: 2003-08-22 07:17:21 $
// $Revision: 1.9 $
// $Author: rherveille $
// $Date: 2003-09-23 13:09:25 $
// $Revision: 1.10 $
// $Author: markom $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/08/22 07:17:21 rherveille
// Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors.
//
// Revision 1.8 2003/05/07 14:39:19 rherveille
// Added DVI tests
//
1055,7 → 1058,7
$display("*** FIFO Underrun Test 1 ***");
$display("*****************************************************\n");
 
s0.delay=5;
s0.delay=15;
int_warn = 0;
 
m0.wb_wr1( `VBARA, 4'hf, 0 );
1082,7 → 1085,7
m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} );
m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
 
mode = 2;
mode = 0;
 
// -------------------------------
// Turn Off VGA before Mode Change
1098,7 → 1101,7
begin
//m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data );
data = s0.mem[ cbar[31:2] + n];
m0.wb_wr1( 32'h8000_0000 + (n*4), 4'hf, data );
m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data );
end
repeat(10) @(posedge clk);
`endif
1340,7 → 1343,7
// For each Pixel
for(p=0;p<thgate+1;p=p+1)
begin
while(~dvi_de_o) @(pclk); // wait for viewable data
while(dvi_de_o == 1'b0) @(pclk); // wait for viewable data
 
//$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);
 
1497,6 → 1500,8
//
// verify pixel data
 
`ifdef VGA_12BIT_DVI
 
// rising edge data
if (pda !== dvi_d_o)
begin
1507,7 → 1512,7
if(error_cnt > 10) $stop;
end
 
@(dvi_pclk_p_o);
@(negedge pclk_i);
 
// falling edge data
if (pdb !== dvi_d_o)
1518,8 → 1523,22
error_cnt = error_cnt + 1;
if(error_cnt > 10) $stop;
end
@(posedge pclk_i);
`else
 
@(dvi_pclk_p_o);
// compare data
if ({pdb, pda} !== dvi_d_o)
begin
$display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h",
{pdb, pda}, dvi_d_o);
$display(" pixel=%0d, line=%0d, (%0t)",p,l,$time);
error_cnt = error_cnt + 1;
if(error_cnt > 10) $stop;
end
 
@(negedge pclk_i);
@(posedge pclk_i);
`endif
end
end
 
/trunk/bench/verilog/sync_check.v
37,16 → 37,19
 
// CVS Log
//
// $Id: sync_check.v,v 1.4 2003-05-07 09:45:28 rherveille Exp $
// $Id: sync_check.v,v 1.5 2003-09-23 13:09:25 markom Exp $
//
// $Date: 2003-05-07 09:45:28 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Date: 2003-09-23 13:09:25 $
// $Revision: 1.5 $
// $Author: markom $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/05/07 09:45:28 rherveille
// Numerous updates and added checks
//
// Revision 1.3 2003/03/19 12:20:53 rherveille
// Changed timing section in VGA core, changed testbench accordingly.
// Fixed bug in 'timing check' test.
174,6 → 177,8
end
end
 
`ifdef VGA_12BIT_DVI
`else
// Verify BLANC Timing
//assign bv_start = tvsync + tvgdel + 2;
//assign bv_end = bv_start + tvgate + 2;
208,13 → 213,8
 
initial bval = 1;
always @(bdel2)
`ifdef VGA_12BIT_DVI
bval = !(bval1 & (bdel2 > bh_start) & (bdel2 < bh_end));
`else
bval = #1 !(bval1 & (bdel2 > bh_start) & (bdel2 < bh_end));
`endif
 
 
always @(bval or blanc)
#0.01
if(enable)
228,13 → 228,7
if( (csync ^ cpol) != ( (vsync ^ vpol) | (hsync ^ hpol) ) )
$display("CSYNC ERROR: Expected: %0d Got: %0d (%0t)",
( (vsync ^ vpol) | (hsync ^ hpol) ), (csync ^ cpol), $time);
`endif
 
 
endmodule
 
 
 
 
 
 
 
/trunk/sim/rtl_sim/bin/Makefile
11,11 → 11,13
DUT_SRC_DIR=../../../rtl/verilog
_TARGETS_= $(DUT_SRC_DIR)/generic_dpram.v \
$(DUT_SRC_DIR)/generic_spram.v \
$(DUT_SRC_DIR)/csm_spram_bw.v \
$(DUT_SRC_DIR)/vga_colproc.v \
$(DUT_SRC_DIR)/vga_csm_pb.v \
$(DUT_SRC_DIR)/vga_cur_cregs.v \
$(DUT_SRC_DIR)/vga_curproc.v \
$(DUT_SRC_DIR)/vga_enh_top.v \
$(DUT_SRC_DIR)/vga_dvi_top.v \
$(DUT_SRC_DIR)/vga_fifo.v \
$(DUT_SRC_DIR)/vga_fifo_dc.v \
$(DUT_SRC_DIR)/vga_pgen.v \
35,9 → 37,16
$(TB_SRC_DIR)/wb_slv_model.v \
$(TB_SRC_DIR)/wb_mast_model.v \
$(TB_SRC_DIR)/sync_check.v \
$(TB_SRC_DIR)/artsmcl18u_ram/art_hssp_512x24_bw_bist.v \
$(TB_SRC_DIR)/artsmcl18u_ram/art_hsdp_128x24_bist.v \
$(TB_SRC_DIR)/bist/rtl/verilog/bist_dp_top.v \
$(TB_SRC_DIR)/bist/rtl/verilog/bist_sp_top.v \
$(TB_SRC_DIR)/bist/rtl/verilog/bist_tp_top.v \
$(TB_SRC_DIR)/bist/rtl/verilog/bist.v \
$(TB_SRC_DIR)/artsmcl18u_ram/art_hssp_512x24_bw/art_hssp_512x24_bw.v \
$(TB_SRC_DIR)/artsmcl18u_ram/art_hsdp_128x24/art_hsdp_128x24.v \
$(TB_SRC_DIR)/wb_b3_check.v
 
 
##########################################################################
#
# Misc Variables
113,8 → 122,8
 
clean:
rm -rf ./waves/*.dsn ./waves/*.trn \
ncwork/work/* ncwork/count/* \
ncwork/work/.i* ncwork/count/.i*
ncwork/worklib/* ncwork/count/* \
ncwork/worklib/.i* ncwork/count/.i*
 
##########################################################################
#
124,7 → 133,7
 
vlog:
ncvlog $(NCCOMMON) $(LOGF) \
-WORK work $(WAVES) $(TARGETS) $(TB) $(INCDIR)
-WORK worklib $(WAVES) $(TARGETS) $(TB) $(INCDIR)
 
##########################################################################
#
134,8 → 143,9
 
elab:
ncelab $(NCCOMMON) $(LOGF) -APPEND_LOG \
-WORK work $(ACCESS) \
work.$(TOP)
-WORK worklib $(ACCESS) \
-NOTIMINGCHECKS \
worklib.$(TOP)
 
##########################################################################
#
145,7 → 155,7
 
ncsim:
ncsim $(NCCOMMON) $(LOGF) -APPEND_LOG \
-EXIT -ERRORMAX 10 work.$(TOP)
-EXIT -ERRORMAX 10 worklib.$(TOP)
 
 
 

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