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https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk
Subversion Repositories vhdl_wb_tb
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- This comparison shows the changes necessary to convert path
/vhdl_wb_tb/trunk/bench
- from Rev 3 to Rev 2
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Rev 3 → Rev 2
/vhdl/testcase_top.vhd
0,0 → 1,49
--============================================================================ |
-- This confidential and proprietary software may be used |
-- only as authorized by a licensing agreement from |
-- Vector Informatik GmbH. |
-- In an event of publication, the following notice is applicable: |
-- |
-- (C) COPYRIGHT 2018 VECTOR INFORMATIK GMBH |
-- ALL RIGHTS RESERVED |
-- |
-- The entire notice above must be reproduced on all authorized copies. |
--============================================================================ |
-- |
-- $URL: https://vistrpnisvn1.vi.vector.int/svn/PNI/VS/trunk/FPGA/Templates/%5Bproject%5D/stimulus/testcase_top.vhd $ |
-- $Revision: 81721 $ |
-- $Date: 2018-03-14 10:44:48 +0100 (Mi, 14 Mrz 2018) $ |
-- $Author: visstt $ |
-- $Id: testcase_top.vhd 81721 2018-03-14 09:44:48Z visstt $ |
-- |
--============================================================================ |
-- |
-- Abstract: |
-- This file contains the entity declaration of the test case player. |
-- Test architectures of all cases will be located in individual tc_xxx.vhdl |
-- files. |
-- |
--============================================================================ |
|
--=library==================================================================== |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
library work; |
use work.convert_pkg.all; |
use work.my_project_pkg.all; |
use work.wishbone_pkg.all; |
use work.wishbone_bfm_pkg.all; |
|
--============================================================================ |
|
--=entity===================================================================== |
entity testcase_top is |
port ( |
wb_o : out wishbone_bfm_master_out_t; |
wb_i : in wishbone_bfm_master_in_t |
); |
end entity testcase_top; |
--============================================================================ |
-- end of file |
--============================================================================ |