OpenCores
URL https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk

Subversion Repositories vhdl_wb_tb

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  • This comparison shows the changes necessary to convert path 
    /vhdl_wb_tb/trunk
    from Rev 4 to Rev 3
    ↔ Reverse comparison
  •

Rev 4 → Rev 3

/bench/vhdl/tc_top.vhd File deleted \ No newline at end of file
/bench/vhdl/stimulator.vhd
3,28 → 3,30
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- https://opencores.org/project/vhdl_wb_tb ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the stimulator module of the design. ----
---- Modify the stimulator to stimulate your DUT ----
---- The stimulator is controlled by the testcase (tc_xxxx files)----
---- via a wishbone bus. ----
---- This file contains the top functional module of the design ----
---- under test. The top functional module will be enclosed by ----
---- the top module for synthesis or the tb_top for simulation. ----
---- The top module can contain some synthesis specific code, ----
---- where the tb_top contains simulation specific code. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- SVN information
----
---- $URL: $
---- $Revision: $
---- $Date: $
---- $Author: $
---- $Id: $
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
122,6 → 124,6
signals_o <= s_register0(signals_o'left downto 0);
--============================================================================
end rtl; --stimulator
----------------------------------------------------------------------
---- end of file ----
----------------------------------------------------------------------
--============================================================================
-- end of file
--============================================================================
/bench/vhdl/tb_pkg.vhd
5,24 → 5,31
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains constants for the test bench, such as ----
---- register definitions. ----
---- This file contains the highest (top) module of the test ----
---- bench. ----
---- It instantiates the design under test (DUT), instantiates ----
---- the stimulator module for test vector generation, ----
---- instantiates the verifier module for result comparison, ----
---- instantiates the test case top (testcase_top) bfm, ----
---- interconnects all three components, generates DUT-external ----
---- clocks and resets. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- SVN information
----
---- $URL: $
---- $Revision: $
---- $Date: $
---- $Author: $
---- $Id: $
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
75,6 → 82,6
constant verifier_register2_c : integer := verifier_base_c + 16#0000_0008#;
----------------------------------------------------------------------
end package;
----------------------------------------------------------------------
---- end of file ----
----------------------------------------------------------------------
--============================================================================
-- end of file
--============================================================================
/bench/vhdl/tb_top.vhd
3,14 → 3,10
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- https://opencores.org/project/vhdl_wb_tb ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the highest (top) module for simulation. ----
---- Like tb_top it instantiates the core_top module and ----
---- provides parameters/generics. Where the top module provides ----
---- parameters for synthesis this file provides parameters for ----
---- simulation. ----
---- ----
---- This file contains the highest (top) module of the test ----
---- bench. ----
---- It instantiates the design under test (DUT), instantiates ----
---- the stimulator module for test vector generation, ----
---- instantiates the verifier module for result comparison, ----
22,16 → 18,17
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
---- SVN information
----
---- $URL: $
---- $Revision: $
---- $Date: $
---- $Author: $
---- $Id: $
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
74,10 → 71,13
-- in the tc_xxx files.
end entity tb_top;
 
-- architecture ------------------------------------------------------
--=architecture===============================================================
architecture rtl of tb_top is
-----------------------------------------------------------------------------
--============================================================================
constant g_wb_clock_period : time := 20.0 ns; -- 50 mhz
--============================================================================
-- signal declaration
--============================================================================
-----------------------------------------------------------------------------
signal s_wb_bfm_out : wishbone_bfm_master_out_t; -- from testcase_top
signal s_wb_bfm_in : wishbone_bfm_master_in_t; -- to testcase_top
100,8 → 100,11
signal s_stimulus : std_logic_vector(number_of_stimulus_signals_c-1 downto 0);
signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0);
-----------------------------------------------------------------------------
-- other signals
 
-----------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------
--============================================================================
--clocks---------------------------------------------------------------------
wb_clock_generator : process -- required for test bench wb bus; 50mhz is standard
begin
125,7 → 128,7
s_wb_reset <= s_wb_reset_p2;
-----------------------------------------------------------------------------
-- instance of test case "player"; runs tc_xxxx modules
tc_top_inst : entity work.tc_top
testcase_top_inst : entity work.testcase_top
port map (
wb_o => s_wb_bfm_out,
wb_i => s_wb_bfm_in
197,7 → 200,7
signals_i => s_verify
);
-----------------------------------------------------------------------------
end rtl;
----------------------------------------------------------------------
---- end of file ----
----------------------------------------------------------------------
end rtl;
--============================================================================
-- end of file
--============================================================================
/bench/vhdl/tc_xxxx.vhd
5,26 → 5,31
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the one test sequence for the test bench.----
---- Several test sequences shall be stored in several tc_xxxx ----
---- files. This file contains the architecture for the tc_top ----
---- enity, lcated in tc_top.vhd. ----
---- This file contains the highest (top) module of the test ----
---- bench. ----
---- It instantiates the design under test (DUT), instantiates ----
---- the stimulator module for test vector generation, ----
---- instantiates the verifier module for result comparison, ----
---- instantiates the test case top (testcase_top) bfm, ----
---- interconnects all three components, generates DUT-external ----
---- clocks and resets. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- SVN information
----
---- $URL: $
---- $Revision: $
---- $Date: $
---- $Author: $
---- $Id: $
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
63,15 → 68,16
use work.tb_pkg.all;
 
-- architecture ------------------------------------------------------
architecture tc_xxxx of tc_top is
----------------------------------------------------------------------
architecture tc_xxxx of testcase_top is
--==========================================================================
-- local constant definitions
----------------------------------------------------------------------
--==========================================================================
--==========================================================================
begin
----------------------------------------------------------------------
--==========================================================================
tc_xxxx_proc : process
begin
----------------------------------------------------------------------
--==========================================================================
-- standard signal initialization
wb_o <= wb_bfm_master_out_idle_c;
82,7 → 88,7
wait for 400 ns;
wait until rising_edge(wb_i.clk);
--
----------------------------------------------------------------------
--==========================================================================
report "-----------------------------------------------------------------";
report "-- tc_xxxx: ADD_DESCRIPTION_HERE --";
134,23 → 140,22
wait until rising_edge(wb_i.clk);
wb_read (verifier_register2_c, 16#0000_0005#, wb_i, wb_o);
wait for 1 us;
----------------------------------------------------------------------
-- =================================================
report "-- tc_xxxx finished";
----------------------------------------------------------------------
-- =================================================
--
wait for 400 ns;
--wait;
--
report "test case tc_xxxx completed successfully"; --severity failure;
report "-----------------------------------------------------------------";
report "-----------------------------------------------------------------";
wait for 100 ns;
if (exit_simulator_at_tc_end_c/="1") then
std.env.stop; -- pause simulation
else
std.env.finish; -- stop simulation
end if;
std.env.stop; -- pause simulation
 
--std.env.finish; -- stop simulation; end modelsim
end process tc_xxxx_proc;
----------------------------------------------------------------------
--==========================================================================
end tc_xxxx;
----------------------------------------------------------------------
---- end of file ----
----------------------------------------------------------------------
--============================================================================
-- end of file
--============================================================================
/bench/vhdl/verifier.vhd
5,27 → 5,28
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the verifier module which monitors the ----
---- DUTs responses. It is controlled via a wishbone interface ----
---- by the tc_xxxx files. ----
---- It can check the signals by itself or forward information ----
---- To the tc_xxxx files. ----
---- This file contains the top functional module of the design ----
---- under test. The top functional module will be enclosed by ----
---- the top module for synthesis or the tb_top for simulation. ----
---- The top module can contain some synthesis specific code, ----
---- where the tb_top contains simulation specific code. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- SVN information
----
---- $URL: $
---- $Revision: $
---- $Date: $
---- $Author: $
---- $Id: $
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
75,14 → 76,14
);
end verifier;
 
-- architecture ----------------------------------------------------------------
--=architecture===============================================================
architecture rtl of verifier is
------------------------------------------------------------------------------
--============================================================================
-- signal declaration
------------------------------------------------------------------------------
--============================================================================
signal s_register0 : std_logic_vector(31 downto 0);
signal s_register1 : std_logic_vector(31 downto 0);
------------------------------------------------------------------------------
--============================================================================
begin
------------------------------------------------------------------------------
wb_o.ack <= '1';
126,7 → 127,8
end process;
------------------------------------------------------------------------------
--============================================================================
end rtl; --verifier
----------------------------------------------------------------------
---- end of file ----
----------------------------------------------------------------------
--============================================================================
-- end of file
--============================================================================
/bench/vhdl/wishbone_bfm_pkg.vhd
12,17 → 12,18
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- SVN information
----
---- $URL: $
---- $Revision: $
---- $Date: $
---- $Author: $
---- $Id: $
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
107,36 → 108,36
tgc => (others=>'0'),
we => '0'
);
----------------------------------------------------------------------
-- BUS FUNCTIONS -----------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
-- generate single write cycle
procedure wb_write(
address_i : in integer; -- address to write to
data_i : in integer; -- data value to be written
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals
signal o : out wishbone_bfm_master_out_t; -- incoming wb signals
display_error_message_i : in integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all
additional_error_message_i : in string := ""
PROCEDURE wb_write(
address_i : IN integer; -- address to write to
data_i : IN integer; -- data value to be written
SIGNAL i : IN wishbone_bfm_master_in_t; -- incoming wb signals
SIGNAL o : OUT wishbone_bfm_master_out_t; -- incoming wb signals
display_error_message_i : IN integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all
additional_error_message_i : IN string := ""
);
 
-- generate single read cycle and verify read word with expected_data_i
procedure wb_read(
address_i : in integer;
expected_data_i : in integer;
signal i : in wishbone_bfm_master_in_t;
signal o : out wishbone_bfm_master_out_t;
display_error_message_i : in integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
additional_error_message_i : in string := "";
expected_data_mask_i : in integer := 0
PROCEDURE wb_read(
address_i : IN INTEGER;
expected_data_i : IN INTEGER;
SIGNAL i : IN wishbone_bfm_master_in_t;
SIGNAL o : OUT wishbone_bfm_master_out_t;
display_error_message_i : IN integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
additional_error_message_i : IN STRING := "";
expected_data_mask_i : IN INTEGER := 0
);
 
-- generate single read cycle and return read data via read_data_o
procedure wb_read(
address_i : in integer;
read_data_o : out std_logic_vector (wishbone_address_width_c-1 downto 0);
signal i : in wishbone_bfm_master_in_t;
signal o : out wishbone_bfm_master_out_t
PROCEDURE wb_read(
address_i : IN INTEGER;
read_data_o : OUT STD_LOGIC_VECTOR (wishbone_address_width_c-1 DOWNTO 0);
SIGNAL i : IN wishbone_bfm_master_in_t;
SIGNAL o : OUT wishbone_bfm_master_out_t
);
----------------------------------------------------------------------
end;
145,16 → 146,16
package body wishbone_bfm_pkg is
----------------------------------------------------------------------
----------------------------------------------------------------------
procedure wb_write(
address_i : in integer;
data_i : in integer;
signal i : in wishbone_bfm_master_in_t;
signal o : out wishbone_bfm_master_out_t;
display_error_message_i : in integer range 0 to 2 := 1;
additional_error_message_i : in string := ""
) is
PROCEDURE wb_write(
address_i : IN integer;
data_i : IN integer;
SIGNAL i : IN wishbone_bfm_master_in_t;
SIGNAL o : OUT wishbone_bfm_master_out_t;
display_error_message_i : IN integer range 0 to 2 := 1;
additional_error_message_i : IN string := ""
) IS
----------------------------------------------------------------------
begin
BEGIN
o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);
o.dat <= to_std_logic_vector(data_i, wishbone_address_width_c);
o.we <= '1';
166,29 → 167,29
o.stb <= '1';
o.tga <= (others => '0');
o.tgc <= (others => '0');
if (display_error_message_i = 2) then
report "writing :" & to_string(data_i, 16, wishbone_address_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4) &
IF (display_error_message_i = 2) THEN
REPORT "Writing :" & to_string(data_i, 16, wishbone_address_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4) &
additional_error_message_i;
end if;
END IF;
 
wait until falling_edge(i.clk);
WAIT UNTIL falling_edge(i.clk);
-- wait for ack
while i.ack = '0' loop
wait until falling_edge(i.clk);
end loop;
wait until rising_edge(i.clk);
WHILE i.ack = '0' LOOP
WAIT UNTIL falling_edge(i.clk);
END LOOP;
WAIT UNTIL rising_edge(i.clk);
o <= wb_bfm_master_out_idle_c; -- reset bus
end wb_write;
END wb_write;
----------------------------------------------------------------------
----------------------------------------------------------------------
procedure wb_read(
address_i : in integer;
read_data_o : out std_logic_vector (wishbone_address_width_c-1 downto 0);
signal i : in wishbone_bfm_master_in_t;
signal o : out wishbone_bfm_master_out_t
) is
PROCEDURE wb_read(
address_i : IN INTEGER;
read_data_o : OUT STD_LOGIC_VECTOR (wishbone_address_width_c-1 DOWNTO 0);
SIGNAL i : IN wishbone_bfm_master_in_t;
SIGNAL o : OUT wishbone_bfm_master_out_t
) IS
----------------------------------------------------------------------
begin
BEGIN
o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);
o.dat <= (others => 'U');
o.we <= '0';
200,60 → 201,60
o.stb <= '1';
o.tga <= (others => '0');
o.tgc <= (others => '0');
wait until falling_edge(i.clk);
WAIT UNTIL falling_edge(i.clk);
-- ack handling
while (i.ack = '0') loop
wait until falling_edge(i.clk);
end loop;
WHILE (i.ack = '0') LOOP
WAIT UNTIL falling_edge(i.clk);
END LOOP;
read_data_o := i.dat;
wait until rising_edge(i.clk);
WAIT UNTIL rising_edge(i.clk);
o <= wb_bfm_master_out_idle_c; -- reset bus
end wb_read;
END wb_read;
------------------------------------------------------------------------
------------------------------------------------------------------------
procedure wb_read(
address_i : in integer;
expected_data_i : in integer;
signal i : in wishbone_bfm_master_in_t;
signal o : out wishbone_bfm_master_out_t;
display_error_message_i : in integer range 0 to 4 := 1;
additional_error_message_i : in string := "";
expected_data_mask_i : in integer := 0
) is
PROCEDURE wb_read(
address_i : IN INTEGER;
expected_data_i : IN INTEGER;
SIGNAL i : IN wishbone_bfm_master_in_t;
SIGNAL o : OUT wishbone_bfm_master_out_t;
display_error_message_i : IN integer range 0 to 4 := 1;
additional_error_message_i : IN STRING := "";
expected_data_mask_i : IN INTEGER := 0
) IS
----------------------------------------------------------------------
variable readdata_v : std_logic_vector (31 downto 0);
variable diff_v : integer;
VARIABLE readdata_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
VARIABLE diff_v : INTEGER;
----------------------------------------------------------------------
begin
BEGIN
wb_read(address_i,readdata_v,i,o); -- read from bus
 
diff_v := to_integer(readdata_v) - expected_data_i;
 
if (display_error_message_i = 1) then -- output errors only
if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then
report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
IF (display_error_message_i = 1) THEN -- output errors only
IF (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN
REPORT "ERROR" & additional_error_message_i & ": Expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4)
severity error;
end if;
elsif (display_error_message_i = 2) then -- output all
report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
SEVERITY error;
END IF;
ELSIF (display_error_message_i = 2) THEN -- Output all
REPORT additional_error_message_i & ": Read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
" was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4)
severity note;
elsif (display_error_message_i = 3) then -- output filter
if ((readdata_v and to_std_logic_vector(expected_data_mask_i, wishbone_address_width_c)) /=
to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then
report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
SEVERITY note;
ELSIF (display_error_message_i = 3) THEN -- Output Filter
IF ((readdata_v AND to_std_logic_vector(expected_data_mask_i, wishbone_address_width_c)) /=
to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN
REPORT additional_error_message_i & ": Read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
" was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4)
severity note;
end if;
elsif display_error_message_i = 4 then
if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then
report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4) & " diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)
severity error;
end if;
end if;
end wb_read;
SEVERITY note;
END IF;
ELSIF display_error_message_i = 4 THEN
IF (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN
REPORT "ERROR" & additional_error_message_i & ": Expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4) & " Diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)
SEVERITY error;
END IF;
END IF;
END wb_read;
--------------------------------------------------------------------
end package body;
----------------------------------------------------------------------
/rtl/vhdl/packages/convert_pkg.vhd
2,26 → 2,42
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This is a universal type conversion library for VHDL. With ----
---- the contained overloaded functions conversions from any to ----
---- any of the following data types are possible: ----
---- ----
---- std_logic_vector ----
---- std_ulogic_vector ----
---- unsigned ----
---- signed ----
---- bit_vector ----
---- integer ----
---- string ----
---- ----
---- To use them just add the prefix "to_" to the desired result ----
---- type with the source type in braces. ----
---- E.g. conversion from integer to std_logic_vector: ----
---- destination<=to_std_logic_vector(source); ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains some type conversion functions. ----
---- ----
---- To Do: ----
---- - ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- - First & Last Name, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- SVN information
----
---- $URL: $
---- $Revision: $
---- $Date: $
---- $Author: $
---- $Id: $
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
47,12 → 63,15
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
-- library -----------------------------------------------------------
--============================================================================
--============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
--============================================================================
 
-- package -----------------------------------------------------------
 
--============================================================================
PACKAGE convert_pkg IS
 
FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector;
62,20 → 81,22
FUNCTION to_string(slv : std_logic_vector; base : integer; length : integer) RETURN string;
END convert_pkg;
--============================================================================
 
-- package body ------------------------------------------------------
--============================================================================
PACKAGE BODY convert_pkg IS
----------------------------------------------------------------------
--==========================================================================
FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector IS
BEGIN
RETURN std_logic_vector(conv_unsigned(input, length));
END;
----------------------------------------------------------------------
 
FUNCTION to_integer(input : std_logic_vector) RETURN integer IS
BEGIN
RETURN conv_integer(unsigned(input));
END;
----------------------------------------------------------------------
 
--==========================================================================
FUNCTION to_char(int : integer) RETURN character IS
VARIABLE c : character;
BEGIN
120,7 → 141,10
END CASE;
RETURN c;
END to_char;
----------------------------------------------------------------------
--========================================================================
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
-- if base=0 convert to 32 bit hex
FUNCTION to_string(int : integer; base : integer := 10; length : integer := 0) RETURN string IS
 
VARIABLE temp : string(1 TO 1000);
208,7 → 232,8
END IF;
END IF;
END to_string;
----------------------------------------------------------------------
 
--========================================================================
FUNCTION to_string(slv : std_logic_vector) RETURN string IS
 
VARIABLE hexlen : integer;
251,13 → 276,14
END LOOP;
RETURN hex(1 TO hexlen);
END to_string;
----------------------------------------------------------------------
 
--========================================================================
FUNCTION to_string(slv : std_logic_vector; base : integer; length : integer) RETURN string IS
 
BEGIN
RETURN to_string(to_integer(slv), base, length);
END to_string;
----------------------------------------------------------------------
 
end package body;
----------------------------------------------------------------------
---- end of file ----
/rtl/vhdl/packages/my_project_pkg.vhd
1,27 → 1,31
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- WISHBONE XXX IP Core ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- This file is part of the XXX project ----
---- http://www.opencores.org/cores/xxx/ ----
---- ----
---- This file contains the project specific defines ----
---- Description ----
---- Implementation of XXX IP core according to ----
---- XXX IP core specification document. ----
---- ----
---- To Do: ----
---- - ----
---- - Adjust and rename this package for your project ----
---- - remove these comments ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- - First & Last Name, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- SVN information
----
---- $URL: $
---- $Revision: $
---- $Date: $
---- $Author: $
---- $Id: $
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
47,22 → 51,20
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
-- library -----------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library work;
 
-- package -----------------------------------------------------------
package my_project_pkg is
 
constant wishbone_address_width_c : integer := 32;
constant wishbone_data_width_c : integer := 32;
constant wishbone_data_of_unused_address_c : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADDEAD"; -- "X" might lead to less resources. Meaningful value might ease debugging
constant wishbone_data_of_unused_address_p : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADBEEF"; -- "X" might lead to less resources. Meaningful value might ease debugging
constant exit_simulator_at_tc_end_c : std_logic_vector := "0"; -- "1": exit simulator at end of tc_xxxx file. used for scripted simulation runs;
-- "0": just pause simulator at end of tc_xxx file. used for manual simulation runs.
subtype wishbone_tag_data_t is std_logic_vector(1 downto 0);
subtype wishbone_tag_address_t is std_logic_vector(1 downto 0);
subtype wishbone_tag_cycle_t is std_logic_vector(1 downto 0);
72,9 → 74,6
constant zero_c : std_logic_vector(511 downto 0) := (others => '0');
end my_project_pkg;
 
-- package body ------------------------------------------------------
package body my_project_pkg is
end my_project_pkg;
----------------------------------------------------------------------
---- end of file ----
----------------------------------------------------------------------
 
/rtl/vhdl/packages/wishbone_pkg.vhd
17,17 → 17,18
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- SVN information
----
---- $URL: $
---- $Revision: $
---- $Date: $
---- $Author: $
---- $Id: $
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
53,10 → 54,12
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
-- library -----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library work;
use work.my_project_pkg.all;
 
/rtl/vhdl/core_top.vhd
15,17 → 15,18
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- SVN information
----
---- $URL: $
---- $Revision: $
---- $Date: $
---- $Author: $
---- $Id: $
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
74,14 → 75,14
);
end core_top;
 
-- architecture ------------------------------------------------------
--=architecture===============================================================
architecture rtl of core_top is
------------------------------------------------------------------------------
--============================================================================
-- signal declaration
------------------------------------------------------------------------------
--============================================================================
signal shift_register_r : std_logic_vector (g_number_of_out_signals-1 downto 0);
signal old_shift_clock_r : std_logic := '0';
------------------------------------------------------------------------------
--============================================================================
begin
------------------------------------------------------------------------------
-- module instantiation
100,7 → 101,11
------------------------------------------------------------------------------
signals_o <= shift_register_r;
------------------------------------------------------------------------------
end rtl;
----------------------------------------------------------------------
---- end of file ----
----------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--============================================================================
end rtl; --core_top
--============================================================================
-- end of file
--============================================================================
/rtl/vhdl/top.vhd
3,29 → 3,33
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- https://opencores.org/project/vhdl_wb_tb ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the highest (top) module for synthesis. ----
---- Like tb_top it instantiates the core_top module and ----
---- provides parameters/generics. Where the tb_top module ----
---- provides parameters for simulation this file provides ----
---- parameters for synthesis. ----
---- This file contains the highest (top) module of the test ----
---- bench. ----
---- It instantiates the design under test (DUT), instantiates ----
---- the stimulator module for test vector generation, ----
---- instantiates the verifier module for result comparison, ----
---- instantiates the test case top (testcase_top) bfm, ----
---- interconnects all three components, generates DUT-external ----
---- clocks and resets. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- SVN information
----
---- $URL: $
---- $Revision: $
---- $Date: $
---- $Author: $
---- $Id: $
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
69,14 → 73,16
);
end entity top;
 
-- architecture ------------------------------------------------------
--=architecture===============================================================
architecture rtl of top is
-----------------------------------------------------------------------------
--============================================================================
-- signal declaration
--============================================================================
-- constant number_of_stimulus_signals_c : integer := 8;
-- signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0);
-----------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------
--============================================================================
-- instance of design
core_top_inst : entity work.core_top
generic map(
91,6 → 97,6
);
-----------------------------------------------------------------------------
end rtl;
----------------------------------------------------------------------
---- end of file ----
----------------------------------------------------------------------
--============================================================================
-- end of file
--============================================================================
/rtl_sim/run/sim.mpf
169,7 → 169,7
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
AssertionFormat = "** [%I] %T %S %R\n"
AssertionFormat = "** %T %S %R [%I]\n"
 
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
335,36 → 335,36
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 15
Project_File_0 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl_sim/run/sim.mpf
Project_File_P_0 = compile_order -1 last_compile 0 folder z_others dont_compile 1 group_id 0 file_type txt ood 1
Project_File_1 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/verifier.vhd
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_2 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/top.vhd
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532164414 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_3 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/core_top.vhd
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532164727 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_4 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tc_xxxx.vhd
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164665 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_5 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tb_pkg.vhd
Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_6 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tb_top.vhd
Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164891 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_7 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/wishbone_pkg.vhd
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532164414 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_8 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tc_top.vhd
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_9 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/convert_pkg.vhd
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532164414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_10 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl_sim/bin/init.do
Project_File_P_10 = compile_order -1 last_compile 0 folder z_others dont_compile 1 group_id 0 file_type tcl ood 1
Project_File_11 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/wishbone_bfm_pkg.vhd
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164775 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_12 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/stimulator.vhd
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532163339 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2008
Project_File_13 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/my_project_pkg.vhd
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532165114 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_14 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl_sim/bin/s.do
Project_File_P_14 = folder z_others last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1
Project_File_0 = D:/OpenCoresOrg/vhdl_wb_tb/bench/vhdl/tb_top.vhd
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532103544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_1 = D:/OpenCoresOrg/vhdl_wb_tb/rtl_sim/bin/s.do
Project_File_P_1 = folder z_others last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1
Project_File_2 = D:/OpenCoresOrg/vhdl_wb_tb/rtl/vhdl/packages/convert_pkg.vhd
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532103347 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_3 = D:/OpenCoresOrg/vhdl_wb_tb/rtl_sim/bin/init.do
Project_File_P_3 = compile_order -1 last_compile 0 folder z_others dont_compile 1 group_id 0 file_type tcl ood 1
Project_File_4 = D:/OpenCoresOrg/vhdl_wb_tb/bench/vhdl/stimulator.vhd
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532103545 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_5 = D:/OpenCoresOrg/vhdl_wb_tb/bench/vhdl/wishbone_bfm_pkg.vhd
Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532104156 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_6 = D:/OpenCoresOrg/vhdl_wb_tb/rtl/vhdl/top.vhd
Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532103544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_7 = D:/OpenCoresOrg/vhdl_wb_tb/bench/vhdl/tc_xxxx.vhd
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532104409 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_8 = D:/OpenCoresOrg/vhdl_wb_tb/rtl/vhdl/packages/wishbone_pkg.vhd
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532103735 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_9 = D:/OpenCoresOrg/vhdl_wb_tb/rtl_sim/run/sim.mpf
Project_File_P_9 = compile_order -1 last_compile 0 folder z_others dont_compile 1 group_id 0 file_type txt ood 1
Project_File_10 = D:/OpenCoresOrg/vhdl_wb_tb/bench/vhdl/verifier.vhd
Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532103544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_11 = D:/OpenCoresOrg/vhdl_wb_tb/rtl/vhdl/packages/my_project_pkg.vhd
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532103652 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_12 = D:/OpenCoresOrg/vhdl_wb_tb/rtl/vhdl/core_top.vhd
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532103545 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_13 = D:/OpenCoresOrg/vhdl_wb_tb/bench/vhdl/testcase_top.vhd
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532103544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_14 = D:/OpenCoresOrg/vhdl_wb_tb/bench/vhdl/tb_pkg.vhd
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532103544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_Sim_Count = 0
Project_Folder_Count = 4
Project_Folder_0 = bench
/rtl_sim/run/vsim.wlf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/rtl_sim/run/wave.do
1,8 → 1,8
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider TestBench_WbMaster
add wave -noupdate /tb_top/tc_top_inst/wb_o
add wave -noupdate /tb_top/tc_top_inst/wb_i
add wave -noupdate /tb_top/testcase_top_inst/wb_o
add wave -noupdate /tb_top/testcase_top_inst/wb_i
add wave -noupdate -divider WbStimulator
add wave -noupdate /tb_top/stimulator_inst/s_register0
add wave -noupdate /tb_top/stimulator_inst/s_register1
33,5 → 33,5
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {7958914428 fs} {7970583452 fs}
WaveRestoreZoom {8258914428 fs} {8270583452 fs}
bookmark add wave A {{187592960 fs} {1276319150 fs}} 0

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