URL
https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk
Subversion Repositories vhdl_wb_tb
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 17 to Rev 18
- ↔ Reverse comparison
Rev 17 → Rev 18
/vhdl_wb_tb/trunk/bench/vhdl/tb_top.vhd
141,6 → 141,9
wb_bfm_in_s.clk <= wb_clock_s; |
wb_bfm_in_s.int <= '0'; |
wb_bfm_in_s.rst <= wb_reset_s; |
wb_bfm_in_s.tgd <= (others => '0'); |
wb_bfm_in_s.err <= '0'; |
wb_bfm_in_s.rty <= '0'; |
for I in number_of_wb_slaves_c-1 downto 0 loop |
wb_slaves_in_s(I) <= work.wishbone_pkg.wb_master_out_idle_c; -- default values are init (idle) values |
wb_slaves_in_s(I).clk <= wb_clock_s; |
148,6 → 151,9
if ( wb_bfm_out_s.adr(31 downto 28) = to_std_logic_vector(I,4)) then -- decode the upper nibble for module decoding |
wb_bfm_in_s.dat <= wb_slaves_out_s(I).dat; |
wb_bfm_in_s.ack <= wb_slaves_out_s(I).ack; |
wb_bfm_in_s.tgd <= wb_slaves_out_s(I).tgd; |
wb_bfm_in_s.err <= wb_slaves_out_s(I).err; |
wb_bfm_in_s.rty <= wb_slaves_out_s(I).rty; |
wb_slaves_in_s(I).dat <= wb_bfm_out_s.dat; |
wb_slaves_in_s(I).tgd <= wb_bfm_out_s.tgd; |
wb_slaves_in_s(I).adr <= wb_bfm_out_s.adr; |