URL
https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk
Subversion Repositories vhdl_wb_tb
Compare Revisions
- This comparison shows the changes necessary to convert path
/vhdl_wb_tb/trunk/bench/vhdl
- from Rev 20 to Rev 23
- ↔ Reverse comparison
Rev 20 → Rev 23
/wishbone_bfm_pkg.vhd
112,31 → 112,33
---------------------------------------------------------------------- |
-- generate single write cycle |
procedure wb_write( |
address_i : in integer; -- address to write to |
data_i : in integer; -- data value to be written |
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals |
signal o : out wishbone_bfm_master_out_t; -- incoming wb signals |
display_error_message_i : in integer range 0 to 2 := 1; -- verbose mode; 2= print all activities; others: print nothing |
additional_error_message_i : in string := "" -- string to be added in front of generated message |
address_i : in integer; -- address to write to |
data_i : in integer; -- data value to be written |
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals |
signal o : out wishbone_bfm_master_out_t; -- incoming wb signals |
verbose_mode_i : in integer range 0 to 2 := 1; -- verbose mode; 2= print all activities; others: print nothing |
message_prolog_i : in string := "" -- string to be added in front of generated message |
); |
|
-- generate single read cycle and verify read word with expected_data_i |
procedure wb_read( |
address_i : in integer; -- address to read from |
expected_data_i : in integer; -- data to be compared to read data; if different an error message is generated |
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals |
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals |
display_error_message_i : in integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp. |
additional_error_message_i : in string := ""; -- string to be added in front of generated message |
expected_data_mask_i : in integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared |
address_i : in integer; -- address to read from |
expected_data_i : in integer; -- data to be compared to read data; if different an error message is generated |
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals |
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals |
verbose_mode_i : in integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp. |
message_prolog_i : in string := ""; -- string to be added in front of generated message |
expected_data_mask_i : in integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared |
); |
|
-- generate single read cycle and return read data via read_data_o |
procedure wb_read( |
address_i : in integer; -- address to read from |
read_data_o : out std_logic_vector (wishbone_data_width_c-1 downto 0); -- read data output |
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals |
signal o : out wishbone_bfm_master_out_t -- outgoing wb signals |
address_i : in integer; -- address to read from |
read_data_o : out std_logic_vector (wishbone_data_width_c-1 downto 0); -- read data output |
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals |
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals |
verbose_mode_i : in integer range 0 to 4 := 0; -- verbose mode; 2 = output read data; others: no output |
message_prolog_i : in string := "" -- string to be added in front of generated message |
); |
---------------------------------------------------------------------- |
end; |
146,12 → 148,12
---------------------------------------------------------------------- |
---------------------------------------------------------------------- |
procedure wb_write( |
address_i : in integer; -- address to write to |
data_i : in integer; -- data value to be written |
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals |
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals |
display_error_message_i : in integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all |
additional_error_message_i : in string := "" -- string to be added in front of generated message |
address_i : in integer; -- address to write to |
data_i : in integer; -- data value to be written |
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals |
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals |
verbose_mode_i : in integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all |
message_prolog_i : in string := "" -- string to be added in front of generated message |
) is |
---------------------------------------------------------------------- |
begin |
166,8 → 168,8
o.stb <= '1'; |
o.tga <= (others => '0'); |
o.tgc <= (others => '0'); |
if (display_error_message_i = 2) then |
report additional_error_message_i & " writing :" & to_string(data_i, 16, wishbone_data_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4); |
if (verbose_mode_i = 2) then |
report message_prolog_i & " writing :" & to_string(data_i, 16, wishbone_data_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4); |
end if; |
|
-- ack handling |
182,10 → 184,12
---------------------------------------------------------------------- |
---------------------------------------------------------------------- |
procedure wb_read( |
address_i : in integer; -- address to read from |
read_data_o : out std_logic_vector (wishbone_data_width_c-1 downto 0);-- read data output |
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals |
signal o : out wishbone_bfm_master_out_t -- outgoing wb signals |
address_i : in integer; -- address to read from |
read_data_o : out std_logic_vector (wishbone_data_width_c-1 downto 0);-- read data output |
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals |
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals |
verbose_mode_i : in integer range 0 to 4 := 0; -- verbose mode; 2 = output read data; others: no output |
message_prolog_i : in string := "" -- string to be added in front of generated message |
) is |
---------------------------------------------------------------------- |
begin |
209,17 → 213,22
end if; |
end loop; |
o <= wb_bfm_master_out_idle_c; -- reset bus |
|
if (verbose_mode_i = 2) then -- output all |
report message_prolog_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
" was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4) |
severity note; |
end wb_read; |
------------------------------------------------------------------------ |
------------------------------------------------------------------------ |
procedure wb_read( |
address_i : in integer; -- address to read from |
expected_data_i : in integer; -- data to be compared to read data; if different an error message is generated |
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals |
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals |
display_error_message_i : in integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp. |
additional_error_message_i : in string := ""; -- string to be added in front of generated message |
expected_data_mask_i : in integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared |
address_i : in integer; -- address to read from |
expected_data_i : in integer; -- data to be compared to read data; if different an error message is generated |
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals |
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals |
verbose_mode_i : in integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp. |
message_prolog_i : in string := ""; -- string to be added in front of generated message |
expected_data_mask_i : in integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared |
) is |
---------------------------------------------------------------------- |
variable readdata_v : std_logic_vector (31 downto 0); |
230,26 → 239,26
|
diff_v := to_integer(readdata_v) - expected_data_i; |
|
if (display_error_message_i = 1) then -- output errors only |
if (verbose_mode_i = 1) then -- output errors only |
if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then |
report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
report "error" & message_prolog_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
" was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4) |
severity error; |
end if; |
elsif (display_error_message_i = 2) then -- output all |
report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
elsif (verbose_mode_i = 2) then -- output all |
report message_prolog_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
" was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4) |
severity note; |
elsif (display_error_message_i = 3) then -- output filter |
elsif (verbose_mode_i = 3) then -- output filter |
if ((readdata_v and to_std_logic_vector(expected_data_mask_i, wishbone_data_width_c)) /= |
to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then |
report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
report message_prolog_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
" was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4) |
severity note; |
end if; |
elsif display_error_message_i = 4 then |
elsif verbose_mode_i = 4 then |
if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then |
report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
report "error" & message_prolog_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) & |
" was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4) & " diff: " & to_string(readdata_v,16,wishbone_address_width_c/4) |
severity error; |
end if; |