OpenCores
URL https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk

Subversion Repositories vhdl_wb_tb

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /vhdl_wb_tb/trunk/bench
    from Rev 4 to Rev 5
    ↔ Reverse comparison
  •

Rev 4 → Rev 5

/vhdl/stimulator.vhd
63,13 → 63,13
-- entity ------------------------------------------------------------
entity stimulator is
generic(
g_number_of_signals : natural := 1
number_of_signals_g : natural := 1
);
port(
wb_i : in wishbone_slave_in_t;
wb_o : out wishbone_slave_out_t;
signals_o : out std_logic_vector(g_number_of_signals-1 downto 0)
signals_o : out std_logic_vector(number_of_signals_g-1 downto 0)
);
end stimulator;
 
78,8 → 78,8
--============================================================================
-- signal declaration
--============================================================================
signal s_register0 : std_logic_vector(wb_i.dat'left downto 0);
signal s_register1 : std_logic_vector(wb_i.dat'left downto 0);
signal register0_s : std_logic_vector(wb_i.dat'left downto 0);
signal register1_s : std_logic_vector(wb_i.dat'left downto 0);
--============================================================================
begin
------------------------------------------------------------------------------
93,9 → 93,9
begin
case wb_i.adr(27 downto 0) is
when 28X"000_0000" =>
wb_o.dat <= s_register0;
wb_o.dat <= register0_s;
when 28X"000_0004" =>
wb_o.dat <= s_register1;
wb_o.dat <= register1_s;
when others =>
wb_o.dat <= (others =>'U');
end case;
104,15 → 104,15
proc_avalon_write_data : process (all)
begin
if (wb_i.rst = '1') then
s_register0 <= (others => '0');
s_register1 <= (others => '0');
register0_s <= (others => '0');
register1_s <= (others => '0');
elsif (rising_edge(wb_i.clk)) then
if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then
case wb_i.adr(27 downto 0) is
when 28X"000_0000" =>
s_register0 <= wb_i.dat;
register0_s <= wb_i.dat;
when 28X"000_0004" =>
s_register1 <= wb_i.dat;
register1_s <= wb_i.dat;
when others =>
end case;
end if;
119,7 → 119,7
end if;
end process;
------------------------------------------------------------------------------
signals_o <= s_register0(signals_o'left downto 0);
signals_o <= register0_s(signals_o'left downto 0);
--============================================================================
end rtl; --stimulator
----------------------------------------------------------------------
/vhdl/tb_top.vhd
77,28 → 77,28
-- architecture ------------------------------------------------------
architecture rtl of tb_top is
-----------------------------------------------------------------------------
constant g_wb_clock_period : time := 20.0 ns; -- 50 mhz
constant wb_clock_period_g : time := 20.0 ns; -- 50 mhz
-----------------------------------------------------------------------------
signal s_wb_bfm_out : wishbone_bfm_master_out_t; -- from testcase_top
signal s_wb_bfm_in : wishbone_bfm_master_in_t; -- to testcase_top
signal wb_bfm_out_s : wishbone_bfm_master_out_t; -- from testcase_top
signal wb_bfm_in_s : wishbone_bfm_master_in_t; -- to testcase_top
signal s_wb_master_out : wishbone_master_out_t; -- from wb_decoder
signal s_wb_master_in : wishbone_master_in_t; -- to wb_decoder
signal wb_master_out_s : wishbone_master_out_t; -- from wb_decoder
signal wb_master_in_s : wishbone_master_in_t; -- to wb_decoder
constant number_of_wb_slaves_c : integer := 2;
signal s_wb_slaves_in : wishbone_slave_in_array_t (number_of_wb_slaves_c-1 downto 0);
signal s_wb_slaves_out : wishbone_slave_out_array_t (number_of_wb_slaves_c-1 downto 0);
signal wb_slaves_in_s : wishbone_slave_in_array_t (number_of_wb_slaves_c-1 downto 0);
signal wb_slaves_out_s : wishbone_slave_out_array_t (number_of_wb_slaves_c-1 downto 0);
signal s_wb_clock : std_logic := '0';
signal s_wb_clock_locked : std_logic := '0';
signal s_wb_reset_p1 : std_logic := '1';
signal s_wb_reset_p2 : std_logic := '1';
signal s_wb_reset : std_logic := '1';
signal wb_clock_s : std_logic := '0';
signal wb_clock_locked_s : std_logic := '0';
signal wb_reset_p1_s : std_logic := '1';
signal wb_reset_p2_s : std_logic := '1';
signal wb_reset_s : std_logic := '1';
constant number_of_stimulus_signals_c : integer := 8;
constant number_of_verify_signals_c : integer := 8;
signal s_stimulus : std_logic_vector(number_of_stimulus_signals_c-1 downto 0);
signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0);
signal stimulus_s : std_logic_vector(number_of_stimulus_signals_c-1 downto 0);
signal verify_s : std_logic_vector(number_of_verify_signals_c-1 downto 0);
-----------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------
105,59 → 105,59
--clocks---------------------------------------------------------------------
wb_clock_generator : process -- required for test bench wb bus; 50mhz is standard
begin
s_wb_clock <= '0';
wait for g_wb_clock_period/2;
s_wb_clock <= '1';
wait for g_wb_clock_period/2;
s_wb_clock_locked <= '1';
wb_clock_s <= '0';
wait for wb_clock_period_g/2;
wb_clock_s <= '1';
wait for wb_clock_period_g/2;
wb_clock_locked_s <= '1';
end process;
-----------------------------------------------------------------------------
synchronize_reset_proc : process(all)
begin
if (s_wb_clock_locked = '0') then
s_wb_reset_p1 <= '1';
s_wb_reset_p2 <= '1';
elsif (rising_edge(s_wb_clock)) then
s_wb_reset_p1 <= '0'; -- or s_tc_reset;
s_wb_reset_p2 <= s_wb_reset_p1;
if (wb_clock_locked_s = '0') then
wb_reset_p1_s <= '1';
wb_reset_p2_s <= '1';
elsif (rising_edge(wb_clock_s)) then
wb_reset_p1_s <= '0'; -- or tc_reset_s;
wb_reset_p2_s <= wb_reset_p1_s;
end if;
end process;
s_wb_reset <= s_wb_reset_p2;
wb_reset_s <= wb_reset_p2_s;
-----------------------------------------------------------------------------
-- instance of test case "player"; runs tc_xxxx modules
tc_top_inst : entity work.tc_top
port map (
wb_o => s_wb_bfm_out,
wb_i => s_wb_bfm_in
wb_o => wb_bfm_out_s,
wb_i => wb_bfm_in_s
);
-----------------------------------------------------------------------------
-- splits the test case wb bus for all stimulation and verifier modules.
-- decodes the given bits (g_decoded_address_msb:g_decoded_address_lsb) and#
-- compares them to 0..n, with n=(g_number_of_ports-1)
-- decodes the given bits (decoded_address_msb_g:decoded_address_lsb_g) and#
-- compares them to 0..n, with n=(number_of_ports_g-1)
proc_readdata_decoder : process (all)
begin
s_wb_bfm_in.dat <= (others => 'U');
s_wb_bfm_in.ack <= '1';
s_wb_bfm_in.clk <= s_wb_clock;
s_wb_bfm_in.int <= '0';
s_wb_bfm_in.rst <= s_wb_reset;
wb_bfm_in_s.dat <= (others => 'U');
wb_bfm_in_s.ack <= '1';
wb_bfm_in_s.clk <= wb_clock_s;
wb_bfm_in_s.int <= '0';
wb_bfm_in_s.rst <= wb_reset_s;
for I in number_of_wb_slaves_c-1 downto 0 loop
s_wb_slaves_in(I) <= work.wishbone_pkg.wb_master_out_idle_c; -- default values are init (idle) values
s_wb_slaves_in(I).clk <= s_wb_clock;
s_wb_slaves_in(I).rst <= s_wb_reset OR s_wb_bfm_out.rst;
if ( s_wb_bfm_out.adr(31 downto 28) = to_std_logic_vector(I,4)) then -- decode the upper nibble for module decoding
s_wb_bfm_in.dat <= s_wb_slaves_out(I).dat;
s_wb_bfm_in.ack <= s_wb_slaves_out(I).ack;
s_wb_slaves_in(I).dat <= s_wb_bfm_out.dat;
s_wb_slaves_in(I).tgd <= s_wb_bfm_out.tgd;
s_wb_slaves_in(I).adr <= s_wb_bfm_out.adr;
s_wb_slaves_in(I).cyc <= s_wb_bfm_out.cyc;
s_wb_slaves_in(I).lock <= s_wb_bfm_out.lock;
s_wb_slaves_in(I).sel <= s_wb_bfm_out.sel;
s_wb_slaves_in(I).stb <= s_wb_bfm_out.stb;
s_wb_slaves_in(I).tga <= s_wb_bfm_out.tga;
s_wb_slaves_in(I).tgc <= s_wb_bfm_out.tgc;
s_wb_slaves_in(I).we <= s_wb_bfm_out.we;
wb_slaves_in_s(I) <= work.wishbone_pkg.wb_master_out_idle_c; -- default values are init (idle) values
wb_slaves_in_s(I).clk <= wb_clock_s;
wb_slaves_in_s(I).rst <= wb_reset_s OR wb_bfm_out_s.rst;
if ( wb_bfm_out_s.adr(31 downto 28) = to_std_logic_vector(I,4)) then -- decode the upper nibble for module decoding
wb_bfm_in_s.dat <= wb_slaves_out_s(I).dat;
wb_bfm_in_s.ack <= wb_slaves_out_s(I).ack;
wb_slaves_in_s(I).dat <= wb_bfm_out_s.dat;
wb_slaves_in_s(I).tgd <= wb_bfm_out_s.tgd;
wb_slaves_in_s(I).adr <= wb_bfm_out_s.adr;
wb_slaves_in_s(I).cyc <= wb_bfm_out_s.cyc;
wb_slaves_in_s(I).lock <= wb_bfm_out_s.lock;
wb_slaves_in_s(I).sel <= wb_bfm_out_s.sel;
wb_slaves_in_s(I).stb <= wb_bfm_out_s.stb;
wb_slaves_in_s(I).tga <= wb_bfm_out_s.tga;
wb_slaves_in_s(I).tgc <= wb_bfm_out_s.tgc;
wb_slaves_in_s(I).we <= wb_bfm_out_s.we;
end if;
end loop;
end process;
165,36 → 165,36
-- instance of design under test
core_top_inst : entity work.core_top
generic map(
g_number_of_in_signals => number_of_stimulus_signals_c,
g_number_of_out_signals => number_of_verify_signals_c
number_of_in_signals_g => number_of_stimulus_signals_c,
number_of_out_signals_g => number_of_verify_signals_c
)
port map(
clock_i => s_wb_clock,
reset_i => s_wb_reset,
signals_i => s_stimulus,
signals_o => s_verify
clock_i => wb_clock_s,
reset_i => wb_reset_s,
signals_i => stimulus_s,
signals_o => verify_s
);
-----------------------------------------------------------------------------
-- instance of stimulator
stimulator_inst : entity work.stimulator
generic map(
g_number_of_signals => number_of_stimulus_signals_c
number_of_signals_g => number_of_stimulus_signals_c
)
port map(
wb_i => s_wb_slaves_in(0),
wb_o => s_wb_slaves_out(0),
signals_o => s_stimulus
wb_i => wb_slaves_in_s(0),
wb_o => wb_slaves_out_s(0),
signals_o => stimulus_s
);
-----------------------------------------------------------------------------
-- instance of stimulator
verifier_inst : entity work.verifier
generic map(
g_number_of_signals => number_of_verify_signals_c
number_of_signals_g => number_of_verify_signals_c
)
port map(
wb_i => s_wb_slaves_in(1),
wb_o => s_wb_slaves_out(1),
signals_i => s_verify
wb_i => wb_slaves_in_s(1),
wb_o => wb_slaves_out_s(1),
signals_i => verify_s
);
-----------------------------------------------------------------------------
end rtl;
/vhdl/verifier.vhd
65,13 → 65,13
-- entity ------------------------------------------------------------
entity verifier is
generic(
g_number_of_signals : natural := 1
number_of_signals_g : natural := 1
);
port(
wb_i : in wishbone_slave_in_t;
wb_o : out wishbone_slave_out_t;
signals_i : in std_logic_vector(g_number_of_signals-1 downto 0)
signals_i : in std_logic_vector(number_of_signals_g-1 downto 0)
);
end verifier;
 
80,8 → 80,8
------------------------------------------------------------------------------
-- signal declaration
------------------------------------------------------------------------------
signal s_register0 : std_logic_vector(31 downto 0);
signal s_register1 : std_logic_vector(31 downto 0);
signal register0_s : std_logic_vector(31 downto 0);
signal register1_s : std_logic_vector(31 downto 0);
------------------------------------------------------------------------------
begin
------------------------------------------------------------------------------
96,9 → 96,9
begin
case wb_i.adr(27 downto 0) is
when 28X"000_0000" =>
wb_o.dat <= s_register0;
wb_o.dat <= register0_s;
when 28X"000_0004" =>
wb_o.dat <= s_register1;
wb_o.dat <= register1_s;
when 28X"000_0008" =>
wb_o.dat <= zero_c(wb_o.dat'left downto signals_i'left+1) & signals_i;
when others =>
110,15 → 110,15
proc_avalon_write_data : process (all)
begin
if (wb_i.rst = '1') then
s_register0 <= (others => '0');
s_register1 <= (others => '0');
register0_s <= (others => '0');
register1_s <= (others => '0');
elsif (rising_edge(wb_i.clk)) then
if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then
case wb_i.adr(27 downto 0) is
when 28X"000_0000" =>
s_register0 <= wb_i.dat;
register0_s <= wb_i.dat;
when 28X"000_0004" =>
s_register1 <= wb_i.dat;
register1_s <= wb_i.dat;
when others =>
end case;
end if;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.