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URL https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk

Subversion Repositories vhdl_wb_tb

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /vhdl_wb_tb/trunk/rtl
    from Rev 17 to Rev 21
    Reverse comparison

Rev 17 → Rev 21

/vhdl/packages/convert_pkg.vhd
1,19 → 1,19
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains some type conversion functions. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- ----
----------------------------------------------------------------------
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- ----
----------------------------------------------------------------------
---- SVN information
----
---- $URL$
21,32 → 21,32
---- $Date$
---- $Author$
---- $Id$
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
-- library -----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
60,7 → 60,7
FUNCTION to_integer(input : std_logic_vector) RETURN integer;
FUNCTION to_string(int : integer; base : integer range 1 to 16 := 16; length : integer range 1 to 8:= 8) RETURN string;
FUNCTION to_string(slv : std_logic_vector; base : integer range 1 to 16 := 16; length : integer range 1 to 8 := 8) RETURN string;
 
END convert_pkg;
 
-- package body ------------------------------------------------------
136,13 → 136,13
abs_int := ABS(int);
num := abs_int;
--
IF (length = 0) THEN -- automatic length detection
IF (length = 0) THEN -- automatic length detection
WHILE num >= base LOOP -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
END LOOP; -- number.
ELSE
len := ABS(length); --
len := ABS(length); --
END IF;
 
IF (base /= 10) THEN
255,8 → 255,8
RETURN hex(1 TO hexlen);
END to_string;
----------------------------------------------------------------------
FUNCTION to_string( slv : std_logic_vector;
base : integer range 1 to 16 := 16;
FUNCTION to_string( slv : std_logic_vector;
base : integer range 1 to 16 := 16;
length : integer range 1 to 8 := 8
) RETURN string IS
 
266,5 → 266,5
----------------------------------------------------------------------
end package body;
----------------------------------------------------------------------
---- end of file ----
---- end of file ----
----------------------------------------------------------------------

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