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URL https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk

Subversion Repositories vhdl_wb_tb

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  • This comparison shows the changes necessary to convert path 
    /vhdl_wb_tb/trunk/rtl
    from Rev 21 to Rev 22
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Rev 21 → Rev 22

/vhdl/packages/wishbone_pkg.vhd
1,25 → 1,25
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the wishbone_pkg package and defines ----
---- basic wishbone types. ----
---- ----
---- basic wishbone types. ----
---- ----
---- This file bases on the file wishbone_pkg.vhd located at ----
---- https://github.com/twlostow/dsi-shield/blob/master/hdl/ip_cores/local/wishbone_pkg.vhd ---
---- See this file also for the authors name. ----
---- Its original file was licensed under LGPL 3.0 ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- ----
----------------------------------------------------------------------
---- See this file also for the authors name. ----
---- Its original file was licensed under LGPL 3.0 ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, sinx@opencores.org ----
---- ----
----------------------------------------------------------------------
---- SVN information
----
---- $URL$
27,32 → 27,32
---- $Date$
---- $Author$
---- $Id$
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
-- library -----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
65,12 → 65,12
 
subtype wishbone_address_t is std_logic_vector(wishbone_address_width_c-1 downto 0);
subtype wishbone_data_t is std_logic_vector(wishbone_data_width_c-1 downto 0);
subtype wishbone_byte_select_t is std_logic_vector((wishbone_address_width_c/8)-1 downto 0);
subtype wishbone_byte_select_t is std_logic_vector((wishbone_data_width_c/8)-1 downto 0);
--subtype wishbone_cycle_type_t is std_logic_vector(2 downto 0);
--subtype wishbone_burst_type_t is std_logic_vector(1 downto 0);
 
type wishbone_master_out_t is record
-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
clk : std_logic; -- clock [mandatory RULE 3.40]
dat : wishbone_data_t; -- data []
rst : std_logic; -- reset [mandatory RULE 3.40]
88,10 → 88,10
subtype wishbone_slave_in_t is wishbone_master_out_t;
 
type wishbone_slave_out_t is record
-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
dat : wishbone_data_t; -- read data []
tgd : wishbone_tag_data_t; -- read data tag []
-- 2.2.4 SLAVE Signals
-- 2.2.4 SLAVE Signals
ack : std_logic; -- acknowledge [mandatory RULE 3.40]
err : std_logic; -- error [optional PERMISSION 3.20]
rty : std_logic; -- retry [optional PERMISSION 3.25]
102,8 → 102,8
 
-- subtype wishbone_device_descriptor_t is std_logic_vector(255 downto 0);
 
-- type wishbone_byte_select_array_t is array(natural range <>) of wishbone_byte_select_t;
-- type wishbone_data_array_t is array(natural range <>) of wishbone_data_t;
-- type wishbone_byte_select_array_t is array(natural range <>) of wishbone_byte_select_t;
-- type wishbone_data_array_t is array(natural range <>) of wishbone_data_t;
type wishbone_address_array_t is array(natural range <>) of wishbone_address_t;
type wishbone_master_out_array_t is array (natural range <>) of wishbone_master_out_t;
type wishbone_slave_in_array_t is array (natural range <>) of wishbone_slave_in_t;
126,7 → 126,18
tgc => (others=>'0'),
we => '0'
);
constant wb_slave_in_idle_c : wishbone_slave_in_t := wb_master_out_idle_c;
 
constant wb_master_in_idle_c : wishbone_master_in_t := (
dat => wishbone_data_of_unused_address_c,
tgd => (others=>'0'),
ack => '0',
err => '0',
rty => '0',
int => '0'
);
constant wb_slave_out_idle_c : wishbone_slave_out_t := wb_master_in_idle_c;
 
-- constant cc_dummy_address : std_logic_vector(wishbone_address_width_c-1 downto 0) :=(others => 'X');
-- constant cc_dummy_data : std_logic_vector(wishbone_address_width_c-1 downto 0) := (others => 'X');
-- constant cc_dummy_sel : std_logic_vector(wishbone_data_width_c/8-1 downto 0) := (others => 'X');
145,5 → 156,5
package body wishbone_pkg is
end wishbone_pkg;
----------------------------------------------------------------------
---- end of file ----
---- end of file ----
----------------------------------------------------------------------

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