URL
https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk
Subversion Repositories vhdl_wb_tb
Compare Revisions
- This comparison shows the changes necessary to convert path
/vhdl_wb_tb/trunk/rtl
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/vhdl/packages/my_project_pkg.vhd
67,8 → 67,8
subtype wishbone_tag_address_t is std_logic_vector(1 downto 0); |
subtype wishbone_tag_cycle_t is std_logic_vector(1 downto 0); |
|
--type t_wishbone_interface_mode is (CLASSIC, PIPELINED); |
--type t_wishbone_address_granularity is (BYTE, WORD); |
--type wishbone_interface_mode_t is (CLASSIC, PIPELINED); |
--type wishbone_address_granularity_t is (BYTE, WORD); |
constant zero_c : std_logic_vector(511 downto 0) := (others => '0'); |
end my_project_pkg; |
|
/vhdl/core_top.vhd
63,14 → 63,14
-- entity ------------------------------------------------------------ |
entity core_top is |
generic( |
g_number_of_in_signals : natural := 1; |
g_number_of_out_signals : natural := 1 |
number_of_in_signals_g : natural := 1; |
number_of_out_signals_g : natural := 1 |
); |
port( |
clock_i : in std_logic; |
reset_i : in std_logic; |
signals_i : in std_logic_vector(g_number_of_in_signals-1 downto 0); |
signals_o : out std_logic_vector(g_number_of_out_signals-1 downto 0) |
signals_i : in std_logic_vector(number_of_in_signals_g-1 downto 0); |
signals_o : out std_logic_vector(number_of_out_signals_g-1 downto 0) |
); |
end core_top; |
|
79,7 → 79,7
------------------------------------------------------------------------------ |
-- signal declaration |
------------------------------------------------------------------------------ |
signal shift_register_r : std_logic_vector (g_number_of_out_signals-1 downto 0); |
signal shift_register_r : std_logic_vector (number_of_out_signals_g-1 downto 0); |
signal old_shift_clock_r : std_logic := '0'; |
------------------------------------------------------------------------------ |
begin |
/vhdl/top.vhd
73,7 → 73,7
architecture rtl of top is |
----------------------------------------------------------------------------- |
-- constant number_of_stimulus_signals_c : integer := 8; |
-- signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0); |
-- signal verify_s : std_logic_vector(number_of_verify_signals_c-1 downto 0); |
----------------------------------------------------------------------------- |
begin |
----------------------------------------------------------------------------- |
80,8 → 80,8
-- instance of design |
core_top_inst : entity work.core_top |
generic map( |
g_number_of_in_signals => 8, |
g_number_of_out_signals => 8 |
number_of_in_signals_g => 8, |
number_of_out_signals_g => 8 |
) |
port map( |
clock_i => clock_i, |