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Rev 1 → Rev 2

/bench/vhdl/stimulator.vhd
0,0 → 1,129
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the top functional module of the design ----
---- under test. The top functional module will be enclosed by ----
---- the top module for synthesis or the tb_top for simulation. ----
---- The top module can contain some synthesis specific code, ----
---- where the tb_top contains simulation specific code. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
-- library -----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.convert_pkg.all;
use work.wishbone_pkg.all;
use work.wishbone_bfm_pkg.all;
 
-- entity ------------------------------------------------------------
entity stimulator is
generic(
g_number_of_signals : natural := 1
);
port(
wb_i : in wishbone_slave_in_t;
wb_o : out wishbone_slave_out_t;
signals_o : out std_logic_vector(g_number_of_signals-1 downto 0)
);
end stimulator;
 
--=architecture===============================================================
architecture rtl of stimulator is
--============================================================================
-- signal declaration
--============================================================================
signal s_register0 : std_logic_vector(wb_i.dat'left downto 0);
signal s_register1 : std_logic_vector(wb_i.dat'left downto 0);
--============================================================================
begin
------------------------------------------------------------------------------
wb_o.ack <= '1';
wb_o.err <= '0';
wb_o.rty <= '0';
wb_o.int <= '0';
wb_o.tgd <= (others => '0');
-- read data multiplexer
proc_read_data_mux : process (all)
begin
case wb_i.adr(27 downto 0) is
when 28X"000_0000" =>
wb_o.dat <= s_register0;
when 28X"000_0004" =>
wb_o.dat <= s_register1;
when others =>
wb_o.dat <= (others =>'U');
end case;
end process;
------------------------------------------------------------------------------
proc_avalon_write_data : process (all)
begin
if (wb_i.rst = '1') then
s_register0 <= (others => '0');
s_register1 <= (others => '0');
elsif (rising_edge(wb_i.clk)) then
if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then
case wb_i.adr(27 downto 0) is
when 28X"000_0000" =>
s_register0 <= wb_i.dat;
when 28X"000_0004" =>
s_register1 <= wb_i.dat;
when others =>
end case;
end if;
end if;
end process;
------------------------------------------------------------------------------
signals_o <= s_register0(signals_o'left downto 0);
--============================================================================
end rtl; --stimulator
--============================================================================
-- end of file
--============================================================================
/bench/vhdl/tb_pkg.vhd
0,0 → 1,87
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the highest (top) module of the test ----
---- bench. ----
---- It instantiates the design under test (DUT), instantiates ----
---- the stimulator module for test vector generation, ----
---- instantiates the verifier module for result comparison, ----
---- instantiates the test case top (testcase_top) bfm, ----
---- interconnects all three components, generates DUT-external ----
---- clocks and resets. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
-- library -----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.convert_pkg.all;
use work.wishbone_pkg.all;
use work.wishbone_bfm_pkg.all;
 
-- package -----------------------------------------------------------
package tb_pkg is
----------------------------------------------------------------------
-- address definitions
----------------------------------------------------------------------
-- ??? model registers
constant stimuator_base_c : integer := 16#00000000#;
constant stimulator_register0_c : integer := stimuator_base_c + 16#0000_0000#;
constant stimulator_register1_c : integer := stimuator_base_c + 16#0000_0004#;
-- ??? model registers
constant verifier_base_c : integer := 16#10000000#;
constant verifier_register0_c : integer := verifier_base_c + 16#0000_0000#;
constant verifier_register1_c : integer := verifier_base_c + 16#0000_0004#;
constant verifier_register2_c : integer := verifier_base_c + 16#0000_0008#;
----------------------------------------------------------------------
end package;
--============================================================================
-- end of file
--============================================================================
/bench/vhdl/tb_top.vhd
0,0 → 1,206
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the highest (top) module of the test ----
---- bench. ----
---- It instantiates the design under test (DUT), instantiates ----
---- the stimulator module for test vector generation, ----
---- instantiates the verifier module for result comparison, ----
---- instantiates the test case top (testcase_top) bfm, ----
---- interconnects all three components, generates DUT-external ----
---- clocks and resets. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
-- library -----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.convert_pkg.all;
use work.wishbone_pkg.all;
use work.wishbone_bfm_pkg.all;
 
-- entity ------------------------------------------------------------
entity tb_top is
-- empty entity, since this is the simulation top and all test cases are defined
-- in the tc_xxx files.
end entity tb_top;
 
--=architecture===============================================================
architecture rtl of tb_top is
--============================================================================
constant g_wb_clock_period : time := 20.0 ns; -- 50 mhz
--============================================================================
-- signal declaration
--============================================================================
-----------------------------------------------------------------------------
signal s_wb_bfm_out : wishbone_bfm_master_out_t; -- from testcase_top
signal s_wb_bfm_in : wishbone_bfm_master_in_t; -- to testcase_top
signal s_wb_master_out : wishbone_master_out_t; -- from wb_decoder
signal s_wb_master_in : wishbone_master_in_t; -- to wb_decoder
constant number_of_wb_slaves_c : integer := 2;
signal s_wb_slaves_in : wishbone_slave_in_array_t (number_of_wb_slaves_c-1 downto 0);
signal s_wb_slaves_out : wishbone_slave_out_array_t (number_of_wb_slaves_c-1 downto 0);
signal s_wb_clock : std_logic := '0';
signal s_wb_clock_locked : std_logic := '0';
signal s_wb_reset_p1 : std_logic := '1';
signal s_wb_reset_p2 : std_logic := '1';
signal s_wb_reset : std_logic := '1';
constant number_of_stimulus_signals_c : integer := 8;
constant number_of_verify_signals_c : integer := 8;
signal s_stimulus : std_logic_vector(number_of_stimulus_signals_c-1 downto 0);
signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0);
-----------------------------------------------------------------------------
-- other signals
 
-----------------------------------------------------------------------------
begin
--============================================================================
--clocks---------------------------------------------------------------------
wb_clock_generator : process -- required for test bench wb bus; 50mhz is standard
begin
s_wb_clock <= '0';
wait for g_wb_clock_period/2;
s_wb_clock <= '1';
wait for g_wb_clock_period/2;
s_wb_clock_locked <= '1';
end process;
-----------------------------------------------------------------------------
synchronize_reset_proc : process(all)
begin
if (s_wb_clock_locked = '0') then
s_wb_reset_p1 <= '1';
s_wb_reset_p2 <= '1';
elsif (rising_edge(s_wb_clock)) then
s_wb_reset_p1 <= '0'; -- or s_tc_reset;
s_wb_reset_p2 <= s_wb_reset_p1;
end if;
end process;
s_wb_reset <= s_wb_reset_p2;
-----------------------------------------------------------------------------
-- instance of test case "player"; runs tc_xxxx modules
testcase_top_inst : entity work.testcase_top
port map (
wb_o => s_wb_bfm_out,
wb_i => s_wb_bfm_in
);
-----------------------------------------------------------------------------
-- splits the test case wb bus for all stimulation and verifier modules.
-- decodes the given bits (g_decoded_address_msb:g_decoded_address_lsb) and#
-- compares them to 0..n, with n=(g_number_of_ports-1)
proc_readdata_decoder : process (all)
begin
s_wb_bfm_in.dat <= (others => 'U');
s_wb_bfm_in.ack <= '1';
s_wb_bfm_in.clk <= s_wb_clock;
s_wb_bfm_in.int <= '0';
s_wb_bfm_in.rst <= s_wb_reset;
for I in number_of_wb_slaves_c-1 downto 0 loop
s_wb_slaves_in(I) <= work.wishbone_pkg.wb_master_out_idle_c; -- default values are init (idle) values
s_wb_slaves_in(I).clk <= s_wb_clock;
s_wb_slaves_in(I).rst <= s_wb_reset OR s_wb_bfm_out.rst;
if ( s_wb_bfm_out.adr(31 downto 28) = to_std_logic_vector(I,4)) then -- decode the upper nibble for module decoding
s_wb_bfm_in.dat <= s_wb_slaves_out(I).dat;
s_wb_bfm_in.ack <= s_wb_slaves_out(I).ack;
s_wb_slaves_in(I).dat <= s_wb_bfm_out.dat;
s_wb_slaves_in(I).tgd <= s_wb_bfm_out.tgd;
s_wb_slaves_in(I).adr <= s_wb_bfm_out.adr;
s_wb_slaves_in(I).cyc <= s_wb_bfm_out.cyc;
s_wb_slaves_in(I).lock <= s_wb_bfm_out.lock;
s_wb_slaves_in(I).sel <= s_wb_bfm_out.sel;
s_wb_slaves_in(I).stb <= s_wb_bfm_out.stb;
s_wb_slaves_in(I).tga <= s_wb_bfm_out.tga;
s_wb_slaves_in(I).tgc <= s_wb_bfm_out.tgc;
s_wb_slaves_in(I).we <= s_wb_bfm_out.we;
end if;
end loop;
end process;
-----------------------------------------------------------------------------
-- instance of design under test
core_top_inst : entity work.core_top
generic map(
g_number_of_in_signals => number_of_stimulus_signals_c,
g_number_of_out_signals => number_of_verify_signals_c
)
port map(
clock_i => s_wb_clock,
reset_i => s_wb_reset,
signals_i => s_stimulus,
signals_o => s_verify
);
-----------------------------------------------------------------------------
-- instance of stimulator
stimulator_inst : entity work.stimulator
generic map(
g_number_of_signals => number_of_stimulus_signals_c
)
port map(
wb_i => s_wb_slaves_in(0),
wb_o => s_wb_slaves_out(0),
signals_o => s_stimulus
);
-----------------------------------------------------------------------------
-- instance of stimulator
verifier_inst : entity work.verifier
generic map(
g_number_of_signals => number_of_verify_signals_c
)
port map(
wb_i => s_wb_slaves_in(1),
wb_o => s_wb_slaves_out(1),
signals_i => s_verify
);
-----------------------------------------------------------------------------
end rtl;
--============================================================================
-- end of file
--============================================================================
/bench/vhdl/tc_xxxx.vhd
0,0 → 1,161
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the highest (top) module of the test ----
---- bench. ----
---- It instantiates the design under test (DUT), instantiates ----
---- the stimulator module for test vector generation, ----
---- instantiates the verifier module for result comparison, ----
---- instantiates the test case top (testcase_top) bfm, ----
---- interconnects all three components, generates DUT-external ----
---- clocks and resets. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
-- library -----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.convert_pkg.all;
use work.wishbone_pkg.all;
use work.wishbone_bfm_pkg.all;
use work.my_project_pkg.all;
use work.tb_pkg.all;
 
-- architecture ------------------------------------------------------
architecture tc_xxxx of testcase_top is
--==========================================================================
-- local constant definitions
--==========================================================================
--==========================================================================
begin
--==========================================================================
tc_xxxx_proc : process
begin
--==========================================================================
-- standard signal initialization
wb_o <= wb_bfm_master_out_idle_c;
wait until wb_i.rst = '0';
wait until rising_edge(wb_i.clk);
wait until rising_edge(wb_i.clk);
--
wait for 400 ns;
wait until rising_edge(wb_i.clk);
--
--==========================================================================
report "-----------------------------------------------------------------";
report "-- tc_xxxx: ADD_DESCRIPTION_HERE --";
report "-----------------------------------------------------------------";
--
report "--configure stimulator";
report "-----------------------------------------------------------------";
 
wb_write(stimulator_register0_c , 0, wb_i, wb_o);
 
report "--configure verifier";
report "-----------------------------------------------------------------";
 
wb_write(verifier_register0_c , 2, wb_i, wb_o);
wb_write(verifier_register1_c , 16#2b#, wb_i, wb_o);
report "--configuration done";
report "-----------------------------------------------------------------";
 
report "--starting stimulator";
report "-----------------------------------------------------------------";
wb_write(stimulator_register0_c , 3, wb_i, wb_o); -- shift '1' in
wb_write(stimulator_register0_c , 1, wb_i, wb_o);
wb_write(stimulator_register0_c , 2, wb_i, wb_o); -- shift '0' in
wb_write(stimulator_register0_c , 0, wb_i, wb_o);
wb_read (verifier_register2_c , 2, wb_i, wb_o);
 
wb_write(stimulator_register0_c , 3, wb_i, wb_o); -- shift '1' in
wb_write(stimulator_register0_c , 1, wb_i, wb_o);
wb_read (verifier_register2_c , 5, wb_i, wb_o); -- reads correct
report "-----------------------------------------------------------------";
report "-----------------------------------------------------------------";
report "-- All fine till here. Now we provoke error messages for illustration.";
wb_read (verifier_register2_c , 6, wb_i, wb_o); -- provoke error (read value is 5)
wb_read (verifier_register2_c , 6, wb_i, wb_o,0); -- provoke error (read value is 5)
wb_read (verifier_register2_c , 6, wb_i, wb_o,1); -- provoke error (read value is 5)
wb_read (verifier_register2_c , 6, wb_i, wb_o,2); -- provoke error (read value is 5)
wb_read (verifier_register2_c , 6, wb_i, wb_o,2,"<TEXT>"); -- provoke error (read value is 5)
wb_read (verifier_register2_c , 6, wb_i, wb_o,3,"",7); -- provoke error (read value is 5)
wb_read (verifier_register2_c , 6, wb_i, wb_o,4); -- provoke error (read value is 5)
 
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
report "-----------------------------------------------------------------";
report "--check results";
report "-----------------------------------------------------------------";
wait for 6 us;
wait until rising_edge(wb_i.clk);
wb_read (verifier_register2_c, 16#0000_0005#, wb_i, wb_o);
wait for 1 us;
-- =================================================
report "-- tc_xxxx finished";
-- =================================================
--
wait for 400 ns;
--wait;
--
report "test case tc_xxxx completed successfully"; --severity failure;
report "-----------------------------------------------------------------";
report "-----------------------------------------------------------------";
std.env.stop; -- pause simulation
 
--std.env.finish; -- stop simulation; end modelsim
end process tc_xxxx_proc;
--==========================================================================
end tc_xxxx;
--============================================================================
-- end of file
--============================================================================
/bench/vhdl/testcase_top.vhd
0,0 → 1,49
--============================================================================
-- This confidential and proprietary software may be used
-- only as authorized by a licensing agreement from
-- Vector Informatik GmbH.
-- In an event of publication, the following notice is applicable:
--
-- (C) COPYRIGHT 2018 VECTOR INFORMATIK GMBH
-- ALL RIGHTS RESERVED
--
-- The entire notice above must be reproduced on all authorized copies.
--============================================================================
--
-- $URL: https://vistrpnisvn1.vi.vector.int/svn/PNI/VS/trunk/FPGA/Templates/%5Bproject%5D/stimulus/testcase_top.vhd $
-- $Revision: 81721 $
-- $Date: 2018-03-14 10:44:48 +0100 (Mi, 14 Mrz 2018) $
-- $Author: visstt $
-- $Id: testcase_top.vhd 81721 2018-03-14 09:44:48Z visstt $
--
--============================================================================
--
-- Abstract:
-- This file contains the entity declaration of the test case player.
-- Test architectures of all cases will be located in individual tc_xxx.vhdl
-- files.
--
--============================================================================
 
--=library====================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.convert_pkg.all;
use work.my_project_pkg.all;
use work.wishbone_pkg.all;
use work.wishbone_bfm_pkg.all;
 
--============================================================================
 
--=entity=====================================================================
entity testcase_top is
port (
wb_o : out wishbone_bfm_master_out_t;
wb_i : in wishbone_bfm_master_in_t
);
end entity testcase_top;
--============================================================================
-- end of file
--============================================================================
/bench/vhdl/verifier.vhd
0,0 → 1,134
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the top functional module of the design ----
---- under test. The top functional module will be enclosed by ----
---- the top module for synthesis or the tb_top for simulation. ----
---- The top module can contain some synthesis specific code, ----
---- where the tb_top contains simulation specific code. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
-- library -----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.convert_pkg.all;
use work.wishbone_pkg.all;
use work.my_project_pkg.all;
use work.wishbone_bfm_pkg.all;
 
-- entity ------------------------------------------------------------
entity verifier is
generic(
g_number_of_signals : natural := 1
);
port(
wb_i : in wishbone_slave_in_t;
wb_o : out wishbone_slave_out_t;
signals_i : in std_logic_vector(g_number_of_signals-1 downto 0)
);
end verifier;
 
--=architecture===============================================================
architecture rtl of verifier is
--============================================================================
-- signal declaration
--============================================================================
signal s_register0 : std_logic_vector(31 downto 0);
signal s_register1 : std_logic_vector(31 downto 0);
--============================================================================
begin
------------------------------------------------------------------------------
wb_o.ack <= '1';
wb_o.err <= '0';
wb_o.rty <= '0';
wb_o.int <= '0';
wb_o.tgd <= (others => '0');
-- read data multiplexer
proc_read_data_mux : process (all)
begin
case wb_i.adr(27 downto 0) is
when 28X"000_0000" =>
wb_o.dat <= s_register0;
when 28X"000_0004" =>
wb_o.dat <= s_register1;
when 28X"000_0008" =>
wb_o.dat <= zero_c(wb_o.dat'left downto signals_i'left+1) & signals_i;
when others =>
wb_o.dat <= (others =>'U');
end case;
end process;
------------------------------------------------------------------------------
-- write signals to control the verifier
proc_avalon_write_data : process (all)
begin
if (wb_i.rst = '1') then
s_register0 <= (others => '0');
s_register1 <= (others => '0');
elsif (rising_edge(wb_i.clk)) then
if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then
case wb_i.adr(27 downto 0) is
when 28X"000_0000" =>
s_register0 <= wb_i.dat;
when 28X"000_0004" =>
s_register1 <= wb_i.dat;
when others =>
end case;
end if;
end if;
end process;
------------------------------------------------------------------------------
--============================================================================
end rtl; --verifier
--============================================================================
-- end of file
--============================================================================
/bench/vhdl/wishbone_bfm_pkg.vhd
0,0 → 1,262
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the wishbone_bfm_pkg package and defines ----
---- wishbone transaction processes functions for simulation. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
-- library -----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library work;
use work.my_project_pkg.all;
use work.wishbone_pkg.all;
use work.convert_pkg.all;
 
-- package -----------------------------------------------------------
package wishbone_bfm_pkg is
-- defines output signals of wb bfm (simulation only)
type wishbone_bfm_master_out_t is record
-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
dat : wishbone_data_t; -- data []
rst : std_logic; -- reset [mandatory RULE 3.40]
tgd : wishbone_tag_data_t; -- data tag []
-- 2.2.3 MASTER Signals
adr : wishbone_address_t; -- address [optional]
cyc : std_logic; -- cycle [mandatory RULE 3.40]
lock: std_logic; -- lock []
sel : wishbone_byte_select_t;
stb : std_logic; -- strobe [mandatory RULE 3.40]
tga : wishbone_tag_address_t; -- address tag []
tgc : wishbone_tag_cycle_t; -- cycle tag []
we : std_logic; -- write enable []
end record wishbone_bfm_master_out_t;
 
-- defines input signals of wb bfm (simulation only)
type wishbone_bfm_master_in_t is record
-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
rst : std_logic; -- reset [mandatory RULE 3.40]
clk : std_logic; -- clock [mandatory RULE 3.40]
dat : wishbone_data_t; -- read data []
tgd : wishbone_tag_data_t; -- read data tag []
-- 2.2.4 SLAVE Signals
ack : std_logic; -- acknowledge [mandatory RULE 3.40]
err : std_logic; -- error [optional PERMISSION 3.20]
rty : std_logic; -- retry [optional PERMISSION 3.25]
--stall : std_logic;
int : std_logic; -- interrupt [non WB signal]
end record wishbone_bfm_master_in_t;
 
-- define the idle state of wb bus
constant wb_bfm_master_out_idle_c : wishbone_bfm_master_out_t := (
dat => wishbone_data_of_unused_address_c,
rst => '0',
tgd => (others=>'0'),
adr => (others=>'U'),
cyc => '0',
lock => '0',
sel => (others=>'0'),
stb => '0',
tga => (others=>'0'),
tgc => (others=>'0'),
we => '0'
);
----------------------------------------------------------------------
-- BUS FUNCTIONS -----------------------------------------------------
----------------------------------------------------------------------
-- generate single write cycle
PROCEDURE wb_write(
address_i : IN integer; -- address to write to
data_i : IN integer; -- data value to be written
SIGNAL i : IN wishbone_bfm_master_in_t; -- incoming wb signals
SIGNAL o : OUT wishbone_bfm_master_out_t; -- incoming wb signals
display_error_message_i : IN integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all
additional_error_message_i : IN string := ""
);
 
-- generate single read cycle and verify read word with expected_data_i
PROCEDURE wb_read(
address_i : IN INTEGER;
expected_data_i : IN INTEGER;
SIGNAL i : IN wishbone_bfm_master_in_t;
SIGNAL o : OUT wishbone_bfm_master_out_t;
display_error_message_i : IN integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
additional_error_message_i : IN STRING := "";
expected_data_mask_i : IN INTEGER := 0
);
 
-- generate single read cycle and return read data via read_data_o
PROCEDURE wb_read(
address_i : IN INTEGER;
read_data_o : OUT STD_LOGIC_VECTOR (wishbone_address_width_c-1 DOWNTO 0);
SIGNAL i : IN wishbone_bfm_master_in_t;
SIGNAL o : OUT wishbone_bfm_master_out_t
);
----------------------------------------------------------------------
end;
 
-- package body ------------------------------------------------------
package body wishbone_bfm_pkg is
----------------------------------------------------------------------
----------------------------------------------------------------------
PROCEDURE wb_write(
address_i : IN integer;
data_i : IN integer;
SIGNAL i : IN wishbone_bfm_master_in_t;
SIGNAL o : OUT wishbone_bfm_master_out_t;
display_error_message_i : IN integer range 0 to 2 := 1;
additional_error_message_i : IN string := ""
) IS
----------------------------------------------------------------------
BEGIN
o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);
o.dat <= to_std_logic_vector(data_i, wishbone_address_width_c);
o.we <= '1';
o.rst <= '0';
o.tgd <= (others => '0');
o.cyc <= '1';
o.lock <= '1';
o.sel <= (others => '1');
o.stb <= '1';
o.tga <= (others => '0');
o.tgc <= (others => '0');
IF (display_error_message_i = 2) THEN
REPORT "Writing :" & to_string(data_i, 16, wishbone_address_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4) &
additional_error_message_i;
END IF;
 
WAIT UNTIL falling_edge(i.clk);
-- wait for ack
WHILE i.ack = '0' LOOP
WAIT UNTIL falling_edge(i.clk);
END LOOP;
WAIT UNTIL rising_edge(i.clk);
o <= wb_bfm_master_out_idle_c; -- reset bus
END wb_write;
----------------------------------------------------------------------
----------------------------------------------------------------------
PROCEDURE wb_read(
address_i : IN INTEGER;
read_data_o : OUT STD_LOGIC_VECTOR (wishbone_address_width_c-1 DOWNTO 0);
SIGNAL i : IN wishbone_bfm_master_in_t;
SIGNAL o : OUT wishbone_bfm_master_out_t
) IS
----------------------------------------------------------------------
BEGIN
o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);
o.dat <= (others => 'U');
o.we <= '0';
o.rst <= '0';
o.tgd <= (others => '0');
o.cyc <= '1';
o.lock <= '1';
o.sel <= (others => '1');
o.stb <= '1';
o.tga <= (others => '0');
o.tgc <= (others => '0');
WAIT UNTIL falling_edge(i.clk);
-- ack handling
WHILE (i.ack = '0') LOOP
WAIT UNTIL falling_edge(i.clk);
END LOOP;
read_data_o := i.dat;
WAIT UNTIL rising_edge(i.clk);
o <= wb_bfm_master_out_idle_c; -- reset bus
END wb_read;
------------------------------------------------------------------------
------------------------------------------------------------------------
PROCEDURE wb_read(
address_i : IN INTEGER;
expected_data_i : IN INTEGER;
SIGNAL i : IN wishbone_bfm_master_in_t;
SIGNAL o : OUT wishbone_bfm_master_out_t;
display_error_message_i : IN integer range 0 to 4 := 1;
additional_error_message_i : IN STRING := "";
expected_data_mask_i : IN INTEGER := 0
) IS
----------------------------------------------------------------------
VARIABLE readdata_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
VARIABLE diff_v : INTEGER;
----------------------------------------------------------------------
BEGIN
wb_read(address_i,readdata_v,i,o); -- read from bus
 
diff_v := to_integer(readdata_v) - expected_data_i;
 
IF (display_error_message_i = 1) THEN -- output errors only
IF (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN
REPORT "ERROR" & additional_error_message_i & ": Expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4)
SEVERITY error;
END IF;
ELSIF (display_error_message_i = 2) THEN -- Output all
REPORT additional_error_message_i & ": Read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
" was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4)
SEVERITY note;
ELSIF (display_error_message_i = 3) THEN -- Output Filter
IF ((readdata_v AND to_std_logic_vector(expected_data_mask_i, wishbone_address_width_c)) /=
to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN
REPORT additional_error_message_i & ": Read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
" was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4)
SEVERITY note;
END IF;
ELSIF display_error_message_i = 4 THEN
IF (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN
REPORT "ERROR" & additional_error_message_i & ": Expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4) & " Diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)
SEVERITY error;
END IF;
END IF;
END wb_read;
--------------------------------------------------------------------
end package body;
----------------------------------------------------------------------
---- end of file ----
----------------------------------------------------------------------
/rtl/vhdl/packages/convert_pkg.vhd
0,0 → 1,290
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This is a universal type conversion library for VHDL. With ----
---- the contained overloaded functions conversions from any to ----
---- any of the following data types are possible: ----
---- ----
---- std_logic_vector ----
---- std_ulogic_vector ----
---- unsigned ----
---- signed ----
---- bit_vector ----
---- integer ----
---- string ----
---- ----
---- To use them just add the prefix "to_" to the desired result ----
---- type with the source type in braces. ----
---- E.g. conversion from integer to std_logic_vector: ----
---- destination<=to_std_logic_vector(source); ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - First & Last Name, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--============================================================================
--============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
--============================================================================
 
 
--============================================================================
PACKAGE convert_pkg IS
 
FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector;
 
FUNCTION to_integer(input : std_logic_vector) RETURN integer;
FUNCTION to_string(int : integer; base : integer := 10; length : integer := 0) RETURN string;
FUNCTION to_string(slv : std_logic_vector; base : integer; length : integer) RETURN string;
END convert_pkg;
--============================================================================
 
--============================================================================
PACKAGE BODY convert_pkg IS
--==========================================================================
FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector IS
BEGIN
RETURN std_logic_vector(conv_unsigned(input, length));
END;
 
FUNCTION to_integer(input : std_logic_vector) RETURN integer IS
BEGIN
RETURN conv_integer(unsigned(input));
END;
 
--==========================================================================
FUNCTION to_char(int : integer) RETURN character IS
VARIABLE c : character;
BEGIN
CASE int IS
WHEN 0 => c := '0';
WHEN 1 => c := '1';
WHEN 2 => c := '2';
WHEN 3 => c := '3';
WHEN 4 => c := '4';
WHEN 5 => c := '5';
WHEN 6 => c := '6';
WHEN 7 => c := '7';
WHEN 8 => c := '8';
WHEN 9 => c := '9';
WHEN 10 => c := 'A';
WHEN 11 => c := 'B';
WHEN 12 => c := 'C';
WHEN 13 => c := 'D';
WHEN 14 => c := 'E';
WHEN 15 => c := 'F';
WHEN 16 => c := 'G';
WHEN 17 => c := 'H';
WHEN 18 => c := 'I';
WHEN 19 => c := 'J';
WHEN 20 => c := 'K';
WHEN 21 => c := 'L';
WHEN 22 => c := 'M';
WHEN 23 => c := 'N';
WHEN 24 => c := 'O';
WHEN 25 => c := 'P';
WHEN 26 => c := 'Q';
WHEN 27 => c := 'R';
WHEN 28 => c := 'S';
WHEN 29 => c := 'T';
WHEN 30 => c := 'U';
WHEN 31 => c := 'V';
WHEN 32 => c := 'W';
WHEN 33 => c := 'X';
WHEN 34 => c := 'Y';
WHEN 35 => c := 'Z';
WHEN OTHERS => c := '?';
END CASE;
RETURN c;
END to_char;
--========================================================================
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
-- if base=0 convert to 32 bit hex
FUNCTION to_string(int : integer; base : integer := 10; length : integer := 0) RETURN string IS
 
VARIABLE temp : string(1 TO 1000);
VARIABLE num : integer;
VARIABLE abs_int : integer;
VARIABLE len : integer := 1;
VARIABLE power : integer := 1;
 
BEGIN
abs_int := ABS(int);
num := abs_int;
--
IF (length = 0) THEN -- automatic length detection
WHILE num >= base LOOP -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
END LOOP; -- number.
ELSE
len := ABS(length); --
END IF;
 
IF (base /= 10) THEN
len := len + (len-1) / 4; -- increase for underlines
END IF;
--
FOR i IN len DOWNTO 1 LOOP -- Convert the number to
IF (((len-i) MOD 5 = 4) AND (base /= 10)) THEN -- every fith char shell be an underline
temp(i) := '_';
ELSE
temp(i) := to_char(abs_int/power MOD base); -- a string starting
power := power * base; -- with the right hand
END IF;
END LOOP; -- side.
--
-- return result and add sign if required
IF (base = 16) THEN
IF (int < 0) THEN
CASE temp(len) IS
WHEN '0' => temp(len) := 'F';
WHEN '1' => temp(len) := '0';
WHEN '2' => temp(len) := '1';
WHEN '3' => temp(len) := '2';
WHEN '4' => temp(len) := '3';
WHEN '5' => temp(len) := '4';
WHEN '6' => temp(len) := '5';
WHEN '7' => temp(len) := '6';
WHEN '8' => temp(len) := '7';
WHEN '9' => temp(len) := '8';
WHEN 'A' => temp(len) := '9';
WHEN 'B' => temp(len) := 'A';
WHEN 'C' => temp(len) := 'B';
WHEN 'D' => temp(len) := 'C';
WHEN 'E' => temp(len) := 'D';
WHEN 'F' => temp(len) := 'E';
WHEN OTHERS => NULL;
END CASE;
FOR i IN len DOWNTO 1 LOOP
CASE temp(i) IS
WHEN '0' => temp(i) := 'F';
WHEN '1' => temp(i) := 'E';
WHEN '2' => temp(i) := 'D';
WHEN '3' => temp(i) := 'C';
WHEN '4' => temp(i) := 'B';
WHEN '5' => temp(i) := 'A';
WHEN '6' => temp(i) := '9';
WHEN '7' => temp(i) := '8';
WHEN '8' => temp(i) := '7';
WHEN '9' => temp(i) := '6';
WHEN 'A' => temp(i) := '5';
WHEN 'B' => temp(i) := '4';
WHEN 'C' => temp(i) := '3';
WHEN 'D' => temp(i) := '2';
WHEN 'E' => temp(i) := '1';
WHEN 'F' => temp(i) := '0';
WHEN OTHERS => NULL;
END CASE;
END LOOP; -- i
END IF;
RETURN temp(1 TO len);
ELSE
IF (int < 0) THEN
RETURN '-'& temp(1 TO len);
ELSE
RETURN temp(1 TO len);
END IF;
END IF;
END to_string;
 
--========================================================================
FUNCTION to_string(slv : std_logic_vector) RETURN string IS
 
VARIABLE hexlen : integer;
VARIABLE longslv : std_logic_vector(131 DOWNTO 0) := (OTHERS => '0');
VARIABLE hex : string(1 TO 32);
VARIABLE fourbit : std_logic_vector(3 DOWNTO 0);
 
BEGIN
hexlen := ((slv'high - slv'low) + 1) / 4;
IF (((slv'high - slv'low) + 1) MOD 4 /= 0) THEN
hexlen := hexlen + 1;
END IF;
--
longslv((slv'high - slv'low) DOWNTO 0) := slv;
--
FOR i IN (hexlen -1) DOWNTO 0 LOOP
fourbit := longslv(((i*4)+3) DOWNTO (i*4));
CASE fourbit IS
WHEN "0000" => hex(hexlen -I) := '0';
WHEN "0001" => hex(hexlen -I) := '1';
WHEN "0010" => hex(hexlen -I) := '2';
WHEN "0011" => hex(hexlen -I) := '3';
WHEN "0100" => hex(hexlen -I) := '4';
WHEN "0101" => hex(hexlen -I) := '5';
WHEN "0110" => hex(hexlen -I) := '6';
WHEN "0111" => hex(hexlen -I) := '7';
WHEN "1000" => hex(hexlen -I) := '8';
WHEN "1001" => hex(hexlen -I) := '9';
WHEN "1010" => hex(hexlen -I) := 'A';
WHEN "1011" => hex(hexlen -I) := 'B';
WHEN "1100" => hex(hexlen -I) := 'C';
WHEN "1101" => hex(hexlen -I) := 'D';
WHEN "1110" => hex(hexlen -I) := 'E';
WHEN "1111" => hex(hexlen -I) := 'F';
WHEN "ZZZZ" => hex(hexlen -I) := 'z';
WHEN "UUUU" => hex(hexlen -I) := 'u';
WHEN "XXXX" => hex(hexlen -I) := 'x';
WHEN OTHERS => hex(hexlen -I) := '?';
END CASE;
END LOOP;
RETURN hex(1 TO hexlen);
END to_string;
 
--========================================================================
FUNCTION to_string(slv : std_logic_vector; base : integer; length : integer) RETURN string IS
 
BEGIN
RETURN to_string(to_integer(slv), base, length);
END to_string;
 
end package body;
----------------------------------------------------------------------
---- end of file ----
----------------------------------------------------------------------
/rtl/vhdl/packages/my_project_pkg.vhd
0,0 → 1,79
----------------------------------------------------------------------
---- ----
---- WISHBONE XXX IP Core ----
---- ----
---- This file is part of the XXX project ----
---- http://www.opencores.org/cores/xxx/ ----
---- ----
---- Description ----
---- Implementation of XXX IP core according to ----
---- XXX IP core specification document. ----
---- ----
---- To Do: ----
---- - Adjust and rename this package for your project ----
---- - remove these comments ----
---- ----
---- Author(s): ----
---- - First & Last Name, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library work;
 
package my_project_pkg is
 
constant wishbone_address_width_c : integer := 32;
constant wishbone_data_width_c : integer := 32;
constant wishbone_data_of_unused_address_c : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADDEAD"; -- "X" might lead to less resources. Meaningful value might ease debugging
constant wishbone_data_of_unused_address_p : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADBEEF"; -- "X" might lead to less resources. Meaningful value might ease debugging
subtype wishbone_tag_data_t is std_logic_vector(1 downto 0);
subtype wishbone_tag_address_t is std_logic_vector(1 downto 0);
subtype wishbone_tag_cycle_t is std_logic_vector(1 downto 0);
 
--type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
--type t_wishbone_address_granularity is (BYTE, WORD);
constant zero_c : std_logic_vector(511 downto 0) := (others => '0');
end my_project_pkg;
 
package body my_project_pkg is
end my_project_pkg;
 
/rtl/vhdl/packages/wishbone_pkg.vhd
0,0 → 1,152
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the wishbone_pkg package and defines ----
---- basic wishbone types. ----
---- ----
---- This file bases on the file wishbone_pkg.vhd located at ----
---- https://github.com/twlostow/dsi-shield/blob/master/hdl/ip_cores/local/wishbone_pkg.vhd ---
---- See this file also for the authors name. ----
---- Its original file was licensed under LGPL 3.0 ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
-- library -----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library work;
use work.my_project_pkg.all;
 
-- package -----------------------------------------------------------
package wishbone_pkg is
 
subtype wishbone_address_t is std_logic_vector(wishbone_address_width_c-1 downto 0);
subtype wishbone_data_t is std_logic_vector(wishbone_data_width_c-1 downto 0);
subtype wishbone_byte_select_t is std_logic_vector((wishbone_address_width_c/8)-1 downto 0);
--subtype wishbone_cycle_type_t is std_logic_vector(2 downto 0);
--subtype wishbone_burst_type_t is std_logic_vector(1 downto 0);
 
type wishbone_master_out_t is record
-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
clk : std_logic; -- clock [mandatory RULE 3.40]
dat : wishbone_data_t; -- data []
rst : std_logic; -- reset [mandatory RULE 3.40]
tgd : wishbone_tag_data_t; -- data tag []
-- 2.2.3 MASTER Signals
adr : wishbone_address_t; -- address [optional]
cyc : std_logic; -- cycle [mandatory RULE 3.40]
lock: std_logic; -- lock []
sel : wishbone_byte_select_t;
stb : std_logic; -- strobe [mandatory RULE 3.40]
tga : wishbone_tag_address_t; -- address tag []
tgc : wishbone_tag_cycle_t; -- cycle tag []
we : std_logic; -- write enable []
end record wishbone_master_out_t;
subtype wishbone_slave_in_t is wishbone_master_out_t;
 
type wishbone_slave_out_t is record
-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
dat : wishbone_data_t; -- read data []
tgd : wishbone_tag_data_t; -- read data tag []
-- 2.2.4 SLAVE Signals
ack : std_logic; -- acknowledge [mandatory RULE 3.40]
err : std_logic; -- error [optional PERMISSION 3.20]
rty : std_logic; -- retry [optional PERMISSION 3.25]
--stall : std_logic;
int : std_logic; -- interrupt [non WB signal]
end record wishbone_slave_out_t;
subtype wishbone_master_in_t is wishbone_slave_out_t;
 
-- subtype wishbone_device_descriptor_t is std_logic_vector(255 downto 0);
 
-- type wishbone_byte_select_array_t is array(natural range <>) of wishbone_byte_select_t;
-- type wishbone_data_array_t is array(natural range <>) of wishbone_data_t;
type wishbone_address_array_t is array(natural range <>) of wishbone_address_t;
type wishbone_master_out_array_t is array (natural range <>) of wishbone_master_out_t;
type wishbone_slave_in_array_t is array (natural range <>) of wishbone_slave_in_t;
-- subtype wishbone_slave_in_array_t is wishbone_master_out_array_t;
type wishbone_slave_out_array_t is array (natural range <>) of wishbone_slave_out_t;
--type wishbone_master_in_array_t is array (natural range <>) of wishbone_master_in_t;
subtype wishbone_master_in_array_t is wishbone_slave_out_array_t;
 
constant wb_master_out_idle_c : wishbone_master_out_t := (
clk => '0',
dat => wishbone_data_of_unused_address_c,
rst => '0',
tgd => (others=>'0'),
adr => (others=>'U'),
cyc => '0',
lock => '0',
sel => (others=>'0'),
stb => '0',
tga => (others=>'0'),
tgc => (others=>'0'),
we => '0'
);
 
-- constant cc_dummy_address : std_logic_vector(wishbone_address_width_c-1 downto 0) :=(others => 'X');
-- constant cc_dummy_data : std_logic_vector(wishbone_address_width_c-1 downto 0) := (others => 'X');
-- constant cc_dummy_sel : std_logic_vector(wishbone_data_width_c/8-1 downto 0) := (others => 'X');
-- constant cc_dummy_slave_in : wishbone_slave_in_t :=('0', '0', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
-- constant cc_dummy_master_out : wishbone_master_out_t := cc_dummy_slave_in;
 
-- -- Dangerous! Will stall a bus.
-- constant cc_dummy_slave_out : wishbone_slave_out_t :=('X', 'X', 'X', 'X', 'X', cc_dummy_data);
-- constant cc_dummy_master_in : wishbone_master_in_t := cc_dummy_slave_out;
 
-- constant cc_dummy_address_array : wishbone_address_array_t(0 downto 0) := (0 => cc_dummy_address);
 
end wishbone_pkg;
 
-- package body ------------------------------------------------------
package body wishbone_pkg is
end wishbone_pkg;
----------------------------------------------------------------------
---- end of file ----
----------------------------------------------------------------------
/rtl/vhdl/core_top.vhd
0,0 → 1,111
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the top functional module of the design ----
---- under test. The top functional module will be enclosed by ----
---- the top module for synthesis or the tb_top for simulation. ----
---- The top module can contain some synthesis specific code, ----
---- where the tb_top contains simulation specific code. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
-- library -----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.convert_pkg.all;
use work.wishbone_pkg.all;
 
-- entity ------------------------------------------------------------
entity core_top is
generic(
g_number_of_in_signals : natural := 1;
g_number_of_out_signals : natural := 1
);
port(
clock_i : in std_logic;
reset_i : in std_logic;
signals_i : in std_logic_vector(g_number_of_in_signals-1 downto 0);
signals_o : out std_logic_vector(g_number_of_out_signals-1 downto 0)
);
end core_top;
 
--=architecture===============================================================
architecture rtl of core_top is
--============================================================================
-- signal declaration
--============================================================================
signal shift_register_r : std_logic_vector (g_number_of_out_signals-1 downto 0);
signal old_shift_clock_r : std_logic := '0';
--============================================================================
begin
------------------------------------------------------------------------------
-- module instantiation
------------------------------------------------------------------------------
proc_shift_register : process (all)
begin
if (reset_i = '1' ) then
shift_register_r <= (others => '0');
elsif (rising_edge(clock_i)) then
old_shift_clock_r <= signals_i(1);
if (signals_i(1) = '1' AND old_shift_clock_r= '0') then
shift_register_r <= shift_register_r(shift_register_r'left-1 downto 0) & signals_i(0);
end if;
end if;
end process;
------------------------------------------------------------------------------
signals_o <= shift_register_r;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--============================================================================
end rtl; --core_top
--============================================================================
-- end of file
--============================================================================
/rtl/vhdl/top.vhd
0,0 → 1,102
----------------------------------------------------------------------
---- ----
---- VHDL Wishbone TESTBENCH ----
---- ----
---- This file is part of the vhdl_wb_tb project ----
---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
---- ----
---- This file contains the highest (top) module of the test ----
---- bench. ----
---- It instantiates the design under test (DUT), instantiates ----
---- the stimulator module for test vector generation, ----
---- instantiates the verifier module for result comparison, ----
---- instantiates the test case top (testcase_top) bfm, ----
---- interconnects all three components, generates DUT-external ----
---- clocks and resets. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Sinx, email@opencores.org ----
---- ----
----------------------------------------------------------------------
-- SVN information
--
-- $URL: $
-- $Revision: $
-- $Date: $
-- $Author: $
-- $Id: $
--
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
 
-- library -----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.convert_pkg.all;
use work.wishbone_pkg.all;
 
-- entity ------------------------------------------------------------
entity top is
port(
clock_i : in std_logic;
signals_i : in std_logic_vector(7 downto 0);
signals_o : out std_logic_vector(7 downto 0)
);
end entity top;
 
--=architecture===============================================================
architecture rtl of top is
--============================================================================
-- signal declaration
--============================================================================
-- constant number_of_stimulus_signals_c : integer := 8;
-- signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0);
-----------------------------------------------------------------------------
begin
--============================================================================
-- instance of design
core_top_inst : entity work.core_top
generic map(
g_number_of_in_signals => 8,
g_number_of_out_signals => 8
)
port map(
clock_i => clock_i,
reset_i => '0',
signals_i => signals_i,
signals_o => signals_o
);
-----------------------------------------------------------------------------
end rtl;
--============================================================================
-- end of file
--============================================================================
/rtl_sim/bin/init.do
0,0 → 1,17
quit -sim
 
# create work-lib (prevents later error)
vlib work
vmap work work
#delete work-lib
vmap -del work
vdel -all -lib work
# create work-lib (empty lib)
vlib work
vmap work work
 
#compile all
project calculateorder
 
#set aliases
alias s "do ../bin/s.do"
/rtl_sim/bin/readme.txt
0,0 → 1,11
This directory contains:
 
readme.txt This file, explaining simulation environment
init.do TCL script to be run out of modelsim. Start it from the Modelsim console with "do init.do"
to initialize the simulation environment. It created all required libs and compiles all sources.
s.do TCL script to be run out of modelsim. Start it to compile all changed files and start the
manual simulation. It assigns the alias "s" to itself which allows it to be run later just by
typing s+ENTER
clean.do TCL script to clean up all waste created by modelsim
 
If you want to relocate or copy this project, all file paths in the .mpf file must be adjusted in the copy.
/rtl_sim/bin/s.do
0,0 → 1,10
quit -sim
project compileoutofdate
alias w "write format wave wave.do"
alias s "do ../bin/s.do"
alias b "bookmark add wave A"
vsim -t 1fs tb_top
#view wave
do ../run/wave.do
#run -all
run 120us
/rtl_sim/run/sim.mpf
0,0 → 1,424
; Copyright 1991-2009 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
 
[Library]
others = $MODEL_TECH/../modelsim.ini
 
; Altera Primitive libraries
;
; VHDL Section
;
;
; Verilog Section
;
 
work = work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Default or value of 3 or 2008 for VHDL-2008.
VHDL93 = 2008
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
 
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
 
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
 
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
 
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
 
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
 
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
 
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
 
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
 
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
 
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
 
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
 
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
 
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
 
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
 
[vlog]
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
 
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
 
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ps
 
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
 
; Default run length
RunLength = 120 us
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
 
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license
; License = plus
 
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
 
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
AssertionFormat = "** %T %S %R [%I]\n"
 
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
 
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = hexadecimal
 
; VSIM Startup command
; Startup = do startup.do
 
; File for saving command transcript
;TranscriptFile = transcript.log
 
; File for saving command history
;CommandHistory = cmdhist.log
 
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
 
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
 
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
 
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
 
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
 
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
 
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
 
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
 
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
 
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
 
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
 
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
 
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
 
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
 
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
 
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
 
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
 
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
 
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
 
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
 
; Automatic SDF compilation
; Disables automatic compilation of SDF files in flows that support it.
; Default is on, uncomment to turn off.
; NoAutoSDFCompile = 1
 
WLFSaveAllRegions = 1
DefaultRadixFlags = showbase
[lmc]
 
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
 
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 15
Project_File_0 = D:/OpenCoresOrg/vhdl_wb_tb/bench/vhdl/tb_top.vhd
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532103544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_1 = D:/OpenCoresOrg/vhdl_wb_tb/rtl_sim/bin/s.do
Project_File_P_1 = folder z_others last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1
Project_File_2 = D:/OpenCoresOrg/vhdl_wb_tb/rtl/vhdl/packages/convert_pkg.vhd
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532103347 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_3 = D:/OpenCoresOrg/vhdl_wb_tb/rtl_sim/bin/init.do
Project_File_P_3 = compile_order -1 last_compile 0 folder z_others dont_compile 1 group_id 0 file_type tcl ood 1
Project_File_4 = D:/OpenCoresOrg/vhdl_wb_tb/bench/vhdl/stimulator.vhd
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532103545 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_5 = D:/OpenCoresOrg/vhdl_wb_tb/bench/vhdl/wishbone_bfm_pkg.vhd
Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532104156 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_6 = D:/OpenCoresOrg/vhdl_wb_tb/rtl/vhdl/top.vhd
Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532103544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_7 = D:/OpenCoresOrg/vhdl_wb_tb/bench/vhdl/tc_xxxx.vhd
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532104409 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_8 = D:/OpenCoresOrg/vhdl_wb_tb/rtl/vhdl/packages/wishbone_pkg.vhd
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532103735 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_9 = D:/OpenCoresOrg/vhdl_wb_tb/rtl_sim/run/sim.mpf
Project_File_P_9 = compile_order -1 last_compile 0 folder z_others dont_compile 1 group_id 0 file_type txt ood 1
Project_File_10 = D:/OpenCoresOrg/vhdl_wb_tb/bench/vhdl/verifier.vhd
Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532103544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_11 = D:/OpenCoresOrg/vhdl_wb_tb/rtl/vhdl/packages/my_project_pkg.vhd
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532103652 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_12 = D:/OpenCoresOrg/vhdl_wb_tb/rtl/vhdl/core_top.vhd
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532103545 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_13 = D:/OpenCoresOrg/vhdl_wb_tb/bench/vhdl/testcase_top.vhd
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532103544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_File_14 = D:/OpenCoresOrg/vhdl_wb_tb/bench/vhdl/tb_pkg.vhd
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532103544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2008
Project_Sim_Count = 0
Project_Folder_Count = 4
Project_Folder_0 = bench
Project_Folder_P_0 = folder {Top Level}
Project_Folder_1 = z_others
Project_Folder_P_1 = folder {Top Level}
Project_Folder_2 = rtl
Project_Folder_P_2 = folder {Top Level}
Project_Folder_3 = PACKAGES
Project_Folder_P_3 = folder PNI
Echo_Compile_Output = 1
Save_Compile_Report = 0
Project_Opt_Count = 0
ForceSoftPaths = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Compile
VERILOG_CustomDoubleClick =
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick =
VHDL_DoubleClick = Compile
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
TDB_DoubleClick = Edit
TDB_CustomDoubleClick =
UPF_DoubleClick = Edit
UPF_CustomDoubleClick =
PCF_DoubleClick = Edit
PCF_CustomDoubleClick =
PROJECT_DoubleClick = Edit
PROJECT_CustomDoubleClick =
VRM_DoubleClick = Edit
VRM_CustomDoubleClick =
DEBUGDATABASE_DoubleClick = Edit
DEBUGDATABASE_CustomDoubleClick =
DEBUGARCHIVE_DoubleClick = Edit
DEBUGARCHIVE_CustomDoubleClick =
Project_Major_Version = 10
Project_Minor_Version = 6
/rtl_sim/run/vsim.wlf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/rtl_sim/run/vsim.wlf
rtl_sim/run/vsim.wlf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: rtl_sim/run/wave.do =================================================================== --- rtl_sim/run/wave.do (nonexistent) +++ rtl_sim/run/wave.do (revision 2) @@ -0,0 +1,37 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider TestBench_WbMaster +add wave -noupdate /tb_top/testcase_top_inst/wb_o +add wave -noupdate /tb_top/testcase_top_inst/wb_i +add wave -noupdate -divider WbStimulator +add wave -noupdate /tb_top/stimulator_inst/s_register0 +add wave -noupdate /tb_top/stimulator_inst/s_register1 +add wave -noupdate -divider WbVerifier +add wave -noupdate /tb_top/verifier_inst/s_register0 +add wave -noupdate /tb_top/verifier_inst/s_register1 +add wave -noupdate -divider Core_top +add wave -noupdate /tb_top/core_top_inst/clock_i +add wave -noupdate /tb_top/core_top_inst/reset_i +add wave -noupdate /tb_top/core_top_inst/signals_i +add wave -noupdate /tb_top/core_top_inst/signals_o +add wave -noupdate /tb_top/core_top_inst/shift_register_r +add wave -noupdate /tb_top/core_top_inst/old_shift_clock_r +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {649701366 fs} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 232 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {8258914428 fs} {8270583452 fs} +bookmark add wave A {{187592960 fs} {1276319150 fs}} 0

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