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URL https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk

Subversion Repositories vhdl_wb_tb

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  • This comparison shows the changes necessary to convert path 
    /vhdl_wb_tb/trunk
    from Rev 19 to Rev 20
    ↔ Reverse comparison
  •

Rev 19 → Rev 20

/bench/vhdl/wishbone_bfm_pkg.vhd
95,18 → 95,18
 
-- define the idle state of wb bus
constant wb_bfm_master_out_idle_c : wishbone_bfm_master_out_t := (
dat => wishbone_data_of_unused_address_c,
rst => '0',
tgd => (others=>'0'),
adr => (others=>'U'),
cyc => '0',
lock => '0',
sel => (others=>'0'),
stb => '0',
tga => (others=>'0'),
tgc => (others=>'0'),
we => '0'
);
dat => wishbone_data_of_unused_address_c,
rst => '0',
tgd => (others=>'0'),
adr => (others=>'U'),
cyc => '0',
lock => '0',
sel => (others=>'0'),
stb => '0',
tga => (others=>'0'),
tgc => (others=>'0'),
we => '0'
);
-- BUS FUNCTIONS -----------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
116,27 → 116,27
data_i : in integer; -- data value to be written
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals
signal o : out wishbone_bfm_master_out_t; -- incoming wb signals
display_error_message_i : in integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all
additional_error_message_i : in string := ""
display_error_message_i : in integer range 0 to 2 := 1; -- verbose mode; 2= print all activities; others: print nothing
additional_error_message_i : in string := "" -- string to be added in front of generated message
);
 
-- generate single read cycle and verify read word with expected_data_i
procedure wb_read(
address_i : in integer;
expected_data_i : in integer;
signal i : in wishbone_bfm_master_in_t;
signal o : out wishbone_bfm_master_out_t;
address_i : in integer; -- address to read from
expected_data_i : in integer; -- data to be compared to read data; if different an error message is generated
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals
display_error_message_i : in integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
additional_error_message_i : in string := "";
expected_data_mask_i : in integer := 0
additional_error_message_i : in string := ""; -- string to be added in front of generated message
expected_data_mask_i : in integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared
);
 
-- generate single read cycle and return read data via read_data_o
procedure wb_read(
address_i : in integer;
read_data_o : out std_logic_vector (wishbone_address_width_c-1 downto 0);
signal i : in wishbone_bfm_master_in_t;
signal o : out wishbone_bfm_master_out_t
address_i : in integer; -- address to read from
read_data_o : out std_logic_vector (wishbone_data_width_c-1 downto 0); -- read data output
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals
signal o : out wishbone_bfm_master_out_t -- outgoing wb signals
);
----------------------------------------------------------------------
end;
146,17 → 146,17
----------------------------------------------------------------------
----------------------------------------------------------------------
procedure wb_write(
address_i : in integer;
data_i : in integer;
signal i : in wishbone_bfm_master_in_t;
signal o : out wishbone_bfm_master_out_t;
display_error_message_i : in integer range 0 to 2 := 1;
additional_error_message_i : in string := ""
address_i : in integer; -- address to write to
data_i : in integer; -- data value to be written
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals
display_error_message_i : in integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all
additional_error_message_i : in string := "" -- string to be added in front of generated message
) is
----------------------------------------------------------------------
begin
o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);
o.dat <= to_std_logic_vector(data_i, wishbone_address_width_c);
o.dat <= to_std_logic_vector(data_i, wishbone_data_width_c);
o.we <= '1';
o.rst <= '0';
o.tgd <= (others => '0');
167,25 → 167,25
o.tga <= (others => '0');
o.tgc <= (others => '0');
if (display_error_message_i = 2) then
report "writing :" & to_string(data_i, 16, wishbone_address_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4) &
additional_error_message_i;
report additional_error_message_i & " writing :" & to_string(data_i, 16, wishbone_data_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4);
end if;
 
wait until falling_edge(i.clk);
-- wait for ack
while i.ack = '0' loop
wait until falling_edge(i.clk);
-- ack handling
loop
wait until rising_edge(i.clk);
if (i.ack = '1') then
exit;
end if;
end loop;
wait until rising_edge(i.clk);
o <= wb_bfm_master_out_idle_c; -- reset bus
end wb_write;
----------------------------------------------------------------------
----------------------------------------------------------------------
procedure wb_read(
address_i : in integer;
read_data_o : out std_logic_vector (wishbone_address_width_c-1 downto 0);
signal i : in wishbone_bfm_master_in_t;
signal o : out wishbone_bfm_master_out_t
address_i : in integer; -- address to read from
read_data_o : out std_logic_vector (wishbone_data_width_c-1 downto 0);-- read data output
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals
signal o : out wishbone_bfm_master_out_t -- outgoing wb signals
) is
----------------------------------------------------------------------
begin
200,25 → 200,26
o.stb <= '1';
o.tga <= (others => '0');
o.tgc <= (others => '0');
wait until falling_edge(i.clk);
-- ack handling
while (i.ack = '0') loop
wait until falling_edge(i.clk);
loop
wait until rising_edge(i.clk);
read_data_o := i.dat;
if (i.ack = '1') then
exit;
end if;
end loop;
read_data_o := i.dat;
wait until rising_edge(i.clk);
o <= wb_bfm_master_out_idle_c; -- reset bus
end wb_read;
------------------------------------------------------------------------
------------------------------------------------------------------------
procedure wb_read(
address_i : in integer;
expected_data_i : in integer;
signal i : in wishbone_bfm_master_in_t;
signal o : out wishbone_bfm_master_out_t;
display_error_message_i : in integer range 0 to 4 := 1;
additional_error_message_i : in string := "";
expected_data_mask_i : in integer := 0
address_i : in integer; -- address to read from
expected_data_i : in integer; -- data to be compared to read data; if different an error message is generated
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals
display_error_message_i : in integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
additional_error_message_i : in string := ""; -- string to be added in front of generated message
expected_data_mask_i : in integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared
) is
----------------------------------------------------------------------
variable readdata_v : std_logic_vector (31 downto 0);
226,30 → 227,30
----------------------------------------------------------------------
begin
wb_read(address_i,readdata_v,i,o); -- read from bus
 
diff_v := to_integer(readdata_v) - expected_data_i;
 
if (display_error_message_i = 1) then -- output errors only
if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then
if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4)
" was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4)
severity error;
end if;
elsif (display_error_message_i = 2) then -- output all
report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
" was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4)
" was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)
severity note;
elsif (display_error_message_i = 3) then -- output filter
if ((readdata_v and to_std_logic_vector(expected_data_mask_i, wishbone_address_width_c)) /=
to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then
if ((readdata_v and to_std_logic_vector(expected_data_mask_i, wishbone_data_width_c)) /=
to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
" was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4)
" was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)
severity note;
end if;
elsif display_error_message_i = 4 then
if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then
if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4) & " diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)
" was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4) & " diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)
severity error;
end if;
end if;

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