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URL https://opencores.org/ocsvn/vhld_tb/vhld_tb/trunk

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Rev 22 → Rev 23

/vhld_tb/trunk/source/template_tb_bhv.vhd
1,5 → 1,6
-------------------------------------------------------------------------------
-- Copyright 2011 Ken Campbell
-- Copyright 2014 Ken Campbell
-- All rights reserved.
-------------------------------------------------------------------------------
-- $Author: sckoarn $
--
9,32 → 10,39
--
-- $Source: $
--
-- Description : The the testbench package template behave file.
-- GNU release 2 Beta.
-- Description : The the testbench template file.
--
------------------------------------------------------------------------------
--This file is part of The VHDL Test Bench.
-- This file is a template used to generate test bench _bhv.vhd file.
--
-- The VHDL Test Bench is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- The VHDL Test Bench is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- You should have received a copy of the GNU General Public License
-- along with The VHDL Test Bench; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------
 
architecture bhv of tb_Top is
 
 
signal tb_clk : std_logic;
 
-------------------------------------------------------------------------
-- Component defintion
 
108,7 → 116,7
variable rand : std_logic_vector(31 downto 0);
variable rand_back : std_logic_vector(31 downto 0);
variable valid : integer;
 
-- scratchpad variables
variable temp_int : integer;
variable temp_index : integer;
126,7 → 134,7
-- procedure arb_write(add: in integer; .....
-- end arb_write;
 
 
begin -- process Read_file
-- parse_tb1 start input initialization
-----------------------------------------------------------------------
184,11 → 192,11
--------------------------------------------------------------------------
--if(instruction(1 to len) = "DEFINE_VAR") then
-- null; -- This instruction was implemented while reading the file
 
--------------------------------------------------------------------------
if(instruction(1 to len) = "INCLUDE") then
null; -- This instruction was implemented while reading the file
 
--------------------------------------------------------------------------
elsif(instruction(1 to len) = "ABORT") then
assert (false)
204,7 → 212,7
--------------------------------------------------------------------------
elsif(instruction(1 to len) = "EQU_VAR") then
update_variable(defined_vars, par1, par2, valid);
 
--------------------------------------------------------------------------
elsif(instruction(1 to len) = "ADD_VAR") then
index_variable(defined_vars, par1, temp_int, valid);
216,7 → 224,7
report "ADD_VAR Error: Not a valid Variable??"
severity failure;
end if;
 
--------------------------------------------------------------------------
elsif(instruction(1 to len) = "SUB_VAR") then
index_variable(defined_vars, par1, temp_int, valid);
228,7 → 236,7
report "SUB_VAR Error: Not a valid Variable??"
severity failure;
end if;
 
--------------------------------------------------------------------------
elsif(instruction(1 to len) = "CALL") then
if(stack_ptr >= 7) then
239,7 → 247,7
stack(stack_ptr) := v_line;
stack_ptr := stack_ptr + 1;
v_line := par1 - 1;
 
--------------------------------------------------------------------------
elsif(instruction(1 to len) = "RETURN_CALL") then
if(stack_ptr <= 0) then
268,10 → 276,10
term_loop_count(loop_num) := par1;
assert (messages)
report LF & "Executing LOOP Command" &
LF & " Nested Loop:" & HT & integer'image(loop_num) &
LF & " Nested Loop:" & HT & integer'image(loop_num) &
LF & " Loop Length:" & HT & integer'image(par1)
severity note;
 
--------------------------------------------------------------------------------
elsif (instruction(1 to len) = "END_LOOP") then
curr_loop_count(loop_num) := curr_loop_count(loop_num) + 1;
316,12 → 324,12
assert (false)
report LF & "ERROR: IF instruction unable to find terminating" &
LF & " ELSE, ELSEIF or END_IF statement."
severity failure;
severity failure;
end if;
end loop;
v_line := v_line - 1; -- re-align so it will be operated on.
end if;
 
--------------------------------------------------------------------------------
elsif (instruction(1 to len) = "ELSEIF") then
if(if_state = true) then -- if the if_state is true then skip to the end
339,11 → 347,11
assert (false)
report LF & "ERROR: IF instruction unable to find terminating" &
LF & " ELSE, ELSEIF or END_IF statement."
severity failure;
severity failure;
end if;
end loop;
v_line := v_line - 1; -- re-align so it will be operated on.
 
else
case par2 is
when 0 => if(par1 = par3) then if_state := true; end if;
359,7 → 367,7
"Found on line " & (ew_to_str(file_line,dec)) & " in file " & file_name
severity failure;
end case;
 
if(if_state = false) then
v_line := v_line + 1;
access_inst_sequ(inst_sequ, defined_vars, file_list, v_line, instruction,
377,13 → 385,13
assert (false)
report LF & "ERROR: ELSEIF instruction unable to find terminating" &
LF & " ELSE, ELSEIF or END_IF statement."
severity failure;
severity failure;
end if;
end loop;
v_line := v_line - 1; -- re-align so it will be operated on.
end if;
end if;
 
--------------------------------------------------------------------------------
elsif (instruction(1 to len) = "ELSE") then
if(if_state = true) then -- if the if_state is true then skip the else
401,16 → 409,16
assert (false)
report LF & "ERROR: IF instruction unable to find terminating" &
LF & " ELSE, ELSEIF or END_IF statement."
severity failure;
severity failure;
end if;
end loop;
v_line := v_line - 1; -- re-align so it will be operated on.
end if;
 
--------------------------------------------------------------------------------
elsif (instruction(1 to len) = "END_IF") then
null; -- instruction is a place holder for finding the end of IF.
 
--------------------------------------------------------------------------------
elsif (instruction(1 to len) = "WHILE") then
wh_state := false;
444,9 → 452,9
assert (false)
report LF & "ERROR: WHILE instruction unable to find terminating" &
LF & " END_WHILE statement."
severity failure;
severity failure;
end if;
 
-- if is a while need to escape it
if(instruction(1 to len) = "WHILE") then
wh_dpth := wh_dpth + 1;
467,7 → 475,7
v_line := wh_stack(wh_ptr - 1) - 1;
wh_ptr := wh_ptr - 1;
end if;
 
--------------------------------------------------------------------------------
elsif (instruction(1 to len) = "MESSAGES_OFF") then
messages := TRUE;
474,8 → 482,8
--------------------------------------------------------------------------------
elsif (instruction(1 to len) = "MESSAGES_ON") then
messages := FALSE;
 
 
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- USER Istruction area. Add all user instructions below this
498,11 → 506,11
-- after the instruction is finished print out any txt and sub vars
txt_print_wvar(defined_vars, txt, hex);
end loop; -- Main Loop end
 
assert (false)
report LF & "The end of the simulation! It was not terminated as expected." & LF
severity failure;
 
end process Read_file;
 
 
/vhld_tb/trunk/source/tb_pkg_body.vhd
1,5 → 1,6
-------------------------------------------------------------------------------
-- Copyright 2011 Ken Campbell
-- Copyright 2014 Ken Campbell
-- All rights reserved.
-------------------------------------------------------------------------------
-- $Author: sckoarn $
--
10,24 → 11,31
-- $Source: $
--
-- Description : The the testbench package body file.
-- GNU release 2 Beta.
--
------------------------------------------------------------------------------
--This file is part of The VHDL Test Bench.
-- This file is part of The VHDL Test Bench Package.
--
-- The VHDL Test Bench is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- The VHDL Test Bench is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- You should have received a copy of the GNU General Public License
-- along with The VHDL Test Bench; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------
 
package body tb_pkg is
/vhld_tb/trunk/source/tb_pkg_header.vhd
1,5 → 1,6
-------------------------------------------------------------------------------
-- Copyright 2011 Ken Campbell
-- Copyright 2014 Ken Campbell
-- All rights reserved.
-------------------------------------------------------------------------------
-- $Author: sckoarn $
--
7,27 → 8,34
--
-- $Id: $
--
-- $Source: $
-- $Source: $
--
-- Description : The the testbench package header file.
-- GNU release 2 Beta.
--
------------------------------------------------------------------------------
--This file is part of The VHDL Test Bench.
-- This file is part of The VHDL Test Bench Package.
--
-- The VHDL Test Bench is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- The VHDL Test Bench is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- You should have received a copy of the GNU General Public License
-- along with The VHDL Test Bench; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------
library IEEE;
 
/vhld_tb/trunk/Doc/VHDLtbusers.odt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/vhld_tb/trunk/examples/packet_gen/build_tb.bat
7,7 → 7,7
vcom -work synthworks -2008 C:\work\vhdl2008c\RandomPkg_2_0\RandomBasePkg.vhd
vcom -work synthworks -2008 C:\work\vhdl2008c\RandomPkg_2_0\RandomPkg.vhd
 
vcom vhdl/tb_pkg_header.vhd vhdl/tb_pkg_body.vhd
vcom ../../source/tb_pkg_header.vhd ../../source/tb_pkg_body.vhd
 
vcom -quiet -2008 vhdl/packet_gen.vhd
 
/vhld_tb/trunk/examples/packet_gen/vhdl/tb_pkg_header.vhd File deleted
/vhld_tb/trunk/examples/packet_gen/vhdl/tb_pkg_body.vhd File deleted
/vhld_tb/trunk/examples/tb_code_snips.vhd
18,9 → 18,22
-- Section 2: Code from CPU emulation: some starter commands
-- Section 3: Code for internal test bench implementation
-- Section 4: Code for Verify commands
--
--
------------------------------------------------------------------------------
-- Redistribution and use in source and binary forms, with or without
-- modification, in whole or part, are permitted:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--###################################################################################
77,7 → 90,7
process(clk, dut_irq)
begin
-- on the falling edge, assume rising edge assertion, one clock wide
if(clk'event and clk = '0') then
if(clk'event and clk = '0') then
if(dut_irq = '1') then
if(irq_expect = true) then
assert (false)
170,7 → 183,7
v_regs(par2) := STM_DAT;
STM_RWN <= '1';
wait for 1 ps;
 
--------------------------------------------------------------------------
-- REG_TO_VAR
-- Write a register array value to a Variable.
191,7 → 204,7
-- par2 reg2 index
elsif(instruction(1 to len) = "MOV") then
v_regs(par2) := v_regs(par1);
 
--------------------------------------------------------------------------
-- MOVI
-- Move value passed to destination register
199,7 → 212,7
-- par2 reg index
elsif(instruction(1 to len) = "MOVI") then
v_regs(par2) := std_logic_vector(conv_unsigned(par1, 32));
 
--------------------------------------------------------------------------
-- AND
-- AND two registers and write results to target register
278,7 → 291,7
v_temp_vec1 := v_regs(par1);
temp_int := par2 - 1;
v_regs(par1) := v_temp_vec1(31-par2 downto 0) & v_temp_vec1(31 downto 31 - temp_int);
 
--------------------------------------------------------------------------
-- SLR
-- Shift the register right rotate the lower bits into the upper bits
288,7 → 301,7
v_temp_vec1 := v_regs(par1);
temp_int := par2 - 1;
v_regs(par1) := v_temp_vec1(temp_int downto 0) & v_temp_vec1(31 downto par2);
 
--------------------------------------------------------------------------
-- CMP
-- Compare one register against another and set CCR bits, no effect on registers
303,11 → 316,11
elsif(v_regs(par1) < v_regs(par2)) then
v_reg_ccr(3) := '1';
end if;
 
if(v_regs(par1) = zeros) then
v_reg_ccr(1) := '0';
end if;
 
--------------------------------------------------------------------------
-- BE
-- Branch if equal
321,8 → 334,8
wh_ptr := 0;
--stack := (others => 0);
--stack_ptr := 0;
end if;
end if;
 
--------------------------------------------------------------------------
-- BZ
-- Branch if Zero
336,8 → 349,8
wh_ptr := 0;
--stack := (others => 0);
--stack_ptr := 0;
end if;
end if;
 
--------------------------------------------------------------------------
-- BB
-- Branch if bit in register is set/clear
360,9 → 373,9
wh_ptr := 0;
--stack := (others => 0);
--stack_ptr := 0;
end if;
end if;
-- ...
end process Read_file;
end process Read_file;
end bhv;
-- Stimulus_file commands used for testing. I used no VERIFY command
-- as I watched the functionality in single stepping through code.
440,20 → 453,20
-- call bin txt to int fuction with dummy fn and sequ idx
result := bin2integer(tmp_str, file_name, idx);
return result;
 
end to_uninteger;
 
 
 
-- Section 2: END
--###################################################################################
 
--
--
--###################################################################################
-- Section 3: Begin
-- This section presents the code needed to make an internal test bench
-- an optional compile item through the use of VHDL generics and generate
-- statements.
-- statements.
 
-- this is the top enity or at the level where you can assign the
-- en_bfm generic and it makes sense
534,8 → 547,8
define_instruction(inst_list, "VERIFY_BIT", 2);
define_instruction(inst_list, "VERIFY_SLICE", 1);
-- ...
 
 
-----------------------------------------------------------------------------
-- SLICE_SET set the slice of the data for testing
-- par1 upper bound value - must be larger than par2 and less than 32
557,13 → 570,13
-- update variables
v_upb := par1;
v_lob := par2;
 
-----------------------------------------------------------------------------
-- VERIFY test that the data in temp_read is the passed value.
-- par1 value to test against.
elsif (instruction(1 to len) = "VERIFY") then
v_temp_vec1 := std_logic_vector(conv_unsigned(par1, 32));
 
assert (v_temp_vec1 = v_temp_read)
report LF & "ERROR: VERIFY command compare value was not as expected!!" &
LF & "Got " & (to_hstring(v_temp_read)) &
570,7 → 583,7
LF & "Expected " & (to_hstring(v_temp_vec1)) & LF &
"Found on line " & (integer'image(file_line)) & " in file " & file_name
severity failure;
 
-----------------------------------------------------------------------------
-- VERIFY_BIT test that the data bit in temp_read is the passed value.
-- par1 index into 32 bit temp_read
590,7 → 603,7
"We tested for " & (integer'image(par2)) & LF &
"Found on line " & (integer'image(file_line)) & " in file " & file_name
severity failure;
 
-----------------------------------------------------------------------------
-- VERIFY_SLICE test that the data in temp_read is the passed value.
-- par1 value
605,6 → 618,6
LF & "Expected " & (to_hstring(v_temp_vec1(v_upb downto v_lob))) & LF &
"Found on line " & (integer'image(file_line)) & " in file " & file_name
severity failure;
 
-- END Section 4
--#######################################################################################

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