OpenCores

/w11/trunk/tools/tcl/rlink/util.tcl

1,6 → 1,6

13,6 → 13,7

32,6 → 33,10

44,16 → 49,16

63,6 → 68,7

70,6 → 76,7

77,6 → 84,7

85,6 → 93,7

107,4 → 116,16

/w11/trunk/tools/tcl/rbtest/test_flow.tcl

0,0 → 1,70

/w11/trunk/tools/tcl/rbtest/test_all.tcl

1,6 → 1,6

13,6 → 13,7

32,6 → 33,7

/w11/trunk/tools/tcl/rbtest/test_data.tcl

1,6 → 1,6

13,6 → 13,7

119,6 → 120,37

/w11/trunk/tools/src/librlink/RlinkConnect.hpp

1,6 → 1,6

13,6 → 13,8

37,7 → 39,7

109,6 → 111,7

129,6 → 132,7

136,6 → 140,7

156,6 → 161,8

236,11 → 243,13

/w11/trunk/tools/src/librlink/RlinkConnect.ipp

1,6 → 1,6

13,6 → 13,8

26,7 → 28,7

106,6 → 108,13

240,6 → 249,14

/w11/trunk/tools/src/librlink/RlinkConnect.cpp

1,6 → 1,6

13,6 → 13,8

36,7 → 38,7

72,6 → 74,8

108,11 → 112,13

174,6 → 180,7

216,10 → 223,22

227,6 → 246,21

575,6 → 609,15

702,8 → 745,8

/w11/trunk/tools/src/librlinktpp/RtclRlinkConnect.cpp

1,6 → 1,6

13,6 → 13,8

38,7 → 40,7

115,6 → 117,8

122,6 → 126,8

141,6 → 147,8

/w11/trunk/tools/bin/tbrun_tbwrri

1,5 → 1,5

6,6 → 6,11

98,23 → 103,14

144,6 → 140,7

165,6 → 162,10

/w11/trunk/tools/bin/xise_msg_summary

0,0 → 1,27

w11/trunk/tools/bin/xise_msg_summary Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: w11/trunk/tools/bin/tbw =================================================================== --- w11/trunk/tools/bin/tbw (revision 35) +++ w11/trunk/tools/bin/tbw (revision 36) @@ -1,5 +1,5 @@ #!/usr/bin/perl -w -# $Id: tbw 727 2016-02-07 13:58:47Z mueller $ +# $Id: tbw 778 2016-06-25 15:18:01Z mueller $ # # Copyright 2007-2016 by Walter F.J. Mueller # @@ -14,6 +14,9 @@ # # Revision History: # Date Rev Version Comment +# 2016-06-25 778 1.5.1 support all sim modes +# 2016-04-17 762 1.5 make '-run' default for [IX]Sim, add '-norun' +# 2016-03-20 748 1.4 recode OPTIONS handling and -fifo handling # 2016-02-06 727 1.3 add XSim support # 2015-01-04 629 1.2.6 BUGFIX: setup proper dsc values after -fifo # 2014-12-23 619 1.2.5 add -fifo and -verbose options @@ -43,13 +46,17 @@ use strict; # require strict checking use POSIX qw(mkfifo); use FileHandle; +use File::Spec; +use Cwd 'abs_path'; my $tb_code; my $is_isim; my $is_isim_run; my $is_xsim; -my $is_fifo; -my $is_verbose; +my $opt_run; +my $opt_norun; +my $opt_fifo; +my $opt_verbose; my @args_pos; # list of positional args my @args_nam; # list of named args @@ -59,7 +66,7 @@ autoflush STDOUT 1; # autoflush, so nothing lost on exec later -if (scalar(@ARGV) && $ARGV[0] =~ /^-*help$/) { # -help or --help given +if (scalar(@ARGV) && $ARGV[0] =~ m/^-+help$/) { # -help or --help given print_usage; exit 0; } @@ -70,6 +77,8 @@ exit 1; } +# process test-bench-filename + $tb_code = shift @ARGV; my $tb_code_path = "."; my $tb_code_name = $tb_code; @@ -78,39 +87,35 @@ $tb_code_name = $2; } +# process -run, -fifo and -verbose options (can be in any order now) + +while (scalar(@ARGV)) { + my $opt = $ARGV[0]; + if ($opt =~ m/^-+norun$/) { $opt_norun = 1; shift @ARGV;} + elsif ($opt =~ m/^-+fifo$/) { $opt_fifo = 1; shift @ARGV;} + elsif ($opt =~ m/^-+verbose$/) { $opt_verbose = 1; shift @ARGV;} + elsif ($opt =~ m/^-+run$/) { + print "tbw-I: legacy option '-run' seen and ignored; is now default\n"; + shift @ARGV; + } + else { last;} +} + my $tb_code_stem = $tb_code_name; -$tb_code_stem =~ s/_[fost]sim$//; # drop _ssim,_fsim, _osim, or _tsim +$tb_code_stem =~ s/_[fsorept]sim$//; # drop sim mode suffix if ($tb_code_stem =~ /_ISim$/) { # is it an ISim executable ? + $tb_code_stem =~ s/_ISim$//; # drop _ISim $is_isim = 1; - $tb_code_stem =~ s/_ISim$//; # drop _ISim - if (scalar(@ARGV) && $ARGV[0] eq "-run") { - $is_isim_run = 1; - shift @ARGV; - } + $is_isim_run = not $opt_norun; } if ($tb_code_stem =~ /_XSim$/) { # is it an XSim executable ? + $tb_code_stem =~ s/_XSim$//; # drop _XSim $is_xsim = 1; - $tb_code_stem =~ s/_XSim$//; # drop _XSim - if (scalar(@ARGV) && $ARGV[0] eq "-run") { # map -run to '-R' - $ARGV[0] = "-R"; - } + unshift @ARGV,'-R' unless $opt_norun; # run all unless '-norun' given } - -if (scalar(@ARGV) && $ARGV[0] eq "-fifo") { - push @file_dsc, {tag=>'rlink_cext_fifo_rx', val=>''}; - push @file_dsc, {tag=>'rlink_cext_fifo_tx', val=>''}; - push @file_dsc, {tag=>'rlink_cext_conf', val=>''}; - $is_fifo = 1; - shift @ARGV; -} -if (scalar(@ARGV) && $ARGV[0] eq "-verbose") { - $is_verbose = 1; - shift @ARGV; -} - if (not -e $tb_code) { print "tbw-E: $tb_code not existing or not executable\n"; print_usage; @@ -124,7 +129,7 @@ my $tbwdat_file = "tbw.dat"; $tbwdat_file = "$tb_code_path/tbw.dat" unless (-r "tbw.dat"); -if ((!$is_fifo) && -r $tbwdat_file) { +if (-r $tbwdat_file) { my $ok = 0; my $done = 0; @@ -145,20 +150,22 @@ print "tbw-E: bad line in tbw.dat:\n $_\n"; } } +} else { + print "tbw-W: failed to find $tbwdat_file\n"; } # # if no tbw.dat or no matching stanza found, setup defaults # - -if (!$is_fifo) { - unless (scalar (@file_dsc)) { +unless (scalar (@file_dsc)) { + if ($opt_fifo) { + push @file_dsc, {tag=>'rlink_cext_fifo_rx', val=>''}; + push @file_dsc, {tag=>'rlink_cext_fifo_tx', val=>''}; + push @file_dsc, {tag=>'rlink_cext_conf', val=>''}; + } else { push @file_dsc, {tag=>$tb_code_stem . "_stim", val=>$tb_code_stem . "_stim.dat"}; } -} else { - push @file_dsc, {tag=>"rlink_cext_fifo_rx", - val=>""}; } # @@ -199,7 +206,7 @@ } } -if ($is_verbose) { +if ($opt_verbose) { foreach my $dsc (@file_dsc) { my $tag = $dsc->{tag}; my $val = $dsc->{val}; @@ -238,10 +245,21 @@ $val = "/dev/null" if ($val eq ""); # null file case } + # handle file names + # - if absolute path keep then + # - if relative path seen note that it is relative to test bench code path + # --> prepent test bench path, canonize, and convert to a relative path + # name relavive to cwd ! + unless ($val =~ m|^/|) { + $val = $tb_code_path . '/' . $val; + $val = File::Spec->abs2rel(abs_path($val)); + } + if (not -r $val) { print "tbw-F: file for $tag not existing or not readable: $val\n"; exit 1; } + if (-l $tag) { my $cur_link = readlink $tag; if ($cur_link ne $val) {

/w11/trunk/tools/bin/ti_w11

1,5 → 1,5

6,6 → 6,9

31,6 → 34,10

150,6 → 157,15

203,11 → 219,19

225,6 → 249,8

310,9 → 336,10

/w11/trunk/tools/bin/tbrun_tbw

1,5 → 1,5

6,6 → 6,9

76,24 → 79,15

100,8 → 94,6

/w11/trunk/tools/bin/xviv_ghdl_unisim

1,11 → 1,12

114,8 → 115,15

/w11/trunk/tools/bin/xviv_msg_summary

0,0 → 1,27

w11/trunk/tools/bin/xviv_msg_summary Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: w11/trunk/tools/bin/xviv_sim_vhdl_cleanup =================================================================== --- w11/trunk/tools/bin/xviv_sim_vhdl_cleanup (nonexistent) +++ w11/trunk/tools/bin/xviv_sim_vhdl_cleanup (revision 36) @@ -0,0 +1,16 @@ +#!/bin/bash +# $Id: xviv_sim_vhdl_cleanup 774 2016-06-12 17:08:47Z mueller $ +# +# Copyright 2014-2016 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2016-06-12 774 1.0 Initial version +# + +# cleanup vivado generated vhdl models for ghdl +# 1. remove 'attribute RTL_KEEP' decorations +# ghdl 0.33 does not accept decorations of port signals ! + +sed -i.bak -e '/^ *attribute *RTL_KEEP/ d' $1

w11/trunk/tools/bin/xviv_sim_vhdl_cleanup Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: w11/trunk/tools/bin/ti_rri =================================================================== --- w11/trunk/tools/bin/ti_rri (revision 35) +++ w11/trunk/tools/bin/ti_rri (revision 36) @@ -1,8 +1,8 @@ #! /usr/bin/env tclshcpp # -*- tcl -*- -# $Id: ti_rri 631 2015-01-09 21:36:51Z mueller $ +# $Id: ti_rri 776 2016-06-18 17:22:51Z mueller $ # -# Copyright 2011-2015 by Walter F.J. Mueller +# Copyright 2011-2016 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -15,6 +15,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-01-09 776 1.2.2 add --tout option to setup rlc timeout before connect # 2015-01-09 631 1.2.1 use rlc get/set rather config # 2014-11-07 601 1.2 use tclshcpp (C++ based) rather tclsh # 2013-05-19 521 1.1.6 setup proper interactive handling; add --run reap @@ -41,6 +42,7 @@ # --logl=n ; default 2 # --dmpl=n ; default 0 # --tiol=n ; default 0 +# --tout=n ; default 1. # --int # --help # -- @@ -63,6 +65,7 @@ logl_ 2 dmpl_ 0 tiol_ 0 + tout_ 1. int 0 help 0 } @@ -119,6 +122,7 @@ ^--?logl=.+$ { regexp -- {=(.*)} $arg dummy opts(logl_) } ^--?dmpl=.+$ { regexp -- {=(.*)} $arg dummy opts(dmpl_) } ^--?tiol=.+$ { regexp -- {=(.*)} $arg dummy opts(tiol_) } + ^--?tout=.+$ { regexp -- {=(.*)} $arg dummy opts(tout_) } ^--?int$ { set opts(int) 1 } ^--?help$ { set opts(help) 1 } ^--$ { set optsendseen 1 } @@ -152,10 +156,11 @@ puts { --term=[NAME[,BAUD[,OPTS]]]} puts { --cuff[=ARGS] open cuff type rlink port. Optional arguments are:} puts { --cuff=[NAME[,OPTS]]} - puts { --log=FILE set log file name. Default is to write to stdout.} - puts { --logl=LVL set log level, default is '2' allowed values 0-3.} + puts { --log=FILE set log file name. Default is to write to stdout} + puts { --logl=LVL set log level, default is '2' allowed values 0-3} puts { --dmpl=LVL set dump level, default is '0', values like logl} - puts { --tiol=LVL set i/o trace level, default is '0', allowed 0-2.} + puts { --tiol=LVL set i/o trace level, default is '0', allowed 0-2} + puts { --tout=dt set timeout, default is '1.', must be >0.} puts { --int enter interactive mode even when commands given} puts { --help display this help and exit} puts { -- all following arguments are treated as tcl commands} @@ -216,6 +221,7 @@ rlc set printlevel $opts(logl_) rlc set dumplevel $opts(dmpl_) rlc set tracelevel $opts(tiol_) +rlc set timeout $opts(tout_) # first start, if specified with --run, the test bench # exec sh -c $cmd is used to execute a shell command including [], '',""

/w11/trunk/tools/bin/vbomconv

1,5 → 1,5

14,6 → 14,14

58,6 → 66,7

88,6 → 97,8

101,6 → 112,7

112,6 → 124,10

122,16 → 138,23

147,6 → 170,10

198,16 → 225,19

294,7 → 324,7

304,10 → 334,11

334,16 → 365,19

352,7 → 386,7

382,6 → 416,7

393,7 → 428,7

401,7 → 436,7

442,12 → 477,21

454,9 → 498,26

473,6 → 534,15

481,24 → 551,45

505,7 → 596,9

513,9 → 606,12

522,7 → 618,9

530,30 → 628,49

566,21 → 683,17

589,7 → 702,7

599,44 → 712,26

673,7 → 768,7

682,7 → 777,7

692,7 → 787,7

741,18 → 836,17

760,22 → 854,24

874,7 → 970,7

1064,7 → 1160,6

1083,7 → 1178,10

1100,12 → 1198,6

1114,25 → 1206,49

1139,10 → 1255,10

1219,7 → 1335,7

1283,7 → 1399,50

/w11/trunk/tools/bin/xviv_msg_filter

0,0 → 1,270

w11/trunk/tools/bin/xviv_msg_filter Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: w11/trunk/tools/bin/makeise =================================================================== --- w11/trunk/tools/bin/makeise (nonexistent) +++ w11/trunk/tools/bin/makeise (revision 36) @@ -0,0 +1,8 @@ +#!/bin/bash +# $Id: makeise 761 2016-04-17 08:53:48Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# + +exec make -f Makefile.ise "$@"

w11/trunk/tools/bin/makeise Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: w11/trunk/tools/dox/w11_vhd_all.Doxyfile =================================================================== --- w11/trunk/tools/dox/w11_vhd_all.Doxyfile (revision 35) +++ w11/trunk/tools/dox/w11_vhd_all.Doxyfile (revision 36) @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - vhd" -PROJECT_NUMBER = 0.72 +PROJECT_NUMBER = 0.73 PROJECT_BRIEF = "W11 CPU core and support modules" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/vhd Index: w11/trunk/tools/dox/w11_cpp.Doxyfile =================================================================== --- w11/trunk/tools/dox/w11_cpp.Doxyfile (revision 35) +++ w11/trunk/tools/dox/w11_cpp.Doxyfile (revision 36) @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - cpp" -PROJECT_NUMBER = 0.72 +PROJECT_NUMBER = 0.73 PROJECT_BRIEF = "Backend server for Rlink and w11" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/cpp Index: w11/trunk/tools/dox/w11_tcl.Doxyfile =================================================================== --- w11/trunk/tools/dox/w11_tcl.Doxyfile (revision 35) +++ w11/trunk/tools/dox/w11_tcl.Doxyfile (revision 36) @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - tcl" -PROJECT_NUMBER = 0.72 +PROJECT_NUMBER = 0.73 PROJECT_BRIEF = "Backend server for Rlink and w11" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/tcl Index: w11/trunk/rtl/make_viv/generic_ghdl.mk =================================================================== --- w11/trunk/rtl/make_viv/generic_ghdl.mk (revision 35) +++ w11/trunk/rtl/make_viv/generic_ghdl.mk (revision 36) @@ -1,10 +1,11 @@ -# $Id: generic_ghdl.mk 733 2016-02-20 12:24:13Z mueller $ +# $Id: generic_ghdl.mk 778 2016-06-25 15:18:01Z mueller $ # -# Copyright 2015- by Walter F.J. Mueller +# Copyright 2015-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-06-24 778 1.1 add rsim model; use ghdl.?sim as workdir # 2015-02-14 646 1.0 Initial version (cloned from make_ise) # GHDLIEEE = --ieee=synopsys @@ -14,12 +15,16 @@ vbomconv --ghdl_i $< vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $< # -# rules for _[o]sim to use 'virtual' [o]sim vbom's (derived from _ssim) +# rules for _[or]sim to use 'virtual' [or]sim vbom's (derived from _ssim) # %_osim : %_ssim.vbom vbomconv --ghdl_i $*_osim.vbom vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $*_osim.vbom # +%_rsim : %_ssim.vbom + vbomconv --ghdl_i $*_rsim.vbom + vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $*_rsim.vbom +# %.dep_ghdl: %.vbom vbomconv --dep_ghdl $< > $@ # @@ -29,10 +34,9 @@ # ghdl_clean: ghdl_tmp_clean rm -f $(EXE_all) - rm -f $(EXE_all:%=%_[so]sim) - rm -f cext_*.o + rm -f $(EXE_all:%=%_[sor]sim) # ghdl_tmp_clean: - find -maxdepth 1 -name "*.o" | grep -v "^\./cext_" | xargs rm -f - rm -f work-obj93.cf + rm -rf ghdl.[bsor]sim + rm -f cext_*.o e~*.o # Index: w11/trunk/rtl/make_viv/generic_xsim.mk =================================================================== --- w11/trunk/rtl/make_viv/generic_xsim.mk (revision 35) +++ w11/trunk/rtl/make_viv/generic_xsim.mk (revision 36) @@ -1,4 +1,4 @@ -# $Id: generic_xsim.mk 733 2016-02-20 12:24:13Z mueller $ +# $Id: generic_xsim.mk 778 2016-06-25 15:18:01Z mueller $ # # Copyright 2016- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory @@ -5,6 +5,7 @@ # # Revision History: # Date Rev Version Comment +# 2016-06-24 778 1.1 add [rep]sim models; use xsim.?sim as workdir # 2016-02-06 727 1.0 Initial version # %_XSim : %.vbom @@ -13,7 +14,7 @@ $*_vsim.sh rm -rf $*_vsim.sh # -# rule to build XSim ssim model from _ssim vbom +# rule to build XSim ssim model from _ssim vbom (post synth, functional) # %_XSim_ssim : %_ssim.vbom vbomconv -vsim_prj $< > $*_vsim.sh @@ -21,7 +22,7 @@ $*_vsim.sh rm -rf $*_vsim.sh # -# rule to build XSim osim model from _ssim vbom +# rule to build XSim osim model from _ssim vbom (post opt, functional) # %_XSim_osim : %_ssim.vbom vbomconv -vsim_prj $*_osim.vbom > $*_vsim.sh @@ -29,8 +30,32 @@ $*_vsim.sh rm -rf $*_vsim.sh # -# rule to build XSim tsim model from _ssim vbom +# rule to build XSim rsim model from _ssim vbom (post route, functional) # +%_XSim_rsim : %_ssim.vbom + vbomconv -vsim_prj $*_rsim.vbom > $*_vsim.sh + chmod +x $*_vsim.sh + $*_vsim.sh + rm -rf $*_vsim.sh +# +# rule to build XSim esim model from _ssim vbom (post synth, timing) +# +%_XSim_esim : %_ssim.vbom + vbomconv -vsim_prj $*_esim.vbom > $*_vsim.sh + chmod +x $*_vsim.sh + $*_vsim.sh + rm -rf $*_vsim.sh +# +# rule to build XSim psim model from _ssim vbom (post opt, timing) +# +%_XSim_psim : %_ssim.vbom + vbomconv -vsim_prj $*_psim.vbom > $*_vsim.sh + chmod +x $*_vsim.sh + $*_vsim.sh + rm -rf $*_vsim.sh +# +# rule to build XSim tsim model from _ssim vbom (post rou, timing) +# %_XSim_tsim : %_ssim.vbom vbomconv -vsim_prj $*_tsim.vbom > $*_vsim.sh chmod +x $*_vsim.sh @@ -48,13 +73,18 @@ rm -f $(EXE_all:%=%_XSim) rm -f $(EXE_all:%=%_XSim_ssim) rm -f $(EXE_all:%=%_XSim_osim) + rm -f $(EXE_all:%=%_XSim_rsim) + rm -f $(EXE_all:%=%_XSim_esim) + rm -f $(EXE_all:%=%_XSim_psim) rm -f $(EXE_all:%=%_XSim_tsim) + rm -rf xsim.[bsorept]sim # xsim_tmp_clean: - rm -f isim.log isim.wdb - rm -f xsim.jou xsim.log - rm -f xsim_*.backup.jou xsim_*.backup.log - rm -f webtalk.jou webtalk.log - rm -f webtalk_*.backup.jou webtalk_*.backup.log - rm -rf xsim.dir + rm -f *.wdb + rm -f xsim.jou xsim_*.backup.jou + rm -f xsim.log xsim_*.backup.log + rm -f webtalk.jou webtalk_*.backup.jou + rm -f webtalk.log webtalk_*.backup.log + rm -rf xsim.[bsorept]sim/xsim.dir/xil_defaultlib + rm -f xsim.dir # Index: w11/trunk/rtl/make_viv/viv_tools_build.tcl =================================================================== --- w11/trunk/rtl/make_viv/viv_tools_build.tcl (revision 35) +++ w11/trunk/rtl/make_viv/viv_tools_build.tcl (revision 36) @@ -1,11 +1,17 @@ -# $Id: viv_tools_build.tcl 738 2016-03-06 13:02:53Z mueller $ +# $Id: viv_tools_build.tcl 767 2016-05-26 07:47:51Z mueller $ # -# Copyright 2015- by Walter F.J. Mueller +# Copyright 2015-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment -# 2016-02-28 649 1.1.1 add 2015.4 specific setups +# 2016-05-22 767 1.2 cleaner setup handling; use explore flows +# add 2016.1 specific setups +# 2016-04-02 758 1.1.5 remove USR_ACCESS setup, must be done in xdc +# 2016-03-26 752 1.1.4 more steps supported: prj,opt,pla +# 2016-03-25 751 1.1.3 suppress some messages +# 2016-03-19 748 1.1.2 set bitstream USR_ACCESS to TIMESTAMP +# 2016-02-28 738 1.1.1 add 2015.4 specific setups # 2015-02-21 649 1.1 add 2014.4 specific setups # 2015-02-14 646 1.0 Initial version # @@ -45,6 +51,13 @@ # # -------------------------------------------------------------------- # +proc rvtb_rm_file {src} { + exec rm -f $src +} + +# +# -------------------------------------------------------------------- +# proc rvtb_cp_file {src dst} { if {[file readable $src]} { exec cp -p $src $dst @@ -58,7 +71,6 @@ # -------------------------------------------------------------------- # proc rvtb_build_check {step} { - get_msg_config -rules return "" } @@ -65,30 +77,67 @@ # # -------------------------------------------------------------------- # +proc rvtb_version_is {val} { + set vers [version -short] + return [expr {$vers eq $val}] +} +# +# -------------------------------------------------------------------- +# +proc rvtb_version_min {val} { + set vers [version -short] + return [expr {[string compare $vers $val] >= 0}] +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_version_max {val} { + set vers [version -short] + return [expr {[string compare $vers $val] <= 0}] +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_version_in {min max} { + set vers [version -short] + return [expr {[string compare $vers $min] >= 0 && \ + [string compare $vers $max] <= 0}] +} + +# +# -------------------------------------------------------------------- +# proc rvtb_default_build {stem step} { - - # general setups - switch [version -short] { - "2014.4" { - # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages - # set here to avoid messages during create_project - set_msg_config -suppress -id {Board 49-26} - } - "2015.4" { - # enable vhdl asserts, see http://www.xilinx.com/support/answers/65415.html - set_param synth.elaboration.rodinMoreOptions \ - {rt::set_parameter ignoreVhdlAssertStmts false} - } + # supported step values + # prj setup project + # syn run synthesis + # opt run synthesis + implementation up to step opt_design + # pla run synthesis + implementation up to step place_design + # imp run synthesis + implementation (but not bit file generation) + # bit Synthesize + Implement + generate bit file + + if {![regexp -- {^(prj|syn|opt|pla|imp|bit)$} $step]} { + error "bad step name $step" } + # general setups (prior to project creation) ------------------ + # version dependent setups + if {[rvtb_version_is "2014.4"]} { + # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages + # set here to avoid messages during create_project + set_msg_config -suppress -id {Board 49-26} + } + # read setup set setup_file [rvtb_locate_setup_file $stem] if {$setup_file ne ""} {source -notrace $setup_file} - # Create project + # Create project ---------------------------------------------- rvtb_trace_cmd "create_project project_mflow ./project_mflow" - # Setup project properties + # Setup project properties ------------------------------- set obj [get_projects project_mflow] set_property "default_lib" "xil_defaultlib" $obj set_property "part" $::rvtb_part $obj @@ -95,26 +144,73 @@ set_property "simulator_language" "Mixed" $obj set_property "target_language" "VHDL" $obj - # version dependent setups - switch [version -short] { - "2014.4" { - # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages - # repeated here because create_project apparently clears msg_config - set_msg_config -suppress -id {Board 49-26} - } + # general setups ----------------------------------------- + # suppress message which don't convey useful information + set_msg_config -suppress -id {DRC 23-20}; # DSP48 output pilelining + set_msg_config -suppress -id {Project 1-120}; # WebTalk mandatory + set_msg_config -suppress -id {Common 17-186}; # WebTalk info send + + # Setup list of extra synthesis options (for later rodinMoreOptions) + set synth_more_opts {} + + # version independent setups ----------------------------- + + # setup synthesis and implementation strategies + set_property strategy Flow_PerfOptimized_high [get_runs synth_1] + set_property strategy Performance_Explore [get_runs impl_1] + + # FSM recognition threshold (default is 5) + # see http://www.xilinx.com/support/answers/58574.html + lappend synth_more_opts {rt::set_parameter minFsmStates 3} + + # version dependent setups ------------------------------- + if {[rvtb_version_is "2014.4"]} { + # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages + # repeated here because create_project apparently clears msg_config + set_msg_config -suppress -id {Board 49-26} } + if {[rvtb_version_is "2015.4"]} { + # enable vhdl asserts, see http://www.xilinx.com/support/answers/65415.html + lappend synth_more_opts {rt::set_parameter ignoreVhdlAssertStmts false} + } + + if {[rvtb_version_min "2016.1"]} { + # enable vhdl asserts via global option (after 2016.1) + set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1] + } + + # now setup extra synthesis options + # see http://www.xilinx.com/support/answers/58248.html + # -> since used via 'set_param' it's a parameter + # -> only last definition counts + # -> use ';' separated list + # -> these options are **NOT** preserved in project file !! + if {[llength $synth_more_opts]} { + puts "# extra synthesis options:" + foreach opt $synth_more_opts { puts "# $opt"} + set_param synth.elaboration.rodinMoreOptions [join $synth_more_opts "; "] + } + # Setup filesets set vbom_prj [exec vbomconv -vsyn_prj "${stem}.vbom"] eval $vbom_prj update_compile_order -fileset sources_1 + if {$step eq "prj"} { + puts "rvtb_default_build-I: new project setup for ${stem}" + return "" + } + # some handy variables set path_runs "project_mflow/project_mflow.runs" set path_syn1 "${path_runs}/synth_1" set path_imp1 "${path_runs}/impl_1" - # build: synthesize + # build: synthesize ------------------------------------------------ + puts "# current rodinMoreOptions:" + puts [get_param synth.elaboration.rodinMoreOptions] + rvtb_trace_cmd "launch_runs synth_1" rvtb_trace_cmd "wait_on_run synth_1" @@ -121,49 +217,82 @@ rvtb_mv_file "$path_syn1/runme.log" "${stem}_syn.log" rvtb_cp_file "$path_syn1/${stem}_utilization_synth.rpt" "${stem}_syn_util.rpt" - rvtb_cp_file "$path_syn1/${stem}.dcp" "${stem}_syn.dcp" + rvtb_cp_file "$path_syn1/${stem}.dcp" "${stem}_syn.dcp" if {$step eq "syn"} {return [rvtb_build_check $step]} - # build: implement - rvtb_trace_cmd "launch_runs impl_1" + # build: implement ------------------------------------------------- + set launch_opt "" + if {$step eq "opt"} {set launch_opt "-to_step opt_design"} + if {$step eq "pla"} {set launch_opt "-to_step place_design"} + + rvtb_trace_cmd "launch_runs ${launch_opt} impl_1" rvtb_trace_cmd "wait_on_run impl_1" rvtb_cp_file "$path_imp1/runme.log" "${stem}_imp.log" + rvtb_cp_file "$path_imp1/${stem}_opt.dcp" "${stem}_opt.dcp" + rvtb_cp_file "$path_imp1/${stem}_drc_opted.rpt" "${stem}_opt_drc.rpt" + + if {$step eq "opt"} { + rvtb_trace_cmd "open_checkpoint $path_imp1/${stem}_opt.dcp" + report_utilization -file "${stem}_opt_util.rpt" + report_utilization -hierarchical -file "${stem}_opt_util_h.rpt" + return [rvtb_build_check $step] + } + + rvtb_cp_file "$path_imp1/${stem}_placed.dcp" "${stem}_pla.dcp" + rvtb_cp_file "$path_imp1/${stem}_io_placed.rpt" "${stem}_pla_io.rpt" + rvtb_cp_file "$path_imp1/${stem}_utilization_placed.rpt" \ + "${stem}_pla_util.rpt" + rvtb_cp_file "$path_imp1/${stem}_control_sets_placed.rpt" \ + "${stem}_pla_clk_set.rpt" + + if {$step eq "pla"} { + return [rvtb_build_check $step] + } + + rvtb_cp_file "$path_imp1/${stem}_routed.dcp" "${stem}_rou.dcp" rvtb_cp_file "$path_imp1/${stem}_route_status.rpt" "${stem}_rou_sta.rpt" rvtb_cp_file "$path_imp1/${stem}_drc_routed.rpt" "${stem}_rou_drc.rpt" - rvtb_cp_file "$path_imp1/${stem}_io_placed.rpt" "${stem}_pla_io.rpt" - rvtb_cp_file "$path_imp1/${stem}_clock_utilization_placed.rpt" \ - "${stem}_pla_clk.rpt" rvtb_cp_file "$path_imp1/${stem}_timing_summary_routed.rpt" \ "${stem}_rou_tim.rpt" - rvtb_cp_file "$path_imp1/${stem}_utilization_placed.rpt" \ - "${stem}_pla_util.rpt" - rvtb_cp_file "$path_imp1/${stem}_drc_opted.rpt" "${stem}_opt_drc.rpt" - rvtb_cp_file "$path_imp1/${stem}_control_sets_placed.rpt" \ - "${stem}_pla_cset.rpt" rvtb_cp_file "$path_imp1/${stem}_power_routed.rpt" "${stem}_rou_pwr.rpt" + rvtb_cp_file "$path_imp1/${stem}_clock_utilization_routed.rpt" \ + "${stem}_rou_clk_util.rpt" - rvtb_cp_file "$path_imp1/${stem}_opt.dcp" "${stem}_opt.dcp" - rvtb_cp_file "$path_imp1/${stem}_placed.dcp" "${stem}_pla.dcp" - rvtb_cp_file "$path_imp1/${stem}_routed.dcp" "${stem}_rou.dcp" - # additional reports rvtb_trace_cmd "open_run impl_1" - report_utilization -file "${stem}_rou_util.rpt" + report_utilization -file "${stem}_rou_util.rpt" report_utilization -hierarchical -file "${stem}_rou_util_h.rpt" - report_datasheet -file "${stem}_rou_ds.rpt" + report_datasheet -file "${stem}_rou_ds.rpt" + report_cdc -file "${stem}_rou_cdc.rpt" + report_clock_interaction -delay_type min_max -significant_digits 3 \ + -file "${stem}_rou_clk_int.rpt" + if {[get_property SSN_REPORT [get_property PART [current_project]]]} { + report_ssn -format TXT -file "${stem}_rou_ssn.rpt" + } if {$step eq "imp"} {return [rvtb_build_check $step]} - # build: bitstream + # build: bitstream ------------------------------------------------- + # check for critical warnings, e.g. + # [Timing 38-282] The design failed to meet the timing requirements. + # in that case abort build + + rvtb_rm_file "./${stem}.bit" + + if {[get_msg_config -severity {critical warning} -count]} { + puts "rvtb_default_build-E: abort due to critical warnings seen before" + puts "rvtb_default_build-E: no bitfile generated" + return [rvtb_build_check $step] + } + rvtb_trace_cmd "launch_runs impl_1 -to_step write_bitstream" rvtb_trace_cmd "wait_on_run impl_1" - rvtb_mv_file "$path_imp1/${stem}.bit" "." - rvtb_mv_file "$path_imp1/runme.log" "${stem}_bit.log" + rvtb_mv_file "$path_imp1/runme.log" "${stem}_bit.log" + rvtb_mv_file "$path_imp1/${stem}.bit" "." return [rvtb_build_check $step] } -

/w11/trunk/rtl/make_viv/viv_tools_model.tcl

1,38 → 1,59

/w11/trunk/rtl/make_viv/generic_vivado.mk

1,10 → 1,14

37,6 → 41,18

48,7 → 64,21

62,6 → 92,7

69,12 → 100,32

85,7 → 136,8

95,8 → 147,72

106,7 → 222,7

133,9 → 249,9

/w11/trunk/rtl/make_viv/viv_tools_config.tcl

1,10 → 1,11

11,6 → 12,19

25,5 → 39,13

/w11/trunk/rtl/ibus/Makefile File deleted

/w11/trunk/rtl/ibus/ibdr_rk11.vbom

4,6 → 4,7

/w11/trunk/rtl/ibus/ibd_ibmon.vbom

4,6 → 4,7

/w11/trunk/rtl/ibus/ibdr_rk11.vhd

1,6 → 1,6

18,7 → 18,7

29,6 → 29,7

168,7 → 169,7

/w11/trunk/rtl/ibus/ibdr_rl11.vhd

1,6 → 1,6

18,7 → 18,7

27,6 → 27,7

238,7 → 239,7

/w11/trunk/rtl/ibus/iblib.vhd

1,6 → 1,6

16,9 → 16,10

115,8 → 116,8

/w11/trunk/rtl/ibus/ibd_iist.vhd

1,6 → 1,6

18,7 → 18,7

29,6 → 29,7

218,7 → 219,7

/w11/trunk/rtl/ibus/ibdr_rl11.vbom

4,6 → 4,7

/w11/trunk/rtl/ibus/ibdr_rhrp.vhd

1,6 → 1,6

18,7 → 18,7

28,6 → 28,7

401,7 → 402,7

/w11/trunk/rtl/ibus/Makefile.ise

0,0 → 1,32

/w11/trunk/rtl/ibus/ibdr_rhrp.vbom

4,6 → 4,7

/w11/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vbom File deleted

/w11/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vhd File deleted

/w11/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop.c File deleted

/w11/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vbom File deleted

/w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_conf.vhd File deleted

/w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.mfset File deleted

/w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.ucf_cpp File deleted

/w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic/.cvsignore File deleted

/w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.vbom File deleted

/w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile File deleted

/w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic

w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic Property changes : Deleted: svn:ignore ## -1,43 +0,0 ## -*.gz -*.tar -*.tgz -*.dep_* -work-obj93.cf -*.vcd -*.ghw -*.sav -*.tmp -*.exe -ise -xflow.his -*.ngc -*.ncd -*.pcf -*.bit -*.msk -*.svf -*.log -isim -*_[sfot]sim.vhd -*_tsim.sdf -rlink_cext_fifo_[rt]x -rlink_cext_conf -tmu_ofile -*.dsk -*.tap -*.lst -*.cof -.Xil -project_mflow -xsim.dir -webtalk_* -*_[sfot]sim -*_[IX]Sim -*_[IX]Sim_[sfot]sim -*.dcp -*.jou -*.pb -*.prj -*.rpt -*.wdb -sys_tst_fx2loop_ic_n2.ucf Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd (nonexistent) @@ -1,58 +0,0 @@ --- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2012- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Package Name: sys_conf --- Description: Definitions for sys_tst_fx2loop_ic3_n2 (for synthesis) --- --- Dependencies: - --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- Revision History: --- Date Rev Version Comment --- 2012-01-15 453 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.slvtypes.all; - -package sys_conf is - - constant sys_conf_clkfx_divide : positive := 1; - constant sys_conf_clkfx_multiply : positive := 2; - - constant sys_conf_fx2_type : string := "ic3"; - - -- dummy values defs for generic parameters of as controller - constant sys_conf_fx2_rdpwldelay : positive := 1; - constant sys_conf_fx2_rdpwhdelay : positive := 1; - constant sys_conf_fx2_wrpwldelay : positive := 1; - constant sys_conf_fx2_wrpwhdelay : positive := 1; - constant sys_conf_fx2_flagdelay : positive := 1; - - -- pktend timer setting - -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) - constant sys_conf_fx2_petowidth : positive := 10; - - constant sys_conf_fx2_ccwidth : positive := 5; - - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - - -- derived constants - - constant sys_conf_clksys : integer := - (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; - constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; - -end package sys_conf; Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset (nonexistent) @@ -1,58 +0,0 @@ -# $Id: sys_tst_fx2loop_ic3_n2.mfset 453 2012-01-15 17:51:18Z mueller $ -# -# ---------------------------------------------------------------------------- -[xst] -INFO:.*Mux is complete : default of case is discarded - -Unconnected output port 'LOCKED' of component 'dcm_sfs' -Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' - -Node of sequential type is unconnected -Node of sequential type is unconnected - -Input is never used -Input > is never used -Input is never used -Input is never used -Input is never used -Input is never used - -Signal is assigned but never used -Signal is assigned but never used -Signal is assigned but never used - -# -# ---------------------------------------------------------------------------- -[tra] -INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP -The Offset constraint .*, is specified without a duration - -# -# ---------------------------------------------------------------------------- -[map] -The signal is incomplete -The signal _IBUF> is incomplete -The signal _IBUF> is incomplete -The signal _IBUF> is incomplete -INFO:.* - -# -# ---------------------------------------------------------------------------- -[par] -A clock IOB / clock component pair have been found that are not placed at -The Offset constraint .*, is specified without a duration -The signal I_MEM_WAIT_IBUF has no load -The signal I_BTN<1>_IBUF has no load -The signal I_BTN<2>_IBUF has no load -The signal I_BTN<3>_IBUF has no load -There are 4 loadless signals in this design - -# -# ---------------------------------------------------------------------------- -[bgn] -Spartan-3 1200E and 1600E devices do not support bitstream -To achieve optimal frequency synthesis performance .* consult -The signal is incomplete -The signal _IBUF> is incomplete -The signal _IBUF> is incomplete -The signal _IBUF> is incomplete Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp (nonexistent) @@ -1,15 +0,0 @@ -## $Id: sys_tst_fx2loop_ic3_n2.ucf_cpp 453 2012-01-15 17:51:18Z mueller $ -## -## Revision History: -## Date Rev Version Comment -## 2011-12-26 445 1.0 Initial version -## - -NET "I_CLK50" TNM_NET = "I_CLK50"; -TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; -OFFSET = IN 10 ns BEFORE "I_CLK50"; -OFFSET = OUT 20 ns AFTER "I_CLK50"; - -#include "bplib/nexys2/nexys2_pins.ucf" -#include "bplib/nexys2/nexys2_pins_fx2.ucf" -#include "bplib/nexys2/nexys2_time_fx2_ic.ucf" Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore (nonexistent) @@ -1 +0,0 @@ -sys_tst_fx2loop_ic3_n2.ucf Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile (nonexistent) @@ -1,30 +0,0 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ -# -# Revision History: -# Date Rev Version Comment -# 2012-01-15 453 1.0 Initial version -# -# -VBOM_all = $(wildcard *.vbom) -BIT_all = $(VBOM_all:.vbom=.bit) -# -include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk -FX2_FILE = nexys2_jtag_3fifo_ic.ihx -# -.PHONY : all clean -# -all : $(BIT_all) -# -clean : ise_clean - rm -f $(VBOM_all:.vbom=.ucf) -# -#---- -# -include ${RETROBASE}/rtl/make_ise/generic_xflow.mk -include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk -# -ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) -include $(VBOM_all:.vbom=.dep_ghdl) -endif -# Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom (nonexistent) @@ -1,8 +0,0 @@ -# conf -sys_conf = sys_conf.vhd -# libs -# components -# design -../sys_tst_fx2loop_n2.vbom -@ucf_cpp: sys_tst_fx2loop_ic3_n2.ucf -@top: sys_tst_fx2loop_n2 Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3 =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3 (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3 (nonexistent)

w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3 Property changes : Deleted: svn:ignore ## -1,43 +0,0 ## -*.gz -*.tar -*.tgz -*.dep_* -work-obj93.cf -*.vcd -*.ghw -*.sav -*.tmp -*.exe -ise -xflow.his -*.ngc -*.ncd -*.pcf -*.bit -*.msk -*.svf -*.log -isim -*_[sfot]sim.vhd -*_tsim.sdf -rlink_cext_fifo_[rt]x -rlink_cext_conf -tmu_ofile -*.dsk -*.tap -*.lst -*.cof -.Xil -project_mflow -xsim.dir -webtalk_* -*_[sfot]sim -*_[IX]Sim -*_[IX]Sim_[sfot]sim -*.dcp -*.jou -*.pb -*.prj -*.rpt -*.wdb -sys_tst_fx2loop_ic3_n2.ucf Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd (nonexistent) @@ -1,316 +0,0 @@ --- $Id: sys_tst_fx2loop_n2.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2011-2015 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: sys_tst_fx2loop_n2 - syn --- Description: test of Cypress EZ-USB FX2 controller --- --- Dependencies: vlib/xlib/dcm_sfs --- vlib/genlib/clkdivce --- bpgen/sn_humanio --- tst_fx2loop_hiomap --- tst_fx2loop --- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"] --- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"] --- bplib/nxcramlib/nx_cram_dummy --- --- Test bench: - --- --- Target Devices: generic --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz --- 2012-04-09 461 13.3 O76d xc3s1200e-4 307 390 64 325 p 9.9 as2/100 --- 2012-04-09 461 13.3 O76d xc3s1200e-4 358 419 64 369 p 9.4 ic2/100 --- 2012-04-09 461 13.3 O76c xc3s1200e-4 436 537 96 476 p 8.9 ic3/100 --- --- Revision History: --- Date Rev Version Comment --- 2015-01-25 638 1.1.1 retire fx2_2fifoctl_as --- 2012-01-15 453 1.1 now generic for as,ic,ic3 controllers --- 2011-12-26 445 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; -use work.xlib.all; -use work.genlib.all; -use work.bpgenlib.all; -use work.tst_fx2looplib.all; -use work.fx2lib.all; -use work.nxcramlib.all; -use work.sys_conf.all; - --- ---------------------------------------------------------------------------- - -entity sys_tst_fx2loop_n2 is -- top level - -- implements nexys2_aif + fx2 pins - port ( - I_CLK50 : in slbit; -- 50 MHz board clock - I_RXD : in slbit; -- receive data (board view) - O_TXD : out slbit; -- transmit data (board view) - I_SWI : in slv8; -- n2 switches - I_BTN : in slv4; -- n2 buttons - O_LED : out slv8; -- n2 leds - O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) - O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) - O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) - O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) - O_MEM_WE_N : out slbit; -- cram: write enable (act.low) - O_MEM_OE_N : out slbit; -- cram: output enable (act.low) - O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) - O_MEM_CLK : out slbit; -- cram: clock - O_MEM_CRE : out slbit; -- cram: command register enable - I_MEM_WAIT : in slbit; -- cram: mem wait - O_MEM_ADDR : out slv23; -- cram: address lines - IO_MEM_DATA : inout slv16; -- cram: data lines - O_FLA_CE_N : out slbit; -- flash ce.. (act.low) - I_FX2_IFCLK : in slbit; -- fx2: interface clock - O_FX2_FIFO : out slv2; -- fx2: fifo address - I_FX2_FLAG : in slv4; -- fx2: fifo flags - O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) - O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) - O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) - O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) - IO_FX2_DATA : inout slv8 -- fx2: data lines - ); -end sys_tst_fx2loop_n2; - -architecture syn of sys_tst_fx2loop_n2 is - - signal CLK : slbit := '0'; - signal RESET : slbit := '0'; - - signal CE_USEC : slbit := '0'; - signal CE_MSEC : slbit := '0'; - - signal SWI : slv8 := (others=>'0'); - signal BTN : slv4 := (others=>'0'); - signal LED : slv8 := (others=>'0'); - signal DSP_DAT : slv16 := (others=>'0'); - signal DSP_DP : slv4 := (others=>'0'); - - signal LED_MAP : slv8 := (others=>'0'); - - signal HIO_CNTL : hio_cntl_type := hio_cntl_init; - signal HIO_STAT : hio_stat_type := hio_stat_init; - - signal FX2_RXDATA : slv8 := (others=>'0'); - signal FX2_RXVAL : slbit := '0'; - signal FX2_RXHOLD : slbit := '0'; - signal FX2_RXAEMPTY : slbit := '0'; - signal FX2_TXDATA : slv8 := (others=>'0'); - signal FX2_TXENA : slbit := '0'; - signal FX2_TXBUSY : slbit := '0'; - signal FX2_TXAFULL : slbit := '0'; - signal FX2_TX2DATA : slv8 := (others=>'0'); - signal FX2_TX2ENA : slbit := '0'; - signal FX2_TX2BUSY : slbit := '1'; - signal FX2_TX2AFULL : slbit := '0'; - signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; - -begin - - assert (sys_conf_clksys mod 1000000) = 0 - report "assert sys_conf_clksys on MHz grid" - severity failure; - - DCM : dcm_sfs - generic map ( - CLKFX_DIVIDE => sys_conf_clkfx_divide, - CLKFX_MULTIPLY => sys_conf_clkfx_multiply, - CLKIN_PERIOD => 20.0) - port map ( - CLKIN => I_CLK50, - CLKFX => CLK, - LOCKED => open - ); - - CLKDIV : clkdivce - generic map ( - CDUWIDTH => 7, -- good for up to 127 MHz ! - USECDIV => sys_conf_clksys_mhz, - MSECDIV => 1000) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC - ); - - HIO : sn_humanio - generic map ( - DEBOUNCE => sys_conf_hio_debounce) - port map ( - CLK => CLK, - RESET => '0', - CE_MSEC => CE_MSEC, - SWI => SWI, - BTN => BTN, - LED => LED, - DSP_DAT => DSP_DAT, - DSP_DP => DSP_DP, - I_SWI => I_SWI, - I_BTN => I_BTN, - O_LED => O_LED, - O_ANO_N => O_ANO_N, - O_SEG_N => O_SEG_N - ); - - RESET <= BTN(0); -- BTN(0) will reset tester !! - - HIOMAP : tst_fx2loop_hiomap - port map ( - CLK => CLK, - RESET => RESET, - HIO_CNTL => HIO_CNTL, - HIO_STAT => HIO_STAT, - FX2_MONI => FX2_MONI, - SWI => SWI, - BTN => BTN, - LED => LED_MAP, - DSP_DAT => DSP_DAT, - DSP_DP => DSP_DP - ); - - proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA, - FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL) - begin - - if SWI(4) = '1' then - LED(7) <= '0'; - LED(6) <= '0'; - LED(5) <= FX2_TX2BUSY; - LED(4) <= FX2_TX2ENA; - LED(3) <= FX2_TXBUSY; - LED(2) <= FX2_TXENA; - LED(1) <= FX2_RXHOLD; - LED(0) <= FX2_RXVAL; - else - LED <= LED_MAP; - end if; - - end process proc_led; - - - TST : tst_fx2loop - port map ( - CLK => CLK, - RESET => RESET, - CE_MSEC => CE_MSEC, - HIO_CNTL => HIO_CNTL, - HIO_STAT => HIO_STAT, - FX2_MONI => FX2_MONI, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TX2DATA => FX2_TX2DATA, - TX2ENA => FX2_TX2ENA, - TX2BUSY => FX2_TX2BUSY - ); - - FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate - CNTL : fx2_2fifoctl_ic - generic map ( - RXFAWIDTH => 5, - TXFAWIDTH => 5, - PETOWIDTH => sys_conf_fx2_petowidth, - CCWIDTH => sys_conf_fx2_ccwidth, - RXAEMPTY_THRES => 1, - TXAFULL_THRES => 1) - port map ( - CLK => CLK, - RESET => RESET, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - RXAEMPTY => FX2_RXAEMPTY, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TXAFULL => FX2_TXAFULL, - MONI => FX2_MONI, - I_FX2_IFCLK => I_FX2_IFCLK, - O_FX2_FIFO => O_FX2_FIFO, - I_FX2_FLAG => I_FX2_FLAG, - O_FX2_SLRD_N => O_FX2_SLRD_N, - O_FX2_SLWR_N => O_FX2_SLWR_N, - O_FX2_SLOE_N => O_FX2_SLOE_N, - O_FX2_PKTEND_N => O_FX2_PKTEND_N, - IO_FX2_DATA => IO_FX2_DATA - ); - end generate FX2_CNTL_IC; - - FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate - CNTL : fx2_3fifoctl_ic - generic map ( - RXFAWIDTH => 5, - TXFAWIDTH => 5, - PETOWIDTH => sys_conf_fx2_petowidth, - CCWIDTH => sys_conf_fx2_ccwidth, - RXAEMPTY_THRES => 1, - TXAFULL_THRES => 1, - TX2AFULL_THRES => 1) - port map ( - CLK => CLK, - RESET => RESET, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - RXAEMPTY => FX2_RXAEMPTY, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TXAFULL => FX2_TXAFULL, - TX2DATA => FX2_TX2DATA, - TX2ENA => FX2_TX2ENA, - TX2BUSY => FX2_TX2BUSY, - TX2AFULL => FX2_TX2AFULL, - MONI => FX2_MONI, - I_FX2_IFCLK => I_FX2_IFCLK, - O_FX2_FIFO => O_FX2_FIFO, - I_FX2_FLAG => I_FX2_FLAG, - O_FX2_SLRD_N => O_FX2_SLRD_N, - O_FX2_SLWR_N => O_FX2_SLWR_N, - O_FX2_SLOE_N => O_FX2_SLOE_N, - O_FX2_PKTEND_N => O_FX2_PKTEND_N, - IO_FX2_DATA => IO_FX2_DATA - ); - end generate FX2_CNTL_IC3; - - SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy - port map ( - O_MEM_CE_N => O_MEM_CE_N, - O_MEM_BE_N => O_MEM_BE_N, - O_MEM_WE_N => O_MEM_WE_N, - O_MEM_OE_N => O_MEM_OE_N, - O_MEM_ADV_N => O_MEM_ADV_N, - O_MEM_CLK => O_MEM_CLK, - O_MEM_CRE => O_MEM_CRE, - I_MEM_WAIT => I_MEM_WAIT, - O_MEM_ADDR => O_MEM_ADDR, - IO_MEM_DATA => IO_MEM_DATA - ); - - O_FLA_CE_N <= '1'; -- keep Flash memory disabled - - O_TXD <= I_RXD; -- loop-back in serial port... - -end syn; - Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom (nonexistent) @@ -1,28 +0,0 @@ -# this is the vbom for the 'generic' top level entity -# to be referenced in the vbom's of the specific systems -# ./ic/sys_tst_fx2loop_ic_n2 -# ./ic3/sys_tst_fx2loop_ic3_n2 -# -# libs -../../../vlib/slvtypes.vhd -../../../vlib/xlib/xlib.vhd -../../../vlib/genlib/genlib.vhd -../../../bplib/bpgen/bpgenlib.vbom -../tst_fx2looplib.vbom -../../../bplib/fx2lib/fx2lib.vhd -../../../bplib/nxcramlib/nxcramlib.vhd -${sys_conf} -# components -[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom -[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom -../../../vlib/genlib/clkdivce.vbom -../../../bplib/bpgen/sn_humanio.vbom -../tst_fx2loop_hiomap.vbom -../tst_fx2loop.vbom -../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom -../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom -../../../bplib/nxcramlib/nx_cram_dummy.vbom -# design -sys_tst_fx2loop_n2.vhd -## no @ucf_cpp - Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2 =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2 (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2 (nonexistent)

w11/trunk/rtl/sys_gen/tst_fx2loop/nexys2 Property changes : Deleted: svn:ignore ## -1,42 +0,0 ## -*.gz -*.tar -*.tgz -*.dep_* -work-obj93.cf -*.vcd -*.ghw -*.sav -*.tmp -*.exe -ise -xflow.his -*.ngc -*.ncd -*.pcf -*.bit -*.msk -*.svf -*.log -isim -*_[sfot]sim.vhd -*_tsim.sdf -rlink_cext_fifo_[rt]x -rlink_cext_conf -tmu_ofile -*.dsk -*.tap -*.lst -*.cof -.Xil -project_mflow -xsim.dir -webtalk_* -*_[sfot]sim -*_[IX]Sim -*_[IX]Sim_[sfot]sim -*.dcp -*.jou -*.pb -*.prj -*.rpt -*.wdb Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd (nonexistent) @@ -1,63 +0,0 @@ --- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2012-2013 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Package Name: sys_conf --- Description: Definitions for sys_tst_fx2loop_ic_n3 (for synthesis) --- --- Dependencies: - --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- Revision History: --- Date Rev Version Comment --- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect --- 2012-04-24 510 1.1 use 3/2 clock-> 150 MHz sysclk --- 2012-04-09 461 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.slvtypes.all; - -package sys_conf is - - constant sys_conf_clksys_vcodivide : positive := 2; - constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz - constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz - constant sys_conf_clksys_gentype : string := "DCM"; - - constant sys_conf_fx2_type : string := "ic2"; - - -- dummy values defs for generic parameters of as controller - constant sys_conf_fx2_rdpwldelay : positive := 1; - constant sys_conf_fx2_rdpwhdelay : positive := 1; - constant sys_conf_fx2_wrpwldelay : positive := 1; - constant sys_conf_fx2_wrpwhdelay : positive := 1; - constant sys_conf_fx2_flagdelay : positive := 1; - - -- pktend timer setting - -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) - constant sys_conf_fx2_petowidth : positive := 10; - - constant sys_conf_fx2_ccwidth : positive := 5; - - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - - -- derived constants - - constant sys_conf_clksys : integer := - ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / - sys_conf_clksys_outdivide; - constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; - -end package sys_conf; Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp (nonexistent) @@ -1,48 +0,0 @@ -## $Id: sys_tst_fx2loop_ic_n3.ucf_cpp 556 2014-05-29 19:01:39Z mueller $ -## -## Revision History: -## Date Rev Version Comment -## 2013-10-13 540 1.1 add pad->clk and fx2 cdc constraints -## 2012-04-09 461 1.0 Initial version -## - -NET "I_CLK100" TNM_NET = "I_CLK100"; -TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; -OFFSET = IN 10 ns BEFORE "I_CLK100"; -OFFSET = OUT 20 ns AFTER "I_CLK100"; - -## constrain pad->net clock delay -NET CLK TNM = TNM_CLK; -TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns; -NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK; -TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns; - -## constrain async pad->pad delays -TIMEGRP TG_SLOW_INS = PADS(I_RXD); -TIMEGRP TG_SLOW_OUTS = PADS(O_TXD); -TIMESPEC TS_ASYNC_PADS=FROM TG_SLOW_INS TO TG_SLOW_OUTS 10 ns; - -## FX2 controller specific constraints -## constrain cdc path in fifos and reset -TIMESPEC TS_CDC_FIFO = - FROM FFS(*FIFO/GC?/GRAY_*.CNT/R_DATA* - *FIFO/R_REG?_rst? - *FIFO/R_REG?_rst?_s) - TO FFS(*FIFO/R_REG?_?addr_c* - *FIFO/R_REG?_rst?_c - *FIFO/R_REG?_rst?_sc) - 5 ns DATAPATHONLY; - -## constrain cdc path in monitor -TIMESPEC TS_CDC_FX2MONI = FROM FFS - TO FFS(FX2_CNTL*/R_MONI_C*) 5 ns DATAPATHONLY; - -## -## std board -## -#include "bplib/nexys3/nexys3_pins.ucf" -## -## FX2 interface -## -#include "bplib/nexys3/nexys3_pins_fx2.ucf" -#include "bplib/nexys3/nexys3_time_fx2_ic.ucf" Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/.cvsignore =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/.cvsignore (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/.cvsignore (nonexistent) @@ -1 +0,0 @@ -sys_tst_fx2loop_ic_n3.ucf Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile (nonexistent) @@ -1,30 +0,0 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ -# -# Revision History: -# Date Rev Version Comment -# 2012-04-09 461 1.0 Initial version -# -# -VBOM_all = $(wildcard *.vbom) -BIT_all = $(VBOM_all:.vbom=.bit) -# -include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk -FX2_FILE = nexys3_jtag_2fifo_ic.ihx -# -.PHONY : all clean -# -all : $(BIT_all) -# -clean : ise_clean - rm -f $(VBOM_all:.vbom=.ucf) -# -#---- -# -include ${RETROBASE}/rtl/make_ise/generic_xflow.mk -include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk -# -ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) -include $(VBOM_all:.vbom=.dep_ghdl) -endif -# Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.vbom =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.vbom (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.vbom (nonexistent) @@ -1,8 +0,0 @@ -# conf -sys_conf = sys_conf.vhd -# libs -# components -# design -../sys_tst_fx2loop_n3.vbom -@ucf_cpp: sys_tst_fx2loop_ic_n3.ucf -@top: sys_tst_fx2loop_n3 Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic (nonexistent)

w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic Property changes : Deleted: svn:ignore ## -1,43 +0,0 ## -*.gz -*.tar -*.tgz -*.dep_* -work-obj93.cf -*.vcd -*.ghw -*.sav -*.tmp -*.exe -ise -xflow.his -*.ngc -*.ncd -*.pcf -*.bit -*.msk -*.svf -*.log -isim -*_[sfot]sim.vhd -*_tsim.sdf -rlink_cext_fifo_[rt]x -rlink_cext_conf -tmu_ofile -*.dsk -*.tap -*.lst -*.cof -.Xil -project_mflow -xsim.dir -webtalk_* -*_[sfot]sim -*_[IX]Sim -*_[IX]Sim_[sfot]sim -*.dcp -*.jou -*.pb -*.prj -*.rpt -*.wdb -sys_tst_fx2loop_ic_n3.ucf Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/.cvsignore =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/.cvsignore (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/.cvsignore (nonexistent) @@ -1 +0,0 @@ -sys_tst_fx2loop_ic3_n3.ucf Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp (nonexistent) @@ -1,20 +0,0 @@ -## $Id: sys_tst_fx2loop_ic3_n3.ucf_cpp 461 2012-04-09 21:17:54Z mueller $ -## -## Revision History: -## Date Rev Version Comment -## 2012-04-09 461 1.0 Initial version -## - -NET "I_CLK100" TNM_NET = "I_CLK100"; -TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; -OFFSET = IN 10 ns BEFORE "I_CLK100"; -OFFSET = OUT 20 ns AFTER "I_CLK100"; - -## std board -## -#include "bplib/nexys3/nexys3_pins.ucf" -## -## FX2 interface -## -#include "bplib/nexys3/nexys3_pins_fx2.ucf" -#include "bplib/nexys3/nexys3_time_fx2_ic.ucf" Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile (nonexistent) @@ -1,30 +0,0 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ -# -# Revision History: -# Date Rev Version Comment -# 2012-04-09 461 1.0 Initial version -# -# -VBOM_all = $(wildcard *.vbom) -BIT_all = $(VBOM_all:.vbom=.bit) -# -include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk -FX2_FILE = nexys3_jtag_3fifo_ic.ihx -# -.PHONY : all clean -# -all : $(BIT_all) -# -clean : ise_clean - rm -f $(VBOM_all:.vbom=.ucf) -# -#---- -# -include ${RETROBASE}/rtl/make_ise/generic_xflow.mk -include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk -# -ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) -include $(VBOM_all:.vbom=.dep_ghdl) -endif -# Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom (nonexistent) @@ -1,8 +0,0 @@ -# conf -sys_conf = sys_conf.vhd -# libs -# components -# design -../sys_tst_fx2loop_n3.vbom -@ucf_cpp: sys_tst_fx2loop_ic3_n3.ucf -@top: sys_tst_fx2loop_n3 Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd (nonexistent) @@ -1,63 +0,0 @@ --- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2012-2013 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Package Name: sys_conf --- Description: Definitions for sys_tst_fx2loop_ic3_n3 (for synthesis) --- --- Dependencies: - --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- Revision History: --- Date Rev Version Comment --- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect --- 2012-04-25 510 1.1 use 3/2 clock-> 150 MHz sysclk --- 2012-04-09 461 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.slvtypes.all; - -package sys_conf is - - constant sys_conf_clksys_vcodivide : positive := 2; - constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz - constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz - constant sys_conf_clksys_gentype : string := "DCM"; - - constant sys_conf_fx2_type : string := "ic3"; - - -- dummy values defs for generic parameters of as controller - constant sys_conf_fx2_rdpwldelay : positive := 1; - constant sys_conf_fx2_rdpwhdelay : positive := 1; - constant sys_conf_fx2_wrpwldelay : positive := 1; - constant sys_conf_fx2_wrpwhdelay : positive := 1; - constant sys_conf_fx2_flagdelay : positive := 1; - - -- pktend timer setting - -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) - constant sys_conf_fx2_petowidth : positive := 10; - - constant sys_conf_fx2_ccwidth : positive := 5; - - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - - -- derived constants - - constant sys_conf_clksys : integer := - ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / - sys_conf_clksys_outdivide; - constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; - -end package sys_conf; Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3 =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3 (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3 (nonexistent)

w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3 Property changes : Deleted: svn:ignore ## -1,43 +0,0 ## -*.gz -*.tar -*.tgz -*.dep_* -work-obj93.cf -*.vcd -*.ghw -*.sav -*.tmp -*.exe -ise -xflow.his -*.ngc -*.ncd -*.pcf -*.bit -*.msk -*.svf -*.log -isim -*_[sfot]sim.vhd -*_tsim.sdf -rlink_cext_fifo_[rt]x -rlink_cext_conf -tmu_ofile -*.dsk -*.tap -*.lst -*.cof -.Xil -project_mflow -xsim.dir -webtalk_* -*_[sfot]sim -*_[IX]Sim -*_[IX]Sim_[sfot]sim -*.dcp -*.jou -*.pb -*.prj -*.rpt -*.wdb -sys_tst_fx2loop_ic3_n3.ucf Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd (nonexistent) @@ -1,330 +0,0 @@ --- $Id: sys_tst_fx2loop_n3.vhd 638 2015-01-25 22:01:38Z mueller $ --- --- Copyright 2012-2015 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: sys_tst_fx2loop_n3 - syn --- Description: test of Cypress EZ-USB FX2 controller --- --- Dependencies: vlib/xlib/s6_cmt_sfs --- vlib/genlib/clkdivce --- bpgen/sn_humanio --- tst_fx2loop_hiomap --- tst_fx2loop --- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"] --- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"] --- bplib/nxcramlib/nx_cram_dummy --- --- Test bench: - --- --- Target Devices: generic --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz --- 2013-04-25 510 14.5 P58f xc6slx16-2 416 516 68 199 p 5.3 ic3/150 --- 2013-04-24 510 13.3 O76d xc6slx16-2 417 674 68 228 p 5.3 ic3/175 --- 2012-04-09 461 13.3 O76d xc6slx16-2 429 620 48 232 p 7.2 ic3/100 --- --- 2013-04-25 510 14.5 P58f xc6slx16-2 349 427 48 163 p 5.4 ic2/150 --- 2013-04-24 510 13.3 O76d xc6slx16-2 355 569 48 208 p 5.4 ic2/175 --- 2012-04-09 461 13.3 O76d xc6slx16-2 347 499 32 175 p 7.9 ic2/100 --- --- 2013-04-24 510 13.3 O76d xc6slx16-2 299 486 32 175 p FAIL as2/100 --- 2012-04-09 461 13.3 O76d xc6slx16-2 299 460 32 164 p FAIL as2/100 --- --- Revision History: --- Date Rev Version Comment --- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect --- 2013-04-24 510 1.0.1 CLKDIV.CDUWIDTH now 8, support >127 sysclk --- 2012-04-09 461 1.0 Initial version (derived from sys_tst_fx2loop_n2) ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; -use work.xlib.all; -use work.genlib.all; -use work.bpgenlib.all; -use work.tst_fx2looplib.all; -use work.fx2lib.all; -use work.nxcramlib.all; -use work.sys_conf.all; - --- ---------------------------------------------------------------------------- - -entity sys_tst_fx2loop_n3 is -- top level - -- implements nexys3_aif + fx2 pins - port ( - I_CLK100 : in slbit; -- 100 MHz clock - I_RXD : in slbit; -- receive data (board view) - O_TXD : out slbit; -- transmit data (board view) - I_SWI : in slv8; -- n3 switches - I_BTN : in slv5; -- n3 buttons - O_LED : out slv8; -- n3 leds - O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) - O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) - O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) - O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) - O_MEM_WE_N : out slbit; -- cram: write enable (act.low) - O_MEM_OE_N : out slbit; -- cram: output enable (act.low) - O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) - O_MEM_CLK : out slbit; -- cram: clock - O_MEM_CRE : out slbit; -- cram: command register enable - I_MEM_WAIT : in slbit; -- cram: mem wait - O_MEM_ADDR : out slv23; -- cram: address lines - IO_MEM_DATA : inout slv16; -- cram: data lines - O_PPCM_CE_N : out slbit; -- ppcm: ... - O_PPCM_RST_N : out slbit; -- ppcm: ... - I_FX2_IFCLK : in slbit; -- fx2: interface clock - O_FX2_FIFO : out slv2; -- fx2: fifo address - I_FX2_FLAG : in slv4; -- fx2: fifo flags - O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) - O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) - O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) - O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) - IO_FX2_DATA : inout slv8 -- fx2: data lines - ); -end sys_tst_fx2loop_n3; - -architecture syn of sys_tst_fx2loop_n3 is - - signal CLK : slbit := '0'; - signal RESET : slbit := '0'; - - signal CE_USEC : slbit := '0'; - signal CE_MSEC : slbit := '0'; - - signal SWI : slv8 := (others=>'0'); - signal BTN : slv5 := (others=>'0'); - signal LED : slv8 := (others=>'0'); - signal DSP_DAT : slv16 := (others=>'0'); - signal DSP_DP : slv4 := (others=>'0'); - - signal LED_MAP : slv8 := (others=>'0'); - - signal HIO_CNTL : hio_cntl_type := hio_cntl_init; - signal HIO_STAT : hio_stat_type := hio_stat_init; - - signal FX2_RXDATA : slv8 := (others=>'0'); - signal FX2_RXVAL : slbit := '0'; - signal FX2_RXHOLD : slbit := '0'; - signal FX2_RXAEMPTY : slbit := '0'; - signal FX2_TXDATA : slv8 := (others=>'0'); - signal FX2_TXENA : slbit := '0'; - signal FX2_TXBUSY : slbit := '0'; - signal FX2_TXAFULL : slbit := '0'; - signal FX2_TX2DATA : slv8 := (others=>'0'); - signal FX2_TX2ENA : slbit := '0'; - signal FX2_TX2BUSY : slbit := '1'; - signal FX2_TX2AFULL : slbit := '0'; - signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; - -begin - - assert (sys_conf_clksys mod 1000000) = 0 - report "assert sys_conf_clksys on MHz grid" - severity failure; - - GEN_CLKSYS : s6_cmt_sfs - generic map ( - VCO_DIVIDE => sys_conf_clksys_vcodivide, - VCO_MULTIPLY => sys_conf_clksys_vcomultiply, - OUT_DIVIDE => sys_conf_clksys_outdivide, - CLKIN_PERIOD => 10.0, - CLKIN_JITTER => 0.01, - STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) - port map ( - CLKIN => I_CLK100, - CLKFX => CLK, - LOCKED => open - ); - - CLKDIV : clkdivce - generic map ( - CDUWIDTH => 8, -- good for up to 255 MHz ! - USECDIV => sys_conf_clksys_mhz, - MSECDIV => 1000) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC - ); - - HIO : sn_humanio - generic map ( - BWIDTH => 5, - DEBOUNCE => sys_conf_hio_debounce) - port map ( - CLK => CLK, - RESET => '0', - CE_MSEC => CE_MSEC, - SWI => SWI, - BTN => BTN, - LED => LED, - DSP_DAT => DSP_DAT, - DSP_DP => DSP_DP, - I_SWI => I_SWI, - I_BTN => I_BTN, - O_LED => O_LED, - O_ANO_N => O_ANO_N, - O_SEG_N => O_SEG_N - ); - - RESET <= BTN(0); -- BTN(0) will reset tester !! - - HIOMAP : tst_fx2loop_hiomap - port map ( - CLK => CLK, - RESET => RESET, - HIO_CNTL => HIO_CNTL, - HIO_STAT => HIO_STAT, - FX2_MONI => FX2_MONI, - SWI => SWI, - BTN => BTN(3 downto 0), - LED => LED_MAP, - DSP_DAT => DSP_DAT, - DSP_DP => DSP_DP - ); - - proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA, - FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL) - begin - - if SWI(4) = '1' then - LED(7) <= '0'; - LED(6) <= '0'; - LED(5) <= FX2_TX2BUSY; - LED(4) <= FX2_TX2ENA; - LED(3) <= FX2_TXBUSY; - LED(2) <= FX2_TXENA; - LED(1) <= FX2_RXHOLD; - LED(0) <= FX2_RXVAL; - else - LED <= LED_MAP; - end if; - - end process proc_led; - - - TST : tst_fx2loop - port map ( - CLK => CLK, - RESET => RESET, - CE_MSEC => CE_MSEC, - HIO_CNTL => HIO_CNTL, - HIO_STAT => HIO_STAT, - FX2_MONI => FX2_MONI, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TX2DATA => FX2_TX2DATA, - TX2ENA => FX2_TX2ENA, - TX2BUSY => FX2_TX2BUSY - ); - - FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate - CNTL : fx2_2fifoctl_ic - generic map ( - RXFAWIDTH => 5, - TXFAWIDTH => 5, - PETOWIDTH => sys_conf_fx2_petowidth, - CCWIDTH => sys_conf_fx2_ccwidth, - RXAEMPTY_THRES => 1, - TXAFULL_THRES => 1) - port map ( - CLK => CLK, - RESET => RESET, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - RXAEMPTY => FX2_RXAEMPTY, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TXAFULL => FX2_TXAFULL, - MONI => FX2_MONI, - I_FX2_IFCLK => I_FX2_IFCLK, - O_FX2_FIFO => O_FX2_FIFO, - I_FX2_FLAG => I_FX2_FLAG, - O_FX2_SLRD_N => O_FX2_SLRD_N, - O_FX2_SLWR_N => O_FX2_SLWR_N, - O_FX2_SLOE_N => O_FX2_SLOE_N, - O_FX2_PKTEND_N => O_FX2_PKTEND_N, - IO_FX2_DATA => IO_FX2_DATA - ); - end generate FX2_CNTL_IC; - - FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate - CNTL : fx2_3fifoctl_ic - generic map ( - RXFAWIDTH => 5, - TXFAWIDTH => 5, - PETOWIDTH => sys_conf_fx2_petowidth, - CCWIDTH => sys_conf_fx2_ccwidth, - RXAEMPTY_THRES => 1, - TXAFULL_THRES => 1, - TX2AFULL_THRES => 1) - port map ( - CLK => CLK, - RESET => RESET, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - RXAEMPTY => FX2_RXAEMPTY, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TXAFULL => FX2_TXAFULL, - TX2DATA => FX2_TX2DATA, - TX2ENA => FX2_TX2ENA, - TX2BUSY => FX2_TX2BUSY, - TX2AFULL => FX2_TX2AFULL, - MONI => FX2_MONI, - I_FX2_IFCLK => I_FX2_IFCLK, - O_FX2_FIFO => O_FX2_FIFO, - I_FX2_FLAG => I_FX2_FLAG, - O_FX2_SLRD_N => O_FX2_SLRD_N, - O_FX2_SLWR_N => O_FX2_SLWR_N, - O_FX2_SLOE_N => O_FX2_SLOE_N, - O_FX2_PKTEND_N => O_FX2_PKTEND_N, - IO_FX2_DATA => IO_FX2_DATA - ); - end generate FX2_CNTL_IC3; - - SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy - port map ( - O_MEM_CE_N => O_MEM_CE_N, - O_MEM_BE_N => O_MEM_BE_N, - O_MEM_WE_N => O_MEM_WE_N, - O_MEM_OE_N => O_MEM_OE_N, - O_MEM_ADV_N => O_MEM_ADV_N, - O_MEM_CLK => O_MEM_CLK, - O_MEM_CRE => O_MEM_CRE, - I_MEM_WAIT => I_MEM_WAIT, - O_MEM_ADDR => O_MEM_ADDR, - IO_MEM_DATA => IO_MEM_DATA - ); - - O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled - O_PPCM_RST_N <= '1'; -- - - O_TXD <= I_RXD; -- loop-back in serial port... - -end syn; - Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom (nonexistent) @@ -1,28 +0,0 @@ -# this is the vbom for the 'generic' top level entity -# to be referenced in the vbom's of the specific systems -# ./ic/sys_tst_fx2loop_ic_n3 -# ./ic3/sys_tst_fx2loop_ic3_n3 -# -# libs -../../../vlib/slvtypes.vhd -../../../vlib/xlib/xlib.vhd -../../../vlib/genlib/genlib.vhd -../../../bplib/bpgen/bpgenlib.vbom -../tst_fx2looplib.vbom -../../../bplib/fx2lib/fx2lib.vhd -../../../bplib/nxcramlib/nxcramlib.vhd -${sys_conf} -# components -[xst,vsyn]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom -[ghdl,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom -../../../vlib/genlib/clkdivce.vbom -../../../bplib/bpgen/sn_humanio.vbom -../tst_fx2loop_hiomap.vbom -../tst_fx2loop.vbom -../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom -../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom -../../../bplib/nxcramlib/nx_cram_dummy.vbom -# design -sys_tst_fx2loop_n3.vhd -## no @ucf_cpp - Index: w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3 =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3 (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3 (nonexistent)

w11/trunk/rtl/sys_gen/tst_fx2loop/nexys3 Property changes : Deleted: svn:ignore ## -1,42 +0,0 ## -*.gz -*.tar -*.tgz -*.dep_* -work-obj93.cf -*.vcd -*.ghw -*.sav -*.tmp -*.exe -ise -xflow.his -*.ngc -*.ncd -*.pcf -*.bit -*.msk -*.svf -*.log -isim -*_[sfot]sim.vhd -*_tsim.sdf -rlink_cext_fifo_[rt]x -rlink_cext_conf -tmu_ofile -*.dsk -*.tap -*.lst -*.cof -.Xil -project_mflow -xsim.dir -webtalk_* -*_[sfot]sim -*_[IX]Sim -*_[IX]Sim_[sfot]sim -*.dcp -*.jou -*.pb -*.prj -*.rpt -*.wdb Index: w11/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd (nonexistent) @@ -1,109 +0,0 @@ --- $Id: tst_fx2looplib.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2011-2012 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Package Name: tst_fx2looplib --- Description: Definitions for tst_fx2loop records and helpers --- --- Dependencies: - --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- Revision History: --- Date Rev Version Comment --- 2012-01-15 453 1.1 drop pecnt, add rxhold,(tx|tx2)busy in hio_stat --- 2011-12-26 445 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.slvtypes.all; -use work.fx2lib.all; - -package tst_fx2looplib is - - constant c_ctltyp_2fifo_as : integer := 0; -- fx2ctl type: 2fifo_as - constant c_ctltyp_2fifo_ic : integer := 1; -- fx2ctl type: 2fifo_ic - constant c_ctltyp_3fifo_ic : integer := 2; -- fx2ctl type: 3fifo_ic - - constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity) - constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity) - constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx) - constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back) - - type hio_cntl_type is record -- humanio controls - mode : slv2; -- mode (idle,(tx|tx)blast,loop) - tx2blast : slbit; -- enable tx2 blast - throttle : slbit; -- enable 1 msec tx throttling - end record hio_cntl_type; - - constant hio_cntl_init : hio_cntl_type := ( - c_mode_idle, -- mode - '0','0' -- tx2blast,throttle - ); - - type hio_stat_type is record -- humanio status - rxhold : slbit; -- rx hold - txbusy : slbit; -- tx busy - tx2busy : slbit; -- tx2 busy - rxsecnt : slv16; -- rx sequence error counter - rxcnt : slv32; -- rx word counter - txcnt : slv32; -- tx word counter - tx2cnt : slv32; -- tx2 word counter - end record hio_stat_type; - - constant hio_stat_init : hio_stat_type := ( - '0','0','0', -- rxhold,txbusy,tx2busy - (others=>'0'), -- rxsecnt - (others=>'0'), -- rxcnt - (others=>'0'), -- txcnt - (others=>'0') -- tx2cnt - ); - --- ------------------------------------- - -component tst_fx2loop is -- tester for serport components - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - CE_MSEC : in slbit; -- msec pulse - HIO_CNTL : in hio_cntl_type; -- humanio controls - HIO_STAT : out hio_stat_type; -- humanio status - FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor - RXDATA : in slv8; -- receiver data out - RXVAL : in slbit; -- receiver data valid - RXHOLD : out slbit; -- receiver data hold - TXDATA : out slv8; -- transmit data in - TXENA : out slbit; -- transmit data enable - TXBUSY : in slbit; -- transmit busy - TX2DATA : out slv8; -- transmit 2 data in - TX2ENA : out slbit; -- transmit 2 data enable - TX2BUSY : in slbit -- transmit 2 busy - ); -end component; - -component tst_fx2loop_hiomap is -- default human I/O mapper - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - HIO_CNTL : out hio_cntl_type; -- tester controls from hio - HIO_STAT : in hio_stat_type; -- tester status to display by hio - FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio - SWI : in slv8; -- switch settings - BTN : in slv4; -- button settings - LED : out slv8; -- led data - DSP_DAT : out slv16; -- display data - DSP_DP : out slv4 -- display decimal points - ); -end component; - -end package tst_fx2looplib; Index: w11/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vbom =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vbom (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vbom (nonexistent) @@ -1,4 +0,0 @@ -# libs -../../vlib/slvtypes.vhd -../../bplib/fx2lib/fx2lib.vhd -tst_fx2looplib.vhd Index: w11/trunk/rtl/sys_gen/tst_fx2loop/.cvsignore =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/.cvsignore (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/.cvsignore (nonexistent) @@ -1,2 +0,0 @@ -tst_fx2loop -tst_fx2loop_si Index: w11/trunk/rtl/sys_gen/tst_fx2loop/Makefile =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/Makefile (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/Makefile (nonexistent) @@ -1,41 +0,0 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ -# -# Revision History: -# Date Rev Version Comment -# 2014-11-08 602 1.3 rename realclean->distclean -# 2013-01-05 470 1.2 fix LDLIBS (must come after objs) -# 2012-02-26 458 1.1 add tst_fx2loop_si -# 2011-12-26 445 1.0 Initial version -# -VBOM_all = $(wildcard *.vbom) -NGC_all = $(VBOM_all:.vbom=.ngc) -# -include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk -# -.PHONY : all clean distclean -# -all : tst_fx2loop tst_fx2loop_si -# -clean : ise_clean - rm -f tst_fx2loop - rm -f tst_fx2loop_si -# -distclean : - rm -f tst_fx2loop tst_fx2loop_si -# -CFLAGS = -Wall -O2 -g -LDLIBS = -lusb-1.0 -# -tst_fx2loop : tst_fx2loop.c - ${CC} ${CFLAGS} -o tst_fx2loop tst_fx2loop.c ${LDLIBS} -tst_fx2loop_si : tst_fx2loop_si.c - ${CC} ${CFLAGS} -o tst_fx2loop_si tst_fx2loop_si.c ${LDLIBS} -# -#---- -# -include ${RETROBASE}/rtl/make_ise/generic_xflow.mk -# -ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) -endif -# Index: w11/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd (nonexistent) @@ -1,194 +0,0 @@ --- $Id: tst_fx2loop_hiomap.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2011-2012 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: tst_fx2loop_hiomap - syn --- Description: default human I/O mapper --- --- Dependencies: - --- Test bench: - --- --- Target Devices: generic --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- --- Revision History: --- Date Rev Version Comment --- 2012-01-15 453 1.0.2 re-arrange DP,DSP usage --- 2012-01-03 449 1.0.1 use new fx2ctl_moni layout --- 2011-12-26 445 1.0 Initial version ------------------------------------------------------------------------------- --- --- Usage of Switches, Buttons, LEDs: --- --- BTN(3) -- unused -- --- (2) -- unused -- --- (1) -- unused -- --- (0) reset state [!! decoded by top level design !!] --- --- SWI(7:5) select display --- (4) -- unused -- --- (3) throttle --- (2) tx2blast --- (1:0) mode 00 idle --- 01 rxblast --- 10 txblast --- 11 loop --- --- LED(7) MONI.fifo_ep4 --- (6) MONI.fifo_ep6 --- (5) MONI.fifo_ep8 --- (4) MONI.flag_ep4_empty --- (3) MONI.flag_ep4_almost --- (2) MONI.flag_ep6_full --- (1) MONI.flag_ep6_almost --- (0) rxsecnt > 0 (sequence error) --- --- DSP data as selected by SWI(7:5) --- 000 -> rxsecnt --- 001 -> -- unused -- (display ffff) --- 010 -> rxcnt.l --- 011 -> rxcnt.h --- 100 -> txcnt.l --- 101 -> txcnt.h --- 110 -> tx2cnt.l --- 111 -> tx2cnt.h --- --- DP(3) FX2_TXBUSY (shows tx back preasure) --- (2) FX2_MONI.slwr (shows tx activity) --- (1) FX2_RXHOLD (shows rx back preasure) --- (0) FX2_MONI.slrd (shows rx activity) --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; -use work.fx2lib.all; -use work.tst_fx2looplib.all; - --- ---------------------------------------------------------------------------- - -entity tst_fx2loop_hiomap is -- default human I/O mapper - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - HIO_CNTL : out hio_cntl_type; -- tester controls from hio - HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio - FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio - SWI : in slv8; -- switch settings - BTN : in slv4; -- button settings - LED : out slv8; -- led data - DSP_DAT : out slv16; -- display data - DSP_DP : out slv4 -- display decimal points - ); -end tst_fx2loop_hiomap; - -architecture syn of tst_fx2loop_hiomap is - - type regs_type is record - dspdat : slv16; -- display data - dummy : slbit; -- - end record regs_type; - - constant regs_init : regs_type := ( - (others=>'0'), -- dspdat - '0' - ); - - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - -begin - - proc_regs: process (CLK) - begin - - if rising_edge(CLK) then - if RESET = '1' then - R_REGS <= regs_init; - else - R_REGS <= N_REGS; - end if; - end if; - - end process proc_regs; - - proc_next: process (R_REGS, HIO_STAT, FX2_MONI, SWI, BTN) - - variable r : regs_type := regs_init; - variable n : regs_type := regs_init; - - variable icntl : hio_cntl_type := hio_cntl_init; - variable iled : slv8 := (others=>'0'); - variable idat : slv16 := (others=>'0'); - variable idp : slv4 := (others=>'0'); - - begin - - r := R_REGS; - n := R_REGS; - - icntl := hio_cntl_init; - iled := (others=>'0'); - idat := (others=>'0'); - idp := (others=>'0'); - - -- setup tester controls - - icntl.mode := SWI(1 downto 0); - icntl.tx2blast := SWI(2); - icntl.throttle := SWI(3); - - -- setup leds - iled(7) := FX2_MONI.fifo_ep4; - iled(6) := FX2_MONI.fifo_ep6; - iled(5) := FX2_MONI.fifo_ep8; - iled(4) := FX2_MONI.flag_ep4_empty; - iled(3) := FX2_MONI.flag_ep4_almost; - iled(2) := FX2_MONI.flag_ep6_full; - iled(1) := FX2_MONI.flag_ep6_almost; - if unsigned(HIO_STAT.rxsecnt) > 0 then iled(0) := '1'; end if; - - -- setup display data - - case SWI(7 downto 5) is - when "000" => idat := HIO_STAT.rxsecnt; - when "001" => idat := (others=>'1'); - when "010" => idat := HIO_STAT.rxcnt(15 downto 0); - when "011" => idat := HIO_STAT.rxcnt(31 downto 16); - when "100" => idat := HIO_STAT.txcnt(15 downto 0); - when "101" => idat := HIO_STAT.txcnt(31 downto 16); - when "110" => idat := HIO_STAT.tx2cnt(15 downto 0); - when "111" => idat := HIO_STAT.tx2cnt(31 downto 16); - when others => null; - end case; - n.dspdat := idat; - - -- setup display decimal points - - idp(3) := HIO_STAT.txbusy; -- tx back preasure - idp(2) := FX2_MONI.slwr; -- tx activity - idp(1) := HIO_STAT.rxhold; -- rx back preasure - idp(0) := FX2_MONI.slrd; -- rx activity - - N_REGS <= n; - - HIO_CNTL <= icntl; - LED <= iled; - DSP_DAT <= r.dspdat; - DSP_DP <= idp; - - end process proc_next; - -end syn; Index: w11/trunk/rtl/sys_gen/tst_fx2loop =================================================================== --- w11/trunk/rtl/sys_gen/tst_fx2loop (revision 35) +++ w11/trunk/rtl/sys_gen/tst_fx2loop (nonexistent)

w11/trunk/rtl/sys_gen/tst_fx2loop Property changes : Deleted: svn:ignore ## -1,44 +0,0 ## -*.gz -*.tar -*.tgz -*.dep_* -work-obj93.cf -*.vcd -*.ghw -*.sav -*.tmp -*.exe -ise -xflow.his -*.ngc -*.ncd -*.pcf -*.bit -*.msk -*.svf -*.log -isim -*_[sfot]sim.vhd -*_tsim.sdf -rlink_cext_fifo_[rt]x -rlink_cext_conf -tmu_ofile -*.dsk -*.tap -*.lst -*.cof -.Xil -project_mflow -xsim.dir -webtalk_* -*_[sfot]sim -*_[IX]Sim -*_[IX]Sim_[sfot]sim -*.dcp -*.jou -*.pb -*.prj -*.rpt -*.wdb -tst_fx2loop -tst_fx2loop_si Index: w11/trunk/rtl/sys_gen/tst_rlink/Makefile =================================================================== --- w11/trunk/rtl/sys_gen/tst_rlink/Makefile (revision 35) +++ w11/trunk/rtl/sys_gen/tst_rlink/Makefile (nonexistent) @@ -1,26 +0,0 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ -# -# Revision History: -# Date Rev Version Comment -# 2011-12-11 438 1.0 Initial version -# -VBOM_all = $(wildcard *.vbom) -NGC_all = $(VBOM_all:.vbom=.ngc) -# -include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk -# -.PHONY : all clean -# -all : $(NGC_all) -# -clean : ise_clean -# -# -#---- -# -include ${RETROBASE}/rtl/make_ise/generic_xflow.mk -# -ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) -endif -# Index: w11/trunk/rtl/sys_gen/tst_rlink/arty/sys_conf.vhd =================================================================== --- w11/trunk/rtl/sys_gen/tst_rlink/arty/sys_conf.vhd (revision 35) +++ w11/trunk/rtl/sys_gen/tst_rlink/arty/sys_conf.vhd (revision 36) @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 743 2016-03-13 16:42:31Z mueller $ +-- $Id: sys_conf.vhd 754 2016-03-28 12:26:13Z mueller $ -- -- Copyright 2016- by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: viv 2015.4; ghdl 0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-28 754 1.2 run at 120 MHz -- 2016-03-12 741 1.1 add sysmon_rbus -- 2016-02-16 731 1.0 Initial version ------------------------------------------------------------------------------ @@ -32,8 +33,8 @@ -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; - constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz - constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz constant sys_conf_clksys_gentype : string := "MMCM"; -- configure rlink and hio interfaces --------------------------------------

/w11/trunk/rtl/sys_gen/tst_rlink/arty/tb/sys_conf_sim.vhd

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/w11/trunk/rtl/sys_gen/tst_rlink/arty/tb/Makefile

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/w11/trunk/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vmfset

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/w11/trunk/rtl/sys_gen/tst_rlink/basys3/tb/sys_conf_sim.vhd

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/w11/trunk/rtl/sys_gen/tst_rlink/basys3/tb/Makefile

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/w11/trunk/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vmfset

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/w11/trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.mfset File deleted \ No newline at end of file

/w11/trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd

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/w11/trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.imfset

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/w11/trunk/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd

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/w11/trunk/rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd

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/w11/trunk/rtl/sys_gen/tst_rlink/nexys4/tb/sys_conf_sim.vhd

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/w11/trunk/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile

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/w11/trunk/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd

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/w11/trunk/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vbom

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/w11/trunk/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vmfset

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/w11/trunk/rtl/sys_gen/tst_rlink/nexys4/Makefile

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/w11/trunk/rtl/sys_gen/tst_rlink/Makefile.ise

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/w11/trunk/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd

1,4 → 1,4

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/w11/trunk/rtl/sys_gen/w11a/arty_bram/sys_conf.vhd

1,4 → 1,4

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/w11/trunk/rtl/sys_gen/w11a/arty_bram/tb/sys_conf_sim.vhd

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/w11/trunk/rtl/sys_gen/w11a/arty_bram/tb/Makefile

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/w11/trunk/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd

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/w11/trunk/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom

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/w11/trunk/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset

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/w11/trunk/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd

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/w11/trunk/rtl/sys_gen/w11a/basys3/tb/Makefile

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/w11/trunk/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd

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/w11/trunk/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom

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/w11/trunk/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset

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/w11/trunk/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.mfset File deleted \ No newline at end of file

/w11/trunk/rtl/sys_gen/w11a/nexys2/sys_conf.vhd

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/w11/trunk/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd

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/w11/trunk/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd

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/w11/trunk/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.imfset

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/w11/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.mfset File deleted

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/w11/trunk/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd

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/w11/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.imfset

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/w11/trunk/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd

1,4 → 1,4

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/w11/trunk/rtl/sys_gen/w11a/nexys4/tb/Makefile

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/w11/trunk/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom

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/w11/trunk/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset

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/w11/trunk/rtl/sys_gen/w11a/s3board/sys_w11a_s3.mfset File deleted

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/w11/trunk/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd

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/w11/trunk/rtl/sys_gen/tst_snhumanio/Makefile File deleted

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/w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/.cvsignore File deleted

/w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile File deleted

/w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_conf.vhd File deleted

/w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.mfset File deleted

/w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.ucf_cpp File deleted

/w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.vbom File deleted

/w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3

w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3 Property changes : Deleted: svn:ignore ## -1,43 +0,0 ## -*.gz -*.tar -*.tgz -*.dep_* -work-obj93.cf -*.vcd -*.ghw -*.sav -*.tmp -*.exe -ise -xflow.his -*.ngc -*.ncd -*.pcf -*.bit -*.msk -*.svf -*.log -isim -*_[sfot]sim.vhd -*_tsim.sdf -rlink_cext_fifo_[rt]x -rlink_cext_conf -tmu_ofile -*.dsk -*.tap -*.lst -*.cof -.Xil -project_mflow -xsim.dir -webtalk_* -*_[sfot]sim -*_[IX]Sim -*_[IX]Sim_[sfot]sim -*.dcp -*.jou -*.pb -*.prj -*.rpt -*.wdb -sys_tst_rlink_cuff_ic3_n2.ucf Index: w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.mfset =================================================================== --- w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.mfset (revision 35) +++ w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.mfset (nonexistent) @@ -1,104 +0,0 @@ -# $Id: sys_tst_rlink_cuff_ic_n2.mfset 466 2012-12-30 13:26:55Z mueller $ -# -# ---------------------------------------------------------------------------- -[xst] -INFO:.*Mux is complete : default of case is discarded - -Register in unit has a constant value -Register in unit has a constant value -Register in unit has a constant value -Register in unit has a constant value -Register in unit has a constant value -Register in unit has a constant value - -Unconnected output port 'SIZE' of component 'fifo_1c_dram' -Unconnected output port 'LOCKED' of component 'dcm_sfs' -Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' -Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen' -Unconnected output port 'RL_MONI' of component 'rlink_core8' - -Input is never used -Input > is never used -Input is never used -Input is never used -Input > is never used -Input > is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used - -Output is never assigned - -Signal > is assigned but never used -Signal is assigned but never used -Signal > is assigned but never used -Signal > is assigned but never used -Signal is assigned but never used -Signal is assigned but never used -Signal is assigned but never used -Signal > is assigned but never used -Signal > is assigned but never used -Signal is assigned but never used -Signal is assigned but never used -Signal is assigned but never used -Signal is assigned but never used -Signal is assigned but never used - -Signal is used but never assigned -Signal is used but never assigned -Signal is used but never assigned - -Signal is never used or assigned - -FF/Latch in Unit is equivalent - -FF/Latch has a constant value of 0 -FF/Latch has a constant value of 0 -FF/Latch has a constant value of 0 -FF/Latch has a constant value of 0 -FF/Latch has a constant value of 0 - -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected - -Node of sequential type is unconnected -# -# ---------------------------------------------------------------------------- -[tra] - -# -# ---------------------------------------------------------------------------- -[map] -The signal is incomplete -Signal I_FX2_FLAG<3> connected to top level port I_FX2_FLAG<3> has been removed -INFO:.* - -# -# ---------------------------------------------------------------------------- -[par] -The signal I_MEM_WAIT_IBUF has no load -There are 1 loadless signals in this design -This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied -# -# ---------------------------------------------------------------------------- -[bgn] -Spartan-3 1200E and 1600E devices do not support bitstream -The signal is incomplete Index: w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.imfset =================================================================== --- w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.imfset (nonexistent) +++ w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.imfset (revision 36) @@ -0,0 +1,104 @@ +# $Id: sys_tst_rlink_cuff_ic_n2.imfset 769 2016-05-28 11:36:22Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Register in unit has a constant value +Register in unit has a constant value +Register in unit has a constant value +Register in unit has a constant value +Register in unit has a constant value +Register in unit has a constant value + +Unconnected output port 'SIZE' of component 'fifo_1c_dram' +Unconnected output port 'LOCKED' of component 'dcm_sfs' +Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' +Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen' +Unconnected output port 'RL_MONI' of component 'rlink_core8' + +Input is never used +Input > is never used +Input is never used +Input is never used +Input > is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used + +Output is never assigned + +Signal > is assigned but never used +Signal is assigned but never used +Signal > is assigned but never used +Signal > is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal > is assigned but never used +Signal > is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +Signal is used but never assigned +Signal is used but never assigned +Signal is used but never assigned + +Signal is never used or assigned + +FF/Latch in Unit is equivalent + +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 + +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected + +Node of sequential type is unconnected +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +The signal is incomplete +Signal I_FX2_FLAG<3> connected to top level port I_FX2_FLAG<3> has been removed +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +The signal I_MEM_WAIT_IBUF has no load +There are 1 loadless signals in this design +This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied +# +# ---------------------------------------------------------------------------- +[bgn] +Spartan-3 1200E and 1600E devices do not support bitstream +The signal is incomplete Index: w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.mfset =================================================================== --- w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.mfset (revision 35) +++ w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.mfset (nonexistent) @@ -1,100 +0,0 @@ -# $Id: sys_tst_rlink_cuff_ic_n3.mfset 472 2013-01-06 14:39:10Z mueller $ -# -# ---------------------------------------------------------------------------- -[xst] -Case statement is complete. others clause is never selected -Using initial value '0' for reset since it is never assigned -Using initial value '0' for fx2_tx2ena_l since it is never assigned - -Net does not have a driver. - -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected or connected -Output port of the instance is unconnected or connected -Output port of the instance is unconnected - -Signal is used but never assigned - -Signal 'FX2_TX2BUSY', unconnected in block 'sys_tst_rlink_cuff_n3' - -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -ode of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected - -Input is never used -Input > is never used -Input is never used -Input > is never used -Input > is never used -Input > is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used - -FF/Latch has a constant value of 0 -FF/Latch has a constant value -FF/Latch has a constant value - -of type RAMB16_S18 has been replaced by RAMB16BWER -of type RAMB16_S36 has been replaced by RAMB16BWER -of type RAMB16_S36_S36 has been replaced by RAMB16BWER - -FF/Latch has a constant value of 0 -FF/Latch has a constant value - -The FF/Latch .* is equivalent -The FF/Latch .* is equivalent -The FF/Latch .* is the opposite - -# -# ---------------------------------------------------------------------------- -[tra] - -# -# ---------------------------------------------------------------------------- -[map] -INFO:.* - -# -# ---------------------------------------------------------------------------- -[par] -The signal I_MEM_WAIT_IBUF has no load -The signal I_FX2_FLAG<3>_IBUF has no load -There are 2 loadless signals in this design - -# -# ---------------------------------------------------------------------------- -[bgn] Index: w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.imfset =================================================================== --- w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.imfset (nonexistent) +++ w11/trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.imfset (revision 36) @@ -0,0 +1,100 @@ +# $Id: sys_tst_rlink_cuff_ic_n3.imfset 769 2016-05-28 11:36:22Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +Case statement is complete. others clause is never selected +Using initial value '0' for reset since it is never assigned +Using initial value '0' for fx2_tx2ena_l since it is never assigned + +Net does not have a driver. + +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected or connected +Output port of the instance is unconnected or connected +Output port of the instance is unconnected + +Signal is used but never assigned + +Signal 'FX2_TX2BUSY', unconnected in block 'sys_tst_rlink_cuff_n3' + +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +ode of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected + +Input is never used +Input > is never used +Input is never used +Input > is never used +Input > is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used + +FF/Latch has a constant value of 0 +FF/Latch has a constant value +FF/Latch has a constant value + +of type RAMB16_S18 has been replaced by RAMB16BWER +of type RAMB16_S36 has been replaced by RAMB16BWER +of type RAMB16_S36_S36 has been replaced by RAMB16BWER + +FF/Latch has a constant value of 0 +FF/Latch has a constant value + +The FF/Latch .* is equivalent +The FF/Latch .* is equivalent +The FF/Latch .* is the opposite + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +The signal I_MEM_WAIT_IBUF has no load +The signal I_FX2_FLAG<3>_IBUF has no load +There are 2 loadless signals in this design + +# +# ---------------------------------------------------------------------------- +[bgn] Index: w11/trunk/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.mfset =================================================================== --- w11/trunk/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.mfset (revision 35) +++ w11/trunk/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.mfset (nonexistent) @@ -1,97 +0,0 @@ -# $Id: sys_tst_rlink_cuff_ic_atlys.mfset 472 2013-01-06 14:39:10Z mueller $ -# -# ---------------------------------------------------------------------------- -[xst] -Case statement is complete. others clause is never selected -Using initial value '0' for reset since it is never assigned -Using initial value '0' for fx2_tx2ena_l since it is never assigned - -Net does not have a driver. - -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected -Output port of the instance is unconnected or connected -Output port of the instance is unconnected or connected -Output port of the instance is unconnected - -Signal is used but never assigned - -Signal 'FX2_TX2BUSY', unconnected in block 'sys_tst_rlink_cuff_atlys' - -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -ode of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected - -Input is never used -Input > is never used -Input > is never used -Input > is never used -Input > is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used - -FF/Latch has a constant value of 0 -FF/Latch has a constant value -FF/Latch has a constant value - -of type RAMB16_S18 has been replaced by RAMB16BWER -of type RAMB16_S36 has been replaced by RAMB16BWER -of type RAMB16_S36_S36 has been replaced by RAMB16BWER - -FF/Latch has a constant value of 0 -FF/Latch has a constant value - -The FF/Latch .* is equivalent -The FF/Latch .* is equivalent - -# -# ---------------------------------------------------------------------------- -[tra] - -# -# ---------------------------------------------------------------------------- -[map] -INFO:.* - -# -# ---------------------------------------------------------------------------- -[par] -The signal I_FX2_FLAG<3>_IBUF has no load -There are 1 loadless signals in this design - -# -# ---------------------------------------------------------------------------- -[bgn] Index: w11/trunk/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.imfset =================================================================== --- w11/trunk/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.imfset (nonexistent) +++ w11/trunk/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.imfset (revision 36) @@ -0,0 +1,97 @@ +# $Id: sys_tst_rlink_cuff_ic_atlys.imfset 769 2016-05-28 11:36:22Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +Case statement is complete. others clause is never selected +Using initial value '0' for reset since it is never assigned +Using initial value '0' for fx2_tx2ena_l since it is never assigned + +Net does not have a driver. + +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected or connected +Output port of the instance is unconnected or connected +Output port of the instance is unconnected + +Signal is used but never assigned + +Signal 'FX2_TX2BUSY', unconnected in block 'sys_tst_rlink_cuff_atlys' + +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node

/w11/trunk/rtl/sys_gen/tst_serloop/Makefile File deleted

/w11/trunk/rtl/sys_gen/tst_serloop/tst_serlooplib.vhd

1,4 → 1,4

16,7 → 16,7

/w11/trunk/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd

1,6 → 1,6

16,8 → 16,8

25,6 → 25,8

38,7 → 40,7

105,7 → 107,7

123,7 → 125,7

450,6 → 452,8

/w11/trunk/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vbom

1,10 → 1,10

/w11/trunk/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop_p0_cts_stim.dat

0,0 → 1,92

/w11/trunk/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom

5,7 → 5,7

/w11/trunk/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom

7,7 → 7,7

/w11/trunk/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom

5,7 → 5,7

/w11/trunk/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vbom

7,6 → 7,8

/w11/trunk/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vmfset

0,0 → 1,35

/w11/trunk/rtl/sys_gen/tst_serloop/nexys4/sys_conf1.vhd

1,6 → 1,6

16,9 → 16,10

29,9 → 30,28

/w11/trunk/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4_ssim.vbom

0,0 → 1,12

/w11/trunk/rtl/sys_gen/tst_serloop/nexys4/tb/tbw.dat

1,6 → 1,6

/w11/trunk/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vhd

1,4 → 1,4

16,6 → 16,7

25,6 → 26,7

36,6 → 38,7

44,6 → 47,8

74,6 → 79,21

93,17 → 113,17

/w11/trunk/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vbom

1,11 → 1,11

/w11/trunk/rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf1_sim.vhd

1,6 → 1,6

16,9 → 16,10

29,15 → 30,30

/w11/trunk/rtl/sys_gen/tst_serloop/nexys4/tb/.cvsignore

1,2 → 1,3

/w11/trunk/rtl/sys_gen/tst_serloop/nexys4/tb/Makefile

1,15 → 1,19

20,13 → 24,13

33,6 → 37,7

/w11/trunk/rtl/sys_gen/tst_serloop/nexys4/tb

w11/trunk/rtl/sys_gen/tst_serloop/nexys4/tb Property changes : Modified: svn:ignore ## -41,4 +41,5 ## *.rpt *.wdb tb_tst_serloop1_n4 +tb_tst_serloop2_n4 tb_tst_serloop_stim Index: w11/trunk/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd =================================================================== --- w11/trunk/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd (revision 35) +++ w11/trunk/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd (revision 36) @@ -1,6 +1,6 @@ --- $Id: sys_tst_serloop1_n4.vhd 646 2015-02-15 12:04:55Z mueller $ +-- $Id: sys_tst_serloop1_n4.vhd 772 2016-06-05 12:55:11Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -13,9 +13,10 @@ -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop1_n4 - syn --- Description: Tester serial link for nexys3 (serport_1clock case) +-- Description: Tester serial link for nexys4 (serport_1clock case) -- --- Dependencies: genlib/clkdivce +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce -- bpgen/bp_rs232_4line_iob -- bpgen/sn_humanio -- tst_serloop_hiomap @@ -25,14 +26,16 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: viv 2014.4; ghdl 0.31 +-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic --- 2015-02-01 641 2014.4 xc7a100t-1 xxx xxxx xx x xxx +-- 2016-03-25 751 2015.4 xc7a100t-1 415 402x 32 0 185 -- -- Revision History: -- Date Rev Version Comment +-- 2016-06-05 772 1.1.1 use CDUWIDTH=7, 120 MHz clock is natural choice +-- 2016-03-27 753 1.1 clock now from cmt and configurable -- 2015-02-06 643 1.1 factor out memory -- 2015-02-01 641 1.0 Initial version (derived from sys_tst_serloop1_n3) ------------------------------------------------------------------------------ @@ -104,13 +107,26 @@ begin - CLK <= I_CLK100; - + GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + CLKDIV : clkdivce generic map ( - CDUWIDTH => 8, - USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20 - MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => sys_conf_clkdiv_msecdiv) port map ( CLK => CLK, CE_USEC => open, @@ -171,7 +187,7 @@ SERPORT : serport_1clock generic map ( - CDWIDTH => 15, + CDWIDTH => 12, CDINIT => sys_conf_uart_cdinit, RXFAWIDTH => 5, TXFAWIDTH => 5)

/w11/trunk/rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd

1,4 → 1,4

19,7 → 19,7

/w11/trunk/rtl/sys_gen/tst_serloop/Makefile.ise

0,0 → 1,30

/w11/trunk/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.mfset File deleted

/w11/trunk/rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom

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/w11/trunk/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.imfset

0,0 → 1,34

/w11/trunk/rtl/sys_gen/tst_serloop/tst_serloop.vhd

1,4 → 1,4

19,7 → 19,7

189,7 → 189,6

235,7 → 234,7

/w11/trunk/rtl/bplib/arty/arty_pins.xdc

1,15 → 1,20

17,6 → 22,7

/w11/trunk/rtl/bplib/arty/tb/tb_arty.vhd

1,4 → 1,4

30,6 → 30,7

81,6 → 82,10

152,7 → 157,7

183,4 → 188,19

/w11/trunk/rtl/bplib/arty/tb/tb_arty.vbom

17,7 → 17,7

/w11/trunk/rtl/bplib/arty/tb/Makefile

1,7 → 1,9

8,17 → 10,25

25,6 → 35,7

/w11/trunk/rtl/bplib/nxcramlib/Makefile File deleted

/w11/trunk/rtl/bplib/nxcramlib/tb/Makefile File deleted

/w11/trunk/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom

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/w11/trunk/rtl/bplib/nxcramlib/tb/Makefile.ise

0,0 → 1,38

/w11/trunk/rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd

1,6 → 1,6

13,7 → 13,7

21,7 → 21,7

31,6 → 31,7

197,8 → 198,8

/w11/trunk/rtl/bplib/nxcramlib/Makefile.ise

0,0 → 1,30

/w11/trunk/rtl/bplib/basys3/tb/tb_basys3.vhd

1,4 → 1,4

26,7 → 26,7

182,6 → 182,12

/w11/trunk/rtl/bplib/basys3/tb/tb_basys3.vbom

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/w11/trunk/rtl/bplib/basys3/basys3_pins.xdc

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/w11/trunk/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom

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/w11/trunk/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom

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/w11/trunk/rtl/bplib/sysmon/sysmon_rbus_core.vhd

1,4 → 1,4

20,10 → 20,12

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/w11/trunk/rtl/bplib/sysmon/sysmonrbuslib.vhd

1,4 → 1,4

19,6 → 19,7

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/w11/trunk/rtl/bplib/sysmon/sysmon_rbus_core.vbom

1,6 → 1,7

/w11/trunk/rtl/bplib/sysmon/Makefile

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/w11/trunk/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom

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/w11/trunk/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom

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/w11/trunk/rtl/bplib/nexys4/nexys4_pins.xdc

1,12 → 1,20

16,6 → 24,7

/w11/trunk/rtl/bplib/nexys4/tb/tb_nexys4.vbom

17,7 → 17,7

/w11/trunk/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom

18,7 → 18,7

/w11/trunk/rtl/bplib/nexys4/tb/Makefile

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8,17 → 10,25

25,6 → 35,7

/w11/trunk/rtl/bplib/bpgen/Makefile File deleted

/w11/trunk/rtl/bplib/bpgen/sn_7segctl.vhd

1,4 → 1,4

100,11 → 100,11

/w11/trunk/rtl/bplib/bpgen/Makefile.ise

0,0 → 1,33

/w11/trunk/rtl/bplib/bpgen/bp_swibtnled.vhd

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22,7 → 22,7

/w11/trunk/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom

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/w11/trunk/rtl/w11a/Makefile File deleted

/w11/trunk/rtl/w11a/pdp11_gpr.vbom

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/w11/trunk/rtl/w11a/pdp11_dmscnt.vbom

5,6 → 5,7

/w11/trunk/rtl/w11a/pdp11_bram_memctl.vhd

1,6 → 1,6

18,10 → 18,12

29,12 → 31,8

42,7 → 40,7

93,8 → 91,8

112,25 → 110,18

/w11/trunk/rtl/w11a/pdp11_core_rbus.vhd

1,6 → 1,6

19,7 → 19,7

27,6 → 27,7

163,8 → 164,8

380,7 → 381,8

/w11/trunk/rtl/w11a/pdp11_vmbox.vhd

1,6 → 1,6

23,10 → 23,11

152,7 → 153,7

/w11/trunk/rtl/w11a/pdp11_sequencer.vbom

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/w11/trunk/rtl/w11a/pdp11_cache.vbom

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/w11/trunk/rtl/w11a/pdp11_dmcmon.vbom

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/w11/trunk/rtl/w11a/pdp11_bram.vbom

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/w11/trunk/rtl/w11a/pdp11_cache.vhd

1,6 → 1,6

18,9 → 18,23

38,6 → 52,8

59,6 → 75,22

69,8 → 101,8

78,21 → 110,21

112,10 → 144,14

123,9 → 159,9

133,7 → 169,7

142,7 → 178,7

152,7 → 188,7

161,7 → 197,7

171,7 → 207,7

180,7 → 216,7

190,7 → 226,7

199,7 → 235,7

229,8 → 265,8

239,7 → 275,7

264,8 → 300,8

279,14 → 315,14

405,32 → 441,32

/w11/trunk/rtl/w11a/tb/tb_pdp11core.vbom

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/w11/trunk/rtl/w11a/tb/tbd_pdp11core.vbom

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/w11/trunk/rtl/w11a/tb/Makefile.ise

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/w11/trunk/rtl/w11a/pdp11_reg70.vhd

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/w11/trunk/rtl/w11a/pdp11_sequencer.vhd

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18,10 → 18,12

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248,9 → 251,12

2395,143 → 2401,148

/w11/trunk/rtl/w11a/pdp11_bram_memctl.vbom

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/w11/trunk/rtl/w11a/pdp11_reg70.vbom

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/w11/trunk/rtl/w11a/Makefile.ise

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/w11/trunk/rtl/w11a/sys_conf.vhd

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16,9 → 16,10

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/w11/trunk/rtl/w11a/pdp11.vhd

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1056,6 → 1056,8

1163,7 → 1165,7

/w11/trunk/rtl/w11a/pdp11_sys70.vhd

1,6 → 1,6

27,10 → 27,11

172,6 → 173,8

/w11/trunk/rtl/w11a/pdp11_ubmap.vbom

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/w11/trunk/rtl/w11a/pdp11_dmscnt.vhd

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19,7 → 19,7

27,6 → 27,7

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/w11/trunk/rtl/w11a/pdp11_mmu_sadr.vbom

5,6 → 5,7

/w11/trunk/rtl/vlib/Makefile File deleted

/w11/trunk/rtl/vlib/rlink/Makefile File deleted

/w11/trunk/rtl/vlib/rlink/rlink_sp2c.vhd

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/w11/trunk/rtl/vlib/rlink/rlinklib.vhd

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16,11 → 16,12

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/w11/trunk/rtl/vlib/rlink/rlink_core.vbom

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/w11/trunk/rtl/vlib/rlink/Makefile.ise

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/w11/trunk/rtl/vlib/rlink/tb/tbu_rlink_sp1c.vbom

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/w11/trunk/rtl/vlib/rlink/tb/Makefile.ise

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/w11/trunk/rtl/vlib/rlink/tb/tbd_rlink_sp1c.vbom

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/w11/trunk/rtl/vlib/rlink/tb/tbd_rlink_direct.vbom

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/w11/trunk/rtl/vlib/rlink/tb/tb_rlink.vbom

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/w11/trunk/rtl/vlib/rlink/rlink_core.vhd

1,6 → 1,6

28,7 → 28,7

39,6 → 39,7

389,9 → 390,9

757,6 → 758,7

/w11/trunk/rtl/vlib/rlink/rlink_sp2c.vbom

0,0 → 1,13

/w11/trunk/rtl/vlib/rlink/tbcore/rlink_cext_iface_dpi.sv

1,4 → 1,4

20,13 → 20,16

46,18 → 49,17

64,8 → 66,9

/w11/trunk/rtl/vlib/simlib/simlib.vhd

1,6 → 1,6

18,10 → 18,11

206,6 → 207,11

1162,11 → 1168,11

1173,15 → 1179,26

/w11/trunk/rtl/vlib/genlib/cdc_pulse.vbom File deleted

/w11/trunk/rtl/vlib/genlib/cdc_pulse.vhd File deleted

/w11/trunk/rtl/vlib/genlib/Makefile File deleted

/w11/trunk/rtl/vlib/genlib/gray_cnt_gen.vhd

1,4 → 1,4

18,7 → 18,7

/w11/trunk/rtl/vlib/genlib/genlib.vhd

1,6 → 1,6

16,9 → 16,11

120,6 → 122,15

155,20 → 166,6

/w11/trunk/rtl/vlib/genlib/gray_cnt_n.vhd

1,4 → 1,4

16,14 → 16,23

38,7 → 47,6

/w11/trunk/rtl/vlib/genlib/clkdivce.vhd

1,4 → 1,4

18,7 → 18,7

69,7 → 69,7

/w11/trunk/rtl/vlib/genlib/gray2bin_gen.vhd

1,4 → 1,4

16,9 → 16,9

/w11/trunk/rtl/vlib/genlib/gray_cnt_4.vhd

1,4 → 1,4

18,7 → 18,7

/w11/trunk/rtl/vlib/genlib/gray_cnt_5.vhd

1,4 → 1,4

18,7 → 18,7

/w11/trunk/rtl/vlib/genlib/Makefile.ise

0,0 → 1,34

/w11/trunk/rtl/vlib/genlib/debounce_gen.vhd

1,4 → 1,4

18,7 → 18,7

/w11/trunk/rtl/vlib/cdclib/cdc_vector_s0.vbom

0,0 → 1,5

/w11/trunk/rtl/vlib/cdclib/cdclib.vhd

0,0 → 1,99

/w11/trunk/rtl/vlib/cdclib/cdc_pulse.vhd

0,0 → 1,128

/w11/trunk/rtl/vlib/cdclib/cdc_pulse.vbom

0,0 → 1,5

/w11/trunk/rtl/vlib/cdclib/cdc_signal_s1.xdc

0,0 → 1,27

/w11/trunk/rtl/vlib/cdclib/cdc_signal_s1.vhd

0,0 → 1,67

/w11/trunk/rtl/vlib/cdclib/cdc_vector_s0.xdc

0,0 → 1,34

/w11/trunk/rtl/vlib/cdclib/cdc_signal_s1.vbom

0,0 → 1,5

/w11/trunk/rtl/vlib/cdclib/Makefile.ise

0,0 → 1,30

/w11/trunk/rtl/vlib/cdclib/cdc_vector_s0.vhd

0,0 → 1,66

/w11/trunk/rtl/vlib/cdclib/Makefile

0,0 → 1,37

/w11/trunk/rtl/vlib/cdclib/cdc_pulse.xdc

0,0 → 1,30

/w11/trunk/rtl/vlib/cdclib

w11/trunk/rtl/vlib/cdclib Property changes : Added: svn:ignore ## -0,0 +1,42 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb Index: w11/trunk/rtl/vlib/generic_clk_100mhz.xdc =================================================================== --- w11/trunk/rtl/vlib/generic_clk_100mhz.xdc (nonexistent) +++ w11/trunk/rtl/vlib/generic_clk_100mhz.xdc (revision 36) @@ -0,0 +1,14 @@ +# -*- tcl -*- +# $Id: generic_clk_100mhz.xdc 777 2016-06-19 20:24:15Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Generic constraint for pin CLK with a 100 MHz clock +# Helpful for test benches and generic test synthesis +# +# Revision History: +# Date Rev Version Comment +# 2016-06-19 777 1.0 Initial version + +create_clock -name CLK -period 10 -waveform {0 5} [get_ports CLK] Index: w11/trunk/rtl/vlib/comlib/byte2word.vbom =================================================================== --- w11/trunk/rtl/vlib/comlib/byte2word.vbom (revision 35) +++ w11/trunk/rtl/vlib/comlib/byte2word.vbom (nonexistent) @@ -1,4 +0,0 @@ -# libs -../slvtypes.vhd -# design -byte2word.vhd Index: w11/trunk/rtl/vlib/comlib/word2byte.vhd =================================================================== --- w11/trunk/rtl/vlib/comlib/word2byte.vhd (revision 35) +++ w11/trunk/rtl/vlib/comlib/word2byte.vhd (nonexistent) @@ -1,151 +0,0 @@ --- $Id: word2byte.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2011- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: word2byte - syn --- Description: 1 word -> 2 byte stream converter --- --- Dependencies: - --- Test bench: - --- Target Devices: generic --- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 --- --- Revision History: --- Date Rev Version Comment --- 2011-11-21 432 1.0.1 now numeric_std clean --- 2011-07-30 400 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; - -entity word2byte is -- 1 word -> 2 byte stream converter - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - DI : in slv16; -- input data (word) - ENA : in slbit; -- write enable - BUSY : out slbit; -- write port hold - DO : out slv8; -- output data (byte) - VAL : out slbit; -- read valid - HOLD : in slbit; -- read hold - ODD : out slbit -- odd byte pending - ); -end word2byte; - - -architecture syn of word2byte is - - type state_type is ( - s_idle, - s_valw, - s_valh - ); - - type regs_type is record - datl : slv8; -- lsb data - dath : slv8; -- msb data - state : state_type; -- state - end record regs_type; - - constant regs_init : regs_type := ( - (others=>'0'), - (others=>'0'), - s_idle - ); - - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - -begin - - proc_regs: process (CLK) - begin - - if rising_edge(CLK) then - if RESET = '1' then - R_REGS <= regs_init; - else - R_REGS <= N_REGS; - end if; - end if; - - end process proc_regs; - - proc_next: process (R_REGS, DI, ENA, HOLD) - - variable r : regs_type := regs_init; - variable n : regs_type := regs_init; - - variable ival : slbit := '0'; - variable ibusy : slbit := '0'; - variable iodd : slbit := '0'; - - begin - - r := R_REGS; - n := R_REGS; - - ival := '0'; - ibusy := '0'; - iodd := '0'; - - case r.state is - - when s_idle => - if ENA = '1' then - n.datl := DI( 7 downto 0); - n.dath := DI(15 downto 8); - n.state := s_valw; - end if; - - when s_valw => - ibusy := '1'; - ival := '1'; - if HOLD = '0' then - n.datl := r.dath; - n.state := s_valh; - end if; - - when s_valh => - ival := '1'; - iodd := '1'; - if HOLD = '0' then - if ENA = '1' then - n.datl := DI( 7 downto 0); - n.dath := DI(15 downto 8); - n.state := s_valw; - else - n.state := s_idle; - end if; - else - ibusy := '1'; - end if; - - when others => null; - end case; - - N_REGS <= n; - - DO <= r.datl; - VAL <= ival; - BUSY <= ibusy; - ODD <= iodd; - - end process proc_next; - - -end syn; Index: w11/trunk/rtl/vlib/comlib/byte2word.vhd =================================================================== --- w11/trunk/rtl/vlib/comlib/byte2word.vhd (revision 35) +++ w11/trunk/rtl/vlib/comlib/byte2word.vhd (nonexistent) @@ -1,147 +0,0 @@ --- $Id: byte2word.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2011- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: byte2word - syn --- Description: 2 byte -> 1 word stream converter --- --- Dependencies: - --- Test bench: - --- Target Devices: generic --- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 --- --- Revision History: --- Date Rev Version Comment --- 2011-11-21 432 1.0.1 now numeric_std clean --- 2011-07-30 400 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; - -entity byte2word is -- 2 byte -> 1 word stream converter - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - DI : in slv8; -- input data (byte) - ENA : in slbit; -- write enable - BUSY : out slbit; -- write port hold - DO : out slv16; -- output data (word) - VAL : out slbit; -- read valid - HOLD : in slbit; -- read hold - ODD : out slbit -- odd byte pending - ); -end byte2word; - - -architecture syn of byte2word is - - type state_type is ( - s_idle, - s_vall, - s_valw - ); - - type regs_type is record - datl : slv8; -- lsb data - dath : slv8; -- msb data - state : state_type; -- state - end record regs_type; - - constant regs_init : regs_type := ( - (others=>'0'), - (others=>'0'), - s_idle - ); - - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - -begin - - proc_regs: process (CLK) - begin - - if rising_edge(CLK) then - if RESET = '1' then - R_REGS <= regs_init; - else - R_REGS <= N_REGS; - end if; - end if; - - end process proc_regs; - - proc_next: process (R_REGS, DI, ENA, HOLD) - - variable r : regs_type := regs_init; - variable n : regs_type := regs_init; - - variable ival : slbit := '0'; - variable ibusy : slbit := '0'; - variable iodd : slbit := '0'; - - begin - - r := R_REGS; - n := R_REGS; - - ival := '0'; - ibusy := '0'; - iodd := '0'; - - case r.state is - - when s_idle => - if ENA = '1' then - n.datl := DI; - n.state := s_vall; - end if; - - when s_vall => - iodd := '1'; - if ENA = '1' then - n.dath := DI; - n.state := s_valw; - end if; - - when s_valw => - ival := '1'; - if HOLD = '0' then - if ENA = '1' then - n.datl := DI; - n.state := s_vall; - else - n.state := s_idle; - end if; - else - ibusy := '1'; - end if; - - when others => null; - end case; - - N_REGS <= n; - - DO <= r.dath & r.datl; - VAL <= ival; - BUSY <= ibusy; - ODD <= iodd; - - end process proc_next; - - -end syn; Index: w11/trunk/rtl/vlib/comlib/word2byte.vbom =================================================================== --- w11/trunk/rtl/vlib/comlib/word2byte.vbom (revision 35) +++ w11/trunk/rtl/vlib/comlib/word2byte.vbom (nonexistent) @@ -1,4 +0,0 @@ -# libs -../slvtypes.vhd -# design -word2byte.vhd Index: w11/trunk/rtl/vlib/comlib/Makefile =================================================================== --- w11/trunk/rtl/vlib/comlib/Makefile (revision 35) +++ w11/trunk/rtl/vlib/comlib/Makefile (nonexistent) @@ -1,32 +0,0 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ -# -# Revision History: -# Date Rev Version Comment -# 2014-07-27 545 1.2.1 make reference board configurable via XTW_BOARD -# 2011-08-13 405 1.2 use includes from rtl/make -# 2007-07-06 64 1.1 use Makefile.xflow -# 2007-06-03 45 1.0 Initial version -# -VBOM_all = $(wildcard *.vbom) -NGC_all = $(VBOM_all:.vbom=.ngc) -# -# reference board for test synthesis is Spartan-6 based Nexys3 -ifndef XTW_BOARD - XTW_BOARD=nexys3 -endif -include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk -# -.PHONY : all clean -# -all : $(NGC_all) -# -clean : ise_clean -# -#---- -# -include ${RETROBASE}/rtl/make_ise/generic_xflow.mk -# -ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) -endif -# Index: w11/trunk/rtl/vlib/comlib/comlib.vhd =================================================================== --- w11/trunk/rtl/vlib/comlib/comlib.vhd (revision 35) +++ w11/trunk/rtl/vlib/comlib/comlib.vhd (revision 36) @@ -1,4 +1,4 @@ --- $Id: comlib.vhd 746 2016-03-19 13:08:36Z mueller $ +-- $Id: comlib.vhd 749 2016-03-20 22:09:03Z mueller $ -- -- Copyright 2007-2016 by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-20 749 1.6.2 crc*_update*: leave return type unconstraint -- 2016-03-13 744 1.6.1 crc16_update_tbl: work around XSim 2015.4 issue -- 2014-09-27 595 1.6 add crc16 (using CRC-CCITT polynomial) -- 2014-09-14 593 1.5 new iface for cdata2byte and byte2cdata @@ -134,12 +135,17 @@ ); end component; - function crc8_update (crc : in slv8; data : in slv8) return slv8; - function crc8_update_tbl (crc : in slv8; data : in slv8) return slv8; + -- Note: leave return type unconstraint ! A direction constraint return + -- type works fine in ghdl and ISim, but XSim will abort with an + -- run time error (there is indeed a mismatch, some simulators + -- tolerate this, some not, so never constrain a return type...). - function crc16_update (crc : in slv16; data : in slv8) return slv16; - function crc16_update_tbl (crc : in slv16; data : in slv8) return slv16; + function crc8_update (crc : in slv8; data : in slv8) return slv; + function crc8_update_tbl (crc : in slv8; data : in slv8) return slv; + function crc16_update (crc : in slv16; data : in slv8) return slv; + function crc16_update_tbl (crc : in slv16; data : in slv8) return slv; + end package comlib; -- ---------------------------------------------------------------------------- @@ -153,7 +159,7 @@ -- http://dx.doi.org/10.1109%2FDSN.2004.1311885 -- http://www.ece.cmu.edu/~koopman/roses/dsn04/koopman04_crc_poly_embedded.pdf -- - function crc8_update (crc: in slv8; data: in slv8) return slv8 is + function crc8_update (crc: in slv8; data: in slv8) return slv is variable t : slv8 := (others=>'0'); variable n : slv8 := (others=>'0'); begin @@ -173,7 +179,7 @@ end function crc8_update; - function crc8_update_tbl (crc: in slv8; data: in slv8) return slv8 is + function crc8_update_tbl (crc: in slv8; data: in slv8) return slv is type crc8_tbl_type is array (0 to 255) of integer; variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl @@ -220,7 +226,7 @@ -- crc16_update and crc16_update_tbl implement the CCITT polynomial -- x^16 + x^12 + x^5 + 1 (0x1021) -- - function crc16_update (crc: in slv16; data: in slv8) return slv16 is + function crc16_update (crc: in slv16; data: in slv8) return slv is variable n : slv16 := (others=>'0'); variable t : slv8 := (others=>'0'); begin @@ -249,7 +255,7 @@ end function crc16_update; - function crc16_update_tbl (crc: in slv16; data: in slv8) return slv16 is + function crc16_update_tbl (crc: in slv16; data: in slv8) return slv is type crc16_tbl_type is array (0 to 255) of integer; variable crc16_tbl : crc16_tbl_type := @@ -298,13 +304,7 @@ ch := crc(7 downto 0) & "00000000"; t := data xor crc(15 downto 8); td := crc16_tbl(to_integer(unsigned(t))); - cu := slv(to_unsigned(td, 16)); - ch := ch xor cu; - return ch; - --- original code was simply --- return ch xor slv(to_unsigned(td, 16)); --- vivado 2015.4 xsim failed on this, issue worked around by equivalent code + return ch xor slv(to_unsigned(td, 16)); end function crc16_update_tbl;

/w11/trunk/rtl/vlib/comlib/tb/tb_cdata2byte.vbom

5,6 → 5,6

/w11/trunk/rtl/vlib/comlib/tb/Makefile.ise

1,4 → 1,5

/w11/trunk/rtl/vlib/comlib/tb/tbd_cdata2byte.vbom

6,3 → 6,4

/w11/trunk/rtl/vlib/comlib/Makefile.ise

0,0 → 1,33

/w11/trunk/rtl/vlib/memlib/Makefile File deleted

/w11/trunk/rtl/vlib/memlib/fifo_1c_dram_raw.vbom

3,6 → 3,7

/w11/trunk/rtl/vlib/memlib/memlib.vhd

1,6 → 1,6

17,9 → 17,10

235,4 → 236,24

/w11/trunk/rtl/vlib/memlib/fifo_2c_dram.vbom

4,7 → 4,8

/w11/trunk/rtl/vlib/memlib/fifo_2c_dram.vhd

1,4 → 1,4

22,7 → 22,7

175,13 → 175,16

257,6 → 260,9

/w11/trunk/rtl/vlib/memlib/Makefile.ise

0,0 → 1,33

/w11/trunk/rtl/vlib/memlib/fifo_2c_dram2.vbom

0,0 → 1,11

/w11/trunk/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd

1,4 → 1,4

30,13 → 30,13

/w11/trunk/rtl/vlib/memlib/fifo_2c_dram2.xdc

0,0 → 1,59

/w11/trunk/rtl/vlib/memlib/fifo_2c_dram2.vhd

0,0 → 1,322

/w11/trunk/rtl/vlib/rbus/Makefile File deleted

/w11/trunk/rtl/vlib/rbus/rbd_rbmon.vhd

1,4 → 1,4

20,7 → 20,7

/w11/trunk/rtl/vlib/rbus/rbd_eyemon.vbom

4,6 → 4,7

/w11/trunk/rtl/vlib/rbus/rb_sres_or_6.vbom

0,0 → 1,7

/w11/trunk/rtl/vlib/rbus/rb_sel.vhd

1,6 → 1,6

18,10 → 18,11

53,15 → 54,14

/w11/trunk/rtl/vlib/rbus/rbd_usracc.vhd

0,0 → 1,108

/w11/trunk/rtl/vlib/rbus/rbd_timer.vhd

1,4 → 1,4

20,7 → 20,7

/w11/trunk/rtl/vlib/rbus/Makefile.ise

0,0 → 1,33

/w11/trunk/rtl/vlib/rbus/rbd_eyemon.vhd

1,6 → 1,6

20,7 → 20,7

29,6 → 29,7

131,7 → 132,7

296,6 → 297,7

/w11/trunk/rtl/vlib/rbus/rb_sres_or_6.vhd

0,0 → 1,97

/w11/trunk/rtl/vlib/rbus/rbd_rbmon.vbom

4,6 → 4,7

/w11/trunk/rtl/vlib/rbus/rbd_usracc.vbom

0,0 → 1,8

/w11/trunk/rtl/vlib/rbus/rbd_bram.vbom

4,6 → 4,7

/w11/trunk/rtl/vlib/rbus/rbd_tester.vhd

1,4 → 1,4

20,7 → 20,7

/w11/trunk/rtl/vlib/rbus/rbdlib.vhd

1,6 → 1,6

16,10 → 16,11

43,6 → 44,7

113,4 → 115,14

/w11/trunk/rtl/vlib/serport/Makefile File deleted

/w11/trunk/rtl/vlib/serport/serport_2clock2.vbom

0,0 → 1,15

/w11/trunk/rtl/vlib/serport/serport_uart_rx.vhd

1,4 → 1,4

24,9 → 24,10

41,9 → 42,9

97,9 → 98,9

/w11/trunk/rtl/vlib/serport/serport_uart_tx.vhd

1,4 → 1,4

18,7 → 18,7

27,9 → 27,9

/w11/trunk/rtl/vlib/serport/Makefile.ise

0,0 → 1,33

/w11/trunk/rtl/vlib/serport/serport_2clock2.vhd

0,0 → 1,386

/w11/trunk/rtl/vlib/serport/serport_2clock.vbom

1,10 → 1,10

/w11/trunk/rtl/vlib/serport/serport_uart_autobaud.vhd

1,4 → 1,4

18,9 → 18,10

28,9 → 29,9

91,14 → 92,14

/w11/trunk/rtl/vlib/serport/serport_uart_rxtx.vhd

1,4 → 1,4

19,14 → 19,14

/w11/trunk/rtl/vlib/serport/serport_uart_rxtx_ab.vhd

1,4 → 1,4

19,7 → 19,7

33,9 → 33,9

/w11/trunk/rtl/vlib/serport/serportlib.vhd

1,4 → 1,4

16,10 → 16,11

32,7 → 33,7

243,6 → 244,33

/w11/trunk/rtl/vlib/serport/tb/tbd_serport_uart_rx.vbom

5,3 → 5,4

/w11/trunk/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vbom

5,6 → 5,6

/w11/trunk/rtl/vlib/serport/tb/serport_uart_rx_tb.vhd

1,4 → 1,4

26,6 → 26,7

81,9 → 82,9

/w11/trunk/rtl/vlib/serport/tb/Makefile

0,0 → 1,44

/w11/trunk/rtl/vlib/serport/tb/tbd_serport_autobaud.vbom

9,3 → 9,4

/w11/trunk/rtl/vlib/serport/tb/tb_serport_uart_rx.vbom

5,6 → 5,6

/w11/trunk/rtl/vlib/serport/tb/Makefile.ise

1,4 → 1,5

/w11/trunk/rtl/vlib/serport/tb/tb_serport_autobaud.vbom

5,6 → 5,6

/w11/trunk/rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vbom

5,3 → 5,4

/w11/trunk/rtl/vlib/serport/serport_1clock.vhd

1,4 → 1,4

185,7 → 185,7

/w11/trunk/rtl/vlib/serport/serport_2clock.vhd

1,4 → 1,4

15,7 → 15,7

31,6 → 31,7

45,7 → 46,7

389,12 → 390,16

/w11/trunk/rtl/vlib/serport/serport_xonrx.vhd

1,4 → 1,4

18,14 → 18,14

/w11/trunk/rtl/vlib/xlib/Makefile File deleted

/w11/trunk/rtl/vlib/xlib/iob_reg_o_gen.vbom

1,4 → 1,5

/w11/trunk/rtl/vlib/xlib/usr_access_unisim.vbom

0,0 → 1,5

/w11/trunk/rtl/vlib/xlib/iob_reg_io_gen.vbom

1,5 → 1,6

/w11/trunk/rtl/vlib/xlib/Makefile.ise

0,0 → 1,32

/w11/trunk/rtl/vlib/xlib/usr_access_unisim.vhd

0,0 → 1,69

/w11/trunk/rtl/vlib/xlib/iob_keeper_gen.vbom

1,4 → 1,5

/w11/trunk/rtl/vlib/xlib/tb/s7_cmt_sfs_tb.vhd

1,4 → 1,4

23,6 → 23,7

120,10 → 121,10

133,7 → 134,8

/w11/trunk/rtl/vlib/xlib/iob_reg_io_gen.vhd

1,4 → 1,4

18,7 → 18,7

99,8 → 99,7

/w11/trunk/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd

1,6 → 1,6

23,6 → 23,7

123,10 → 124,10

/w11/trunk/rtl/vlib/xlib/iob_reg_i_gen.vbom

1,4 → 1,5

/w11/trunk/rtl/vlib/xlib/xlib.vhd

1,6 → 1,6

16,9 → 16,10

214,4 → 215,10

/w11/trunk/rtl/make_ise/generic_ghdl.mk

1,10 → 1,11

42,9 → 43,8

/w11/trunk/rtl/make_ise/generic_xflow.mk

1,10 → 1,12

100,8 → 102,8

122,8 → 124,8

155,19 → 157,19

185,11 → 187,11

225,18 → 227,27

/w11/trunk/doc/README_known_issues.txt

1,12 → 1,22

25,12 → 35,8

/w11/trunk/doc/w11a_tb_guide.txt

1,9 → 1,10

47,27 → 48,18

85,17 → 77,17

102,7 → 94,7

109,38 → 101,45

147,7 → 146,7

177,7 → 176,7

184,11 → 183,11

195,7 → 194,7

209,8 → 208,8

217,16 → 216,16

236,8 → 235,8

244,16 → 243,16

266,8 → 265,8

274,8 → 273,8

296,8 → 295,8

306,8 → 305,8

315,9 → 314,9

324,10 → 323,10

334,13 → 333,13

/w11/trunk/doc/README_buildsystem_ISE.txt

1,4 → 1,4

114,13 → 114,17

/w11/trunk/doc/w11a_os_guide.txt

1,4 → 1,4

107,7 → 107,7

123,7 → 123,7

164,7 → 164,7

/w11/trunk/doc/README_buildsystem_Vivado.txt

1,4 → 1,4

12,8 → 12,9

102,8 → 103,7

115,18 → 115,29

139,16 → 150,25

191,16 → 211,48

208,6 → 260,8

/w11/trunk/doc/README.txt

1,4 → 1,4

22,6 → 22,213

70,7 → 277,7

/w11/trunk/doc/man/man5/vbom.5

1,5 → 1,5

34,7 → 34,7

58,7 → 58,28

104,7 → 125,7

111,14 → 132,15

134,13 → 156,6

/w11/trunk/doc/man/man1/xise_msg_filter.1

1,10 → 1,10

14,7 → 14,7

27,7 → 27,7

69,7 → 69,7

86,22 → 86,23

/w11/trunk/doc/man/man1/tbrun_tbwrri.1

1,5 → 1,5

63,7 → 63,7

97,8 → 97,8

/w11/trunk/doc/man/man1/xviv_sim_vhdl_cleanup.1

0,0 → 1,37

/w11/trunk/doc/man/man1/ti_rri.1

1,11 → 1,11

34,6 → 34,8

191,6 → 193,12

/w11/trunk/doc/man/man1/vbomconv.1

1,5 → 1,5

208,7 → 208,7

220,13 → 220,6

452,6 → 445,15

550,7 → 552,6

/w11/trunk/doc/man/man1/xise_ghdl_unisim.1

1,5 → 1,5

41,7 → 41,7

/w11/trunk/doc/man/man1/xise_msg_summary.1

0,0 → 1,34

/w11/trunk/doc/man/man1/tbw.1

1,11 → 1,11

52,9 → 52,10

68,15 → 69,18

111,9 → 115,10

179,6 → 184,9

188,14 → 196,19

/w11/trunk/doc/man/man1/ti_w11.1

1,5 → 1,5

87,12 → 87,21

/w11/trunk/doc/man/man1/tbrun_tbw.1

1,5 → 1,5

55,7 → 55,7

77,7 → 77,7

/w11/trunk/doc/man/man1/xise_ghdl_simprim.1

1,5 → 1,5

47,7 → 47,7

/w11/trunk/doc/man/man1/xviv_msg_filter.1

0,0 → 1,128

/w11/trunk/doc/man/man1/xviv_ghdl_unisim.1

1,5 → 1,5

42,7 → 42,7

/w11/trunk/doc/man/man1/xviv_msg_summary.1

0,0 → 1,34

/w11/trunk/Makefile

1,4 → 1,4

6,6 → 6,8

30,18 → 32,18

111,6 → 113,7

129,6 → 132,8

206,6 → 211,11

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