URL
https://opencores.org/ocsvn/w11/w11/trunk
Subversion Repositories w11
Compare Revisions
- This comparison shows the changes necessary to convert path
/w11/trunk
- from Rev 14 to Rev 15
- ↔ Reverse comparison
Rev 14 → Rev 15
/tools/tcl/setup_packages
1,5 → 1,5
#! /usr/bin/env tclsh |
# $Id: setup_packages 429 2011-11-20 12:54:56Z mueller $ |
# $Id: setup_packages 431 2011-11-21 17:56:37Z mueller $ |
# |
pkg_mkIndex -verbose ../lib libr*tpp.so |
# |
/tools/src/librlink/RlinkConnect.hpp
1,4 → 1,4
// $Id: RlinkConnect.hpp 380 2011-04-25 18:14:52Z mueller $ |
// $Id: RlinkConnect.hpp 434 2011-12-02 19:17:38Z mueller $ |
// |
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,6 → 13,7
// |
// Revision History: |
// Date Rev Version Comment |
// 2011-11-28 434 1.1.1 struct LogOpts: use uint32_t for lp64 compatibility |
// 2011-04-24 380 1.1 use boost::noncopyable (instead of private dcl's); |
// use boost::(mutex&lock), implement Lockable IF |
// 2011-04-22 379 1.0.1 add Lock(), Unlock() |
23,7 → 24,7
|
/*! |
\file |
\version $Id: RlinkConnect.hpp 380 2011-04-25 18:14:52Z mueller $ |
\version $Id: RlinkConnect.hpp 434 2011-12-02 19:17:38Z mueller $ |
\brief Declaration of class \c RlinkConnect. |
*/ |
|
52,12 → 53,12
class RlinkConnect : private boost::noncopyable { |
public: |
struct LogOpts { |
size_t baseaddr; |
size_t basedata; |
size_t basestat; |
size_t printlevel; // 0=off,1=err,2=chk,3=all |
size_t dumplevel; // 0=off,1=err,2=chk,3=all |
size_t tracelevel; // 0=off,1=buf,2=char |
uint32_t baseaddr; |
uint32_t basedata; |
uint32_t basestat; |
uint32_t printlevel; // 0=off,1=err,2=chk,3=all |
uint32_t dumplevel; // 0=off,1=err,2=chk,3=all |
uint32_t tracelevel; // 0=off,1=buf,2=char |
|
LogOpts() |
: baseaddr(16), basedata(16), basestat(16), |
/tools/src/librlink/RlinkCommandExpect.cpp
1,4 → 1,4
// $Id: RlinkCommandExpect.cpp 375 2011-04-02 07:56:47Z mueller $ |
// $Id: RlinkCommandExpect.cpp 434 2011-12-02 19:17:38Z mueller $ |
// |
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,6 → 13,7
// |
// Revision History: |
// Date Rev Version Comment |
// 2011-11-28 434 1.0.1 Dump(): use proper cast for lp64 compatibility |
// 2011-03-12 368 1.0 Initial version |
// 2011-01-15 355 0.1 First draft |
// --------------------------------------------------------------------------- |
19,7 → 20,7
|
/*! |
\file |
\version $Id: RlinkCommandExpect.cpp 375 2011-04-02 07:56:47Z mueller $ |
\version $Id: RlinkCommandExpect.cpp 434 2011-12-02 19:17:38Z mueller $ |
\brief Implemenation of class RlinkCommandExpect. |
*/ |
|
167,7 → 168,7
if (fBlockVal.size() > 0) { |
os << bl << " fBlockVal & Msk data: "; |
size_t width = (fBlockMsk.size()>0) ? 9 : 4; |
size_t ncol = max(1u, (80-ind-4-5)/(width+1)); |
size_t ncol = max(((size_t) 1), (80-ind-4-5)/(width+1)); |
for (size_t i=0; i< fBlockVal.size(); i++) { |
if (i%ncol == 0) os << "\n" << bl << " " << RosPrintf(i,"d",3) << ": "; |
|
/tools/src/librlink/RlinkAddrMap.cpp
1,4 → 1,4
// $Id: RlinkAddrMap.cpp 375 2011-04-02 07:56:47Z mueller $ |
// $Id: RlinkAddrMap.cpp 434 2011-12-02 19:17:38Z mueller $ |
// |
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,6 → 13,7
// |
// Revision History: |
// Date Rev Version Comment |
// 2011-11-28 434 1.0.1 Print(): use proper cast for lp64 compatibility |
// 2011-03-06 367 1.0 Initial version |
// 2011-03-05 366 0.1 First draft |
// --------------------------------------------------------------------------- |
19,7 → 20,7
|
/*! |
\file |
\version $Id: RlinkAddrMap.cpp 375 2011-04-02 07:56:47Z mueller $ |
\version $Id: RlinkAddrMap.cpp 434 2011-12-02 19:17:38Z mueller $ |
\brief Implemenation of class RlinkAddrMap. |
*/ |
|
157,7 → 158,7
|
void RlinkAddrMap::Print(std::ostream& os, int ind) const |
{ |
size_t maxlen = max(6u, MaxNameLength()); |
size_t maxlen = max(((size_t) 6), MaxNameLength()); |
|
RosFill bl(ind); |
for (amap_cit_t it=fAddrMap.begin(); it!=fAddrMap.end(); it++) { |
/tools/src/librlink/RlinkPortTerm.cpp
1,4 → 1,4
// $Id: RlinkPortTerm.cpp 388 2011-07-06 18:40:47Z mueller $ |
// $Id: RlinkPortTerm.cpp 435 2011-12-04 20:15:25Z mueller $ |
// |
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,6 → 13,7
// |
// Revision History: |
// Date Rev Version Comment |
// 2011-12-04 435 1.0.2 Open(): add cts attr, hw flow control now optional |
// 2011-07-04 388 1.0.1 add termios readback and verification |
// 2011-03-27 374 1.0 Initial version |
// --------------------------------------------------------------------------- |
19,7 → 20,7
|
/*! |
\file |
\version $Id: RlinkPortTerm.cpp 388 2011-07-06 18:40:47Z mueller $ |
\version $Id: RlinkPortTerm.cpp 435 2011-12-04 20:15:25Z mueller $ |
\brief Implemenation of RlinkPortTerm. |
*/ |
|
65,7 → 66,7
{ |
if (IsOpen()) Close(); |
|
if (!ParseUrl(url, "|baud=|break|", emsg)) return false; |
if (!ParseUrl(url, "|baud=|break|cts|", emsg)) return false; |
|
speed_t speed = B115200; |
string baud; |
120,12 → 121,17
|
fTiosNew.c_iflag = IGNBRK | // ignore breaks on input |
IGNPAR; // ignore parity errors |
|
fTiosNew.c_oflag = 0; |
|
fTiosNew.c_cflag = CS8 | // 8 bit chars |
CSTOPB | // 2 stop bits |
CREAD | // enable receiver |
CLOCAL | // ignore modem control |
CRTSCTS; // enable hardware flow control |
CLOCAL; // ignore modem control |
if (UrlFindOpt("cts")) { |
fTiosNew.c_cflag |= CRTSCTS; // enable hardware flow control |
} |
|
fTiosNew.c_lflag = 0; |
|
if (cfsetspeed(&fTiosNew, speed) != 0) { |
/tools/src/librlinktpp/RtclRlinkConnect.cpp
1,4 → 1,4
// $Id: RtclRlinkConnect.cpp 380 2011-04-25 18:14:52Z mueller $ |
// $Id: RtclRlinkConnect.cpp 434 2011-12-02 19:17:38Z mueller $ |
// |
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,6 → 13,7
// |
// Revision History: |
// Date Rev Version Comment |
// 2011-11-28 434 1.1.1 ConfigBase(): use uint32_t for lp64 compatibility |
// 2011-04-23 380 1.1 use boost/bind instead of RmethDsc |
// 2011-04-17 376 1.0.1 M_wtlam: now correct log levels |
// 2011-03-27 374 1.0 Initial version |
21,7 → 22,7
|
/*! |
\file |
\version $Id: RtclRlinkConnect.cpp 380 2011-04-25 18:14:52Z mueller $ |
\version $Id: RtclRlinkConnect.cpp 434 2011-12-02 19:17:38Z mueller $ |
\brief Implemenation of class RtclRlinkConnect. |
*/ |
|
801,9 → 802,9
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
bool RtclRlinkConnect::ConfigBase(RtclArgs& args, size_t& base) |
bool RtclRlinkConnect::ConfigBase(RtclArgs& args, uint32_t& base) |
{ |
size_t tmp = base; |
uint32_t tmp = base; |
if (!args.Config("??base", tmp, 16, 2)) return false; |
if (tmp != base && tmp != 2 && tmp !=8 && tmp != 16) { |
args.AppendResult("-E: base must be 2, 8, or 16, found \"", |
/tools/src/librlinktpp/RtclRlinkConnect.hpp
1,4 → 1,4
// $Id: RtclRlinkConnect.hpp 375 2011-04-02 07:56:47Z mueller $ |
// $Id: RtclRlinkConnect.hpp 434 2011-12-02 19:17:38Z mueller $ |
// |
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,6 → 13,7
// |
// Revision History: |
// Date Rev Version Comment |
// 2011-11-28 434 1.0.1 ConfigBase(): use uint32_t for lp64 compatibility |
// 2011-03-27 374 1.0 Initial version |
// 2011-02-11 360 0.1 First draft |
// --------------------------------------------------------------------------- |
19,7 → 20,7
|
/*! |
\file |
\version $Id: RtclRlinkConnect.hpp 375 2011-04-02 07:56:47Z mueller $ |
\version $Id: RtclRlinkConnect.hpp 434 2011-12-02 19:17:38Z mueller $ |
\brief Declaration of class RtclRlinkConnect. |
*/ |
|
59,7 → 60,7
bool GetAddr(RtclArgs& args, RlinkConnect& conn, uint16_t& addr); |
bool GetVarName(RtclArgs& args, const char* argname, |
size_t nind, std::vector<std::string>& varname); |
bool ConfigBase(RtclArgs& args, size_t& base); |
bool ConfigBase(RtclArgs& args, uint32_t& base); |
bool ClistNonEmpty(RtclArgs& args, |
const RlinkCommandList& clist); |
|
/tools/src/librutiltpp/RtclBvi.cpp
1,4 → 1,4
// $Id: RtclBvi.cpp 375 2011-04-02 07:56:47Z mueller $ |
// $Id: RtclBvi.cpp 434 2011-12-02 19:17:38Z mueller $ |
// |
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
13,6 → 13,7
// |
// Revision History: |
// Date Rev Version Comment |
// 2011-11-28 434 1.0.1 DoCmd(): use intptr_t cast for lp64 compatibility |
// 2011-03-27 374 1.0 Initial version |
// 2011-02-13 361 0.1 First draft |
// --------------------------------------------------------------------------- |
19,7 → 20,7
|
/*! |
\file |
\version $Id: RtclBvi.cpp 375 2011-04-02 07:56:47Z mueller $ |
\version $Id: RtclBvi.cpp 434 2011-12-02 19:17:38Z mueller $ |
\brief Implemenation of RtclBvi. |
*/ |
|
64,7 → 65,8
int nbit = 0; |
if (!CheckFormat(interp, objc, objv, list, form, nbit)) return kERR; |
|
ConvMode mode = (ConvMode)((int) cdata); |
//ConvMode mode = (ConvMode)((int) cdata); |
ConvMode mode = (ConvMode)((intptr_t) cdata); |
|
if (list) { |
int lobjc = 0; |
/tools/src/Makefile
1,4 → 1,4
# $Id: Makefile 429 2011-11-20 12:54:56Z mueller $ |
# $Id: Makefile 431 2011-11-21 17:56:37Z mueller $ |
# |
# Top level makefile, using the recipe found in |
# http://www.lackof.org/taggart/hacking/make-example/ |
/tools/bin/pi_rri
1,7 → 1,7
#!/usr/bin/perl -w |
# $Id: pi_rri 410 2011-09-18 11:23:09Z mueller $ |
# $Id: pi_rri 435 2011-12-04 20:15:25Z mueller $ |
# |
# Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
14,6 → 14,7
# |
# Revision History: |
# Date Rev Version Comment |
# 2011-12-04 435 1.6.5 add control over flow control (cts or none) |
# 2011-09-17 410 1.6.4 use for crc8 now a6 polynomial |
# 2010-12-29 351 1.6.3 rename rriext->cext and cpmon->rlmon |
# 2010-06-27 310 1.6.2 fix autoflush for fh_log; duplicate exec err to log |
6425,13 → 6426,14
} |
|
#------------------------------------------------------------------------------- |
|
# |
sub term_open { # term fifo: open handler |
my ($arg) = @_; |
my ($dev,$baud,$break) = split /,/,$arg; |
$dev = "/dev/ttyS0" unless $dev; |
$baud = 115200 unless $baud; |
$break = 0 unless $break; |
my ($dev,$baud,$break,$flow) = split /,/,$arg; |
$dev = "/dev/ttyS0" unless defined $dev; |
$baud = 115200 unless defined $baud; |
$break = 0 unless defined $break; # default: no break |
$flow = 1 unless defined $flow; # default: cts |
|
$fdset_filercv = ""; |
|
6451,6 → 6453,9
$term_oldtios = new POSIX::Termios; |
$term_oldtios->getattr($fd) || die "getattr failed: $!"; |
|
print_fatal("flow attribute must be 0(none),1(cts), or 2(xon)") |
unless ($flow>=0 && $flow<=2); |
|
## term_tios_print($term_oldtios); |
|
my $newtios = new POSIX::Termios; |
6461,8 → 6466,10
my $c_cflag = &POSIX::CS8 | # 8 bit chars |
&POSIX::CSTOPB | # 2 stop bits |
&POSIX::CREAD | # enable receiver |
&POSIX::CLOCAL | # ignore modem control |
LINUX_CRTSCTS; # enable hardware flow control |
&POSIX::CLOCAL; # ignore modem control |
if ($flow == 1) { # if cts/rts flow control |
$c_cflag |= LINUX_CRTSCTS; # enable hardware flow control |
} |
my $c_lflag = 0; |
my $speed = 0; |
|
/tools/bin/ti_rri
1,6 → 1,6
#! /usr/bin/env tclsh |
# -*- tcl -*- |
# $Id: ti_rri 386 2011-07-01 17:31:03Z mueller $ |
# $Id: ti_rri 435 2011-12-04 20:15:25Z mueller $ |
# |
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
15,6 → 15,7
# |
# Revision History: |
# Date Rev Version Comment |
# 2011-12-04 435 1.0.2 add flow attribute to --term |
# 2011-04-22 379 1.0.1 check for RETROBASE; proper exit handling; help text |
# 2011-04-17 376 1.0 Initial version |
# 2011-03-19 371 0.1 First draft |
21,7 → 22,7
# |
# |
# --fifo[=name,keep] |
# --term[=name,baud,break] |
# --term[=name,baud,break,flow] |
# --run=command |
# --log=filename ; default "-" |
# --logl=n ; default 2 |
109,7 → 110,7
puts { NAME fifo name prefix, default 'rlink_cext_fifo'} |
puts { KEEP if non-empty the fifo is kept open on exit} |
puts { --term[=ARGS] open term type rlink port. Optional arguments are:} |
puts { --term=[NAME,[BAUD,[BREAK]]]} |
puts { --term=[NAME[,BAUD[,BREAK[,FLOW]]]]} |
puts { NAME tty device name, default 'USB0'} |
puts { if not starting with '/' the name is} |
puts { prefixed with '/dev/tty'} |
119,6 → 120,12
puts { 115200, 115k, 230400, 230k, 460800, 460k} |
puts { 500000, 500k, 921600, 921k, 1000000, 1M} |
puts { 2000000, 2M, 3000000, 3M} |
puts { BREAK controls whether a break will be send:} |
puts { 0 no break (default)} |
puts { 1 send break, do autobaud} |
puts { FLOW controls flow control regime:} |
puts { 0 no flow control (default)} |
puts { 1 cts/rts hardware flow control} |
puts { --log=FILE set log file name. Default is to write to stdout.} |
puts { --logl=LVL set log level, default is '2' allowed values:} |
puts { 0 no logging} |
197,13 → 204,18
set dev [lindex $nlist 0] |
set baud [lindex $nlist 1] |
set brk [lindex $nlist 2] |
set flow [lindex $nlist 3] |
if {$dev eq ""} {set dev "USB0"} |
if {$baud eq ""} {set baud "115k"} |
if {$brk eq ""} {set brk 0} |
if {$flow eq ""} {set flow 0} |
if {! [regexp -- {^/} $dev]} { |
set dev "/dev/tty$dev" |
} |
set url "term:$dev?baud=$baud" |
if {$brk ne ""} {append url ";break"} |
if {$brk eq 1} {append url ";break"} |
if {$flow eq 1} {append url ";cts"} |
# puts "-I: $url" |
rlc open $url |
} |
|
/tools/bin/vbomconv
1,5 → 1,5
#!/usr/bin/perl -w |
# $Id: vbomconv 405 2011-08-14 08:16:28Z mueller $ |
# $Id: vbomconv 433 2011-11-27 22:04:39Z mueller $ |
# |
# Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
14,6 → 14,7
# |
# Revision History: |
# Date Rev Version Comment |
# 2011-11-27 433 1.9.2 use in ghdl_m -fexplicit when unisim used |
# 2011-08-13 405 1.9.1 always write 'vhdl' into xst prj files again; for |
# -xst_export: remove opt file export, add ucf_cpp |
# handling |
296,6 → 297,7
|
$cmd .= "ghdl -m"; |
$cmd .= " -o $stem"; |
$cmd .= ' -fexplicit' if $has_unisim; # needed for ISE 13.1 |
$cmd .= ' -P$XILINX/ghdl/unisim' if $has_unisim; |
$cmd .= ' -P$XILINX/ghdl/simprim' if $has_simprim; |
$cmd .= " --ieee=synopsys"; |
/tools/bin/config_wrapper
1,5 → 1,5
#!/usr/bin/perl -w |
# $Id: config_wrapper 402 2011-08-05 18:56:44Z mueller $ |
# $Id: config_wrapper 435 2011-12-04 20:15:25Z mueller $ |
# |
# Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
14,6 → 14,7
# |
# Revision History: |
# Date Rev Version Comment |
# 2011-12-03 435 1.1.5 add nexys3 support; |
# 2011-08-04 402 1.1.4 add atlys support; |
# 2011-07-25 399 1.1.3 add nexys2-500 support; bsdl path for sp605 |
# 2011-07-18 395 1.1.2 cleanup bsdl path creation for jtag |
43,6 → 44,7
if (not defined $opts{path}) { |
$opts{path} = "xc3s1000" if $opts{board} eq "s3board"; |
$opts{path} = "xc3s1200e" if $opts{board} eq "nexys2"; |
$opts{path} = "xc6slx16" if $opts{board} eq "nexys3"; |
$opts{path} = "xc6slx45" if $opts{board} eq "atlys"; |
$opts{path} = "xc6slx45t" if $opts{board} eq "sp605"; |
} |
85,6 → 87,10
@plist = ($ipath, "xcf04s"); |
$pfpga = 1; |
|
} elsif ($board eq "nexys3" && $ipath eq "xc6slx16") { # nexys3 |
@plist = ($ipath); |
$pfpga = 1; |
|
} elsif ($board eq "atlys" && $ipath eq "xc6slx45") { # atlys |
@plist = ($ipath); |
$pfpga = 1; |
93,7 → 99,8
@plist = ("xccace", $ipath); |
$pfpga = 2; |
} else { |
print STDERR "config_wrapper-E: only s3board/nexys2/sp605 supported\n"; |
print STDERR |
"config_wrapper-E: only s3board/nexys2,3/atlys/sp605 supported\n"; |
exit 1; |
} |
|
/tools/make/generic_cpp.mk
1,7 → 1,9
# $Id: generic_cpp.mk 355 2011-01-15 09:06:23Z mueller $ |
# $Id: generic_cpp.mk 434 2011-12-02 19:17:38Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2011-11-28 434 1.0.2 use -fno-strict-aliasing to avoid warings from boost bind |
# 2011-11-21 432 1.0.1 gcc 4.4.5 wants explict -fPIC for .so code |
# 2011-01-09 354 1.0 Initial version (from wrepo/make/generic_cxx.mk) |
#--- |
# |
22,7 → 24,7
endif |
# |
CC = gcc |
CFLAGS = -Wall $(CCOPTFLAGS) $(INCLFLAGS) |
CFLAGS = -Wall -fPIC $(CCOPTFLAGS) $(INCLFLAGS) |
# |
# -- handle C++ |
# |
40,7 → 42,7
CXXOPTFLAGS = -O2 |
endif |
# |
CXXFLAGS = -Wall -std=c++0x $(CXXOPTFLAGS) $(INCLFLAGS) |
CXXFLAGS = -Wall -fPIC -fno-strict-aliasing -std=c++0x $(CXXOPTFLAGS) $(INCLFLAGS) |
COMPILE.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c |
# |
LINK.o = $(CXX) $(CXXOPTFLAGS) $(LDOPTFLAGS) $(LDFLAGS) $(TARGET_ARCH) |
/rtl/sys_gen/tst_rlink/nexys2/tb/tb_tst_rlink_n2.vhd
1,4 → 1,4
-- $Id: tb_tst_rlink_n2.vhd 351 2010-12-30 21:50:54Z mueller $ |
-- $Id: tb_tst_rlink_n2.vhd 433 2011-11-27 22:04:39Z mueller $ |
-- |
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
13,7 → 13,7
-- |
------------------------------------------------------------------------------ |
-- Module Name: tb_tst_rlink |
-- Description: Configuration for tb_tst_rlink_s2 for tb_nexys2_fusp |
-- Description: Configuration for tb_tst_rlink_n2 for tb_nexys2_fusp |
-- |
-- Dependencies: sys_tst_rlink_n2 |
-- |
/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd
1,4 → 1,4
-- $Id: sys_tst_rlink_n2.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- $Id: sys_tst_rlink_n2.vhd 433 2011-11-27 22:04:39Z mueller $ |
-- |
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
20,7 → 20,7
-- bplib/bpgen/bp_rs232_2l4l_iob |
-- bplib/bpgen/sn_humanio_rbus |
-- tst_rlink |
-- vlib/nexys2/n2_cram_dummy |
-- vlib/nxcramlib/nx_cram_dummy |
-- |
-- Test bench: tb/tb_tst_rlink_n2 |
-- |
35,6 → 35,8
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-26 433 1.1.5 use nx_cram_dummy now |
-- 2011-11-23 432 1.1.4 update O_FLA_CE_N usage |
-- 2011-11-17 426 1.1.3 use dcm_sfs now |
-- 2011-07-09 391 1.1.2 use now bp_rs232_2l4l_iob |
-- 2011-07-08 390 1.1.1 use now sn_humanio |
68,7 → 70,7
use work.rblib.all; |
use work.rlinklib.all; |
use work.bpgenlib.all; |
use work.nexys2lib.all; |
use work.nxcramlib.all; |
use work.sys_conf.all; |
|
-- ---------------------------------------------------------------------------- |
80,9 → 82,9
O_CLKSYS : out slbit; -- DCM derived system clock |
I_RXD : in slbit; -- receive data (board view) |
O_TXD : out slbit; -- transmit data (board view) |
I_SWI : in slv8; -- s3 switches |
I_BTN : in slv4; -- s3 buttons |
O_LED : out slv8; -- s3 leds |
I_SWI : in slv8; -- n2 switches |
I_BTN : in slv4; -- n2 buttons |
O_LED : out slv8; -- n2 leds |
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) |
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) |
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) |
93,9 → 95,9
O_MEM_CLK : out slbit; -- cram: clock |
O_MEM_CRE : out slbit; -- cram: command register enable |
I_MEM_WAIT : in slbit; -- cram: mem wait |
O_FLA_CE_N : out slbit; -- flash ce.. (act.low) |
O_MEM_ADDR : out slv23; -- cram: address lines |
IO_MEM_DATA : inout slv16; -- cram: data lines |
O_FLA_CE_N : out slbit; -- flash ce.. (act.low) |
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n |
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n |
I_FUSP_RXD : in slbit; -- fusp: rs232 rx |
218,7 → 220,7
STAT => STAT |
); |
|
SRAM_PROT : n2_cram_dummy -- connect CRAM to protection dummy |
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy |
port map ( |
O_MEM_CE_N => O_MEM_CE_N, |
O_MEM_BE_N => O_MEM_BE_N, |
228,11 → 230,12
O_MEM_CLK => O_MEM_CLK, |
O_MEM_CRE => O_MEM_CRE, |
I_MEM_WAIT => I_MEM_WAIT, |
O_FLA_CE_N => O_FLA_CE_N, |
O_MEM_ADDR => O_MEM_ADDR, |
IO_MEM_DATA => IO_MEM_DATA |
); |
|
O_FLA_CE_N <= '1'; -- keep Flash memory disabled |
|
DSP_DAT <= RL_SER_MONI.clkdiv; |
DSP_DP(0) <= RL_SER_MONI.rxact; |
DSP_DP(1) <= RTS_N; |
/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom
5,7 → 5,7
../../../vlib/rbus/rblib.vhd |
../../../vlib/rlink/rlinklib.vbom |
../../../bplib/bpgen/bpgenlib.vbom |
../../../bplib/nexys2/nexys2lib.vhd |
../../../bplib/nxcramlib/nxcramlib.vhd |
sys_conf : sys_conf.vhd |
# components |
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom |
14,7 → 14,7
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom |
../../../bplib/bpgen/sn_humanio_rbus.vbom |
../tst_rlink.vbom |
../../../bplib/nexys2/n2_cram_dummy.vbom |
../../../bplib/nxcramlib/nx_cram_dummy.vbom |
# design |
sys_tst_rlink_n2.vhd |
@ucf_cpp: sys_tst_rlink_n2.ucf |
/rtl/sys_gen/tst_rlink/nexys3/sys_conf.vhd
0,0 → 1,49
-- $Id: sys_conf.vhd 433 2011-11-27 22:04:39Z mueller $ |
-- |
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Package Name: sys_conf |
-- Description: Definitions for sys_tst_rlink_n2 (for synthesis) |
-- |
-- Dependencies: - |
-- Tool versions: xst 13.1; ghdl 0.29 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-26 433 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
|
package sys_conf is |
|
constant sys_conf_clkfx_divide : positive := 1; |
constant sys_conf_clkfx_multiply : positive := 1; -- |
|
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud |
|
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers |
|
-- derived constants |
|
constant sys_conf_clksys : integer := |
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; |
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; |
|
constant sys_conf_ser2rri_cdinit : integer := |
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; |
|
end package sys_conf; |
|
/rtl/sys_gen/tst_rlink/nexys3/tb/tb_tst_rlink_n3.vbom
0,0 → 1,7
# configure tb_nexsy3_fusp with sys_tst_rlink_n3 target; |
# use vhdl configure file (tb_tst_rlink_n3.vhd) to allow |
# that all configurations will co-exist in work library |
nexys3_fusp_aif : ../sys_tst_rlink_n3.vbom |
sys_conf = sys_conf_sim.vhd |
../../../../bplib/nexys3/tb/tb_nexys3_fusp.vbom |
tb_tst_rlink_n3.vhd |
/rtl/sys_gen/tst_rlink/nexys3/tb/tbw.dat
0,0 → 1,6
# $Id: tbw.dat 433 2011-11-27 22:04:39Z mueller $ |
# |
[tb_tst_rlink_n3] |
rlink_cext_fifo_rx = <fifo> |
rlink_cext_fifo_tx = <fifo> |
rlink_cext_conf = <null> |
/rtl/sys_gen/tst_rlink/nexys3/tb/sys_tst_rlink_n3.ucf_cpp
0,0 → 1,6
link ../sys_tst_rlink_n3.ucf_cpp |
rtl/sys_gen/tst_rlink/nexys3/tb/sys_tst_rlink_n3.ucf_cpp
Property changes :
Added: svn:special
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/sys_gen/tst_rlink/nexys3/tb/sys_conf_sim.vhd
===================================================================
--- rtl/sys_gen/tst_rlink/nexys3/tb/sys_conf_sim.vhd (nonexistent)
+++ rtl/sys_gen/tst_rlink/nexys3/tb/sys_conf_sim.vhd (revision 15)
@@ -0,0 +1,45 @@
+-- $Id: sys_conf_sim.vhd 433 2011-11-27 22:04:39Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_tst_rlink_n3 (for simulation)
+--
+-- Dependencies: -
+-- Tool versions: xst 13.1; ghdl 0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-26 433 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_clkfx_divide : positive := 1;
+ constant sys_conf_clkfx_multiply : positive := 1;
+
+ constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
+
+ constant sys_conf_hio_debounce : boolean := false; -- no debouncers
+
+ -- derived constants
+
+ constant sys_conf_clksys : integer :=
+ (100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
+ constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
+
+end package sys_conf;
Index: rtl/sys_gen/tst_rlink/nexys3/tb/tb_tst_rlink_n3_ssim.vbom
===================================================================
--- rtl/sys_gen/tst_rlink/nexys3/tb/tb_tst_rlink_n3_ssim.vbom (nonexistent)
+++ rtl/sys_gen/tst_rlink/nexys3/tb/tb_tst_rlink_n3_ssim.vbom (revision 15)
@@ -0,0 +1,6 @@
+# configure for _*sim case
+# Note: this tb uses sys_tst_rlink_n3.vbom in local directory
+# (not in .. as usual) to allow a tb specific configure !!!
+nexys2_aif = sys_tst_rlink_n3_ssim.vhd
+tb_tst_rlink_n3.vbom
+@top:tb_tst_rlink_n3
Index: rtl/sys_gen/tst_rlink/nexys3/tb/.cvsignore
===================================================================
--- rtl/sys_gen/tst_rlink/nexys3/tb/.cvsignore (nonexistent)
+++ rtl/sys_gen/tst_rlink/nexys3/tb/.cvsignore (revision 15)
@@ -0,0 +1,7 @@
+tb_tst_rlink_n3
+tb_tst_rlink_n3_[sft]sim
+rlink_cext_fifo_rx
+rlink_cext_fifo_tx
+rlink_cext_conf
+sys_tst_rlink_n3.ucf
+*.dep_ucf_cpp
Index: rtl/sys_gen/tst_rlink/nexys3/tb/Makefile
===================================================================
--- rtl/sys_gen/tst_rlink/nexys3/tb/Makefile (nonexistent)
+++ rtl/sys_gen/tst_rlink/nexys3/tb/Makefile (revision 15)
@@ -0,0 +1,34 @@
+# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2011-11-26 433 1.0 Initial version
+#
+EXE_all = tb_tst_rlink_n3
+#
+ISE_BOARD = nexys3
+ISE_PATH = xc6slx16-csg324-2
+#
+XFLOWOPT_SYN = syn_s6_speed.opt
+XFLOWOPT_IMP = imp_s6_speed.opt
+#
+.PHONY : all all_ssim all_tsim clean
+#
+all : $(EXE_all)
+all_ssim : $(EXE_all:=_ssim)
+all_tsim : $(EXE_all:=_tsim)
+#
+clean : ise_clean ghdl_clean
+ rm -f sys_tst_rlink_n3.ucf
+#
+#-----
+#
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+#
+VBOM_all = $(wildcard *.vbom)
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+include $(wildcard *.o.dep_ghdl)
+#
Index: rtl/sys_gen/tst_rlink/nexys3/tb/tb_tst_rlink_n3.vhd
===================================================================
--- rtl/sys_gen/tst_rlink/nexys3/tb/tb_tst_rlink_n3.vhd (nonexistent)
+++ rtl/sys_gen/tst_rlink/nexys3/tb/tb_tst_rlink_n3.vhd (revision 15)
@@ -0,0 +1,39 @@
+-- $Id: tb_tst_rlink_n3.vhd 435 2011-12-04 20:15:25Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_tst_rlink_n3
+-- Description: Configuration for tb_tst_rlink_n3 for tb_nexys3_fusp
+--
+-- Dependencies: sys_tst_rlink_n3
+--
+-- To test: sys_tst_rlink_n3
+--
+-- Verified:
+-- Date Rev Code ghdl ise Target Comment
+-- 2011-11-xx xxx - 0.29 13.1 O40d xc6slx16-2 u:???
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-26 433 1.0 Initial version
+------------------------------------------------------------------------------
+
+configuration tb_tst_rlink_n3 of tb_nexys3_fusp is
+
+ for sim
+ for all : nexys3_fusp_aif
+ use entity work.sys_tst_rlink_n3;
+ end for;
+ end for;
+
+end tb_tst_rlink_n3;
Index: rtl/sys_gen/tst_rlink/nexys3/tb
===================================================================
--- rtl/sys_gen/tst_rlink/nexys3/tb (nonexistent)
+++ rtl/sys_gen/tst_rlink/nexys3/tb (revision 15)
rtl/sys_gen/tst_rlink/nexys3/tb
Property changes :
Added: svn:ignore
## -0,0 +1,39 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_tst_rlink_n3
+tb_tst_rlink_n3_[sft]sim
+rlink_cext_fifo_rx
+rlink_cext_fifo_tx
+rlink_cext_conf
+sys_tst_rlink_n3.ucf
+*.dep_ucf_cpp
Index: rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.ucf_cpp
===================================================================
--- rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.ucf_cpp (nonexistent)
+++ rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.ucf_cpp (revision 15)
@@ -0,0 +1,19 @@
+## $Id: sys_tst_rlink_n3.ucf_cpp 433 2011-11-27 22:04:39Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2011-11-26 433 1.0 Initial version
+##
+
+NET "I_CLK100" TNM_NET = "I_CLK100";
+TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
+OFFSET = IN 10 ns BEFORE "I_CLK100";
+OFFSET = OUT 20 ns AFTER "I_CLK100";
+
+## std board
+##
+#include "bplib/nexys3/nexys3_pins.ucf"
+##
+## Pmod B0 - RS232
+##
+#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf"
Index: rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd
===================================================================
--- rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd (nonexistent)
+++ rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd (revision 15)
@@ -0,0 +1,242 @@
+-- $Id: sys_tst_rlink_n3.vhd 433 2011-11-27 22:04:39Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: sys_tst_rlink_n3 - syn
+-- Description: rlink tester design for nexys3
+--
+-- Dependencies: vlib/xlib/dcm_sfs
+-- vlib/genlib/clkdivce
+-- bplib/bpgen/bp_rs232_2l4l_iob
+-- bplib/bpgen/sn_humanio_rbus
+-- tst_rlink
+-- vlib/nxcramlib/nx_cram_dummy
+--
+-- Test bench: tb/tb_tst_rlink_n3
+--
+-- Target Devices: generic
+-- Tool versions: xst 13.1; ghdl 0.29
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2011-11-26 433 13.1 O40d xc6slx16-2 722 1199 36 423 t 9.7
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-26 433 1.0 Initial version (derived from sys_tst_rlink_n2)
+------------------------------------------------------------------------------
+-- Usage of Nexys 3 Switches, Buttons, LEDs:
+--
+-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
+-- 1 -> Pmod B/top RS232 port /
+-- (1:7): no function (only connected to s3_humanio_rbus)
+--
+-- LED(0): timer 0 busy
+-- LED(1): timer 1 busy
+-- LED(2:6): no function (only connected to s3_humanio_rbus)
+-- LED(7): RL_SER_MONI.abact
+--
+-- DSP: RL_SER_MONI.clkdiv (from auto bauder)
+-- DP(0): RL_SER_MONI.rxact
+-- DP(1): RTS_N (shows rx back preasure)
+-- DP(2): RL_SER_MONI.txact
+-- DP(3): CTS_N (shows tx back preasure)
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.genlib.all;
+use work.rblib.all;
+use work.rlinklib.all;
+use work.bpgenlib.all;
+use work.nxcramlib.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity sys_tst_rlink_n3 is -- top level
+ -- implements nexys3_fusp_aif
+ port (
+ I_CLK100 : in slbit; -- 100 MHz clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- n3 switches
+ I_BTN : in slv5; -- n3 buttons
+ O_LED : out slv8; -- n3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_PPCM_CE_N : out slbit; -- ppcm: ...
+ O_PPCM_RST_N : out slbit; -- ppcm: ...
+ O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
+ I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
+ I_FUSP_RXD : in slbit; -- fusp: rs232 rx
+ O_FUSP_TXD : out slbit -- fusp: rs232 tx
+ );
+end sys_tst_rlink_n3;
+
+architecture syn of sys_tst_rlink_n3 is
+
+ signal CLK : slbit := '0';
+
+ signal RXD : slbit := '1';
+ signal TXD : slbit := '0';
+ signal RTS_N : slbit := '0';
+ signal CTS_N : slbit := '0';
+
+ signal SWI : slv8 := (others=>'0');
+ signal BTN : slv5 := (others=>'0');
+ signal LED : slv8 := (others=>'0');
+ signal DSP_DAT : slv16 := (others=>'0');
+ signal DSP_DP : slv4 := (others=>'0');
+
+ signal RESET : slbit := '0';
+ signal CE_USEC : slbit := '0';
+ signal CE_MSEC : slbit := '0';
+
+ signal RB_MREQ_TOP : rb_mreq_type := rb_mreq_init;
+ signal RB_SRES_TOP : rb_sres_type := rb_sres_init;
+ signal RL_SER_MONI : rl_ser_moni_type := rl_ser_moni_init;
+ signal STAT : slv8 := (others=>'0');
+
+ constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
+
+begin
+
+ assert (sys_conf_clksys mod 1000000) = 0
+ report "assert sys_conf_clksys on MHz grid"
+ severity failure;
+
+ RESET <= '0'; -- so far not used
+
+ DCM : dcm_sfs
+ generic map (
+ CLKFX_DIVIDE => sys_conf_clkfx_divide,
+ CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
+ CLKIN_PERIOD => 10.0)
+ port map (
+ CLKIN => I_CLK100,
+ CLKFX => CLK,
+ LOCKED => open
+ );
+
+ CLKDIV : clkdivce
+ generic map (
+ CDUWIDTH => 7,
+ USECDIV => sys_conf_clksys_mhz,
+ MSECDIV => 1000)
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC
+ );
+
+ IOB_RS232 : bp_rs232_2l4l_iob
+ port map (
+ CLK => CLK,
+ RESET => '0',
+ SEL => SWI(0),
+ RXD => RXD,
+ TXD => TXD,
+ CTS_N => CTS_N,
+ RTS_N => RTS_N,
+ I_RXD0 => I_RXD,
+ O_TXD0 => O_TXD,
+ I_RXD1 => I_FUSP_RXD,
+ O_TXD1 => O_FUSP_TXD,
+ I_CTS1_N => I_FUSP_CTS_N,
+ O_RTS1_N => O_FUSP_RTS_N
+ );
+
+ HIO : sn_humanio_rbus
+ generic map (
+ BWIDTH => 5,
+ DEBOUNCE => sys_conf_hio_debounce,
+ RB_ADDR => rbaddr_hio)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CE_MSEC => CE_MSEC,
+ RB_MREQ => RB_MREQ_TOP,
+ RB_SRES => RB_SRES_TOP,
+ SWI => SWI,
+ BTN => BTN,
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => O_LED,
+ O_ANO_N => O_ANO_N,
+ O_SEG_N => O_SEG_N
+ );
+
+ RLTEST : entity work.tst_rlink
+ generic map (
+ CDINIT => sys_conf_ser2rri_cdinit)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC,
+ RXD => RXD,
+ TXD => TXD,
+ CTS_N => CTS_N,
+ RTS_N => RTS_N,
+ RB_MREQ_TOP => RB_MREQ_TOP,
+ RB_SRES_TOP => RB_SRES_TOP,
+ RL_SER_MONI => RL_SER_MONI,
+ STAT => STAT
+ );
+
+ SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
+ port map (
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
+ O_PPCM_RST_N <= '1'; --
+
+ DSP_DAT <= RL_SER_MONI.clkdiv;
+ DSP_DP(0) <= RL_SER_MONI.rxact;
+ DSP_DP(1) <= RTS_N;
+ DSP_DP(2) <= RL_SER_MONI.txact;
+ DSP_DP(3) <= CTS_N;
+
+ LED(7) <= RL_SER_MONI.abact;
+ LED(6 downto 2) <= (others=>'0');
+ LED(1) <= STAT(1);
+ LED(0) <= STAT(0);
+
+end syn;
Index: rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom
===================================================================
--- rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom (nonexistent)
+++ rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom (revision 15)
@@ -0,0 +1,20 @@
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/xlib/xlib.vhd
+../../../vlib/genlib/genlib.vhd
+../../../vlib/rbus/rblib.vhd
+../../../vlib/rlink/rlinklib.vbom
+../../../bplib/bpgen/bpgenlib.vbom
+../../../bplib/nxcramlib/nxcramlib.vhd
+sys_conf : sys_conf.vhd
+# components
+[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
+[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
+../../../vlib/genlib/clkdivce.vbom
+../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
+../../../bplib/bpgen/sn_humanio_rbus.vbom
+../tst_rlink.vbom
+../../../bplib/nxcramlib/nx_cram_dummy.vbom
+# design
+sys_tst_rlink_n3.vhd
+@ucf_cpp: sys_tst_rlink_n3.ucf
Index: rtl/sys_gen/tst_rlink/nexys3/Makefile
===================================================================
--- rtl/sys_gen/tst_rlink/nexys3/Makefile (nonexistent)
+++ rtl/sys_gen/tst_rlink/nexys3/Makefile (revision 15)
@@ -0,0 +1,30 @@
+# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2011-11-26 433 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+BIT_all = $(VBOM_all:.vbom=.bit)
+#
+ISE_BOARD = nexys3
+ISE_PATH = xc6slx16-csg324-2
+#
+XFLOWOPT_SYN = syn_s6_speed.opt
+XFLOWOPT_IMP = imp_s6_speed.opt
+#
+.PHONY : all clean
+#
+all : $(BIT_all)
+#
+clean : ise_clean
+ rm -f sys_tst_rlink_n3.ucf
+#
+#----
+#
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+#
Index: rtl/sys_gen/tst_rlink/nexys3/.cvsignore
===================================================================
--- rtl/sys_gen/tst_rlink/nexys3/.cvsignore (nonexistent)
+++ rtl/sys_gen/tst_rlink/nexys3/.cvsignore (revision 15)
@@ -0,0 +1,4 @@
+_impactbatch.log
+sys_tst_rlink_n3.ucf
+*.dep_ucf_cpp
+*.svf
Index: rtl/sys_gen/tst_rlink/nexys3
===================================================================
--- rtl/sys_gen/tst_rlink/nexys3 (nonexistent)
+++ rtl/sys_gen/tst_rlink/nexys3 (revision 15)
rtl/sys_gen/tst_rlink/nexys3
Property changes :
Added: svn:ignore
## -0,0 +1,36 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+_impactbatch.log
+sys_tst_rlink_n3.ucf
+*.dep_ucf_cpp
+*.svf
Index: rtl/sys_gen/w11a/tb/dorri
===================================================================
--- rtl/sys_gen/w11a/tb/dorri (revision 14)
+++ rtl/sys_gen/w11a/tb/dorri (revision 15)
@@ -1,8 +1,9 @@
#!/usr/bin/perl -w
-# $Id: dorri 296 2010-05-29 21:45:09Z mueller $
+# $Id: dorri 435 2011-12-04 20:15:25Z mueller $
#
# Revision History:
# Date Rev Version Comment
+# 2011-12-03 435 1.5 add w11a_n3 support; add break/flow control to -u
# 2010-05-29 296 1.4 allow -ux,baud (usb devnum and baudrate)
# 2010-05-28 295 1.3 w11a_s3/w11a_n2 support: -s3 and -n2 instead of -f
# add -tmu option
@@ -30,6 +31,7 @@
my $val_log="rri.log";
my $val_tb_s3="tbw ../s3board/tb/tb_w11a_s3";
my $val_tb_n2="tbw ../nexys2/tb/tb_w11a_n2";
+my $val_tb_n3="tbw ../nexys3/tb/tb_w11a_n3";
my $val_tb;
my $val_e;
@@ -65,30 +67,35 @@
$opt_io = "f";
$val_tb = $val_tb_n2;
shift @ARGV;
+ } elsif ($curarg =~ m{^-n3$} ) { # -n3
+ $opt_io = "f";
+ $val_tb = $val_tb_n3;
+ shift @ARGV;
} elsif ($curarg =~ m{^-t$} ) { # -t
$opt_io = "t";
- } elsif ($curarg =~ m{^-u(\d)} ) { # -ux...
+ } elsif ($curarg =~ m{^-u(\d),?} ) { # -ux...
my $devnum = $1;
- my $rest = $';
- my $baudspec = "115";
+ my ($dev,$baud,$break,$flow) = split /,/,$curarg;
+ $baud = "115" unless defined $baud;
+ $break = 1 unless defined $break; # default: break
+ $flow = 1 unless defined $flow; # default: cts
+
+ if ($baud !~ m{^\d*$} || $break !~ m{^[01]$} || $flow !~ m{^[012]$}) {
+ print STDERR "dorri-E: invalid format of -u option\n";
+ exit 1;
+ }
+
my $baudrate;
- if ($rest ne "") {
- if ($rest =~ m{^,(\d*)$}) {
- $baudspec = $1;
- } else {
- print STDERR "dorri-E: invalid format of -u option\n";
- exit 1;
- }
- }
- if (defined $baudtbl{$baudspec}) {
- $baudrate = $baudtbl{$baudspec};
+ if (defined $baudtbl{$baud}) {
+ $baudrate = $baudtbl{$baud};
} else {
- print STDERR "dorri-E: invalid baudrate specification\n";
+ print STDERR "dorri-E: invalid baudrate specification $baud\n";
exit 1;
}
$opt_io = "t";
- $val_term = sprintf "/dev/ttyUSB%d,%d,1", $devnum, $baudrate;
+ $val_term = sprintf "/dev/ttyUSB%d,%d,%d,%d",
+ $devnum, $baudrate, $break, $flow;
shift @ARGV;
} elsif ($curarg =~ m{^-e$} ) { # -e
@@ -121,7 +128,7 @@
}
#
-# check that either -s3/n2 or -t given
+# check that either -s3/n2/n3 or -t given
# setup pi_rri options for either case
#
@@ -132,7 +139,7 @@
} elsif ($opt_io eq "t") {
push @arglist, "--term=$val_term";
} else {
- print STDERR "dorri-E: neither -s3/-n2 nor -t specified\n";
+ print STDERR "dorri-E: neither -s3/-n2/-n3 nor -t specified\n";
print_usage();
exit 1;
}
/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 341 2010-11-27 23:05:43Z mueller $ |
-- $Id: sys_conf_sim.vhd 433 2011-11-27 22:04:39Z mueller $ |
-- |
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
16,9 → 16,10
-- Description: Definitions for sys_w11a_n2 (for simulation) |
-- |
-- Dependencies: - |
-- Tool versions: xst 11.4; ghdl 0.26 |
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-27 433 1.1.1 use /1*1 to skip dcm in sim, _ssim fails with dcm |
-- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58) |
-- 2010-05-28 295 1.0 Initial version (cloned from _s3) |
------------------------------------------------------------------------------ |
30,8 → 31,10
|
package sys_conf is |
|
constant sys_conf_clkfx_divide : positive := 25; |
constant sys_conf_clkfx_multiply : positive := 29; -- ==> 58 MHz |
constant sys_conf_clkfx_divide : positive := 1; |
constant sys_conf_clkfx_multiply : positive := 1; -- no dcm in sim... |
-- constant sys_conf_clkfx_divide : positive := 25; |
-- constant sys_conf_clkfx_multiply : positive := 28; -- ==> 56 MHz |
|
constant sys_conf_memctl_read0delay : positive := 3; |
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; |
/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
1,4 → 1,4
-- $Id: sys_w11a_n2.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- $Id: sys_w11a_n2.vhd 433 2011-11-27 22:04:39Z mueller $ |
-- |
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
24,10 → 24,10
-- w11a/pdp11_core_rbus |
-- w11a/pdp11_core |
-- w11a/pdp11_bram |
-- vlib/nexys2/n2_cram_dummy |
-- vlib/nxcramlib/nx_cram_dummy |
-- w11a/pdp11_cache |
-- w11a/pdp11_mem70 |
-- bplib/nexys2/n2_cram_memctl |
-- bplib/nxcramlib/nx_cram_memctl_as |
-- ibus/ib_sres_or_2 |
-- ibus/ibdr_minisys |
-- ibus/ibdr_maxisys |
63,6 → 63,8
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-26 433 1.2.6 use nx_cram_(dummy|memctl_as) now |
-- 2011-11-23 432 1.2.5 update O_FLA_CE_N usage |
-- 2011-11-19 427 1.2.4 now numeric_std clean |
-- 2011-11-17 426 1.2.3 use dcm_sfs now |
-- 2011-07-09 391 1.2.2 use now bp_rs232_2l4l_iob |
122,7 → 124,7
use work.rblib.all; |
use work.rlinklib.all; |
use work.bpgenlib.all; |
use work.nexys2lib.all; |
use work.nxcramlib.all; |
use work.iblib.all; |
use work.ibdlib.all; |
use work.pdp11.all; |
137,9 → 139,9
O_CLKSYS : out slbit; -- DCM derived system clock |
I_RXD : in slbit; -- receive data (board view) |
O_TXD : out slbit; -- transmit data (board view) |
I_SWI : in slv8; -- s3 switches |
I_BTN : in slv4; -- s3 buttons |
O_LED : out slv8; -- s3 leds |
I_SWI : in slv8; -- n2 switches |
I_BTN : in slv4; -- n2 buttons |
O_LED : out slv8; -- n2 leds |
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) |
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) |
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) |
150,9 → 152,9
O_MEM_CLK : out slbit; -- cram: clock |
O_MEM_CRE : out slbit; -- cram: command register enable |
I_MEM_WAIT : in slbit; -- cram: mem wait |
O_FLA_CE_N : out slbit; -- flash ce.. (act.low) |
O_MEM_ADDR : out slv23; -- cram: address lines |
IO_MEM_DATA : inout slv16; -- cram: data lines |
O_FLA_CE_N : out slbit; -- flash ce.. (act.low) |
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n |
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n |
I_FUSP_RXD : in slbit; -- fusp: rs232 rx |
409,7 → 411,7
IB_SRES => IB_SRES_MEM70 |
); |
|
SRAM_PROT : n2_cram_dummy -- connect CRAM to protection dummy |
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy |
port map ( |
O_MEM_CE_N => O_MEM_CE_N, |
O_MEM_BE_N => O_MEM_BE_N, |
419,10 → 421,11
O_MEM_CLK => O_MEM_CLK, |
O_MEM_CRE => O_MEM_CRE, |
I_MEM_WAIT => I_MEM_WAIT, |
O_FLA_CE_N => O_FLA_CE_N, |
O_MEM_ADDR => O_MEM_ADDR, |
IO_MEM_DATA => IO_MEM_DATA |
); |
|
O_FLA_CE_N <= '1'; -- keep Flash memory disabled |
|
end generate MEM_BRAM; |
|
462,7 → 465,7
|
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) |
|
SRAM_CTL: n2_cram_memctl_as |
SRAM_CTL: nx_cram_memctl_as |
generic map ( |
READ0DELAY => sys_conf_memctl_read0delay, |
READ1DELAY => sys_conf_memctl_read1delay, |
489,10 → 492,11
O_MEM_CLK => O_MEM_CLK, |
O_MEM_CRE => O_MEM_CRE, |
I_MEM_WAIT => I_MEM_WAIT, |
O_FLA_CE_N => O_FLA_CE_N, |
O_MEM_ADDR => O_MEM_ADDR, |
IO_MEM_DATA => IO_MEM_DATA |
); |
|
O_FLA_CE_N <= '1'; -- keep Flash memory disabled |
|
end generate MEM_SRAM; |
|
/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom
5,7 → 5,7
../../../vlib/rbus/rblib.vhd |
../../../vlib/rlink/rlinklib.vbom |
../../../bplib/bpgen/bpgenlib.vbom |
../../../bplib/nexys2/nexys2lib.vhd |
../../../bplib/nxcramlib/nxcramlib.vhd |
../../../ibus/iblib.vhd |
../../../ibus/ibdlib.vhd |
../../../w11a/pdp11.vhd |
21,10 → 21,10
../../../w11a/pdp11_core_rbus.vbom |
../../../w11a/pdp11_core.vbom |
../../../w11a/pdp11_bram.vbom |
../../../bplib/nexys2/n2_cram_dummy.vbom |
../../../bplib/nxcramlib/nx_cram_dummy.vbom |
../../../w11a/pdp11_cache.vbom |
../../../w11a/pdp11_mem70.vbom |
../../../bplib/nexys2/n2_cram_memctl_as.vbom |
../../../bplib/nxcramlib/nx_cram_memctl_as.vbom |
../../../ibus/ib_sres_or_2.vbom |
../../../ibus/ibdr_minisys.vbom |
../../../ibus/ibdr_maxisys.vbom |
/rtl/sys_gen/w11a/nexys3/sys_conf.vhd
0,0 → 1,85
-- $Id: sys_conf.vhd 433 2011-11-27 22:04:39Z mueller $ |
-- |
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Package Name: sys_conf |
-- Description: Definitions for sys_w11a_n3 (for synthesis) |
-- |
-- Dependencies: - |
-- Tool versions: xst 13.1; ghdl 0.29 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-26 433 1.0.1 use 80 MHz clksys (no closure for 85 after rev 432) |
-- 2011-11-20 430 1.0 Initial version (derived from _n2 version) |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
|
-- valid system clock / delay combinations (see n2_cram_memctl_as.vhd): |
-- div mul clksys read0 read1 write |
-- 2 1 50.0 2 2 3 |
-- 4 3 75.0 4 4 5 (also 70 MHz) |
-- 5 4 80.0 5 5 5 |
-- 20 17 85.0 5 5 6 |
-- 10 9 90.0 6 6 6 (also 95 MHz) |
-- 1 1 100.0 6 6 7 |
|
package sys_conf is |
|
constant sys_conf_clkfx_divide : positive := 5; |
constant sys_conf_clkfx_multiply : positive := 4; -- ==> 80 MHz |
|
constant sys_conf_memctl_read0delay : positive := 5; |
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; |
constant sys_conf_memctl_writedelay : positive := 5; |
|
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud |
|
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers |
|
constant sys_conf_bram : integer := 0; -- no bram, use cache |
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) |
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte |
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) |
|
-- constant sys_conf_bram : integer := 1; -- bram only |
-- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB) |
-- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
|
-- derived constants |
|
constant sys_conf_clksys : integer := |
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; |
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; |
|
constant sys_conf_ser2rri_cdinit : integer := |
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; |
|
end package sys_conf; |
|
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory |
-- 2 211 111 111 110 000 000 000 |
-- 1 098 765 432 109 876 543 210 |
-- |
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte |
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte |
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte |
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte |
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte |
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte |
-- upper 256 kB excluded for 11/70 UB |
/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.mfset
0,0 → 1,36
# $Id: sys_w11a_n3.mfset 433 2011-11-27 22:04:39Z mueller $ |
# |
# ---------------------------------------------------------------------------- |
[xst] |
INFO:.*Case statement is complete. others clause is never selected |
INFO:.*The small RAM <.*> will be implemented on LUTs |
|
sys_w11a_n3\..*Output port <LOCKED> of the instance <DCM> is unconnected |
sys_w11a_n3\..*Output port <BTN> of the instance <HIO> is unconnected |
sys_w11a_n3\..*Output port <RL_SER_MONI_.*> of the instance <RLINK> is unconnected |
sys_w11a_n3\..*Output port <RL_MONI_.*> of the instance <RLINK> is unconnected |
sys_w11a_n3\..*Output port <DM_STAT_.*> of the instance <CORE> is unconnected |
# |
# ---------------------------------------------------------------------------- |
[tra] |
INFO:.*TNM 'I_CLK100'.*was traced into DCM_SP |
INFO:.*Setting CLKIN_PERIOD attribute associated with DCM instance |
# |
# ---------------------------------------------------------------------------- |
[map] |
WARNING:.*has the attribute CLK_FEEDBACK set to NONE |
WARNING:.*The signal <I_MEM_WAIT_IBUF> is incomplete |
WARNING:.*to use input parity pin.*dangling output for parity pin |
INFO:.* |
# |
# ---------------------------------------------------------------------------- |
[par] |
WARNING:.*has the attribute CLK_FEEDBACK set to NONE |
WARNING:.*The signal I_MEM_WAIT_IBUF has no load |
WARNING:.*There are 1 loadless signals in this design |
# |
# ---------------------------------------------------------------------------- |
[bgn] |
WARNING:.*The signal <I_MEM_WAIT_IBUF> is incomplete |
WARNING:.*to use input parity pin.*dangling output for parity pin |
INFO:.*To achieve optimal frequency synthesis performance |
/rtl/sys_gen/w11a/nexys3/tb/tb_w11a_n3.vbom
0,0 → 1,7
# configure tb_nexys3_fusp with sys_w11a_n3 target; |
# use vhdl configure file (tb_w11a_n3.vhd) to allow |
# that all configurations will co-exist in work library |
nexys3_fusp_aif = ../sys_w11a_n3.vbom |
sys_conf = sys_conf_sim.vhd |
../../../../bplib/nexys3/tb/tb_nexys3_fusp.vbom |
tb_w11a_n3.vhd |
/rtl/sys_gen/w11a/nexys3/tb/tbw.dat
0,0 → 1,6
# $Id: tbw.dat 432 2011-11-25 20:16:28Z mueller $ |
# |
[tb_w11a_n3] |
rlink_cext_fifo_rx = <fifo> |
rlink_cext_fifo_tx = <fifo> |
rlink_cext_conf = <null> |
/rtl/sys_gen/w11a/nexys3/tb/sys_w11a_n3.ucf_cpp
0,0 → 1,6
link ../sys_w11a_n3.ucf_cpp |
rtl/sys_gen/w11a/nexys3/tb/sys_w11a_n3.ucf_cpp
Property changes :
Added: svn:special
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/sys_gen/w11a/nexys3/tb/tb_w11a_n3_ssim.vbom
===================================================================
--- rtl/sys_gen/w11a/nexys3/tb/tb_w11a_n3_ssim.vbom (nonexistent)
+++ rtl/sys_gen/w11a/nexys3/tb/tb_w11a_n3_ssim.vbom (revision 15)
@@ -0,0 +1,6 @@
+# configure for _*sim case
+# Note: this tb uses sys_w11a_n3.vbom in local directory
+# (not in .. as usual) to allow a tb specific configure !!!
+nexys3_fusp_aif = sys_w11a_n3_ssim.vhd
+tb_w11a_n3.vbom
+@top:tb_w11a_n3
Index: rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd
===================================================================
--- rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd (nonexistent)
+++ rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd (revision 15)
@@ -0,0 +1,74 @@
+-- $Id: sys_conf_sim.vhd 433 2011-11-27 22:04:39Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_w11a_n3 (for simulation)
+--
+-- Dependencies: -
+-- Tool versions: xst 13.1; ghdl 0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-25 432 1.0 Initial version (cloned from _n3)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_clkfx_divide : positive := 1;
+ constant sys_conf_clkfx_multiply : positive := 1; -- no dcm in sim...
+-- constant sys_conf_clkfx_divide : positive := 5;
+-- constant sys_conf_clkfx_multiply : positive := 4; -- ==> 80 MHz
+
+ constant sys_conf_memctl_read0delay : positive := 6; -- for 100 MHz
+ constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
+ constant sys_conf_memctl_writedelay : positive := 7;
+
+ constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
+
+ constant sys_conf_hio_debounce : boolean := false; -- no debouncers
+
+ constant sys_conf_bram : integer := 0; -- no bram, use cache
+ constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
+ constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
+--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
+
+-- constant sys_conf_bram : integer := 1; -- bram only
+-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB)
+-- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte
+
+ constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
+
+ -- derived constants
+
+ constant sys_conf_clksys : integer :=
+ (100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
+ constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
+
+end package sys_conf;
+
+-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
+-- 2 211 111 111 110 000 000 000
+-- 1 098 765 432 109 876 543 210
+--
+-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
+-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
+-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
+-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
+-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
+-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
+-- upper 256 kB excluded for 11/70 UB
Index: rtl/sys_gen/w11a/nexys3/tb/Makefile
===================================================================
--- rtl/sys_gen/w11a/nexys3/tb/Makefile (nonexistent)
+++ rtl/sys_gen/w11a/nexys3/tb/Makefile (revision 15)
@@ -0,0 +1,33 @@
+# $Id: Makefile 432 2011-11-25 20:16:28Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2011-11-25 432 1.0 Initial version
+#
+EXE_all = tb_w11a_n3
+#
+ISE_PATH = xc6slx16-csg324-2
+#
+XFLOWOPT_SYN = syn_s6_speed.opt
+XFLOWOPT_IMP = imp_s6_speed.opt
+#
+#
+.PHONY : all all_ssim all_tsim clean
+#
+all : $(EXE_all)
+all_ssim : $(EXE_all:=_ssim)
+all_tsim : $(EXE_all:=_tsim)
+#
+clean : ise_clean ghdl_clean
+#
+#-----
+#
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+#
+VBOM_all = $(wildcard *.vbom)
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+include $(wildcard *.o.dep_ghdl)
+#
Index: rtl/sys_gen/w11a/nexys3/tb/.cvsignore
===================================================================
--- rtl/sys_gen/w11a/nexys3/tb/.cvsignore (nonexistent)
+++ rtl/sys_gen/w11a/nexys3/tb/.cvsignore (revision 15)
@@ -0,0 +1,8 @@
+tb_w11a_n3
+tb_w11a_n3_[sft]sim
+rlink_cext_fifo_rx
+rlink_cext_fifo_tx
+rlink_cext_conf
+tmu_ofile
+sys_w11a_n3.ucf
+*.dep_ucf_cpp
Index: rtl/sys_gen/w11a/nexys3/tb/tb_w11a_n3.vhd
===================================================================
--- rtl/sys_gen/w11a/nexys3/tb/tb_w11a_n3.vhd (nonexistent)
+++ rtl/sys_gen/w11a/nexys3/tb/tb_w11a_n3.vhd (revision 15)
@@ -0,0 +1,40 @@
+-- $Id: tb_w11a_n3.vhd 432 2011-11-25 20:16:28Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_w11a_n3
+-- Description: Configuration for tb_w11a_n3 for tb_nexys3_fusp
+--
+-- Dependencies: sys_w11a_n3
+--
+-- To test: sys_w11a_n3
+--
+-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat
+-- (#2) ../../tb/tb_pdp11_core_stim.dat):
+-- Date Rev Code ghdl ise Target Comment
+-- 2011-11-25 295 - -.-- - - -:--
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-25 432 1.0 Initial version (cloned from _n2)
+------------------------------------------------------------------------------
+
+configuration tb_w11a_n3 of tb_nexys3_fusp is
+
+ for sim
+ for all : nexys3_fusp_aif
+ use entity work.sys_w11a_n3;
+ end for;
+ end for;
+
+end tb_w11a_n3;
Index: rtl/sys_gen/w11a/nexys3/tb
===================================================================
--- rtl/sys_gen/w11a/nexys3/tb (nonexistent)
+++ rtl/sys_gen/w11a/nexys3/tb (revision 15)
rtl/sys_gen/w11a/nexys3/tb
Property changes :
Added: svn:ignore
## -0,0 +1,40 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_w11a_n3
+tb_w11a_n3_[sft]sim
+rlink_cext_fifo_rx
+rlink_cext_fifo_tx
+rlink_cext_conf
+tmu_ofile
+sys_w11a_n3.ucf
+*.dep_ucf_cpp
Index: rtl/sys_gen/w11a/nexys3/sys_w11a_n3.ucf_cpp
===================================================================
--- rtl/sys_gen/w11a/nexys3/sys_w11a_n3.ucf_cpp (nonexistent)
+++ rtl/sys_gen/w11a/nexys3/sys_w11a_n3.ucf_cpp (revision 15)
@@ -0,0 +1,19 @@
+## $Id: sys_w11a_n3.ucf_cpp 430 2011-11-20 20:48:39Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2011-11-20 430 1.0 Initial version
+##
+
+NET "I_CLK100" TNM_NET = "I_CLK100";
+TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
+OFFSET = IN 10 ns BEFORE "I_CLK100";
+OFFSET = OUT 20 ns AFTER "I_CLK100";
+
+## std board
+##
+#include "bplib/nexys3/nexys3_pins.ucf"
+##
+## Pmod B0 - RS232
+##
+#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf"
Index: rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd
===================================================================
--- rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd (nonexistent)
+++ rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd (revision 15)
@@ -0,0 +1,564 @@
+-- $Id: sys_w11a_n3.vhd 435 2011-12-04 20:15:25Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: sys_w11a_n3 - syn
+-- Description: w11a test design for nexys3
+--
+-- Dependencies: vlib/xlib/dcm_sfs
+-- vlib/genlib/clkdivce
+-- bplib/bpgen/bp_rs232_2l4l_iob
+-- bplib/bpgen/sn_humanio_rbus
+-- vlib/rlink/rlink_base_serport
+-- vlib/rri/rb_sres_or_3
+-- w11a/pdp11_core_rbus
+-- w11a/pdp11_core
+-- w11a/pdp11_bram
+-- vlib/nxcramlib/nx_cram_dummy
+-- w11a/pdp11_cache
+-- w11a/pdp11_mem70
+-- bplib/nxcramlib/nx_cram_memctl_as
+-- ibus/ib_sres_or_2
+-- ibus/ibdr_minisys
+-- ibus/ibdr_maxisys
+-- w11a/pdp11_tmu_sb [sim only]
+--
+-- Test bench: tb/tb_sys_w11a_n3
+--
+-- Target Devices: generic
+-- Tool versions: xst 13.1; ghdl 0.29
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks)
+-- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now
+-- 2011-11-23 432 1.0.1 fixup PPCM handling
+-- 2011-11-20 430 1.0 Initial version (derived from sys_w11a_n2)
+------------------------------------------------------------------------------
+--
+-- w11a test design for nexys3
+-- w11a + rlink + serport
+--
+-- Usage of Nexys 3 Switches, Buttons, LEDs:
+--
+-- SWI(0): 0 -> main board RS232 port
+-- 1 -> Pmod B/top RS232 port
+--
+-- LED(0:4): if cpugo=1 show cpu mode activity
+-- (0) user mode
+-- (1) supervisor mode
+-- (2) kernel mode, wait
+-- (3) kernel mode, pri=0
+-- (4) kernel mode, pri>0
+-- if cpugo=0 shows cpurust
+-- (3:0) cpurust code
+-- (4) '1'
+-- (5) cmdbusy (all rlink access, mostly rdma)
+-- (6) MEM_ACT_R
+-- (7) MEM_ACT_W
+--
+-- DP(0): RXSD (inverted to signal activity)
+-- DP(1): RTS_N (shows rx back preasure)
+-- DP(2): TXSD (inverted to signal activity)
+-- DP(3): CTS_N (shows tx back preasure)
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.genlib.all;
+use work.rblib.all;
+use work.rlinklib.all;
+use work.bpgenlib.all;
+use work.nxcramlib.all;
+use work.iblib.all;
+use work.ibdlib.all;
+use work.pdp11.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity sys_w11a_n3 is -- top level
+ -- implements nexys3_fusp_aif
+ port (
+ I_CLK100 : in slbit; -- 100 MHz clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- n3 switches
+ I_BTN : in slv5; -- n3 buttons
+ O_LED : out slv8; -- n3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_PPCM_CE_N : out slbit; -- ppcm: ...
+ O_PPCM_RST_N : out slbit; -- ppcm: ...
+ O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
+ I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
+ I_FUSP_RXD : in slbit; -- fusp: rs232 rx
+ O_FUSP_TXD : out slbit -- fusp: rs232 tx
+ );
+end sys_w11a_n3;
+
+architecture syn of sys_w11a_n3 is
+
+ signal CLK : slbit := '0';
+
+ signal RXD : slbit := '1';
+ signal TXD : slbit := '0';
+ signal RTS_N : slbit := '0';
+ signal CTS_N : slbit := '0';
+
+ signal SWI : slv8 := (others=>'0');
+ signal BTN : slv5 := (others=>'0');
+ signal LED : slv8 := (others=>'0');
+ signal DSP_DAT : slv16 := (others=>'0');
+ signal DSP_DP : slv4 := (others=>'0');
+
+ signal RB_LAM : slv16 := (others=>'0');
+ signal RB_STAT : slv3 := (others=>'0');
+
+ signal RB_MREQ : rb_mreq_type := rb_mreq_init;
+ signal RB_SRES : rb_sres_type := rb_sres_init;
+ signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
+ signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
+ signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
+
+ signal RESET : slbit := '0';
+ signal CE_USEC : slbit := '0';
+ signal CE_MSEC : slbit := '0';
+
+ signal CPU_RESET : slbit := '0';
+ signal CP_CNTL : cp_cntl_type := cp_cntl_init;
+ signal CP_ADDR : cp_addr_type := cp_addr_init;
+ signal CP_DIN : slv16 := (others=>'0');
+ signal CP_STAT : cp_stat_type := cp_stat_init;
+ signal CP_DOUT : slv16 := (others=>'0');
+
+ signal EI_PRI : slv3 := (others=>'0');
+ signal EI_VECT : slv9_2 := (others=>'0');
+ signal EI_ACKM : slbit := '0';
+
+ signal EM_MREQ : em_mreq_type := em_mreq_init;
+ signal EM_SRES : em_sres_type := em_sres_init;
+
+ signal HM_ENA : slbit := '0';
+ signal MEM70_FMISS : slbit := '0';
+ signal CACHE_FMISS : slbit := '0';
+ signal CACHE_CHIT : slbit := '0';
+
+ signal MEM_REQ : slbit := '0';
+ signal MEM_WE : slbit := '0';
+ signal MEM_BUSY : slbit := '0';
+ signal MEM_ACK_R : slbit := '0';
+ signal MEM_ACT_R : slbit := '0';
+ signal MEM_ACT_W : slbit := '0';
+ signal MEM_ADDR : slv20 := (others=>'0');
+ signal MEM_BE : slv4 := (others=>'0');
+ signal MEM_DI : slv32 := (others=>'0');
+ signal MEM_DO : slv32 := (others=>'0');
+
+ signal MEM_ADDR_EXT : slv22 := (others=>'0');
+
+ signal BRESET : slbit := '0';
+ signal IB_MREQ : ib_mreq_type := ib_mreq_init;
+ signal IB_SRES : ib_sres_type := ib_sres_init;
+
+ signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
+ signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
+
+ signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
+ signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
+ signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
+ signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
+
+ signal DISPREG : slv16 := (others=>'0');
+
+ constant rbaddr_core0 : slv8 := "00000000";
+ constant rbaddr_ibus : slv8 := "10000000";
+ constant rbaddr_hio : slv8 := "11000000";
+
+begin
+
+ assert (sys_conf_clksys mod 1000000) = 0
+ report "assert sys_conf_clksys on MHz grid"
+ severity failure;
+
+ DCM : dcm_sfs
+ generic map (
+ CLKFX_DIVIDE => sys_conf_clkfx_divide,
+ CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
+ CLKIN_PERIOD => 10.0)
+ port map (
+ CLKIN => I_CLK100,
+ CLKFX => CLK,
+ LOCKED => open
+ );
+
+ CLKDIV : clkdivce
+ generic map (
+ CDUWIDTH => 7,
+ USECDIV => sys_conf_clksys_mhz,
+ MSECDIV => 1000)
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC
+ );
+
+ IOB_RS232 : bp_rs232_2l4l_iob
+ port map (
+ CLK => CLK,
+ RESET => '0',
+ SEL => SWI(0),
+ RXD => RXD,
+ TXD => TXD,
+ CTS_N => CTS_N,
+ RTS_N => RTS_N,
+ I_RXD0 => I_RXD,
+ O_TXD0 => O_TXD,
+ I_RXD1 => I_FUSP_RXD,
+ O_TXD1 => O_FUSP_TXD,
+ I_CTS1_N => I_FUSP_CTS_N,
+ O_RTS1_N => O_FUSP_RTS_N
+ );
+
+ HIO : sn_humanio_rbus
+ generic map (
+ BWIDTH => 5,
+ DEBOUNCE => sys_conf_hio_debounce,
+ RB_ADDR => rbaddr_hio)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CE_MSEC => CE_MSEC,
+ RB_MREQ => RB_MREQ,
+ RB_SRES => RB_SRES_HIO,
+ SWI => SWI,
+ BTN => BTN,
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => O_LED,
+ O_ANO_N => O_ANO_N,
+ O_SEG_N => O_SEG_N
+ );
+
+ RLINK : rlink_base_serport
+ generic map (
+ ATOWIDTH => 7, -- 128 cycles access timeout
+ ITOWIDTH => 6, -- 64 periods max idle timeout
+ IFAWIDTH => 5, -- 32 word input fifo
+ OFAWIDTH => 0, -- no output fifo
+ CDWIDTH => 13,
+ CDINIT => sys_conf_ser2rri_cdinit)
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC,
+ CE_INT => CE_MSEC,
+ RESET => RESET,
+ RXSD => RXD,
+ TXSD => TXD,
+ CTS_N => CTS_N,
+ RTS_N => RTS_N,
+ RB_MREQ => RB_MREQ,
+ RB_SRES => RB_SRES,
+ RB_LAM => RB_LAM,
+ RB_STAT => RB_STAT,
+ RL_MONI => open,
+ RL_SER_MONI => open
+ );
+
+ RB_SRES_OR : rb_sres_or_3
+ port map (
+ RB_SRES_1 => RB_SRES_CPU,
+ RB_SRES_2 => RB_SRES_IBD,
+ RB_SRES_3 => RB_SRES_HIO,
+ RB_SRES_OR => RB_SRES
+ );
+
+ RB2CP : pdp11_core_rbus
+ generic map (
+ RB_ADDR_CORE => rbaddr_core0,
+ RB_ADDR_IBUS => rbaddr_ibus)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ RB_MREQ => RB_MREQ,
+ RB_SRES => RB_SRES_CPU,
+ RB_STAT => RB_STAT,
+ RB_LAM => RB_LAM(0),
+ CPU_RESET => CPU_RESET,
+ CP_CNTL => CP_CNTL,
+ CP_ADDR => CP_ADDR,
+ CP_DIN => CP_DIN,
+ CP_STAT => CP_STAT,
+ CP_DOUT => CP_DOUT
+ );
+
+ CORE : pdp11_core
+ port map (
+ CLK => CLK,
+ RESET => CPU_RESET,
+ CP_CNTL => CP_CNTL,
+ CP_ADDR => CP_ADDR,
+ CP_DIN => CP_DIN,
+ CP_STAT => CP_STAT,
+ CP_DOUT => CP_DOUT,
+ EI_PRI => EI_PRI,
+ EI_VECT => EI_VECT,
+ EI_ACKM => EI_ACKM,
+ EM_MREQ => EM_MREQ,
+ EM_SRES => EM_SRES,
+ BRESET => BRESET,
+ IB_MREQ_M => IB_MREQ,
+ IB_SRES_M => IB_SRES,
+ DM_STAT_DP => DM_STAT_DP,
+ DM_STAT_VM => DM_STAT_VM,
+ DM_STAT_CO => DM_STAT_CO
+ );
+
+ MEM_BRAM: if sys_conf_bram > 0 generate
+ signal HM_VAL_BRAM : slbit := '0';
+ begin
+
+ MEM : pdp11_bram
+ generic map (
+ AWIDTH => sys_conf_bram_awidth)
+ port map (
+ CLK => CLK,
+ GRESET => CPU_RESET,
+ EM_MREQ => EM_MREQ,
+ EM_SRES => EM_SRES
+ );
+
+ HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write
+
+ MEM70: pdp11_mem70
+ port map (
+ CLK => CLK,
+ CRESET => BRESET,
+ HM_ENA => EM_MREQ.req,
+ HM_VAL => HM_VAL_BRAM,
+ CACHE_FMISS => MEM70_FMISS,
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_MEM70
+ );
+
+ SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
+ port map (
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
+ O_PPCM_RST_N <= '1'; --
+
+ end generate MEM_BRAM;
+
+ MEM_SRAM: if sys_conf_bram = 0 generate
+
+ CACHE: pdp11_cache
+ port map (
+ CLK => CLK,
+ GRESET => CPU_RESET,
+ EM_MREQ => EM_MREQ,
+ EM_SRES => EM_SRES,
+ FMISS => CACHE_FMISS,
+ CHIT => CACHE_CHIT,
+ MEM_REQ => MEM_REQ,
+ MEM_WE => MEM_WE,
+ MEM_BUSY => MEM_BUSY,
+ MEM_ACK_R => MEM_ACK_R,
+ MEM_ADDR => MEM_ADDR,
+ MEM_BE => MEM_BE,
+ MEM_DI => MEM_DI,
+ MEM_DO => MEM_DO
+ );
+
+ MEM70: pdp11_mem70
+ port map (
+ CLK => CLK,
+ CRESET => BRESET,
+ HM_ENA => HM_ENA,
+ HM_VAL => CACHE_CHIT,
+ CACHE_FMISS => MEM70_FMISS,
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_MEM70
+ );
+
+ HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;
+ CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
+
+ MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
+
+ SRAM_CTL: nx_cram_memctl_as
+ generic map (
+ READ0DELAY => sys_conf_memctl_read0delay,
+ READ1DELAY => sys_conf_memctl_read1delay,
+ WRITEDELAY => sys_conf_memctl_writedelay)
+ port map (
+ CLK => CLK,
+ RESET => CPU_RESET,
+ REQ => MEM_REQ,
+ WE => MEM_WE,
+ BUSY => MEM_BUSY,
+ ACK_R => MEM_ACK_R,
+ ACK_W => open,
+ ACT_R => MEM_ACT_R,
+ ACT_W => MEM_ACT_W,
+ ADDR => MEM_ADDR_EXT,
+ BE => MEM_BE,
+ DI => MEM_DI,
+ DO => MEM_DO,
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
+ O_PPCM_RST_N <= '1'; --
+
+ end generate MEM_SRAM;
+
+ IB_SRES_OR : ib_sres_or_2
+ port map (
+ IB_SRES_1 => IB_SRES_MEM70,
+ IB_SRES_2 => IB_SRES_IBDR,
+ IB_SRES_OR => IB_SRES
+ );
+
+ IBD_MINI : if false generate
+ begin
+ IBDR_SYS : ibdr_minisys
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC,
+ RESET => CPU_RESET,
+ BRESET => BRESET,
+ RB_LAM => RB_LAM(15 downto 1),
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_IBDR,
+ EI_ACKM => EI_ACKM,
+ EI_PRI => EI_PRI,
+ EI_VECT => EI_VECT,
+ DISPREG => DISPREG
+ );
+ end generate IBD_MINI;
+
+ IBD_MAXI : if true generate
+ begin
+ IBDR_SYS : ibdr_maxisys
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC,
+ RESET => CPU_RESET,
+ BRESET => BRESET,
+ RB_LAM => RB_LAM(15 downto 1),
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_IBDR,
+ EI_ACKM => EI_ACKM,
+ EI_PRI => EI_PRI,
+ EI_VECT => EI_VECT,
+ DISPREG => DISPREG
+ );
+ end generate IBD_MAXI;
+
+ DSP_DAT(15 downto 0) <= DISPREG;
+ DSP_DP(0) <= not RXD;
+ DSP_DP(1) <= RTS_N;
+ DSP_DP(2) <= not TXD;
+ DSP_DP(3) <= CTS_N;
+
+ proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
+ variable iled : slv8 := (others=>'0');
+ begin
+ iled := (others=>'0');
+ iled(7) := MEM_ACT_W;
+ iled(6) := MEM_ACT_R;
+ iled(5) := CP_STAT.cmdbusy;
+ if CP_STAT.cpugo = '1' then
+ case DM_STAT_DP.psw.cmode is
+ when c_psw_kmode =>
+ if CP_STAT.cpuwait = '1' then
+ iled(2) := '1';
+ elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
+ iled(3) := '1';
+ else
+ iled(4) := '1';
+ end if;
+ when c_psw_smode =>
+ iled(1) := '1';
+ when c_psw_umode =>
+ iled(0) := '1';
+ when others => null;
+ end case;
+ else
+ iled(4) := '1';
+ iled(3 downto 0) := CP_STAT.cpurust;
+ end if;
+ LED <= iled;
+ end process;
+
+-- synthesis translate_off
+ DM_STAT_SY.emmreq <= EM_MREQ;
+ DM_STAT_SY.emsres <= EM_SRES;
+ DM_STAT_SY.chit <= CACHE_CHIT;
+
+ TMU : pdp11_tmu_sb
+ generic map (
+ ENAPIN => 13)
+ port map (
+ CLK => CLK,
+ DM_STAT_DP => DM_STAT_DP,
+ DM_STAT_VM => DM_STAT_VM,
+ DM_STAT_CO => DM_STAT_CO,
+ DM_STAT_SY => DM_STAT_SY
+ );
+-- synthesis translate_on
+
+end syn;
Index: rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom
===================================================================
--- rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom (nonexistent)
+++ rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom (revision 15)
@@ -0,0 +1,34 @@
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/xlib/xlib.vhd
+../../../vlib/genlib/genlib.vhd
+../../../vlib/rbus/rblib.vhd
+../../../vlib/rlink/rlinklib.vbom
+../../../bplib/bpgen/bpgenlib.vbom
+../../../bplib/nxcramlib/nxcramlib.vhd
+../../../ibus/iblib.vhd
+../../../ibus/ibdlib.vhd
+../../../w11a/pdp11.vhd
+sys_conf = sys_conf.vhd
+# components
+[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
+[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
+../../../vlib/genlib/clkdivce.vbom
+../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
+../../../bplib/bpgen/sn_humanio_rbus.vbom
+../../../vlib/rlink/rlink_base_serport.vbom
+../../../vlib/rbus/rb_sres_or_3.vbom
+../../../w11a/pdp11_core_rbus.vbom
+../../../w11a/pdp11_core.vbom
+../../../w11a/pdp11_bram.vbom
+../../../bplib/nxcramlib/nx_cram_dummy.vbom
+../../../w11a/pdp11_cache.vbom
+../../../w11a/pdp11_mem70.vbom
+../../../bplib/nxcramlib/nx_cram_memctl_as.vbom
+../../../ibus/ib_sres_or_2.vbom
+../../../ibus/ibdr_minisys.vbom
+../../../ibus/ibdr_maxisys.vbom
+[ghdl,isim]../../../w11a/pdp11_tmu_sb.vbom
+# design
+sys_w11a_n3.vhd
+@ucf_cpp: sys_w11a_n3.ucf
Index: rtl/sys_gen/w11a/nexys3/Makefile
===================================================================
--- rtl/sys_gen/w11a/nexys3/Makefile (nonexistent)
+++ rtl/sys_gen/w11a/nexys3/Makefile (revision 15)
@@ -0,0 +1,30 @@
+# $Id: Makefile 430 2011-11-20 20:48:39Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2011-11-20 430 1.0 Initial version (derived from _n2 version)
+#
+VBOM_all = $(wildcard *.vbom)
+BIT_all = $(VBOM_all:.vbom=.bit)
+#
+ISE_BOARD = nexys3
+ISE_PATH = xc6slx16-csg324-2
+#
+XFLOWOPT_SYN = syn_s6_speed.opt
+XFLOWOPT_IMP = imp_s6_speed.opt
+#
+.PHONY : all clean
+#
+all : $(BIT_all)
+#
+clean : ise_clean
+ rm -f sys_w11a_n3.ucf
+#
+#----
+#
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+#
Index: rtl/sys_gen/w11a/nexys3/.cvsignore
===================================================================
--- rtl/sys_gen/w11a/nexys3/.cvsignore (nonexistent)
+++ rtl/sys_gen/w11a/nexys3/.cvsignore (revision 15)
@@ -0,0 +1,4 @@
+sys_w11a_n3.ucf
+*.dep_ucf_cpp
+log_*
+_impact*
Index: rtl/sys_gen/w11a/nexys3
===================================================================
--- rtl/sys_gen/w11a/nexys3 (nonexistent)
+++ rtl/sys_gen/w11a/nexys3 (revision 15)
rtl/sys_gen/w11a/nexys3
Property changes :
Added: svn:ignore
## -0,0 +1,36 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+sys_w11a_n3.ucf
+*.dep_ucf_cpp
+log_*
+_impact*
Index: rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd
===================================================================
--- rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd (revision 14)
+++ rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd (revision 15)
@@ -1,4 +1,4 @@
--- $Id: sys_tst_snhumanio_n2.vhd 419 2011-11-01 19:42:30Z mueller $
+-- $Id: sys_tst_snhumanio_n2.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller
--
@@ -18,7 +18,7 @@
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
--- vlib/nexys2/n2_cram_dummy
+-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
@@ -31,6 +31,8 @@
--
-- Revision History:
-- Date Rev Version Comment
+-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
+-- 2011-11-23 432 1.0.3 update O_FLA_CE_N usage
-- 2011-10-25 419 1.0.2 get entity name right...
-- 2011-09-17 410 1.0 Initial version
------------------------------------------------------------------------------
@@ -43,7 +45,7 @@
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
-use work.nexys2lib.all;
+use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
@@ -55,9 +57,9 @@
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
- I_SWI : in slv8; -- s3 switches
- I_BTN : in slv4; -- s3 buttons
- O_LED : out slv8; -- s3 leds
+ I_SWI : in slv8; -- n2 switches
+ I_BTN : in slv4; -- n2 buttons
+ O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
@@ -68,9 +70,9 @@
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
- O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_MEM_ADDR : out slv23; -- cram: address lines
- IO_MEM_DATA : inout slv16 -- cram: data lines
+ IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_FLA_CE_N : out slbit -- flash ce.. (act.low)
);
end sys_tst_snhumanio_n2;
@@ -141,7 +143,7 @@
O_TXD <= I_RXD;
- SRAM_PROT : n2_cram_dummy -- connect CRAM to protection dummy
+ SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
@@ -151,9 +153,10 @@
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
- O_FLA_CE_N => O_FLA_CE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
+ O_FLA_CE_N <= '1'; -- keep Flash memory disabled
+
end syn;
/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vbom
2,13 → 2,13
../../../vlib/slvtypes.vhd |
../../../vlib/genlib/genlib.vhd |
../../../bplib/bpgen/bpgenlib.vbom |
../../../bplib/nexys2/nexys2lib.vhd |
../../../bplib/nxcramlib/nxcramlib.vhd |
sys_conf : sys_conf.vhd |
# components |
../../../vlib/genlib/clkdivce.vbom |
../../../bplib/bpgen/sn_humanio.vbom |
../tst_snhumanio.vbom |
../../../bplib/nexys2/n2_cram_dummy.vbom |
../../../bplib/nxcramlib/nx_cram_dummy.vbom |
# design |
sys_tst_snhumanio_n2.vhd |
@ucf_cpp: sys_tst_snhumanio_n2.ucf |
/rtl/sys_gen/tst_snhumanio/nexys3/sys_conf.vhd
0,0 → 1,35
-- $Id: sys_conf.vhd 433 2011-11-27 22:04:39Z mueller $ |
-- |
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Package Name: sys_conf |
-- Description: Definitions for sys_tst_snhumanio_n3 (for synthesis) |
-- |
-- Dependencies: - |
-- Tool versions: xst 13.1; ghdl 0.29 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-27 433 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
|
package sys_conf is |
|
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers |
|
end package sys_conf; |
|
/rtl/sys_gen/tst_snhumanio/nexys3/sys_tst_snhumanio_n3.ucf_cpp
0,0 → 1,15
## $Id: sys_tst_snhumanio_n3.ucf_cpp 433 2011-11-27 22:04:39Z mueller $ |
## |
## Revision History: |
## Date Rev Version Comment |
## 2011-11-27 433 1.0 Initial version |
## |
|
NET "I_CLK100" TNM_NET = "I_CLK100"; |
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; |
OFFSET = IN 10 ns BEFORE "I_CLK100"; |
OFFSET = OUT 20 ns AFTER "I_CLK100"; |
|
## std board |
## |
#include "bplib/nexys3/nexys3_pins.ucf" |
/rtl/sys_gen/tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vhd
0,0 → 1,159
-- $Id: sys_tst_snhumanio_n3.vhd 433 2011-11-27 22:04:39Z mueller $ |
-- |
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: sys_tst_snhumanio_n3 - syn |
-- Description: snhumanio tester design for nexys3 |
-- |
-- Dependencies: vlib/genlib/clkdivce |
-- bplib/bpgen/sn_humanio |
-- tst_snhumanio |
-- vlib/nxcramlib/nx_cram_dummy |
-- |
-- Test bench: - |
-- |
-- Target Devices: generic |
-- Tool versions: xst 13.1; ghdl 0.29 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2011-11-27 433 13.1 O40d xc3s1200e-4 151 195 - 65 t 6.1 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-27 433 1.0 Initial version |
------------------------------------------------------------------------------ |
-- Usage of Nexys 2 Switches, Buttons, LEDs: |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.genlib.all; |
use work.bpgenlib.all; |
use work.nxcramlib.all; |
use work.sys_conf.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity sys_tst_snhumanio_n3 is -- top level |
-- implements nexys3_aif |
port ( |
I_CLK100 : in slbit; -- 100 MHz clock |
I_RXD : in slbit; -- receive data (board view) |
O_TXD : out slbit; -- transmit data (board view) |
I_SWI : in slv8; -- n3 switches |
I_BTN : in slv5; -- n3 buttons |
O_LED : out slv8; -- n3 leds |
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) |
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) |
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) |
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) |
O_MEM_WE_N : out slbit; -- cram: write enable (act.low) |
O_MEM_OE_N : out slbit; -- cram: output enable (act.low) |
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) |
O_MEM_CLK : out slbit; -- cram: clock |
O_MEM_CRE : out slbit; -- cram: command register enable |
I_MEM_WAIT : in slbit; -- cram: mem wait |
O_MEM_ADDR : out slv23; -- cram: address lines |
IO_MEM_DATA : inout slv16; -- cram: data lines |
O_PPCM_CE_N : out slbit; -- ppcm: ... |
O_PPCM_RST_N : out slbit -- ppcm: ... |
); |
end sys_tst_snhumanio_n3; |
|
architecture syn of sys_tst_snhumanio_n3 is |
|
signal CLK : slbit := '0'; |
|
signal SWI : slv8 := (others=>'0'); |
signal BTN : slv5 := (others=>'0'); |
signal LED : slv8 := (others=>'0'); |
signal DSP_DAT : slv16 := (others=>'0'); |
signal DSP_DP : slv4 := (others=>'0'); |
|
signal RESET : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
begin |
|
RESET <= '0'; -- so far not used |
|
CLK <= I_CLK100; |
|
CLKDIV : clkdivce |
generic map ( |
CDUWIDTH => 7, |
USECDIV => 100, |
MSECDIV => 1000) |
port map ( |
CLK => CLK, |
CE_USEC => open, |
CE_MSEC => CE_MSEC |
); |
|
HIO : sn_humanio |
generic map ( |
BWIDTH => 5, |
DEBOUNCE => sys_conf_hio_debounce) |
port map ( |
CLK => CLK, |
RESET => RESET, |
CE_MSEC => CE_MSEC, |
SWI => SWI, |
BTN => BTN, |
LED => LED, |
DSP_DAT => DSP_DAT, |
DSP_DP => DSP_DP, |
I_SWI => I_SWI, |
I_BTN => I_BTN, |
O_LED => O_LED, |
O_ANO_N => O_ANO_N, |
O_SEG_N => O_SEG_N |
); |
|
HIOTEST : entity work.tst_snhumanio |
generic map ( |
BWIDTH => 5) |
port map ( |
CLK => CLK, |
RESET => RESET, |
CE_MSEC => CE_MSEC, |
SWI => SWI, |
BTN => BTN, |
LED => LED, |
DSP_DAT => DSP_DAT, |
DSP_DP => DSP_DP |
); |
|
O_TXD <= I_RXD; |
|
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy |
port map ( |
O_MEM_CE_N => O_MEM_CE_N, |
O_MEM_BE_N => O_MEM_BE_N, |
O_MEM_WE_N => O_MEM_WE_N, |
O_MEM_OE_N => O_MEM_OE_N, |
O_MEM_ADV_N => O_MEM_ADV_N, |
O_MEM_CLK => O_MEM_CLK, |
O_MEM_CRE => O_MEM_CRE, |
I_MEM_WAIT => I_MEM_WAIT, |
O_MEM_ADDR => O_MEM_ADDR, |
IO_MEM_DATA => IO_MEM_DATA |
); |
|
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled |
O_PPCM_RST_N <= '1'; -- |
|
end syn; |
/rtl/sys_gen/tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vbom
0,0 → 1,14
# libs |
../../../vlib/slvtypes.vhd |
../../../vlib/genlib/genlib.vhd |
../../../bplib/bpgen/bpgenlib.vbom |
../../../bplib/nxcramlib/nxcramlib.vhd |
sys_conf : sys_conf.vhd |
# components |
../../../vlib/genlib/clkdivce.vbom |
../../../bplib/bpgen/sn_humanio.vbom |
../tst_snhumanio.vbom |
../../../bplib/nxcramlib/nx_cram_dummy.vbom |
# design |
sys_tst_snhumanio_n3.vhd |
@ucf_cpp: sys_tst_snhumanio_n3.ucf |
/rtl/sys_gen/tst_snhumanio/nexys3/Makefile
0,0 → 1,30
# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2011-11-27 433 1.0 Initial version |
# |
VBOM_all = $(wildcard *.vbom) |
BIT_all = $(VBOM_all:.vbom=.bit) |
# |
ISE_BOARD = nexys3 |
ISE_PATH = xc6slx16-csg324-2 |
# |
XFLOWOPT_SYN = syn_s6_speed.opt |
XFLOWOPT_IMP = imp_s6_speed.opt |
# |
.PHONY : all clean |
# |
all : $(BIT_all) |
# |
clean : ise_clean |
rm -f sys_tst_snhumanio_n3.ucf |
# |
#---- |
# |
include $(RETROBASE)/rtl/make/generic_xflow.mk |
include $(RETROBASE)/rtl/make/generic_ghdl.mk |
# |
include $(VBOM_all:.vbom=.dep_xst) |
include $(VBOM_all:.vbom=.dep_ghdl) |
# |
/rtl/sys_gen/tst_snhumanio/nexys3/.cvsignore
0,0 → 1,4
_impactbatch.log |
sys_tst_snhumanio_n3.ucf |
*.dep_ucf_cpp |
*.svf |
rtl/sys_gen/tst_snhumanio/nexys3
Property changes :
Added: svn:ignore
## -0,0 +1,36 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+_impactbatch.log
+sys_tst_snhumanio_n3.ucf
+*.dep_ucf_cpp
+*.svf
Index: rtl/bplib/nxcramlib/nxcramlib.vhd
===================================================================
--- rtl/bplib/nxcramlib/nxcramlib.vhd (nonexistent)
+++ rtl/bplib/nxcramlib/nxcramlib.vhd (revision 15)
@@ -0,0 +1,80 @@
+-- $Id: nxcramlib.vhd 433 2011-11-27 22:04:39Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: nxcramlib
+-- Description: Nexys 2/3 CRAM drivers
+--
+-- Dependencies: -
+-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-26 433 1.0 Initial version (extracted from nexys2lib)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package nxcramlib is
+
+component nx_cram_dummy is -- CRAM protection dummy
+ port (
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16 -- cram: data lines
+ );
+end component;
+
+component nx_cram_memctl_as is -- CRAM driver (async+page mode)
+ generic (
+ READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
+ READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
+ WRITEDELAY : positive := 3); -- write delay in clock cycles
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ REQ : in slbit; -- request
+ WE : in slbit; -- write enable
+ BUSY : out slbit; -- controller busy
+ ACK_R : out slbit; -- acknowledge read
+ ACK_W : out slbit; -- acknowledge write
+ ACT_R : out slbit; -- signal active read
+ ACT_W : out slbit; -- signal active write
+ ADDR : in slv22; -- address (32 bit word address)
+ BE : in slv4; -- byte enable
+ DI : in slv32; -- data in (memory view)
+ DO : out slv32; -- data out (memory view)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16 -- cram: data lines
+ );
+end component;
+
+end package nxcramlib;
Index: rtl/bplib/nxcramlib/nx_cram_dummy.vhd
===================================================================
--- rtl/bplib/nxcramlib/nx_cram_dummy.vhd (nonexistent)
+++ rtl/bplib/nxcramlib/nx_cram_dummy.vhd (revision 15)
@@ -0,0 +1,64 @@
+-- $Id: nx_cram_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
+--
+-- Copyright 2010-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: nx_cram_dummy - syn
+-- Description: nexys2/3: CRAM protection dummy
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-26 433 1.2 renamed from n2_cram_dummy
+-- 2011-11-23 432 1.1 remove O_FLA_CE_N port
+-- 2010-05-28 295 1.0.1 use _ADV_N
+-- 2010-05-21 292 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+entity nx_cram_dummy is -- CRAM protection dummy
+ port (
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16 -- cram: data lines
+ );
+end nx_cram_dummy;
+
+
+architecture syn of nx_cram_dummy is
+begin
+
+ O_MEM_CE_N <= '1'; -- disable cram chip
+ O_MEM_BE_N <= "11";
+ O_MEM_WE_N <= '1';
+ O_MEM_OE_N <= '1';
+ O_MEM_ADV_N <= '1';
+ O_MEM_CLK <= '0';
+ O_MEM_CRE <= '0';
+ O_MEM_ADDR <= (others=>'0');
+ IO_MEM_DATA <= (others=>'0');
+
+end syn;
Index: rtl/bplib/nxcramlib/nx_cram_dummy.vbom
===================================================================
--- rtl/bplib/nxcramlib/nx_cram_dummy.vbom (nonexistent)
+++ rtl/bplib/nxcramlib/nx_cram_dummy.vbom (revision 15)
@@ -0,0 +1,5 @@
+# libs
+../../vlib/slvtypes.vhd
+# components
+# design
+nx_cram_dummy.vhd
Index: rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd
===================================================================
--- rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd (nonexistent)
+++ rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd (revision 15)
@@ -0,0 +1,587 @@
+-- $Id: nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $
+--
+-- Copyright 2010-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: nx_cram_memctl_as - syn
+-- Description: nexys2/3: CRAM driver - async and page mode
+--
+-- Dependencies: vlib/xlib/iob_reg_o
+-- vlib/xlib/iob_reg_o_gen
+-- vlib/xlib/iob_reg_io_gen
+-- Test bench: tb/tb_nx_cram_memctl_as
+-- sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
+-- Target Devices: generic
+-- Tool versions: xst 11.4, 13.1; ghdl 0.26
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 100 0 96 s 6.7
+-- 2010-05-24 294 11.4 L68 xc3s1200e-4 91 99 0 95 s 6.7
+-- 2010-05-23 293 11.4 L68 xc3s1200e-4 91 139 0 99 s 6.7
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-26 433 1.2 renamed from n2_cram_memctl_as
+-- 2011-11-19 432 1.1 remove O_FLA_CE_N port
+-- 2011-11-19 427 1.0.5 now numeric_std clean
+-- 2010-11-22 339 1.0.4 cntdly now 3 bit; add assert for DELAY generics
+-- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read
+-- cycle;
+-- 2010-05-30 297 1.0.2 use READ(0|1)DELAY generic
+-- 2010-05-24 294 1.0.1 more compact n.memdi logic; extra wait in s_rdwait1
+-- 2010-05-23 293 1.0 Initial version
+--
+-- Notes:
+-- 1. READ1DELAY of 2 is needed even though the timing of the memory suggests
+-- that 1 cycle is enough (T_apa is 20 ns, so 40 ns round trip is ok). A
+-- short READ1 delay works in sim, but not on fpga where the data od the
+-- ADDR(0)=0 cycle is re-read (see notes_tst_sram_n2.txt).
+-- tb_n2_cram_memctl_as_ISim_tsim works with full sdf even when T_apa is
+-- 40ns or 50 ns, only T_apa 60 ns fails !
+-- Unclear what is wrong here, the timing of the memory model seems ok.
+-- 2. There is no 'bus-turn-around' cycle needed for a write->read change
+-- FPGA_OE goes 1->0 and MEM_OE goes 0->1 on the s_wrput1->s_rdinit
+-- transition simultaneously. The FPGA will go high-Z quickly, the memory
+-- low-Z delay by the IOB and internal memory delays. No clash.
+-- 3. There is a hidden 'bus-turn-around' cycle for a read->write change.
+-- MEM_OE goes 1->0 on s_rdget1->s_wrinit and the memory will go high-z with
+-- some dekal. FPGA_OE goes 0->1 in the next cycle at s_wrinit->s_wrwait0.
+-- Again no clash due to the 1 cycle delay.
+--
+-- Nominal timings:
+-- READ0/1 = N_rd_cycle - 2
+-- WRITE = N_wr_cycle - 1
+--
+-- from notes_nexys2.txt (Rev 339):
+-- clksys RD WR < use for > Test case
+-- MHz div mul
+-- <51.20 2 3 <-- 50 50 1 1
+-- 51.20- 54.80 3 3 <-- 52,54 54 25 27
+-- 54.80- 64.10 3 4 <-- 55,56,58,60,62,64 64 25 32
+-- 64.10- 68.50 4 4 <-- 65 65 10 13
+-- 68.50- 76.92 4 5 <-- 70,75 75 2 3
+-- 76.92- 82.19 5 5 <-- 80 80 5 8
+-- 82.19- 89.74 5 6 <-- 85 85 10 17
+-- 89.74- 95.89 6 6 <-- 90,95 95 10 19
+-- 95.89-102.56 6 7 <-- 100 100 1 2
+--
+-- Timing of some signals:
+--
+-- single read request:
+--
+-- state |_idle |_rdinit|_rdwt0 |_rdwt0 |_rdget0|_rdwt1 |_rdget1|
+-- 0 20 40 60 80 100 120
+-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|
+--
+-- REQ _______|^^^^^|_____________________________________________
+-- WE ___________________________________________________________
+--
+-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
+-- IOB_OE _________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
+--
+-- DO oooooooooooooooooooooooooooooooooooooooooo|lllllll|lllllll|h
+-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|________________
+-- ACK_R ___________________________________________________________|^^^^^^^|_
+--
+-- single write request:
+--
+-- state |_idle |_wrinit|_wrwt0 |_wrwt0 |_wrwt0 |_wrput0|_idle |
+-- 0 20 40 60 80 100 120
+-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|
+--
+-- REQ _______|^^^^^|______________________________________
+-- WE _______|^^^^^|______________________________________
+--
+-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
+-- IOB_BE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
+-- IOB_OE ____________________________________________________
+-- IOB_WE ______________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_____
+--
+-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_________
+-- ACK_W __________________________________________|^^^^^^^|_
+--
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+
+entity nx_cram_memctl_as is -- CRAM driver (async+page mode)
+ generic (
+ READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
+ READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
+ WRITEDELAY : positive := 3); -- write delay in clock cycles
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ REQ : in slbit; -- request
+ WE : in slbit; -- write enable
+ BUSY : out slbit; -- controller busy
+ ACK_R : out slbit; -- acknowledge read
+ ACK_W : out slbit; -- acknowledge write
+ ACT_R : out slbit; -- signal active read
+ ACT_W : out slbit; -- signal active write
+ ADDR : in slv22; -- address (32 bit word address)
+ BE : in slv4; -- byte enable
+ DI : in slv32; -- data in (memory view)
+ DO : out slv32; -- data out (memory view)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16 -- cram: data lines
+ );
+end nx_cram_memctl_as;
+
+
+architecture syn of nx_cram_memctl_as is
+
+ type state_type is (
+ s_idle, -- s_idle: wait for req
+ s_rdinit, -- s_rdinit: read init cycle
+ s_rdwait0, -- s_rdwait0: read wait low word
+ s_rdget0, -- s_rdget0: read get low word
+ s_rdwait1, -- s_rdwait1: read wait high word
+ s_rdget1, -- s_rdget1: read get high word
+ s_wrinit, -- s_wrinit: write init cycle
+ s_wrwait0, -- s_rdwait0: write wait 1st word
+ s_wrput0, -- s_rdput0: write put 1st word
+ s_wrini1, -- s_wrini1: write init 2nd word
+ s_wrwait1, -- s_wrwait1: write wait 2nd word
+ s_wrput1 -- s_wrput1: write put 2nd word
+ );
+
+ type regs_type is record
+ state : state_type; -- state
+ ackr : slbit; -- signal ack_r
+ addr0 : slbit; -- current addr0
+ be2nd : slv2; -- be's of 2nd write cycle
+ cntdly : slv3; -- wait delay counter
+ cntce : slv7; -- ce counter
+ fidle : slbit; -- force idle flag
+ memdo0 : slv16; -- mem data out, low word
+ memdi : slv32; -- mem data in
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ s_idle, --
+ '0', -- ackr
+ '0', -- addr0
+ "00", -- be2nd
+ (others=>'0'), -- cntdly
+ (others=>'0'), -- cntce
+ '0', -- fidle
+ (others=>'0'), -- memdo0
+ (others=>'0') -- memdi
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+ signal CLK_180 : slbit := '0';
+ signal MEM_CE_N : slbit := '1';
+ signal MEM_BE_N : slv2 := "11";
+ signal MEM_WE_N : slbit := '1';
+ signal MEM_OE_N : slbit := '1';
+ signal BE_CE : slbit := '0';
+ signal ADDRH_CE : slbit := '0';
+ signal ADDR0_CE : slbit := '0';
+ signal ADDR0 : slbit := '0';
+ signal DATA_CEI : slbit := '0';
+ signal DATA_CEO : slbit := '0';
+ signal DATA_OE : slbit := '0';
+ signal MEM_DO : slv16 := (others=>'0');
+ signal MEM_DI : slv16 := (others=>'0');
+
+-- these attributes aren't accepted by ghdl 0.26
+-- attribute s : string;
+-- attribute s of I_MEM_WAIT : signal is "true";
+
+begin
+
+ assert READ0DELAY<=2**R_REGS.cntdly'length and
+ READ1DELAY<=2**R_REGS.cntdly'length and
+ WRITEDELAY<=2**R_REGS.cntdly'length
+ report "assert(READ0,READ1,WRITEDELAY <= 2**cntdly'length)"
+ severity failure;
+
+ CLK_180 <= not CLK;
+
+ IOB_MEM_CE : iob_reg_o
+ generic map (
+ INIT => '1')
+ port map (
+ CLK => CLK,
+ CE => '1',
+ DO => MEM_CE_N,
+ PAD => O_MEM_CE_N
+ );
+
+ IOB_MEM_BE : iob_reg_o_gen
+ generic map (
+ DWIDTH => 2,
+ INIT => '1')
+ port map (
+ CLK => CLK,
+ CE => BE_CE,
+ DO => MEM_BE_N,
+ PAD => O_MEM_BE_N
+ );
+
+ IOB_MEM_WE : iob_reg_o
+ generic map (
+ INIT => '1')
+ port map (
+ CLK => CLK_180,
+ CE => '1',
+ DO => MEM_WE_N,
+ PAD => O_MEM_WE_N
+ );
+
+ IOB_MEM_OE : iob_reg_o
+ generic map (
+ INIT => '1')
+ port map (
+ CLK => CLK,
+ CE => '1',
+ DO => MEM_OE_N,
+ PAD => O_MEM_OE_N
+ );
+
+ IOB_MEM_ADDRH : iob_reg_o_gen
+ generic map (
+ DWIDTH => 22)
+ port map (
+ CLK => CLK,
+ CE => ADDRH_CE,
+ DO => ADDR,
+ PAD => O_MEM_ADDR(22 downto 1)
+ );
+
+ IOB_MEM_ADDR0 : iob_reg_o
+ port map (
+ CLK => CLK,
+ CE => ADDR0_CE,
+ DO => ADDR0,
+ PAD => O_MEM_ADDR(0)
+ );
+
+ IOB_MEM_DATA : iob_reg_io_gen
+ generic map (
+ DWIDTH => 16,
+ PULL => "KEEP")
+ port map (
+ CLK => CLK,
+ CEI => DATA_CEI,
+ CEO => DATA_CEO,
+ OE => DATA_OE,
+ DI => MEM_DO,
+ DO => MEM_DI,
+ PAD => IO_MEM_DATA
+ );
+
+ O_MEM_ADV_N <= '0';
+ O_MEM_CLK <= '0';
+ O_MEM_CRE <= '0';
+
+ proc_regs: process (CLK)
+ begin
+
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, REQ, WE, BE, DI, MEM_DO)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+ variable ibusy : slbit := '0';
+ variable iackw : slbit := '0';
+ variable iactr : slbit := '0';
+ variable iactw : slbit := '0';
+ variable imem_ce : slbit := '0';
+ variable imem_be : slv2 := "00";
+ variable imem_we : slbit := '0';
+ variable imem_oe : slbit := '0';
+ variable ibe_ce : slbit := '0';
+ variable iaddrh_ce : slbit := '0';
+ variable iaddr0_ce : slbit := '0';
+ variable iaddr0 : slbit := '0';
+ variable idata_cei : slbit := '0';
+ variable idata_ceo : slbit := '0';
+ variable idata_oe : slbit := '0';
+
+ procedure do_dispatch(nstate : out state_type;
+ iaddrh_ce : out slbit;
+ iaddr0_ce : out slbit;
+ iaddr0 : out slbit;
+ ibe_ce : out slbit;
+ imem_be : out slv2;
+ imem_ce : out slbit;
+ imem_oe : out slbit;
+ nbe2nd : out slv2) is
+ begin
+ iaddrh_ce := '1'; -- latch address (high part)
+ iaddr0_ce := '1'; -- latch address 0 bit
+ ibe_ce := '1'; -- latch be's
+ imem_ce := '1'; -- ce CRAM next cycle
+ nbe2nd := "00"; -- assume no 2nd write cycle
+ if WE = '0' then -- if READ requested
+ iaddr0 := '0'; -- go first for low word
+ imem_be := "11"; -- on read always on
+ imem_oe := '1'; -- oe CRAM next cycle
+ nstate := s_rdinit; -- next: read init part
+ else -- if WRITE requested
+ if BE(1 downto 0) /= "00" then -- low word write
+ iaddr0 := '0'; -- access word 0
+ imem_be := BE(1 downto 0); -- set be's for 1st cycle
+ nbe2nd := BE(3 downto 2); -- keep be's for 2nd cycle
+ else -- high word write
+ iaddr0 := '1'; -- access word 1
+ imem_be := BE(3 downto 2); -- set be's for 1st cycle
+ end if;
+ nstate := s_wrinit; -- next: write init part
+ end if;
+ end procedure do_dispatch;
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+ n.ackr := '0';
+
+ ibusy := '0';
+ iackw := '0';
+ iactr := '0';
+ iactw := '0';
+
+ imem_ce := '0';
+ imem_be := "11";
+ imem_we := '0';
+ imem_oe := '0';
+ ibe_ce := '0';
+ iaddrh_ce := '0';
+ iaddr0_ce := '0';
+ iaddr0 := '0';
+ idata_cei := '0';
+ idata_ceo := '0';
+ idata_oe := '0';
+
+ if unsigned(r.cntdly) /= 0 then
+ n.cntdly := slv(unsigned(r.cntdly) - 1);
+ end if;
+
+ case r.state is
+ when s_idle => -- s_idle: wait for req
+ if REQ = '1' then -- if IO requested
+ do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
+ ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
+ end if;
+
+ when s_rdinit => -- s_rdinit: read init cycle
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactr := '1'; -- signal mem read
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_oe := '1'; -- oe CRAM next cycle
+ n.cntdly:= slv(to_unsigned(READ0DELAY-1, n.cntdly'length));
+ n.state := s_rdwait0; -- next: wait
+
+ when s_rdwait0 => -- s_rdwait0: read wait low word
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactr := '1'; -- signal mem read
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_oe := '1'; -- oe CRAM next cycle
+ if unsigned(r.cntdly) = 0 then -- wait expired ?
+ n.state := s_rdget0; -- next: get low word
+ end if;
+
+ when s_rdget0 => -- s_rdget0: read get low word
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactr := '1'; -- signal mem read
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_oe := '1'; -- oe CRAM next cycle
+ idata_cei := '1'; -- latch input data
+ iaddr0_ce := '1'; -- latch address 0 bit
+ iaddr0 := '1'; -- now go for high word
+ n.cntdly:= slv(to_unsigned(READ1DELAY-1, n.cntdly'length));
+ n.state := s_rdwait1; -- next: wait high word
+
+ when s_rdwait1 => -- s_rdwait1: read wait high word
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactr := '1'; -- signal mem read
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_oe := '1'; -- oe CRAM next cycle
+ if unsigned(r.cntdly) = 0 then -- wait expired ?
+ n.state := s_rdget1; -- next: get low word
+ end if; --
+
+ when s_rdget1 => -- s_rdget1: read get high word
+ iactr := '1'; -- signal mem read
+ n.memdo0:= MEM_DO; -- save low word data
+ idata_cei := '1'; -- latch input data
+ n.ackr := '1'; -- ACK_R next cycle
+ n.state := s_idle; -- next: wait next request
+ if r.fidle = '1' then -- forced idle cycle
+ ibusy := '1'; -- signal busy, unable to handle req
+ else
+ if REQ = '1' then -- if IO requested
+ do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
+ ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
+ end if;
+ end if;
+
+ when s_wrinit => -- s_wrinit: write init cycle
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactw := '1'; -- signal mem write
+ iackw := '1'; -- signal write done (all latched)
+ idata_ceo:= '1'; -- latch output data
+ idata_oe := '1'; -- oe FPGA next cycle
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_we := '1'; -- we CRAM in half cycle
+ n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
+ n.state := s_wrwait0; -- next: wait
+
+ when s_wrwait0 => -- s_rdput0: write wait 1st word
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactw := '1'; -- signal mem write
+ idata_oe := '1'; -- oe FPGA next cycle
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_we := '1'; -- we CRAM next cycle
+ if unsigned(r.cntdly) = 0 then -- wait expired ?
+ n.state := s_wrput0; -- next: put 1st word
+ end if;
+
+ when s_wrput0 => -- s_rdput0: write put 1st word
+ iactw := '1'; -- signal mem write
+ imem_we := '0'; -- deassert we CRAM in half cycle
+ if r.be2nd /= "00" then
+ ibusy := '1'; -- signal busy, unable to handle req
+ imem_ce := '1'; -- ce CRAM next cycle
+ iaddr0_ce := '1'; -- latch address 0 bit
+ iaddr0 := '1'; -- now go for high word
+ ibe_ce := '1'; -- latch be's
+ imem_be := r.be2nd; -- now be's of high word
+ n.state := s_wrini1; -- next: start 2nd write
+ else
+ n.state := s_idle; -- next: wait next request
+ if r.fidle = '1' then -- forced idle cycle
+ ibusy := '1'; -- signal busy
+ else
+ if REQ = '1' then -- if IO requested
+ do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
+ ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
+ end if;
+ end if;
+ end if;
+
+ when s_wrini1 => -- s_wrini1: write init 2nd word
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactw := '1'; -- signal mem write
+ idata_ceo:= '1'; -- latch output data
+ idata_oe := '1'; -- oe FPGA next cycle
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_we := '1'; -- we CRAM in half cycle
+ n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
+ n.state := s_wrwait1; -- next: wait
+
+ when s_wrwait1 => -- s_wrwait1: write wait 2nd word
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactw := '1'; -- signal mem write
+ idata_oe := '1'; -- oe FPGA next cycle
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_we := '1'; -- we CRAM next cycle
+ if unsigned(r.cntdly) = 0 then -- wait expired ?
+ n.state := s_wrput1; -- next: put 2nd word
+ end if;
+
+ when s_wrput1 => -- s_wrput1: write put 2nd word
+ iactw := '1'; -- signal mem write
+ imem_we := '0'; -- deassert we CRAM in half cycle
+ n.state := s_idle; -- next: wait next request
+ if r.fidle = '1' then -- forced idle cycle
+ ibusy := '1'; -- signal busy, unable to handle req
+ else
+ if REQ = '1' then -- if IO requested
+ do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
+ ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
+ end if;
+ end if;
+
+ when others => null;
+ end case;
+
+ if imem_ce = '0' then -- if cmem not active
+ n.cntce := (others=>'0'); -- clear counter
+ n.fidle := '0'; -- clear force idle flag
+ else -- if cmem active
+ if unsigned(r.cntce) >= 127 then -- if max ce count expired
+ n.fidle := '1'; -- set forced idle flag
+ else -- if max ce count not yet reached
+ n.cntce := slv(unsigned(r.cntce) + 1); -- increment counter
+ end if;
+ end if;
+
+ if iaddrh_ce = '1' then -- if addresses are latched
+ n.memdi := DI; -- latch data too...
+ end if;
+
+ if iaddr0_ce = '1' then -- if address bit 0 changed
+ n.addr0 := iaddr0; -- mirror it in state regs
+ end if;
+
+ N_REGS <= n;
+
+ MEM_CE_N <= not imem_ce;
+ MEM_WE_N <= not imem_we;
+ MEM_BE_N <= not imem_be;
+ MEM_OE_N <= not imem_oe;
+
+ if r.addr0 = '0' then
+ MEM_DI <= r.memdi(15 downto 0);
+ else
+ MEM_DI <= r.memdi(31 downto 16);
+ end if;
+
+ BE_CE <= ibe_ce;
+ ADDRH_CE <= iaddrh_ce;
+ ADDR0_CE <= iaddr0_ce;
+ ADDR0 <= iaddr0;
+ DATA_CEI <= idata_cei;
+ DATA_CEO <= idata_ceo;
+ DATA_OE <= idata_oe;
+
+ BUSY <= ibusy;
+ ACK_R <= r.ackr;
+ ACK_W <= iackw;
+ ACT_R <= iactr;
+ ACT_W <= iactw;
+
+ DO <= MEM_DO & r.memdo0;
+
+ end process proc_next;
+
+end syn;
Index: rtl/bplib/nxcramlib/nx_cram_memctl_as.vbom
===================================================================
--- rtl/bplib/nxcramlib/nx_cram_memctl_as.vbom (nonexistent)
+++ rtl/bplib/nxcramlib/nx_cram_memctl_as.vbom (revision 15)
@@ -0,0 +1,9 @@
+# libs
+../../vlib/slvtypes.vhd
+../../vlib/xlib/xlib.vhd
+# components
+../../vlib/xlib/iob_reg_o.vbom
+../../vlib/xlib/iob_reg_o_gen.vbom
+../../vlib/xlib/iob_reg_io_gen.vbom
+# design
+nx_cram_memctl_as.vhd
Index: rtl/bplib/nxcramlib/Makefile
===================================================================
--- rtl/bplib/nxcramlib/Makefile (nonexistent)
+++ rtl/bplib/nxcramlib/Makefile (revision 15)
@@ -0,0 +1,23 @@
+# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2011-11-26 433 1.0 Initial version (cloned..)
+#
+VBOM_all = $(wildcard *.vbom)
+NGC_all = $(VBOM_all:.vbom=.ngc)
+#
+ISE_PATH = xc3s1200e-fg320-4
+#
+.PHONY : all clean
+#
+all : $(NGC_all)
+#
+clean : ise_clean
+#
+#----
+#
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+#
+include $(VBOM_all:.vbom=.dep_xst)
+#
Index: rtl/bplib/nxcramlib
===================================================================
--- rtl/bplib/nxcramlib (nonexistent)
+++ rtl/bplib/nxcramlib (revision 15)
rtl/bplib/nxcramlib
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: rtl/bplib/nexys2/n2_cram_memctl_as.vbom
===================================================================
--- rtl/bplib/nexys2/n2_cram_memctl_as.vbom (revision 14)
+++ rtl/bplib/nexys2/n2_cram_memctl_as.vbom (nonexistent)
@@ -1,9 +0,0 @@
-# libs
-../../vlib/slvtypes.vhd
-../../vlib/xlib/xlib.vhd
-# components
-../../vlib/xlib/iob_reg_o.vbom
-../../vlib/xlib/iob_reg_o_gen.vbom
-../../vlib/xlib/iob_reg_io_gen.vbom
-# design
-n2_cram_memctl_as.vhd
Index: rtl/bplib/nexys2/n2_cram_dummy.vhd
===================================================================
--- rtl/bplib/nexys2/n2_cram_dummy.vhd (revision 14)
+++ rtl/bplib/nexys2/n2_cram_dummy.vhd (nonexistent)
@@ -1,64 +0,0 @@
--- $Id: n2_cram_dummy.vhd 426 2011-11-18 18:14:08Z mueller $
---
--- Copyright 2010- by Walter F.J. Mueller
---
--- This program is free software; you may redistribute and/or modify it under
--- the terms of the GNU General Public License as published by the Free
--- Software Foundation, either version 2, or at your option any later version.
---
--- This program is distributed in the hope that it will be useful, but
--- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
--- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
--- for complete details.
---
-------------------------------------------------------------------------------
--- Module Name: n2_cram_dummy - syn
--- Description: nexys2: CRAM protection dummy
---
--- Dependencies: -
--- Test bench: -
--- Target Devices: generic
--- Tool versions: xst 11.4; ghdl 0.26
--- Revision History:
--- Date Rev Version Comment
--- 2010-05-28 295 1.0.1 use _ADV_N
--- 2010-05-21 292 1.0 Initial version
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.slvtypes.all;
-
-entity n2_cram_dummy is -- CRAM protection dummy
- port (
- O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
- O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
- O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
- O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
- O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
- O_MEM_CLK : out slbit; -- cram: clock
- O_MEM_CRE : out slbit; -- cram: command register enable
- I_MEM_WAIT : in slbit; -- cram: mem wait
- O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
- O_MEM_ADDR : out slv23; -- cram: address lines
- IO_MEM_DATA : inout slv16 -- cram: data lines
- );
-end n2_cram_dummy;
-
-
-architecture syn of n2_cram_dummy is
-begin
-
- O_MEM_CE_N <= '1'; -- disable cram chip
- O_MEM_BE_N <= "11";
- O_MEM_WE_N <= '1';
- O_MEM_OE_N <= '1';
- O_MEM_ADV_N <= '1';
- O_MEM_CLK <= '0';
- O_MEM_CRE <= '0';
- O_FLA_CE_N <= '1';
- O_MEM_ADDR <= (others=>'0');
- IO_MEM_DATA <= (others=>'0');
-
-end syn;
Index: rtl/bplib/nexys2/n2_cram_memctl_as.vhd
===================================================================
--- rtl/bplib/nexys2/n2_cram_memctl_as.vhd (revision 14)
+++ rtl/bplib/nexys2/n2_cram_memctl_as.vhd (nonexistent)
@@ -1,587 +0,0 @@
--- $Id: n2_cram_memctl_as.vhd 427 2011-11-19 21:04:11Z mueller $
---
--- Copyright 2010-2011 by Walter F.J. Mueller
---
--- This program is free software; you may redistribute and/or modify it under
--- the terms of the GNU General Public License as published by the Free
--- Software Foundation, either version 2, or at your option any later version.
---
--- This program is distributed in the hope that it will be useful, but
--- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
--- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
--- for complete details.
---
-------------------------------------------------------------------------------
--- Module Name: n2_cram_memctl_as - syn
--- Description: nexys2: CRAM driver - async and page mode
---
--- Dependencies: vlib/xlib/iob_reg_o
--- vlib/xlib/iob_reg_o_gen
--- vlib/xlib/iob_reg_io_gen
--- Test bench: tb/tb_n2_cram_memctl
--- fw_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
--- Target Devices: generic
--- Tool versions: xst 11.4, 13.1; ghdl 0.26
---
--- Synthesized (xst):
--- Date Rev ise Target flop lutl lutm slic t peri
--- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 100 0 96 s 6.7
--- 2010-05-24 294 11.4 L68 xc3s1200e-4 91 99 0 95 s 6.7
--- 2010-05-23 293 11.4 L68 xc3s1200e-4 91 139 0 99 s 6.7
---
--- Revision History:
--- Date Rev Version Comment
--- 2011-11-19 427 1.0.5 now numeric_std clean
--- 2010-11-22 339 1.0.4 cntdly now 3 bit; add assert for DELAY generics
--- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read
--- cycle;
--- 2010-05-30 297 1.0.2 use READ(0|1)DELAY generic
--- 2010-05-24 294 1.0.1 more compact n.memdi logic; extra wait in s_rdwait1
--- 2010-05-23 293 1.0 Initial version
---
--- Notes:
--- 1. READ1DELAY of 2 is needed even though the timing of the memory suggests
--- that 1 cycle is enough (T_apa is 20 ns, so 40 ns round trip is ok). A
--- short READ1 delay works in sim, but not on fpga where the data od the
--- ADDR(0)=0 cycle is re-read (see notes_tst_sram_n2.txt).
--- tb_n2_cram_memctl_as_ISim_tsim works with full sdf even when T_apa is
--- 40ns or 50 ns, only T_apa 60 ns fails !
--- Unclear what is wrong here, the timing of the memory model seems ok.
--- 2. There is no 'bus-turn-around' cycle needed for a write->read change
--- FPGA_OE goes 1->0 and MEM_OE goes 0->1 on the s_wrput1->s_rdinit
--- transition simultaneously. The FPGA will go high-Z quickly, the memory
--- low-Z delay by the IOB and internal memory delays. No clash.
--- 3. There is a hidden 'bus-turn-around' cycle for a read->write change.
--- MEM_OE goes 1->0 on s_rdget1->s_wrinit and the memory will go high-z with
--- some dekal. FPGA_OE goes 0->1 in the next cycle at s_wrinit->s_wrwait0.
--- Again no clash due to the 1 cycle delay.
---
--- Nominal timings:
--- READ0/1 = N_rd_cycle - 2
--- WRITE = N_wr_cycle - 1
---
--- from notes_nexys2.txt (Rev 339):
--- clksys RD WR < use for > Test case
--- MHz div mul
--- <51.20 2 3 <-- 50 50 1 1
--- 51.20- 54.80 3 3 <-- 52,54 54 25 27
--- 54.80- 64.10 3 4 <-- 55,56,58,60,62,64 64 25 32
--- 64.10- 68.50 4 4 <-- 65 65 10 13
--- 68.50- 76.92 4 5 <-- 70,75 75 2 3
--- 76.92- 82.19 5 5 <-- 80 80 5 8
--- 82.19- 89.74 5 6 <-- 85 85 10 17
--- 89.74- 95.89 6 6 <-- 90,95 95 10 19
--- 95.89-102.56 6 7 <-- 100 100 1 2
---
--- Timing of some signals:
---
--- single read request:
---
--- state |_idle |_rdinit|_rdwt0 |_rdwt0 |_rdget0|_rdwt1 |_rdget1|
--- 0 20 40 60 80 100 120
--- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|
---
--- REQ _______|^^^^^|_____________________________________________
--- WE ___________________________________________________________
---
--- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
--- IOB_OE _________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
---
--- DO oooooooooooooooooooooooooooooooooooooooooo|lllllll|lllllll|h
--- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|________________
--- ACK_R ___________________________________________________________|^^^^^^^|_
---
--- single write request:
---
--- state |_idle |_wrinit|_wrwt0 |_wrwt0 |_wrwt0 |_wrput0|_idle |
--- 0 20 40 60 80 100 120
--- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|
---
--- REQ _______|^^^^^|______________________________________
--- WE _______|^^^^^|______________________________________
---
--- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
--- IOB_BE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
--- IOB_OE ____________________________________________________
--- IOB_WE ______________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_____
---
--- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_________
--- ACK_W __________________________________________|^^^^^^^|_
---
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.slvtypes.all;
-use work.xlib.all;
-
-entity n2_cram_memctl_as is -- CRAM driver (async+page mode)
- generic (
- READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
- READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
- WRITEDELAY : positive := 3); -- write delay in clock cycles
- port (
- CLK : in slbit; -- clock
- RESET : in slbit; -- reset
- REQ : in slbit; -- request
- WE : in slbit; -- write enable
- BUSY : out slbit; -- controller busy
- ACK_R : out slbit; -- acknowledge read
- ACK_W : out slbit; -- acknowledge write
- ACT_R : out slbit; -- signal active read
- ACT_W : out slbit; -- signal active write
- ADDR : in slv22; -- address (32 bit word address)
- BE : in slv4; -- byte enable
- DI : in slv32; -- data in (memory view)
- DO : out slv32; -- data out (memory view)
- O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
- O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
- O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
- O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
- O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
- O_MEM_CLK : out slbit; -- cram: clock
- O_MEM_CRE : out slbit; -- cram: command register enable
- I_MEM_WAIT : in slbit; -- cram: mem wait
- O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
- O_MEM_ADDR : out slv23; -- cram: address lines
- IO_MEM_DATA : inout slv16 -- cram: data lines
- );
-end n2_cram_memctl_as;
-
-
-architecture syn of n2_cram_memctl_as is
-
- type state_type is (
- s_idle, -- s_idle: wait for req
- s_rdinit, -- s_rdinit: read init cycle
- s_rdwait0, -- s_rdwait0: read wait low word
- s_rdget0, -- s_rdget0: read get low word
- s_rdwait1, -- s_rdwait1: read wait high word
- s_rdget1, -- s_rdget1: read get high word
- s_wrinit, -- s_wrinit: write init cycle
- s_wrwait0, -- s_rdwait0: write wait 1st word
- s_wrput0, -- s_rdput0: write put 1st word
- s_wrini1, -- s_wrini1: write init 2nd word
- s_wrwait1, -- s_wrwait1: write wait 2nd word
- s_wrput1 -- s_wrput1: write put 2nd word
- );
-
- type regs_type is record
- state : state_type; -- state
- ackr : slbit; -- signal ack_r
- addr0 : slbit; -- current addr0
- be2nd : slv2; -- be's of 2nd write cycle
- cntdly : slv3; -- wait delay counter
- cntce : slv7; -- ce counter
- fidle : slbit; -- force idle flag
- memdo0 : slv16; -- mem data out, low word
- memdi : slv32; -- mem data in
- end record regs_type;
-
- constant regs_init : regs_type := (
- s_idle, --
- '0', -- ackr
- '0', -- addr0
- "00", -- be2nd
- (others=>'0'), -- cntdly
- (others=>'0'), -- cntce
- '0', -- fidle
- (others=>'0'), -- memdo0
- (others=>'0') -- memdi
- );
-
- signal R_REGS : regs_type := regs_init; -- state registers
- signal N_REGS : regs_type := regs_init; -- next value state regs
-
- signal CLK_180 : slbit := '0';
- signal MEM_CE_N : slbit := '1';
- signal MEM_BE_N : slv2 := "11";
- signal MEM_WE_N : slbit := '1';
- signal MEM_OE_N : slbit := '1';
- signal BE_CE : slbit := '0';
- signal ADDRH_CE : slbit := '0';
- signal ADDR0_CE : slbit := '0';
- signal ADDR0 : slbit := '0';
- signal DATA_CEI : slbit := '0';
- signal DATA_CEO : slbit := '0';
- signal DATA_OE : slbit := '0';
- signal MEM_DO : slv16 := (others=>'0');
- signal MEM_DI : slv16 := (others=>'0');
-
--- these attributes aren't accepted by ghdl 0.26
--- attribute s : string;
--- attribute s of I_MEM_WAIT : signal is "true";
-
-begin
-
- assert READ0DELAY<=2**R_REGS.cntdly'length and
- READ1DELAY<=2**R_REGS.cntdly'length and
- WRITEDELAY<=2**R_REGS.cntdly'length
- report "assert(READ0,READ1,WRITEDELAY <= 2**cntdly'length)"
- severity failure;
-
- CLK_180 <= not CLK;
-
- IOB_MEM_CE : iob_reg_o
- generic map (
- INIT => '1')
- port map (
- CLK => CLK,
- CE => '1',
- DO => MEM_CE_N,
- PAD => O_MEM_CE_N
- );
-
- IOB_MEM_BE : iob_reg_o_gen
- generic map (
- DWIDTH => 2,
- INIT => '1')
- port map (
- CLK => CLK,
- CE => BE_CE,
- DO => MEM_BE_N,
- PAD => O_MEM_BE_N
- );
-
- IOB_MEM_WE : iob_reg_o
- generic map (
- INIT => '1')
- port map (
- CLK => CLK_180,
- CE => '1',
- DO => MEM_WE_N,
- PAD => O_MEM_WE_N
- );
-
- IOB_MEM_OE : iob_reg_o
- generic map (
- INIT => '1')
- port map (
- CLK => CLK,
- CE => '1',
- DO => MEM_OE_N,
- PAD => O_MEM_OE_N
- );
-
- IOB_MEM_ADDRH : iob_reg_o_gen
- generic map (
- DWIDTH => 22)
- port map (
- CLK => CLK,
- CE => ADDRH_CE,
- DO => ADDR,
- PAD => O_MEM_ADDR(22 downto 1)
- );
-
- IOB_MEM_ADDR0 : iob_reg_o
- port map (
- CLK => CLK,
- CE => ADDR0_CE,
- DO => ADDR0,
- PAD => O_MEM_ADDR(0)
- );
-
- IOB_MEM_DATA : iob_reg_io_gen
- generic map (
- DWIDTH => 16,
- PULL => "KEEP")
- port map (
- CLK => CLK,
- CEI => DATA_CEI,
- CEO => DATA_CEO,
- OE => DATA_OE,
- DI => MEM_DO,
- DO => MEM_DI,
- PAD => IO_MEM_DATA
- );
-
- O_MEM_ADV_N <= '0';
- O_MEM_CLK <= '0';
- O_MEM_CRE <= '0';
- O_FLA_CE_N <= '1';
-
- proc_regs: process (CLK)
- begin
-
- if rising_edge(CLK) then
- if RESET = '1' then
- R_REGS <= regs_init;
- else
- R_REGS <= N_REGS;
- end if;
- end if;
-
- end process proc_regs;
-
- proc_next: process (R_REGS, REQ, WE, BE, DI, MEM_DO)
-
- variable r : regs_type := regs_init;
- variable n : regs_type := regs_init;
- variable ibusy : slbit := '0';
- variable iackw : slbit := '0';
- variable iactr : slbit := '0';
- variable iactw : slbit := '0';
- variable imem_ce : slbit := '0';
- variable imem_be : slv2 := "00";
- variable imem_we : slbit := '0';
- variable imem_oe : slbit := '0';
- variable ibe_ce : slbit := '0';
- variable iaddrh_ce : slbit := '0';
- variable iaddr0_ce : slbit := '0';
- variable iaddr0 : slbit := '0';
- variable idata_cei : slbit := '0';
- variable idata_ceo : slbit := '0';
- variable idata_oe : slbit := '0';
-
- procedure do_dispatch(nstate : out state_type;
- iaddrh_ce : out slbit;
- iaddr0_ce : out slbit;
- iaddr0 : out slbit;
- ibe_ce : out slbit;
- imem_be : out slv2;
- imem_ce : out slbit;
- imem_oe : out slbit;
- nbe2nd : out slv2) is
- begin
- iaddrh_ce := '1'; -- latch address (high part)
- iaddr0_ce := '1'; -- latch address 0 bit
- ibe_ce := '1'; -- latch be's
- imem_ce := '1'; -- ce CRAM next cycle
- nbe2nd := "00"; -- assume no 2nd write cycle
- if WE = '0' then -- if READ requested
- iaddr0 := '0'; -- go first for low word
- imem_be := "11"; -- on read always on
- imem_oe := '1'; -- oe CRAM next cycle
- nstate := s_rdinit; -- next: read init part
- else -- if WRITE requested
- if BE(1 downto 0) /= "00" then -- low word write
- iaddr0 := '0'; -- access word 0
- imem_be := BE(1 downto 0); -- set be's for 1st cycle
- nbe2nd := BE(3 downto 2); -- keep be's for 2nd cycle
- else -- high word write
- iaddr0 := '1'; -- access word 1
- imem_be := BE(3 downto 2); -- set be's for 1st cycle
- end if;
- nstate := s_wrinit; -- next: write init part
- end if;
- end procedure do_dispatch;
-
- begin
-
- r := R_REGS;
- n := R_REGS;
- n.ackr := '0';
-
- ibusy := '0';
- iackw := '0';
- iactr := '0';
- iactw := '0';
-
- imem_ce := '0';
- imem_be := "11";
- imem_we := '0';
- imem_oe := '0';
- ibe_ce := '0';
- iaddrh_ce := '0';
- iaddr0_ce := '0';
- iaddr0 := '0';
- idata_cei := '0';
- idata_ceo := '0';
- idata_oe := '0';
-
- if unsigned(r.cntdly) /= 0 then
- n.cntdly := slv(unsigned(r.cntdly) - 1);
- end if;
-
- case r.state is
- when s_idle => -- s_idle: wait for req
- if REQ = '1' then -- if IO requested
- do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
- ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
- end if;
-
- when s_rdinit => -- s_rdinit: read init cycle
- ibusy := '1'; -- signal busy, unable to handle req
- iactr := '1'; -- signal mem read
- imem_ce := '1'; -- ce CRAM next cycle
- imem_oe := '1'; -- oe CRAM next cycle
- n.cntdly:= slv(to_unsigned(READ0DELAY-1, n.cntdly'length));
- n.state := s_rdwait0; -- next: wait
-
- when s_rdwait0 => -- s_rdwait0: read wait low word
- ibusy := '1'; -- signal busy, unable to handle req
- iactr := '1'; -- signal mem read
- imem_ce := '1'; -- ce CRAM next cycle
- imem_oe := '1'; -- oe CRAM next cycle
- if unsigned(r.cntdly) = 0 then -- wait expired ?
- n.state := s_rdget0; -- next: get low word
- end if;
-
- when s_rdget0 => -- s_rdget0: read get low word
- ibusy := '1'; -- signal busy, unable to handle req
- iactr := '1'; -- signal mem read
- imem_ce := '1'; -- ce CRAM next cycle
- imem_oe := '1'; -- oe CRAM next cycle
- idata_cei := '1'; -- latch input data
- iaddr0_ce := '1'; -- latch address 0 bit
- iaddr0 := '1'; -- now go for high word
- n.cntdly:= slv(to_unsigned(READ1DELAY-1, n.cntdly'length));
- n.state := s_rdwait1; -- next: wait high word
-
- when s_rdwait1 => -- s_rdwait1: read wait high word
- ibusy := '1'; -- signal busy, unable to handle req
- iactr := '1'; -- signal mem read
- imem_ce := '1'; -- ce CRAM next cycle
- imem_oe := '1'; -- oe CRAM next cycle
- if unsigned(r.cntdly) = 0 then -- wait expired ?
- n.state := s_rdget1; -- next: get low word
- end if; --
-
- when s_rdget1 => -- s_rdget1: read get high word
- iactr := '1'; -- signal mem read
- n.memdo0:= MEM_DO; -- save low word data
- idata_cei := '1'; -- latch input data
- n.ackr := '1'; -- ACK_R next cycle
- n.state := s_idle; -- next: wait next request
- if r.fidle = '1' then -- forced idle cycle
- ibusy := '1'; -- signal busy, unable to handle req
- else
- if REQ = '1' then -- if IO requested
- do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
- ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
- end if;
- end if;
-
- when s_wrinit => -- s_wrinit: write init cycle
- ibusy := '1'; -- signal busy, unable to handle req
- iactw := '1'; -- signal mem write
- iackw := '1'; -- signal write done (all latched)
- idata_ceo:= '1'; -- latch output data
- idata_oe := '1'; -- oe FPGA next cycle
- imem_ce := '1'; -- ce CRAM next cycle
- imem_we := '1'; -- we CRAM in half cycle
- n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
- n.state := s_wrwait0; -- next: wait
-
- when s_wrwait0 => -- s_rdput0: write wait 1st word
- ibusy := '1'; -- signal busy, unable to handle req
- iactw := '1'; -- signal mem write
- idata_oe := '1'; -- oe FPGA next cycle
- imem_ce := '1'; -- ce CRAM next cycle
- imem_we := '1'; -- we CRAM next cycle
- if unsigned(r.cntdly) = 0 then -- wait expired ?
- n.state := s_wrput0; -- next: put 1st word
- end if;
-
- when s_wrput0 => -- s_rdput0: write put 1st word
- iactw := '1'; -- signal mem write
- imem_we := '0'; -- deassert we CRAM in half cycle
- if r.be2nd /= "00" then
- ibusy := '1'; -- signal busy, unable to handle req
- imem_ce := '1'; -- ce CRAM next cycle
- iaddr0_ce := '1'; -- latch address 0 bit
- iaddr0 := '1'; -- now go for high word
- ibe_ce := '1'; -- latch be's
- imem_be := r.be2nd; -- now be's of high word
- n.state := s_wrini1; -- next: start 2nd write
- else
- n.state := s_idle; -- next: wait next request
- if r.fidle = '1' then -- forced idle cycle
- ibusy := '1'; -- signal busy
- else
- if REQ = '1' then -- if IO requested
- do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
- ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
- end if;
- end if;
- end if;
-
- when s_wrini1 => -- s_wrini1: write init 2nd word
- ibusy := '1'; -- signal busy, unable to handle req
- iactw := '1'; -- signal mem write
- idata_ceo:= '1'; -- latch output data
- idata_oe := '1'; -- oe FPGA next cycle
- imem_ce := '1'; -- ce CRAM next cycle
- imem_we := '1'; -- we CRAM in half cycle
- n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
- n.state := s_wrwait1; -- next: wait
-
- when s_wrwait1 => -- s_wrwait1: write wait 2nd word
- ibusy := '1'; -- signal busy, unable to handle req
- iactw := '1'; -- signal mem write
- idata_oe := '1'; -- oe FPGA next cycle
- imem_ce := '1'; -- ce CRAM next cycle
- imem_we := '1'; -- we CRAM next cycle
- if unsigned(r.cntdly) = 0 then -- wait expired ?
- n.state := s_wrput1; -- next: put 2nd word
- end if;
-
- when s_wrput1 => -- s_wrput1: write put 2nd word
- iactw := '1'; -- signal mem write
- imem_we := '0'; -- deassert we CRAM in half cycle
- n.state := s_idle; -- next: wait next request
- if r.fidle = '1' then -- forced idle cycle
- ibusy := '1'; -- signal busy, unable to handle req
- else
- if REQ = '1' then -- if IO requested
- do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
- ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
- end if;
- end if;
-
- when others => null;
- end case;
-
- if imem_ce = '0' then -- if cmem not active
- n.cntce := (others=>'0'); -- clear counter
- n.fidle := '0'; -- clear force idle flag
- else -- if cmem active
- if unsigned(r.cntce) >= 127 then -- if max ce count expired
- n.fidle := '1'; -- set forced idle flag
- else -- if max ce count not yet reached
- n.cntce := slv(unsigned(r.cntce) + 1); -- increment counter
- end if;
- end if;
-
- if iaddrh_ce = '1' then -- if addresses are latched
- n.memdi := DI; -- latch data too...
- end if;
-
- if iaddr0_ce = '1' then -- if address bit 0 changed
- n.addr0 := iaddr0; -- mirror it in state regs
- end if;
-
- N_REGS <= n;
-
- MEM_CE_N <= not imem_ce;
- MEM_WE_N <= not imem_we;
- MEM_BE_N <= not imem_be;
- MEM_OE_N <= not imem_oe;
-
- if r.addr0 = '0' then
- MEM_DI <= r.memdi(15 downto 0);
- else
- MEM_DI <= r.memdi(31 downto 16);
- end if;
-
- BE_CE <= ibe_ce;
- ADDRH_CE <= iaddrh_ce;
- ADDR0_CE <= iaddr0_ce;
- ADDR0 <= iaddr0;
- DATA_CEI <= idata_cei;
- DATA_CEO <= idata_ceo;
- DATA_OE <= idata_oe;
-
- BUSY <= ibusy;
- ACK_R <= r.ackr;
- ACK_W <= iackw;
- ACT_R <= iactr;
- ACT_W <= iactw;
-
- DO <= MEM_DO & r.memdo0;
-
- end process proc_next;
-
-end syn;
Index: rtl/bplib/nexys2/n2_cram_dummy.vbom
===================================================================
--- rtl/bplib/nexys2/n2_cram_dummy.vbom (revision 14)
+++ rtl/bplib/nexys2/n2_cram_dummy.vbom (nonexistent)
@@ -1,5 +0,0 @@
-# libs
-../../vlib/slvtypes.vhd
-# components
-# design
-n2_cram_dummy.vhd
Index: rtl/bplib/nexys2/nexys2lib.vhd
===================================================================
--- rtl/bplib/nexys2/nexys2lib.vhd (revision 14)
+++ rtl/bplib/nexys2/nexys2lib.vhd (revision 15)
@@ -1,6 +1,6 @@
--- $Id: nexys2lib.vhd 389 2011-07-07 21:59:00Z mueller $
+-- $Id: nexys2lib.vhd 433 2011-11-27 22:04:39Z mueller $
--
--- Copyright 2010- by Walter F.J. Mueller
+-- Copyright 2010-2011 by Walter F.J. Mueller
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,10 +16,12 @@
-- Description: Nexys 2 components
--
-- Dependencies: -
--- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
+-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
+-- 2011-11-26 433 1.2 remove n2_cram_* modules, now in nxcramlib
+-- 2011-11-23 432 1.1 remove O_FLA_CE_N port in cram driver/dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS to aif's (DCM derived system clock)
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0.3 use _ADV_N also for n2_cram_dummy
@@ -41,9 +43,9 @@
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
- I_SWI : in slv8; -- s3 switches
- I_BTN : in slv4; -- s3 buttons
- O_LED : out slv8; -- s3 leds
+ I_SWI : in slv8; -- n2 switches
+ I_BTN : in slv4; -- n2 buttons
+ O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
@@ -54,9 +56,9 @@
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
- O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_MEM_ADDR : out slv23; -- cram: address lines
- IO_MEM_DATA : inout slv16 -- cram: data lines
+ IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_FLA_CE_N : out slbit -- flash ce.. (act.low)
);
end component;
@@ -66,9 +68,9 @@
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
- I_SWI : in slv8; -- s3 switches
- I_BTN : in slv4; -- s3 buttons
- O_LED : out slv8; -- s3 leds
+ I_SWI : in slv8; -- n2 switches
+ I_BTN : in slv4; -- n2 buttons
+ O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
@@ -79,9 +81,9 @@
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
- O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
@@ -89,53 +91,4 @@
);
end component;
-component n2_cram_dummy is -- CRAM protection dummy
- port (
- O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
- O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
- O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
- O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
- O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
- O_MEM_CLK : out slbit; -- cram: clock
- O_MEM_CRE : out slbit; -- cram: command register enable
- I_MEM_WAIT : in slbit; -- cram: mem wait
- O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
- O_MEM_ADDR : out slv23; -- cram: address lines
- IO_MEM_DATA : inout slv16 -- cram: data lines
- );
-end component;
-
-component n2_cram_memctl_as is -- CRAM driver (async+page mode)
- generic (
- READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
- READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
- WRITEDELAY : positive := 3); -- write delay in clock cycles
- port (
- CLK : in slbit; -- clock
- RESET : in slbit; -- reset
- REQ : in slbit; -- request
- WE : in slbit; -- write enable
- BUSY : out slbit; -- controller busy
- ACK_R : out slbit; -- acknowledge read
- ACK_W : out slbit; -- acknowledge write
- ACT_R : out slbit; -- signal active read
- ACT_W : out slbit; -- signal active write
- ADDR : in slv22; -- address (32 bit word address)
- BE : in slv4; -- byte enable
- DI : in slv32; -- data in (memory view)
- DO : out slv32; -- data out (memory view)
- O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
- O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
- O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
- O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
- O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
- O_MEM_CLK : out slbit; -- cram: clock
- O_MEM_CRE : out slbit; -- cram: command register enable
- I_MEM_WAIT : in slbit; -- cram: mem wait
- O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
- O_MEM_ADDR : out slv23; -- cram: address lines
- IO_MEM_DATA : inout slv16 -- cram: data lines
- );
-end component;
-
end package nexys2lib;
/rtl/bplib/nexys2/tb/tbw.dat
File deleted
/rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vhd
1,6 → 1,6
-- $Id: nexys2_fusp_dummy.vhd 338 2010-11-13 22:19:25Z mueller $ |
-- $Id: nexys2_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $ |
-- |
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
18,10 → 18,12
-- Dependencies: - |
-- To test: tb_nexys2 |
-- Target Devices: generic |
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29 |
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-26 433 1.2 use nxcramlib |
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy |
-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock) |
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50 |
-- 2010-05-28 295 1.0 Initial version (derived from s3board_fusp_dummy) |
31,7 → 33,7
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.nexys2lib.all; |
use work.nxcramlib.all; |
|
entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback) |
-- implements nexys2_fusp_aif |
40,9 → 42,9
O_CLKSYS : out slbit; -- DCM derived system clock |
I_RXD : in slbit; -- receive data (board view) |
O_TXD : out slbit; -- transmit data (board view) |
I_SWI : in slv8; -- s3 switches |
I_BTN : in slv4; -- s3 buttons |
O_LED : out slv8; -- s3 leds |
I_SWI : in slv8; -- n2 switches |
I_BTN : in slv4; -- n2 buttons |
O_LED : out slv8; -- n2 leds |
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) |
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) |
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) |
53,9 → 55,9
O_MEM_CLK : out slbit; -- cram: clock |
O_MEM_CRE : out slbit; -- cram: command register enable |
I_MEM_WAIT : in slbit; -- cram: mem wait |
O_FLA_CE_N : out slbit; -- flash ce.. (act.low) |
O_MEM_ADDR : out slv23; -- cram: address lines |
IO_MEM_DATA : inout slv16; -- cram: data lines |
O_FLA_CE_N : out slbit; -- flash ce.. (act.low) |
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n |
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n |
I_FUSP_RXD : in slbit; -- fusp: rs232 rx |
72,7 → 74,7
O_FUSP_TXD <= I_FUSP_RXD; |
O_FUSP_RTS_N <= I_FUSP_CTS_N; |
|
CRAM : n2_cram_dummy -- connect CRAM to protection dummy |
CRAM : nx_cram_dummy -- connect CRAM to protection dummy |
port map ( |
O_MEM_CE_N => O_MEM_CE_N, |
O_MEM_BE_N => O_MEM_BE_N, |
82,9 → 84,10
O_MEM_CLK => O_MEM_CLK, |
O_MEM_CRE => O_MEM_CRE, |
I_MEM_WAIT => I_MEM_WAIT, |
O_FLA_CE_N => O_FLA_CE_N, |
O_MEM_ADDR => O_MEM_ADDR, |
IO_MEM_DATA => IO_MEM_DATA |
); |
|
O_FLA_CE_N <= '1'; -- keep Flash memory disabled |
|
end syn; |
/rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vbom
1,7 → 1,7
# libs |
../../../vlib/slvtypes.vhd |
../nexys2lib.vhd |
../../nxcramlib/nxcramlib.vhd |
# components |
../n2_cram_dummy.vbom |
../../nxcramlib/nx_cram_dummy.vbom |
# design |
nexys2_fusp_dummy.vhd |
/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd
1,4 → 1,4
-- $Id: tb_nexys2_core.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- $Id: tb_nexys2_core.vhd 433 2011-11-27 22:04:39Z mueller $ |
-- |
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
23,6 → 23,8
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-26 433 1.1.1 remove O_FLA_CE_N from tb_nexys2_core |
-- 2011-11-21 432 1.1 update O_FLA_CE_N usage |
-- 2011-11-19 427 1.0.1 now numeric_std clean |
-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board_core) |
------------------------------------------------------------------------------ |
49,7 → 51,6
O_MEM_CLK : in slbit; -- cram: clock |
O_MEM_CRE : in slbit; -- cram: command register enable |
I_MEM_WAIT : out slbit; -- cram: mem wait |
O_FLA_CE_N : in slbit; -- flash ce.. (act.low) |
O_MEM_ADDR : in slv23; -- cram: address lines |
IO_MEM_DATA : inout slv16 -- cram: data lines |
); |
/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
1,4 → 1,4
-- $Id: tb_nexys2_fusp.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- $Id: tb_nexys2_fusp.vhd 433 2011-11-27 22:04:39Z mueller $ |
-- |
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
27,6 → 27,8
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core |
-- 2011-11-21 432 3.1 update O_FLA_CE_N usage |
-- 2011-11-19 427 3.0.1 now numeric_std clean |
-- 2010-12-29 351 3.0 use rlink/tb now |
-- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm |
84,9 → 86,9
signal O_MEM_CLK : slbit := '0'; |
signal O_MEM_CRE : slbit := '0'; |
signal I_MEM_WAIT : slbit := '0'; |
signal O_FLA_CE_N : slbit := '0'; |
signal O_MEM_ADDR : slv23 := (others=>'Z'); |
signal IO_MEM_DATA : slv16 := (others=>'0'); |
signal O_FLA_CE_N : slbit := '0'; |
|
signal O_FUSP_RTS_N : slbit := '0'; |
signal I_FUSP_CTS_N : slbit := '0'; |
140,7 → 142,6
O_MEM_CLK => O_MEM_CLK, |
O_MEM_CRE => O_MEM_CRE, |
I_MEM_WAIT => I_MEM_WAIT, |
O_FLA_CE_N => O_FLA_CE_N, |
O_MEM_ADDR => O_MEM_ADDR, |
IO_MEM_DATA => IO_MEM_DATA |
); |
164,9 → 165,9
O_MEM_CLK => O_MEM_CLK, |
O_MEM_CRE => O_MEM_CRE, |
I_MEM_WAIT => I_MEM_WAIT, |
O_FLA_CE_N => O_FLA_CE_N, |
O_MEM_ADDR => O_MEM_ADDR, |
IO_MEM_DATA => IO_MEM_DATA, |
O_FLA_CE_N => O_FLA_CE_N, |
O_FUSP_RTS_N => O_FUSP_RTS_N, |
I_FUSP_CTS_N => I_FUSP_CTS_N, |
I_FUSP_RXD => I_FUSP_RXD, |
/rtl/bplib/nexys2/tb/.cvsignore
1,7 → 1,2
tb_nexys2_dummy |
tb_nexys2_fusp_dummy |
tb_n2_cram_memctl_as |
tb_n2_cram_memctl_as_[sft]sim |
tb_n2_cram_memctl_as_ISim |
tb_n2_cram_memctl_as_ISim_[sft]sim |
tb_n2_cram_memctl_stim |
/rtl/bplib/nexys2/tb/Makefile
1,13 → 1,14
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $ |
# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2011-11-26 433 1.2 remove tb_n2_cram_memctl_as (moved to nxcramlib) |
# 2011-08-13 405 1.1 use includes from rtl/make |
# 2010-05-30 297 1.0.2 use tb_n2_cram_memctl_as now |
# 2010-05-28 295 1.0.1 add tb_.._dummy's |
# 2007-09-23 84 1.0 Initial version |
# |
EXE_all = tb_nexys2_dummy tb_nexys2_fusp_dummy tb_n2_cram_memctl_as |
EXE_all = tb_nexys2_dummy tb_nexys2_fusp_dummy |
# |
ISE_PATH = xc3s1200e-fg320-4 |
# |
rtl/bplib/nexys2/tb
Property changes :
Modified: svn:ignore
## -32,8 +32,3 ##
*_[dsft]sim.log
tb_nexys2_dummy
tb_nexys2_fusp_dummy
-tb_n2_cram_memctl_as
-tb_n2_cram_memctl_as_[sft]sim
-tb_n2_cram_memctl_as_ISim
-tb_n2_cram_memctl_as_ISim_[sft]sim
-tb_n2_cram_memctl_stim
Index: rtl/bplib/nexys2/nexys2_pins.ucf
===================================================================
--- rtl/bplib/nexys2/nexys2_pins.ucf (revision 14)
+++ rtl/bplib/nexys2/nexys2_pins.ucf (revision 15)
@@ -1,4 +1,4 @@
-## $Id: nexys2_pins.ucf 402 2011-08-05 18:56:44Z mueller $
+## $Id: nexys2_pins.ucf 432 2011-11-25 20:16:28Z mueller $
##
## Pin locks for Nexys 2 core functionality (for 1200k FPGA)
## - internal RS232
@@ -82,8 +82,6 @@
NET "O_MEM_CRE" LOC = "p7" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "I_MEM_WAIT" LOC = "f5" | IOSTANDARD=LVCMOS33 | PULLDOWN;
##
-NET "O_FLA_CE_N" LOC = "r5" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
-##
NET "O_MEM_ADDR<0>" LOC = "j1" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<1>" LOC = "j2" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<2>" LOC = "h4" | IOSTANDARD=LVCMOS33;
@@ -127,3 +125,6 @@
NET "IO_MEM_DATA<15>" LOC = "t1" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER;
##
+## Flash ---------------------------------------------------------------------
+NET "O_FLA_CE_N" LOC = "r5" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW;
+##
Index: rtl/bplib/nexys3/nexys3lib.vhd
===================================================================
--- rtl/bplib/nexys3/nexys3lib.vhd (nonexistent)
+++ rtl/bplib/nexys3/nexys3lib.vhd (revision 15)
@@ -0,0 +1,87 @@
+-- $Id: nexys3lib.vhd 432 2011-11-25 20:16:28Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: nexys3lib
+-- Description: Nexys 3 components
+--
+-- Dependencies: -
+-- Tool versions: xst 13.1; ghdl 0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-25 432 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package nexys3lib is
+
+component nexys3_aif is -- NEXYS 3, abstract iface, base
+ port (
+ I_CLK100 : in slbit; -- 100 MHz clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- n3 switches
+ I_BTN : in slv5; -- n3 buttons
+ O_LED : out slv8; -- n3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_PPCM_CE_N : out slbit; -- ppcm: ...
+ O_PPCM_RST_N : out slbit -- ppcm: ...
+ );
+end component;
+
+component nexys3_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
+ port (
+ I_CLK100 : in slbit; -- 100 MHz clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- n3 switches
+ I_BTN : in slv5; -- n3 buttons
+ O_LED : out slv8; -- n3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_PPCM_CE_N : out slbit; -- ppcm: ...
+ O_PPCM_RST_N : out slbit; -- ppcm: ...
+ O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
+ I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
+ I_FUSP_RXD : in slbit; -- fusp: rs232 rx
+ O_FUSP_TXD : out slbit -- fusp: rs232 tx
+ );
+end component;
+
+end package nexys3lib;
Index: rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vhd
===================================================================
--- rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vhd (nonexistent)
+++ rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vhd (revision 15)
@@ -0,0 +1,90 @@
+-- $Id: nexys3_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: nexys3_dummy - syn
+-- Description: nexys3 minimal target (base; serport loopback)
+--
+-- Dependencies: -
+-- To test: tb_nexys3
+-- Target Devices: generic
+-- Tool versions: xst 13.1; ghdl 0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-26 433 1.1 use nxcramlib
+-- 2011-11-25 432 1.0 Initial version (derived from nexys2_fusp_dummy)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.nxcramlib.all;
+
+entity nexys3_fusp_dummy is -- NEXYS 3 dummy (base+fusp; loopback)
+ -- implements nexys3_fusp_aif
+ port (
+ I_CLK100 : in slbit; -- 100 MHz board clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- n3 switches
+ I_BTN : in slv5; -- n3 buttons
+ O_LED : out slv8; -- n3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_PPCM_CE_N : out slbit; -- ppcm: ...
+ O_PPCM_RST_N : out slbit; -- ppcm: ...
+ O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
+ I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
+ I_FUSP_RXD : in slbit; -- fusp: rs232 rx
+ O_FUSP_TXD : out slbit -- fusp: rs232 tx
+ );
+end nexys3_fusp_dummy;
+
+architecture syn of nexys3_fusp_dummy is
+
+begin
+
+ O_TXD <= I_RXD; -- loop back
+ O_FUSP_TXD <= I_FUSP_RXD;
+ O_FUSP_RTS_N <= I_FUSP_CTS_N;
+
+ CRAM : nx_cram_dummy -- connect CRAM to protection dummy
+ port map (
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
+ O_PPCM_RST_N <= '1'; --
+
+end syn;
Index: rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vbom
===================================================================
--- rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vbom (nonexistent)
+++ rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vbom (revision 15)
@@ -0,0 +1,7 @@
+# libs
+../../../vlib/slvtypes.vhd
+../../nxcramlib/nxcramlib.vhd
+# components
+../../nxcramlib/nx_cram_dummy.vbom
+# design
+nexys3_fusp_dummy.vhd
Index: rtl/bplib/nexys3/tb/tb_nexys3_core.vhd
===================================================================
--- rtl/bplib/nexys3/tb/tb_nexys3_core.vhd (nonexistent)
+++ rtl/bplib/nexys3/tb/tb_nexys3_core.vhd (revision 15)
@@ -0,0 +1,96 @@
+-- $Id: tb_nexys3_core.vhd 432 2011-11-25 20:16:28Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_nexys3_core - sim
+-- Description: Test bench for nexys3 - core device handling
+--
+-- Dependencies: vlib/parts/micron/mt45w8mw16b
+--
+-- To test: generic, any nexys3 target
+--
+-- Target Devices: generic
+-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.serport.all;
+use work.simbus.all;
+
+entity tb_nexys3_core is
+ port (
+ I_SWI : out slv8; -- n3 switches
+ I_BTN : out slv5; -- n3 buttons
+ O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : in slbit; -- cram: clock
+ O_MEM_CRE : in slbit; -- cram: command register enable
+ I_MEM_WAIT : out slbit; -- cram: mem wait
+ O_MEM_ADDR : in slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16 -- cram: data lines
+ );
+end tb_nexys3_core;
+
+architecture sim of tb_nexys3_core is
+
+ signal R_SWI : slv8 := (others=>'0');
+ signal R_BTN : slv5 := (others=>'0');
+
+ constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
+ constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
+
+begin
+
+ MEM : entity work.mt45w8mw16b
+ port map (
+ CLK => O_MEM_CLK,
+ CE_N => O_MEM_CE_N,
+ OE_N => O_MEM_OE_N,
+ WE_N => O_MEM_WE_N,
+ UB_N => O_MEM_BE_N(1),
+ LB_N => O_MEM_BE_N(0),
+ ADV_N => O_MEM_ADV_N,
+ CRE => O_MEM_CRE,
+ MWAIT => I_MEM_WAIT,
+ ADDR => O_MEM_ADDR,
+ DATA => IO_MEM_DATA
+ );
+
+ proc_simbus: process (SB_VAL)
+ begin
+ if SB_VAL'event and to_x01(SB_VAL)='1' then
+ if SB_ADDR = sbaddr_swi then
+ R_SWI <= to_x01(SB_DATA(R_SWI'range));
+ end if;
+ if SB_ADDR = sbaddr_btn then
+ R_BTN <= to_x01(SB_DATA(R_BTN'range));
+ end if;
+ end if;
+ end process proc_simbus;
+
+ I_SWI <= R_SWI;
+ I_BTN <= R_BTN;
+
+end sim;
Index: rtl/bplib/nexys3/tb/tb_nexys3_core.vbom
===================================================================
--- rtl/bplib/nexys3/tb/tb_nexys3_core.vbom (nonexistent)
+++ rtl/bplib/nexys3/tb/tb_nexys3_core.vbom (revision 15)
@@ -0,0 +1,10 @@
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/serport/serport.vhd
+../../../vlib/simlib/simbus.vhd
+# components
+../../../vlib/serport/serport_uart_rx.vbom
+../../../vlib/serport/serport_uart_tx.vbom
+../../micron/mt45w8mw16b.vbom
+# design
+tb_nexys3_core.vhd
Index: rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd
===================================================================
--- rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd (nonexistent)
+++ rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd (revision 15)
@@ -0,0 +1,250 @@
+-- $Id: tb_nexys3_fusp.vhd 433 2011-11-27 22:04:39Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_nexys3_fusp - sim
+-- Description: Test bench for nexys3 (base+fusp)
+--
+-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
+-- vlib/xlib/dcm_sfs
+-- tb_nexys3_core
+-- vlib/serport/serport_uart_rxtx
+-- nexys3_fusp_aif [UUT]
+--
+-- To test: generic, any nexys3_fusp_aif target
+--
+-- Target Devices: generic
+-- Tool versions: xst 13.1; ghdl 0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.rlinklib.all;
+use work.rlinktblib.all;
+use work.serport.all;
+use work.xlib.all;
+use work.nexys3lib.all;
+use work.simlib.all;
+use work.simbus.all;
+use work.sys_conf.all;
+
+entity tb_nexys3_fusp is
+end tb_nexys3_fusp;
+
+architecture sim of tb_nexys3_fusp is
+
+ signal CLKOSC : slbit := '0';
+ signal CLKSYS : slbit := '0';
+
+ signal RESET : slbit := '0';
+ signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
+ signal RXDATA : slv8 := (others=>'0');
+ signal RXVAL : slbit := '0';
+ signal RXERR : slbit := '0';
+ signal RXACT : slbit := '0';
+ signal TXDATA : slv8 := (others=>'0');
+ signal TXENA : slbit := '0';
+ signal TXBUSY : slbit := '0';
+
+ signal RX_HOLD : slbit := '0';
+
+ signal I_RXD : slbit := '1';
+ signal O_TXD : slbit := '1';
+ signal I_SWI : slv8 := (others=>'0');
+ signal I_BTN : slv5 := (others=>'0');
+ signal O_LED : slv8 := (others=>'0');
+ signal O_ANO_N : slv4 := (others=>'0');
+ signal O_SEG_N : slv8 := (others=>'0');
+
+ signal O_MEM_CE_N : slbit := '1';
+ signal O_MEM_BE_N : slv2 := (others=>'1');
+ signal O_MEM_WE_N : slbit := '1';
+ signal O_MEM_OE_N : slbit := '1';
+ signal O_MEM_ADV_N : slbit := '1';
+ signal O_MEM_CLK : slbit := '0';
+ signal O_MEM_CRE : slbit := '0';
+ signal I_MEM_WAIT : slbit := '0';
+ signal O_MEM_ADDR : slv23 := (others=>'Z');
+ signal IO_MEM_DATA : slv16 := (others=>'0');
+ signal O_PPCM_CE_N : slbit := '0';
+ signal O_PPCM_RST_N : slbit := '0';
+
+ signal O_FUSP_RTS_N : slbit := '0';
+ signal I_FUSP_CTS_N : slbit := '0';
+ signal I_FUSP_RXD : slbit := '1';
+ signal O_FUSP_TXD : slbit := '1';
+
+ signal UART_RESET : slbit := '0';
+ signal UART_RXD : slbit := '1';
+ signal UART_TXD : slbit := '1';
+ signal CTS_N : slbit := '0';
+ signal RTS_N : slbit := '0';
+
+ signal R_PORTSEL : slbit := '0';
+
+ constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
+
+ constant clockosc_period : time := 10 ns;
+ constant clockosc_offset : time := 200 ns;
+ constant setup_time : time := 5 ns;
+ constant c2out_time : time := 9 ns;
+
+begin
+
+ TBCORE : tbcore_rlink_dcm
+ generic map (
+ CLKOSC_PERIOD => clockosc_period,
+ CLKOSC_OFFSET => clockosc_offset,
+ SETUP_TIME => setup_time,
+ C2OUT_TIME => c2out_time)
+ port map (
+ CLKOSC => CLKOSC,
+ CLKSYS => CLKSYS,
+ RX_DATA => TXDATA,
+ RX_VAL => TXENA,
+ RX_HOLD => RX_HOLD,
+ TX_DATA => RXDATA,
+ TX_ENA => RXVAL
+ );
+
+ DCM_SYS : dcm_sfs
+ generic map (
+ CLKFX_DIVIDE => sys_conf_clkfx_divide,
+ CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
+ CLKIN_PERIOD => 10.0)
+ port map (
+ CLKIN => CLKOSC,
+ CLKFX => CLKSYS,
+ LOCKED => open
+ );
+
+ RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
+
+ N3CORE : entity work.tb_nexys3_core
+ port map (
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ UUT : nexys3_fusp_aif
+ port map (
+ I_CLK100 => CLKOSC,
+ I_RXD => I_RXD,
+ O_TXD => O_TXD,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => O_LED,
+ O_ANO_N => O_ANO_N,
+ O_SEG_N => O_SEG_N,
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA,
+ O_PPCM_CE_N => O_PPCM_CE_N,
+ O_PPCM_RST_N => O_PPCM_RST_N,
+ O_FUSP_RTS_N => O_FUSP_RTS_N,
+ I_FUSP_CTS_N => I_FUSP_CTS_N,
+ I_FUSP_RXD => I_FUSP_RXD,
+ O_FUSP_TXD => O_FUSP_TXD
+ );
+
+ UART : serport_uart_rxtx
+ generic map (
+ CDWIDTH => CLKDIV'length)
+ port map (
+ CLK => CLKSYS,
+ RESET => UART_RESET,
+ CLKDIV => CLKDIV,
+ RXSD => UART_RXD,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXERR => RXERR,
+ RXACT => RXACT,
+ TXSD => UART_TXD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY
+ );
+
+ proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
+ O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
+ begin
+
+ if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
+ I_RXD <= UART_TXD; -- write port 0 inputs
+ UART_RXD <= O_TXD; -- get port 0 outputs
+ RTS_N <= '0';
+ I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
+ I_FUSP_CTS_N <= '0';
+ else -- otherwise use pmod1 rs232
+ I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
+ I_FUSP_CTS_N <= CTS_N;
+ UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
+ RTS_N <= O_FUSP_RTS_N;
+ I_RXD <= '1'; -- port 0 inputs to idle state
+ end if;
+
+ end process proc_port_mux;
+
+ proc_moni: process
+ variable oline : line;
+ begin
+
+ loop
+ wait until rising_edge(CLKSYS);
+ wait for c2out_time;
+
+ if RXERR = '1' then
+ writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
+ writeline(output, oline);
+ end if;
+
+ end loop;
+
+ end process proc_moni;
+
+ proc_simbus: process (SB_VAL)
+ begin
+ if SB_VAL'event and to_x01(SB_VAL)='1' then
+ if SB_ADDR = sbaddr_portsel then
+ R_PORTSEL <= to_x01(SB_DATA(0));
+ end if;
+ end if;
+ end process proc_simbus;
+
+end sim;
Index: rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom
===================================================================
--- rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom (nonexistent)
+++ rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom (revision 15)
@@ -0,0 +1,23 @@
+# Not meant for direct top level usage. Used with
+# tb_nexys3_fusp_(....)[_ssim].vbom and config
+# lines to generate the different cases.
+#
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/rlink/rlinklib.vbom
+../../../vlib/rlink/tb/rlinktblib.vhd
+../../../vlib/serport/serport.vhd
+../../../vlib/xlib/xlib.vhd
+../nexys3lib.vhd
+../../../vlib/simlib/simlib.vhd
+../../../vlib/simlib/simbus.vhd
+sys_conf : sys_conf_sim.vhd
+# components
+../../../vlib/rlink/tb/tbcore_rlink_dcm.vbom
+../../../vlib/xlib/dcm_sfs_gsim.vbom
+tb_nexys3_core.vbom
+../../../vlib/serport/serport_uart_rxtx.vbom
+nexys3_fusp_aif : nexys3_fusp_dummy.vbom
+# design
+tb_nexys3_fusp.vhd
+@top:tb_nexys3_fusp
Index: rtl/bplib/nexys3/tb/Makefile
===================================================================
--- rtl/bplib/nexys3/tb/Makefile (nonexistent)
+++ rtl/bplib/nexys3/tb/Makefile (revision 15)
@@ -0,0 +1,34 @@
+# $Id: Makefile 433 2011-11-27 22:04:39Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2011-11-26 432 1.0 Initial version
+#
+EXE_all = tb_nexys3_fusp_dummy
+#
+ISE_PATH = xc6slx16-csg324-2
+#
+XFLOWOPT_SYN = syn_s6_speed.opt
+XFLOWOPT_IMP = imp_s6_speed.opt
+#
+.PHONY : all all_ssim all_tsim clean
+#
+all : $(EXE_all)
+all_ssim : $(EXE_all:=_ssim)
+all_tsim : $(EXE_all:=_tsim)
+#
+clean : ise_clean ghdl_clean isim_clean
+#
+#-----
+#
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+include $(RETROBASE)/rtl/make/generic_isim.mk
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+#
+VBOM_all = $(wildcard *.vbom)
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+include $(VBOM_all:.vbom=.dep_isim)
+include $(wildcard *.o.dep_ghdl)
+#
Index: rtl/bplib/nexys3/tb/.cvsignore
===================================================================
--- rtl/bplib/nexys3/tb/.cvsignore (nonexistent)
+++ rtl/bplib/nexys3/tb/.cvsignore (revision 15)
@@ -0,0 +1,7 @@
+tb_nexys3_dummy
+tb_nexys3_fusp_dummy
+tb_n3_cram_memctl_as
+tb_n3_cram_memctl_as_[sft]sim
+tb_n3_cram_memctl_as_ISim
+tb_n3_cram_memctl_as_ISim_[sft]sim
+tb_n3_cram_memctl_stim
Index: rtl/bplib/nexys3/tb
===================================================================
--- rtl/bplib/nexys3/tb (nonexistent)
+++ rtl/bplib/nexys3/tb (revision 15)
rtl/bplib/nexys3/tb
Property changes :
Added: svn:ignore
## -0,0 +1,39 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_nexys3_dummy
+tb_nexys3_fusp_dummy
+tb_n3_cram_memctl_as
+tb_n3_cram_memctl_as_[sft]sim
+tb_n3_cram_memctl_as_ISim
+tb_n3_cram_memctl_as_ISim_[sft]sim
+tb_n3_cram_memctl_stim
Index: rtl/bplib/nexys3/nexys3_pins_pmb0_rs232.ucf
===================================================================
--- rtl/bplib/nexys3/nexys3_pins_pmb0_rs232.ucf (nonexistent)
+++ rtl/bplib/nexys3/nexys3_pins_pmb0_rs232.ucf (revision 15)
@@ -0,0 +1,12 @@
+## $Id: nexys3_pins_pmb0_rs232.ucf 430 2011-11-20 20:48:39Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2011-11-20 430 1.0 Initial version
+##
+## Pmod connector B top / usage RS232 for FTDI USB serport -------------------
+##
+NET "O_FUSP_RTS_N" LOC = "k2" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
+NET "I_FUSP_CTS_N" LOC = "k1" | IOSTANDARD=LVCMOS33 | PULLDOWN;
+NET "I_FUSP_RXD" LOC = "l4" | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "O_FUSP_TXD" LOC = "l3" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
Index: rtl/bplib/nexys3/nexys3_pins.ucf
===================================================================
--- rtl/bplib/nexys3/nexys3_pins.ucf (nonexistent)
+++ rtl/bplib/nexys3/nexys3_pins.ucf (revision 15)
@@ -0,0 +1,135 @@
+## $Id: nexys3_pins.ucf 432 2011-11-25 20:16:28Z mueller $
+##
+## Pin locks for Nexys 3 core functionality
+## - USB UART
+## - human I/O (switches, buttons, leds, display)
+## - cram
+##
+## Revision History:
+## Date Rev Version Comment
+## 2011-11-23 432 1.0.2 add PPCM controls
+## 2011-10-10 413 1.0.1 new BTN sequence: clockwise(U-R-D-L) - middle
+## 2011-07-04 388 1.0 Initial version
+##
+## Note: default is DRIVE=12 | SLEW=SLOW
+##
+## Assume that VCCB0 is jumpered for 2.5 V (for VHDCI LVDS usage)
+##
+## clocks -- in bank 2 -------------------------------------------------------
+NET "I_CLK100" LOC = "v10" | IOSTANDARD=LVCMOS33;
+##
+## USB UART Interface -- in bank 1--------------------------------------------
+## I_RXD -> signal MCU_RX -> TXD pin of FT232R
+## O_TXD -> signal MCU_TX -> RXD pin of FT232R
+## I_CTS_N ?? signal RTS -> RTS pin of FT232R (only on J14)
+## O_RTS_N ?? signal CTS -> CTS pin of FT232R (only on J14)
+NET "I_RXD" LOC = "n17" | IOSTANDARD=LVCMOS33;
+NET "O_TXD" LOC = "n18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW;
+##
+## switches -- in bank 2 -----------------------------------------------------
+NET "I_SWI<0>" LOC = "t10" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<1>" LOC = "t9" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<2>" LOC = "v9" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<3>" LOC = "m8" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<4>" LOC = "n8" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<5>" LOC = "u8" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<6>" LOC = "v8" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<7>" LOC = "t5" | IOSTANDARD=LVCMOS33;
+##
+## buttons -- in bank 0-------------------------------------------------------
+## sequence: clockwise(U-R-D-L) - middle
+NET "I_BTN<0>" LOC = "a8" | IOSTANDARD=LVCMOS25; # BTNU
+NET "I_BTN<1>" LOC = "d9" | IOSTANDARD=LVCMOS25; # BTNR
+NET "I_BTN<2>" LOC = "c9" | IOSTANDARD=LVCMOS25; # BTND
+NET "I_BTN<3>" LOC = "c4" | IOSTANDARD=LVCMOS25; # BTNL
+NET "I_BTN<4>" LOC = "b8" | IOSTANDARD=LVCMOS25; # BTNS
+##
+## LEDs -- in bank 2 ---------------------------------------------------------
+NET "O_LED<0>" LOC = "u16" | IOSTANDARD=LVCMOS33;
+NET "O_LED<1>" LOC = "v16" | IOSTANDARD=LVCMOS33;
+NET "O_LED<2>" LOC = "u15" | IOSTANDARD=LVCMOS33;
+NET "O_LED<3>" LOC = "v15" | IOSTANDARD=LVCMOS33;
+NET "O_LED<4>" LOC = "m11" | IOSTANDARD=LVCMOS33;
+NET "O_LED<5>" LOC = "n11" | IOSTANDARD=LVCMOS33;
+NET "O_LED<6>" LOC = "r11" | IOSTANDARD=LVCMOS33;
+NET "O_LED<7>" LOC = "t11" | IOSTANDARD=LVCMOS33;
+NET "O_LED<*>" DRIVE=12 | SLEW=SLOW;
+##
+## 7 segment display -- in bank 1 --------------------------------------------
+NET "O_ANO_N<0>" LOC = "n16" | IOSTANDARD=LVCMOS33;
+NET "O_ANO_N<1>" LOC = "n15" | IOSTANDARD=LVCMOS33;
+NET "O_ANO_N<2>" LOC = "p18" | IOSTANDARD=LVCMOS33;
+NET "O_ANO_N<3>" LOC = "p17" | IOSTANDARD=LVCMOS33;
+NET "O_ANO_N<*>" DRIVE=12 | SLEW=SLOW;
+##
+NET "O_SEG_N<0>" LOC = "t17" | IOSTANDARD=LVCMOS33; # CA
+NET "O_SEG_N<1>" LOC = "t18" | IOSTANDARD=LVCMOS33; # CB
+NET "O_SEG_N<2>" LOC = "u17" | IOSTANDARD=LVCMOS33; # CC
+NET "O_SEG_N<3>" LOC = "u18" | IOSTANDARD=LVCMOS33; # CD
+NET "O_SEG_N<4>" LOC = "m14" | IOSTANDARD=LVCMOS33; # CE
+NET "O_SEG_N<5>" LOC = "n14" | IOSTANDARD=LVCMOS33; # CF
+NET "O_SEG_N<6>" LOC = "l14" | IOSTANDARD=LVCMOS33; # CG
+NET "O_SEG_N<7>" LOC = "m13" | IOSTANDARD=LVCMOS33; # DP
+NET "O_SEG_N<*>" DRIVE=12 | SLEW=SLOW;
+##
+## CRAM -- in bank 2 (data) and 1 (addr) -------------------------------------
+NET "O_MEM_CE_N" LOC = "l15" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_MEM_WE_N" LOC = "m16" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_MEM_OE_N" LOC = "l18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+##
+NET "O_MEM_BE_N<0>" LOC = "k16" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_BE_N<1>" LOC = "k15" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_BE_N<*>" DRIVE=12 | SLEW=FAST;
+##
+NET "O_MEM_ADV_N" LOC = "h18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_MEM_CLK" LOC = "r10" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_MEM_CRE" LOC = "m18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "I_MEM_WAIT" LOC = "v4" | IOSTANDARD=LVCMOS33 | PULLDOWN;
+##
+NET "O_MEM_ADDR<0>" LOC = "k18" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<1>" LOC = "k17" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<2>" LOC = "j18" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<3>" LOC = "j16" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<4>" LOC = "g18" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<5>" LOC = "g16" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<6>" LOC = "h16" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<7>" LOC = "h15" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<8>" LOC = "h14" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<9>" LOC = "h13" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<10>" LOC = "f18" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<11>" LOC = "f17" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<12>" LOC = "k13" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<13>" LOC = "k12" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<14>" LOC = "e18" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<15>" LOC = "e16" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<16>" LOC = "g13" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<17>" LOC = "h12" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<18>" LOC = "d18" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<19>" LOC = "d17" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<20>" LOC = "g14" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<21>" LOC = "f14" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<22>" LOC = "c18" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<*>" DRIVE=6 | SLEW=FAST;
+##
+NET "IO_MEM_DATA<0>" LOC = "r13" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<1>" LOC = "t14" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<2>" LOC = "v14" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<3>" LOC = "u5" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<4>" LOC = "v5" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<5>" LOC = "r3" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<6>" LOC = "t3" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<7>" LOC = "r5" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<8>" LOC = "n5" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<9>" LOC = "p6" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<10>" LOC = "p12" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<11>" LOC = "u13" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<12>" LOC = "v13" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<13>" LOC = "u10" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<14>" LOC = "r8" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<15>" LOC = "t8" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER;
+##
+## PPCM -- parallel PCM memory -----------------------------------------------
+NET "O_PPCM_CE_N" LOC = "l17" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW;
+NET "O_PPCM_RST_N" LOC = "t4" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW;
+##
Index: rtl/bplib/nexys3
===================================================================
--- rtl/bplib/nexys3 (nonexistent)
+++ rtl/bplib/nexys3 (revision 15)
rtl/bplib/nexys3
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: rtl/vlib/xlib/xlib.vhd
===================================================================
--- rtl/vlib/xlib/xlib.vhd (revision 14)
+++ rtl/vlib/xlib/xlib.vhd (revision 15)
@@ -1,4 +1,4 @@
--- $Id: xlib.vhd 426 2011-11-18 18:14:08Z mueller $
+-- $Id: xlib.vhd 432 2011-11-25 20:16:28Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller
--
@@ -19,6 +19,7 @@
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
+-- 2011-11-24 432 1.0.8 add iob_oddr2_simple
-- 2011-11-17 426 1.0.7 rename dcm_sp_sfs -> dcm_sfs; remove family generic
-- 2011-11-10 423 1.0.6 add family generic for dcm_sp_sfs
-- 2010-11-07 337 1.0.5 add dcm_sp_sfs
@@ -128,6 +129,19 @@
);
end component;
+component iob_oddr2_simple is -- DDR2 output I/O pad
+ generic (
+ ALIGN : string := "NONE"; -- ddr_alignment
+ INIT : slbit := '0'); -- initial state
+ port (
+ CLK : in slbit; -- clock
+ CE : in slbit := '1'; -- clock enable
+ DO0 : in slbit; -- output data
+ DO1 : in slbit; -- output data
+ PAD : out slbit -- i/o pad
+ );
+end component;
+
component iob_io_gen is -- un-registered IOB, in/output, vector
generic (
DWIDTH : positive := 16; -- data port width
/doc/INSTALL.txt
1,4 → 1,4
# $Id: INSTALL.txt 409 2011-09-17 10:40:55Z mueller $ |
# $Id: INSTALL.txt 433 2011-11-27 22:04:39Z mueller $ |
|
Guide to install and build w11a systems, test benches and support software |
|
219,6 → 219,7
Note: Currently ready to build versions exist for |
Digilent S3BOARD (-1000 FPGA version) |
Digilent Nexys2 board (-1200 FPGA version) |
Digilent Nexys3 board |
|
1. rlink tester |
a. for Digilent Nexys2 board |
226,6 → 227,11
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2 |
make sys_tst_rlink_n2.bit |
|
b. for Digilent Nexys3 board |
|
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3 |
make sys_tst_rlink_n3.bit |
|
2. w11a systems |
a. for Digilent S3BOARD |
|
236,3 → 242,8
|
cd $RETROBASE/rtl/sys_gen/w11a/nexys2 |
make sys_w11a_n2.bit |
|
c. for Digilent Nexys3 board |
|
cd $RETROBASE/rtl/sys_gen/w11a/nexys3 |
make sys_w11a_n3.bit |
/doc/w11a_os_guide.txt
35,12 → 35,18
|
2. FPGA Board setup ------------------------------------------------------- |
|
- connect the USB-RS232 cable to the RS232 port of the s3board or nexys2 |
- set the latency timer of the USB-RS232, e.g. with |
sudo $RETROBASE/tools/bin/set_ftdi_lat USB0 1 |
- ensure that all 8 switches are in '0' position |
- load the w11a design into the FPGA, e.g. via impact |
- for s3board and nexys2 |
- connect the USB-RS232 cable to the RS232 port of the s3board or nexys2 |
- set the latency timer of the USB-RS232, e.g. with |
sudo $RETROBASE/tools/bin/set_ftdi_lat USB0 1 |
- ensure that all 8 switches are in '0' position |
- load the w11a design into the FPGA, e.g. via impact |
|
- for nexys3 |
- connect USB cable to the 'usb uart' port (next to the 5 buttons) |
- ensure that all 8 switches are in '0' position |
- load the w11a design into the FPGA, e.g. via impact |
|
3. Unix V5 system --------------------------------------------------------- |
|
- A disk set is available from |
53,7 → 59,8
cd $RETROBASE/rtl/sys_gen/w11a/tb |
sudo $RETROBASE/tools/bin/set_ftdi_lat USB0 1 |
telnet_starter -d DL0 & |
dorri -u0,460 @uv5_boot.pcmd |
[for s3,n2:] dorri -u0,460 @uv5_boot.pcmd |
[for n3:] dorri -u0,500,1,0 @uv5_boot.pcmd |
|
- the boot dialog in the console xterm window will look like |
(required input is in {..}, with {<CR>} denoting a carriage return: |
92,7 → 99,8
sudo $RETROBASE/tools/bin/set_ftdi_lat USB0 1 |
telnet_starter -d DL0 & |
telnet_starter -d DL1 & |
dorri -u0,460 @211bsd_rk_boot.pcmd |
[for s3,n2:] dorri -u0,460 @211bsd_rk_boot.pcmd |
[for n3:] dorri -u0,500,1,0 @211bsd_rk_boot.pcmd |
|
- the boot dialog in the console xterm window will look like |
(required input is in {..}, with {<CR>} denoting a carriage return: |
/doc/w11a_tb_guide.txt
1,4 → 1,4
# $Id: w11a_tb_guide.txt 428 2011-11-20 12:19:31Z mueller $ |
# $Id: w11a_tb_guide.txt 433 2011-11-27 22:04:39Z mueller $ |
|
Guide to running w11a test benches |
|
159,6 → 159,16
-> 1769140.0 ns 88446: DONE |
-> real 0m15.289s |
|
- sys_tst_rlink_n3 test bench |
|
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb |
make tb_tst_rlink_n3 |
time ti_rri --run="tbw tb_tst_rlink_n3" --fifo --logl=3 -- \ |
"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\ |
tee tb_tst_rlink_n3_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)" |
-> 893590.0 ns 89338: DONE |
-> real 0m9.510s |
|
4b. w11a systems ----------------------------------------------------- |
|
The stimulus file used in the w11a core test can be executed in the |
189,3 → 199,14
tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)" |
-> 6673237.2 ns 387035: DONE |
-> real 0m56.173s user 0m56.612s sys 0m00.604s |
|
- sys_w11a_n3 test bench |
|
cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb |
make tb_w11a_n3 |
time pi_rri --fifo --timeout=40. --cmax=3 \ |
--run="tbw tb_w11a_n3" -- \ |
@../../../../w11a/tb/tb_pdp11core_stim.dat |\ |
tee tb_w11a_n3_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)" |
-> 4593598.2 ns 390438: DONE |
-> real 0m55.326s user 0m55.711s sys 0m00.752s |
/doc/README.txt
1,4 → 1,4
# $Id: README.txt 428 2011-11-20 12:19:31Z mueller $ |
# $Id: README.txt 434 2011-12-02 19:17:38Z mueller $ |
|
Release notes for w11a |
|
28,13 → 28,16
rtl/bplib/issi - for ISSI parts |
rtl/bplib/micron - for Micron parts |
rtl/bplib/nexys2 - for Digilent Nexsy2 board |
rtl/bplib/nexys3 - for Digilent Nexsy3 board |
rtl/bplib/s3board - for Digilent S3BOARD |
rtl/ibus - ibus devices (UNIBUS peripherals) |
rtl/sys_gen - top level designs |
rtl/sys_gen/tst_rlink - top level designs for an rlink tester |
rtl/sys_gen/tst_rlink/nexys2 - rlink tester system for Digilent Nexsy2 |
rtl/sys_gen/tst_rlink/nexys3 - rlink tester system for Digilent Nexsy3 |
rtl/sys_gen/w11a - top level designs for w11a SoC |
rtl/sys_gen/w11a/nexys2 - w11a SoC for Digilent Nexsy2 |
rtl/sys_gen/w11a/nexys3 - w11a SoC for Digilent Nexsy3 |
rtl/sys_gen/w11a/s3board - w11a SoC for Digilent S3BOARD |
rtl/vlib - VHDL component libs |
rtl/vlib/comlib - communication |
60,9 → 63,27
|
3. Change Log ---------------------------------------------------------------- |
|
- trunk (2011-11-20: svn rev 13(oc) 428(wfjm); untagged w11a_V0.532) +++++++++ |
- trunk (2011-12-04: svn rev 15(oc) 436(wfjm); untagged w11a_V0.54) +++++++++ |
|
- Summary |
- added support for nexys3 board for w11a |
|
- New features |
- new systems |
- sys_gen/w11a/sys_w11a_n3 |
- sys_gen/w11a/sys_tst_rlink_n3 |
|
- Changes |
- module renames: |
bplib/nexys2/n2_cram_dummy -> bplib/nxcramlib/nx_cram_dummy |
bplib/nexys2/n2_cram_memctl_as -> bplib/nxcramlib/nx_cram_memctl_as |
|
- Bug fixes |
- tools/src/lib*: backend libraries compile now on 64 bit systems |
|
- trunk (2011-11-20: svn rev 14(oc) 428(wfjm); untagged w11a_V0.532) +++++++++ |
|
- Summary |
- generalized the 'human I/O' interface for s3board,nexys2/3 and atlys |
- added test design for the 'human I/O' interface |
- no functional change of w11a CPU core or any existing test systems |