OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /w11
    from Rev 11 to Rev 12
    Reverse comparison

Rev 11 → Rev 12

/trunk/tools/tcl/rlink/util.tcl
1,4 → 1,4
# $Id: util.tcl 375 2011-04-02 07:56:47Z mueller $
# $Id: util.tcl 403 2011-08-06 17:36:22Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
13,6 → 13,7
#
# Revision History:
# Date Rev Version Comment
# 2011-08-06 403 1.0.1 add SINT and SINIT defs for serport init
# 2011-03-26 373 1.0 Initial version
# 2011-03-19 372 0.1 First draft
#
22,8 → 23,9
package require rutil 1.0
 
namespace eval rlink {
regdsc STAT {stat 7 3} {attn 4} {cerr 3} {derr 2} {rbnak 1} {rberr 0}
regdsc INIT {anena 15} {itoena 14} {itoval 7 8}
regdsc STAT {stat 7 3} {attn 4} {cerr 3} {derr 2} {rbnak 1} {rberr 0}
regdsc INIT {anena 15} {itoena 14} {itoval 7 8}
regdsc SINIT {fena 12} {fwidth 11 3} {fdelay 8 3} {rtsoff 5 3} {rtson 2 3}
#
# 'pseudo register', describes 3rd word in return list element for -rlist
regdsc FLAGS {vol 16} \
33,13 → 35,15
{done 2} {send 1} {init 0}
 
variable IINT 0x00ff
variable SINT 0x00fe
 
#
# init: reset rlink (disable enables; clear attn register
# init: reset rlink: disable enables; clear attn register
#
proc init {} {
rlc exec \
-init $rlink::IINT 0x0000 \
-init $rlink::SINT [regbld rlink::SINIT {rtsoff 7} {rtson 6} ] \
-attn
return ""
}
/trunk/tools/tcl/.tclshrc
1,8 → 1,10
# -*- tcl -*-
# $Id: .tclshrc 376 2011-04-17 12:24:07Z mueller $
# $Id: .tclshrc 379 2011-04-22 20:56:19Z mueller $
#
lappend auto_path [file join $env(RETROBASE) tools tcl]
lappend auto_path [file join $env(RETROBASE) tools lib]
if {[info exists env(RETROBASE)]} {
lappend auto_path [file join $env(RETROBASE) tools tcl]
lappend auto_path [file join $env(RETROBASE) tools lib]
}
#
if {$tcl_interactive} {
package require tclreadline
/trunk/tools/tcl/rbs3hio/util.tcl
1,4 → 1,4
# $Id: util.tcl 376 2011-04-17 12:24:07Z mueller $
# $Id: util.tcl 406 2011-08-14 21:06:44Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
13,6 → 13,7
#
# Revision History:
# Date Rev Version Comment
# 2011-08-14 406 1.0.2 adopt to common register layout
# 2011-04-17 376 1.0.1 print: show also switch values; add proc disptest
# 2011-03-27 374 1.0 Initial version
# 2011-03-19 372 0.1 First draft
27,8 → 28,8
#
# setup register descriptions for s3_humanio_rbus
#
regdsc CNTL {daten 11} {dpen 10} {leden 9} {swien 8} {btn 3 4}
regdsc LED {dp 11 4} {led 7 8}
regdsc CNTL {btn 12 4} {dspen 3} {dpen 2} {leden 1} {swien 0}
regdsc LED {dp 15 4} {led 7 8}
 
#
# setup: amap definitions for s3_humanio_rbus
79,7 → 80,7
proc disptest {} {
rlc exec -rreg hi.cntl r_cntl
set swien [regget rbs3hio::CNTL(swien) $r_cntl]
rlc exec -wreg hi.cntl [regbld rbs3hio::CNTL daten dpen leden \
rlc exec -wreg hi.cntl [regbld rbs3hio::CNTL dspen dpen leden \
[list swien $swien] ]
 
foreach ledval {0x0f 0xf0 0xff} {
/trunk/tools/tcl/.wishrc
1,8 → 1,10
# -*- tcl -*-
# $Id: .wishrc 376 2011-04-17 12:24:07Z mueller $
# $Id: .wishrc 379 2011-04-22 20:56:19Z mueller $
#
lappend auto_path [file join $env(RETROBASE) tools tcl]
lappend auto_path [file join $env(RETROBASE) tools lib]
if {[info exists env(RETROBASE)]} {
lappend auto_path [file join $env(RETROBASE) tools tcl]
lappend auto_path [file join $env(RETROBASE) tools lib]
}
#
if {$tcl_interactive} {
package require tclreadline
/trunk/tools/tcl/setup_packages
1,4 → 1,5
#! /usr/bin/env tclsh
# $Id: setup_packages 403 2011-08-06 17:36:22Z mueller $
#
pkg_mkIndex -verbose ../lib libr*tpp.so
#
/trunk/tools/src/librlink/RlinkConnect.hpp
1,4 → 1,4
// $Id: RlinkConnect.hpp 375 2011-04-02 07:56:47Z mueller $
// $Id: RlinkConnect.hpp 380 2011-04-25 18:14:52Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,6 → 13,9
//
// Revision History:
// Date Rev Version Comment
// 2011-04-24 380 1.1 use boost::noncopyable (instead of private dcl's);
// use boost::(mutex&lock), implement Lockable IF
// 2011-04-22 379 1.0.1 add Lock(), Unlock()
// 2011-04-02 375 1.0 Initial version
// 2011-01-15 356 0.1 First draft
// ---------------------------------------------------------------------------
20,7 → 23,7
 
/*!
\file
\version $Id: RlinkConnect.hpp 375 2011-04-02 07:56:47Z mueller $
\version $Id: RlinkConnect.hpp 380 2011-04-25 18:14:52Z mueller $
\brief Declaration of class \c RlinkConnect.
*/
 
32,6 → 35,9
#include <vector>
#include <ostream>
 
#include "boost/utility.hpp"
#include "boost/thread/recursive_mutex.hpp"
 
#include "librtools/RerrMsg.hpp"
#include "librtools/Rstats.hpp"
#include "librtools/RlogFile.hpp"
43,7 → 49,7
 
namespace Retro {
 
class RlinkConnect {
class RlinkConnect : private boost::noncopyable {
public:
struct LogOpts {
size_t baseaddr;
67,9 → 73,12
bool IsOpen() const;
RlinkPort* Port() const;
 
// provide boost Lockable interface
void lock();
bool try_lock();
void unlock();
 
bool Exec(RlinkCommandList& clist, RerrMsg& emsg);
bool ExecPart(RlinkCommandList& clist, size_t ibeg, size_t iend,
RerrMsg& emsg);
 
double WaitAttn(double timeout, RerrMsg& emsg);
bool SndOob(uint16_t addr, uint16_t data, RerrMsg& emsg);
91,7 → 100,6
void Print(std::ostream& os) const;
void Dump(std::ostream& os, int ind=0, const char* text=0) const;
 
 
// statistics counter indices
enum stats {
kStatNExec = 0,
123,6 → 131,10
};
 
protected:
bool ExecPart(RlinkCommandList& clist, size_t ibeg, size_t iend,
RerrMsg& emsg);
 
protected:
RlinkPort* fpPort; //!< ptr to port
uint8_t fSeqNumber[8]; //!< command sequence number
RlinkPacketBuf fTxPkt; //!< transmit packet buffer
131,11 → 143,7
Rstats fStats; //!< statistics
LogOpts fLogOpts; //!< log options
RlogFile fLogFile; //!< connection log file
 
// RlinkConnect is not copyable and assignable
private:
RlinkConnect(const RlinkConnect& rhs);
RlinkConnect& operator=(const RlinkConnect& rhs);
boost::recursive_mutex fMutexConn; //!< mutex to lock whole connect
};
} // end namespace Retro
/trunk/tools/src/librlink/RlinkPort.hpp
1,4 → 1,4
// $Id: RlinkPort.hpp 375 2011-04-02 07:56:47Z mueller $
// $Id: RlinkPort.hpp 380 2011-04-25 18:14:52Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,6 → 13,7
//
// Revision History:
// Date Rev Version Comment
// 2011-04-24 380 1.0.1 use boost::noncopyable (instead of private dcl's)
// 2011-03-27 375 1.0 Initial version
// 2011-01-15 356 0.1 First draft
// ---------------------------------------------------------------------------
20,7 → 21,7
 
/*!
\file
\version $Id: RlinkPort.hpp 375 2011-04-02 07:56:47Z mueller $
\version $Id: RlinkPort.hpp 380 2011-04-25 18:14:52Z mueller $
\brief Declaration of class RlinkPort.
*/
 
30,6 → 31,8
#include <string>
#include <map>
 
#include "boost/utility.hpp"
 
#include "librtools/RerrMsg.hpp"
#include "librtools/RlogFile.hpp"
#include "librtools/Rstats.hpp"
36,7 → 39,7
 
namespace Retro {
 
class RlinkPort {
class RlinkPort : private boost::noncopyable {
public:
typedef std::map<std::string, std::string> omap_t;
typedef omap_t::iterator omap_it_t;
106,12 → 109,6
RlogFile* fpLogFile; //!< ptr to log file dsc
size_t fTraceLevel; //!< trace level
Rstats fStats; //!< statistics
 
// RlinkPort is not copyable and assignable
private:
RlinkPort(const RlinkPort& rhs);
RlinkPort& operator=(const RlinkPort& rhs);
 
};
} // end namespace Retro
/trunk/tools/src/librlink/Makefile
1,7 → 1,9
# $Id: $
# $Id: Makefile 403 2011-08-06 17:36:22Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-07-31 401 1.1 rename realclean->distclean
# 2011-07-01 386 1.0.1 add BOOSTINC
# 2011-01-09 354 1.0 Initial version (adopted from CTB...)
#---
#
13,8 → 15,8
#
# Compile and Link search paths
#
INCLFLAGS = -I${RETROBASE}/tools/src
LDLIBS = -L${RETROBASE}/tools/lib -lrtools
INCLFLAGS = -I${RETROBASE}/tools/src -I${BOOSTINC}
LDLIBS = -lboost_thread -L${RETROBASE}/tools/lib -lrtools
#
# Object files to be included
#
42,7 → 44,7
#
# cleanup phonies:
#
.PHONY : clean cleandep realclean
.PHONY : clean cleandep distclean
clean :
@ rm -f $(OBJ_all)
@ echo "Object files removed"
51,7 → 53,7
@ rm -f $(DEP_all)
@ echo "Dependency files removed"
#
realclean : clean cleandep
distclean : clean cleandep
@ rm -f $(SOPATH)/lib$(SONAME).a $(SOPATH)/lib$(SONAME).so*
@ echo "Libraries removed"
#
/trunk/tools/src/librlink/RlinkCommandList.cpp
1,4 → 1,4
// $Id: RlinkCommandList.cpp 375 2011-04-02 07:56:47Z mueller $
// $Id: RlinkCommandList.cpp 380 2011-04-25 18:14:52Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,6 → 13,7
//
// Revision History:
// Date Rev Version Comment
// 2011-04-25 380 1.0.1 use boost/foreach
// 2011-03-05 366 1.0 Initial version
// 2011-01-15 355 0.1 First draft
// ---------------------------------------------------------------------------
19,7 → 20,7
 
/*!
\file
\version $Id: RlinkCommandList.cpp 375 2011-04-02 07:56:47Z mueller $
\version $Id: RlinkCommandList.cpp 380 2011-04-25 18:14:52Z mueller $
\brief Implemenation of class RlinkCommandList.
*/
 
26,6 → 27,9
#include <string>
#include <stdexcept>
 
#include "boost/foreach.hpp"
#define foreach BOOST_FOREACH
 
#include "RlinkCommandList.hpp"
 
#include "librtools/RosPrintf.hpp"
62,7 → 66,7
 
RlinkCommandList::~RlinkCommandList()
{
for (size_t i=0; i<fList.size(); i++) delete fList[i];
foreach (RlinkCommand* pcmd, fList) { delete pcmd; }
}
 
//------------------------------------------+-----------------------------------
224,8 → 228,8
void RlinkCommandList::Print(std::ostream& os, const RlinkAddrMap* pamap,
size_t abase, size_t dbase, size_t sbase) const
{
for (size_t i=0; i<fList.size(); i++) {
fList[i]->Print(os, pamap, abase, dbase, sbase);
foreach (RlinkCommand* pcmd, fList) {
pcmd->Print(os, pamap, abase, dbase, sbase);
}
return;
}
254,7 → 258,8
Retro::RlinkCommandList::operator=( const RlinkCommandList& rhs)
{
if (&rhs == this) return *this;
for (size_t i=0; i<fList.size(); i++) delete fList[i];
foreach (RlinkCommand* pcmd, fList) { delete pcmd; }
fList.clear();
for (size_t i=0; i<rhs.Size(); i++) AddCommand(rhs[i]);
return *this;
/trunk/tools/src/librlink/RlinkPortTerm.cpp
1,4 → 1,4
// $Id: RlinkPortTerm.cpp 375 2011-04-02 07:56:47Z mueller $
// $Id: RlinkPortTerm.cpp 388 2011-07-06 18:40:47Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,12 → 13,13
//
// Revision History:
// Date Rev Version Comment
// 2011-07-04 388 1.0.1 add termios readback and verification
// 2011-03-27 374 1.0 Initial version
// ---------------------------------------------------------------------------
 
/*!
\file
\version $Id: RlinkPortTerm.cpp 375 2011-04-02 07:56:47Z mueller $
\version $Id: RlinkPortTerm.cpp 388 2011-07-06 18:40:47Z mueller $
\brief Implemenation of RlinkPortTerm.
*/
 
155,6 → 156,39
return false;
}
 
// tcsetattr() returns success if any of the requested changes could be
// successfully carried out. Therefore the termios structure is read back
// and verified.
 
struct termios tios;
if (tcgetattr(fd, &tios) != 0) {
emsg.InitErrno("RlinkPortTerm::Open()",
string("2nd tcgetattr() for \"") + fPath +
string("\" failed: "),
errno);
close(fd);
return false;
}
 
const char* pmsg = 0;
if (tios.c_iflag != fTiosNew.c_iflag) pmsg = "c_iflag";
if (tios.c_oflag != fTiosNew.c_oflag) pmsg = "c_oflag";
if (tios.c_cflag != fTiosNew.c_cflag) pmsg = "c_cflag";
if (tios.c_lflag != fTiosNew.c_lflag) pmsg = "c_lflag";
if (cfgetispeed(&tios) != speed) pmsg = "ispeed";
if (cfgetospeed(&tios) != speed) pmsg = "ospeed";
for (int i=0; i<NCCS; i++) {
if (tios.c_cc[i] != fTiosNew.c_cc[i]) pmsg = "c_cc char";
}
 
if (pmsg) {
emsg.Init("RlinkPortTerm::Open()",
string("tcsetattr() failed to set") +
string(pmsg));
close(fd);
return false;
}
 
fFdWrite = fd;
fFdRead = fd;
fIsOpen = true;
/trunk/tools/src/librlink/RlinkConnect.cpp
1,4 → 1,4
// $Id: RlinkConnect.cpp 375 2011-04-02 07:56:47Z mueller $
// $Id: RlinkConnect.cpp 386 2011-07-01 17:31:03Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,6 → 13,8
//
// Revision History:
// Date Rev Version Comment
// 2011-04-25 380 1.1 use boost::(mutex&lock), implement Lockable IF
// 2011-04-22 379 1.0.1 add Lock(), Unlock(), lock connect in Exec()
// 2011-04-02 375 1.0 Initial version
// 2011-01-15 356 0.1 First draft
// ---------------------------------------------------------------------------
19,14 → 21,15
 
/*!
\file
\version $Id: RlinkConnect.cpp 375 2011-04-02 07:56:47Z mueller $
\version $Id: RlinkConnect.cpp 386 2011-07-01 17:31:03Z mueller $
\brief Implemenation of RlinkConnect.
*/
 
#include <iostream>
 
#include <stdexcept>
 
#include "boost/thread/locks.hpp"
 
#include "RlinkConnect.hpp"
#include "RlinkPortFactory.hpp"
 
33,6 → 36,7
#include "librtools/RosFill.hpp"
#include "librtools/RosPrintf.hpp"
#include "librtools/RosPrintBvi.hpp"
#include "librtools/Rtools.hpp"
 
using namespace std;
using namespace Retro;
52,10 → 56,12
fAddrMap(),
fStats(),
fLogOpts(),
fLogFile(&cout)
fLogFile(&cout),
fMutexConn()
{
for (size_t i=0; i<8; i++) fSeqNumber[i] = 0;
// Statistic setup
fStats.Define(kStatNExec, "NExec", "Exec() calls");
fStats.Define(kStatNSplitVol, "NSplitVol", "clist splits: Volatile");
fStats.Define(kStatNExecPart, "NExecPart", "ExecPart() calls");
88,7 → 94,7
 
RlinkConnect::~RlinkConnect()
{
delete fpPort;
if (fpPort) Close();
}
 
//------------------------------------------+-----------------------------------
128,13 → 134,41
//------------------------------------------+-----------------------------------
//! FIXME_docs
 
void RlinkConnect::lock()
{
fMutexConn.lock();
return;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_docs
 
bool RlinkConnect::try_lock()
{
return fMutexConn.try_lock();
}
 
//------------------------------------------+-----------------------------------
//! FIXME_docs
 
void RlinkConnect::unlock()
{
fMutexConn.unlock();
return;
}
 
//------------------------------------------+-----------------------------------
//! FIXME_docs
 
bool RlinkConnect::Exec(RlinkCommandList& clist, RerrMsg& emsg)
{
{
if (clist.Size() == 0)
throw invalid_argument("RlinkConnect::Exec(): clist empty");
if (! IsOpen())
throw logic_error("RlinkConnect::Exec(): port not open");
 
boost::lock_guard<RlinkConnect> lock(*this);
 
fStats.Inc(kStatNExec);
 
size_t ibeg = 0;
/trunk/tools/src/librtools/RlogFile.hpp
1,4 → 1,4
// $Id: RlogFile.hpp 357 2011-01-31 08:00:13Z mueller $
// $Id: RlogFile.hpp 380 2011-04-25 18:14:52Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,12 → 13,13
//
// Revision History:
// Date Rev Version Comment
// 2011-04-24 380 1.0.1 use boost::noncopyable (instead of private dcl's)
// 2011-01-30 357 1.0 Initial version
// ---------------------------------------------------------------------------
 
/*!
\file
\version $Id: RlogFile.hpp 357 2011-01-31 08:00:13Z mueller $
\version $Id: RlogFile.hpp 380 2011-04-25 18:14:52Z mueller $
\brief Declaration of class RlogFile.
*/
 
29,9 → 30,11
#include <ostream>
#include <fstream>
 
#include "boost/utility.hpp"
 
namespace Retro {
 
class RlogFile {
class RlogFile : private boost::noncopyable {
public:
RlogFile();
explicit RlogFile(std::ostream* os);
53,13 → 56,6
int fTagYear; //!< year of last time tag
int fTagMonth; //!< month of last time tag
int fTagDay; //!< day of last time tag
 
// RlogFile is not copy or assignable
private:
RlogFile(const RlogFile& rhs);
RlogFile& operator=(const RlogFile& rhs);
 
 
};
} // end namespace Retro
/trunk/tools/src/librtools/RosPrintfBase.cpp
1,4 → 1,4
// $Id: $
// $Id: RosPrintfBase.cpp 403 2011-08-06 17:36:22Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
18,7 → 18,7
 
/*!
\file
\version $Id: $
\version $Id: RosPrintfBase.cpp 403 2011-08-06 17:36:22Z mueller $
\brief Implemenation of RosPrintfBase .
*/
 
/trunk/tools/src/librtools/Rtools.cpp
1,4 → 1,4
// $Id: $
// $Id: Rtools.cpp 403 2011-08-06 17:36:22Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
19,7 → 19,7
 
/*!
\file
\version $Id: $
\version $Id: Rtools.cpp 403 2011-08-06 17:36:22Z mueller $
\brief Implemenation of Rtools .
*/
 
/trunk/tools/src/librtools/Rtools.hpp
1,4 → 1,4
// $Id: $
// $Id: Rtools.hpp 403 2011-08-06 17:36:22Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
19,7 → 19,7
 
/*!
\file
\version $Id: $
\version $Id: Rtools.hpp 403 2011-08-06 17:36:22Z mueller $
\brief Declaration of class Rtools .
*/
 
/trunk/tools/src/librtools/Makefile
1,7 → 1,8
# $Id: Makefile 374 2011-03-27 17:02:47Z mueller $
# $Id: Makefile 401 2011-07-31 21:02:33Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-07-31 401 1.1 rename realclean->distclean
# 2011-03-27 374 1.0.1 removed Rnamed (obsolete now)
# 2011-01-15 357 1.0 Initial version (adopted from CTB...)
#---
42,7 → 43,7
#
# cleanup phonies:
#
.PHONY : clean cleandep realclean
.PHONY : clean cleandep distclean
clean :
@ rm -f $(OBJ_all)
@ echo "Object files removed"
51,7 → 52,7
@ rm -f $(DEP_all)
@ echo "Dependency files removed"
#
realclean : clean cleandep
distclean : clean cleandep
@ rm -f $(SOPATH)/lib$(SONAME).a $(SOPATH)/lib$(SONAME).so*
@ echo "Libraries removed"
#
/trunk/tools/src/librlinktpp/RtclRlinkConnect.cpp
1,4 → 1,4
// $Id: RtclRlinkConnect.cpp 376 2011-04-17 12:24:07Z mueller $
// $Id: RtclRlinkConnect.cpp 380 2011-04-25 18:14:52Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,6 → 13,7
//
// Revision History:
// Date Rev Version Comment
// 2011-04-23 380 1.1 use boost/bind instead of RmethDsc
// 2011-04-17 376 1.0.1 M_wtlam: now correct log levels
// 2011-03-27 374 1.0 Initial version
// 2011-02-11 360 0.1 First draft
20,7 → 21,7
 
/*!
\file
\version $Id: RtclRlinkConnect.cpp 376 2011-04-17 12:24:07Z mueller $
\version $Id: RtclRlinkConnect.cpp 380 2011-04-25 18:14:52Z mueller $
\brief Implemenation of class RtclRlinkConnect.
*/
 
29,11 → 30,12
#include <stdexcept>
#include <iostream>
 
#include "boost/bind.hpp"
 
#include "librtcltools/Rtcl.hpp"
#include "librtcltools/RtclOPtr.hpp"
#include "librtcltools/RtclNameSet.hpp"
#include "librtcltools/RtclStats.hpp"
#include "librtools/RmethDsc.hpp"
#include "librtools/RosPrintf.hpp"
#include "librlink/RlinkCommandList.hpp"
#include "RtclRlinkConnect.hpp"
55,20 → 57,19
fErrCnt(0),
fLogFileName("-")
{
typedef RmethDsc<RtclRlinkConnect, RtclArgs> mdsc_t;
AddMeth("open", new mdsc_t(this, &RtclRlinkConnect::M_open));
AddMeth("close", new mdsc_t(this, &RtclRlinkConnect::M_close));
AddMeth("exec", new mdsc_t(this, &RtclRlinkConnect::M_exec));
AddMeth("amap", new mdsc_t(this, &RtclRlinkConnect::M_amap));
AddMeth("errcnt", new mdsc_t(this, &RtclRlinkConnect::M_errcnt));
AddMeth("wtlam", new mdsc_t(this, &RtclRlinkConnect::M_wtlam));
AddMeth("oob", new mdsc_t(this, &RtclRlinkConnect::M_oob));
AddMeth("stats", new mdsc_t(this, &RtclRlinkConnect::M_stats));
AddMeth("log", new mdsc_t(this, &RtclRlinkConnect::M_log));
AddMeth("print", new mdsc_t(this, &RtclRlinkConnect::M_print));
AddMeth("dump", new mdsc_t(this, &RtclRlinkConnect::M_dump));
AddMeth("config", new mdsc_t(this, &RtclRlinkConnect::M_config));
AddMeth("$default", new mdsc_t(this, &RtclRlinkConnect::M_default));
AddMeth("open", boost::bind(&RtclRlinkConnect::M_open, this, _1));
AddMeth("close", boost::bind(&RtclRlinkConnect::M_close, this, _1));
AddMeth("exec", boost::bind(&RtclRlinkConnect::M_exec, this, _1));
AddMeth("amap", boost::bind(&RtclRlinkConnect::M_amap, this, _1));
AddMeth("errcnt", boost::bind(&RtclRlinkConnect::M_errcnt, this, _1));
AddMeth("wtlam", boost::bind(&RtclRlinkConnect::M_wtlam, this, _1));
AddMeth("oob", boost::bind(&RtclRlinkConnect::M_oob, this, _1));
AddMeth("stats", boost::bind(&RtclRlinkConnect::M_stats, this, _1));
AddMeth("log", boost::bind(&RtclRlinkConnect::M_log, this, _1));
AddMeth("print", boost::bind(&RtclRlinkConnect::M_print, this, _1));
AddMeth("dump", boost::bind(&RtclRlinkConnect::M_dump, this, _1));
AddMeth("config", boost::bind(&RtclRlinkConnect::M_config, this, _1));
AddMeth("$default", boost::bind(&RtclRlinkConnect::M_default, this, _1));
 
for (size_t i=0; i<8; i++) {
fCmdnameObj[i] = Tcl_NewStringObj(RlinkCommand::CommandName(i), -1);
/trunk/tools/src/librlinktpp/Makefile
1,7 → 1,9
# $Id: Makefile 372 2011-03-20 22:48:11Z mueller $
# $Id: Makefile 401 2011-07-31 21:02:33Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-07-31 401 1.1 rename realclean->distclean
# 2011-07-01 386 1.0.2 add BOOSTINC
# 2011-03-20 372 1.0.1 renamed ..tcl -> ..tpp
# 2011-02-12 360 1.0 Initial version
#---
14,7 → 16,7
#
# Compile and Link search paths
#
INCLFLAGS = -I/usr/include/tcl8.4 -I${RETROBASE}/tools/src
INCLFLAGS = -I/usr/include/tcl8.4 -I${RETROBASE}/tools/src -I${BOOSTINC}
LDLIBS = -L${RETROBASE}/tools/lib -lrtools -lrtcltools -lrlink
#
# Object files to be included
39,7 → 41,7
#
# cleanup phonies:
#
.PHONY : clean cleandep realclean
.PHONY : clean cleandep distclean
clean :
@ rm -f $(OBJ_all)
@ echo "Object files removed"
48,7 → 50,7
@ rm -f $(DEP_all)
@ echo "Dependency files removed"
#
realclean : clean cleandep
distclean : clean cleandep
@ rm -f $(SOPATH)/lib$(SONAME).a $(SOPATH)/lib$(SONAME).so*
@ echo "Libraries removed"
#
/trunk/tools/src/librutiltpp/Makefile
1,7 → 1,9
# $Id: Makefile 372 2011-03-20 22:48:11Z mueller $
# $Id: Makefile 401 2011-07-31 21:02:33Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-07-31 401 1.1 rename realclean->distclean
# 2011-07-01 386 1.0.2 add BOOSTINC
# 2011-03-20 372 1.0.1 renamed ..tcl -> ..tpp
# 2011-03-19 371 1.0 Initial version
#---
14,7 → 16,7
#
# Compile and Link search paths
#
INCLFLAGS = -I/usr/include/tcl8.4 -I${RETROBASE}/tools/src
INCLFLAGS = -I/usr/include/tcl8.4 -I${RETROBASE}/tools/src -I${BOOSTINC}
LDLIBS = -L${RETROBASE}/tools/lib -lrtcltools
#
# Object files to be included
39,7 → 41,7
#
# cleanup phonies:
#
.PHONY : clean cleandep realclean
.PHONY : clean cleandep distclean
clean :
@ rm -f $(OBJ_all)
@ echo "Object files removed"
48,7 → 50,7
@ rm -f $(DEP_all)
@ echo "Dependency files removed"
#
realclean : clean cleandep
distclean : clean cleandep
@ rm -f $(SOPATH)/lib$(SONAME).a $(SOPATH)/lib$(SONAME).so*
@ echo "Libraries removed"
#
/trunk/tools/src/librtcltools/RtclProxyBase.cpp
1,4 → 1,4
// $Id: RtclProxyBase.cpp 374 2011-03-27 17:02:47Z mueller $
// $Id: RtclProxyBase.cpp 401 2011-07-31 21:02:33Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,6 → 13,8
//
// Revision History:
// Date Rev Version Comment
// 2011-07-31 401 1.2 add ctor(type,interp,name) for direct usage
// 2011-04-23 380 1.1 use boost/function instead of RmethDsc
// 2011-03-05 366 1.0.1 use AppendResultNewLines() in exception catcher
// 2011-02-20 363 1.0 Initial version
// 2011-02-11 360 0.1 First draft
20,7 → 22,7
 
/*!
\file
\version $Id: RtclProxyBase.cpp 374 2011-03-27 17:02:47Z mueller $
\version $Id: RtclProxyBase.cpp 401 2011-07-31 21:02:33Z mueller $
\brief Implemenation of RtclProxyBase.
*/
 
50,14 → 52,23
{}
 
//------------------------------------------+-----------------------------------
//! FIXME_docs
 
RtclProxyBase::RtclProxyBase(const std::string& type, Tcl_Interp* interp,
const char* name)
: fType(type),
fMapMeth(),
fInterp(0)
{
CreateObjectCmd(interp, name);
}
 
//------------------------------------------+-----------------------------------
//! Destructor
 
RtclProxyBase::~RtclProxyBase()
{
if (fInterp) RtclContext::Find(fInterp).UnRegisterProxy(this);
for (mmap_it_t it=fMapMeth.begin(); it!=fMapMeth.end(); it++) {
delete it->second;
}
}
 
//------------------------------------------+-----------------------------------
76,10 → 87,9
//------------------------------------------+-----------------------------------
//! FIXME_docs
 
void RtclProxyBase::AddMeth(const std::string& name,
RmethDscBase<RtclArgs>* pmeth)
void RtclProxyBase::AddMeth(const std::string& name, const methfo_t& methfo)
{
mmap_ins_t ret = fMapMeth.insert(mmap_val_t(name, pmeth));
mmap_ins_t ret = fMapMeth.insert(mmap_val_t(name, methfo));
if (ret.second == false) // or use !(ret.second)
throw logic_error(string("RtclProxyBase::AddMeth: duplicate name: ") +
name);
106,7 → 116,7
int RtclProxyBase::TclObjectCmd(Tcl_Interp* interp, int objc,
Tcl_Obj* const objv[])
{
mdsc_t* pmdsc = 0;
mmap_cit_t it_match;
 
if (objc == 1) { // no args
mmap_cit_t it = fMapMeth.find("$default"); // default method registered ?
114,7 → 124,7
Tcl_WrongNumArgs(interp, 1, objv, "option ?args?");
return TCL_ERROR;
}
pmdsc = it->second;
it_match = it;
 
} else { // at least method name given
string name(Tcl_GetString(objv[1]));
134,7 → 144,7
return TCL_ERROR;
}
pmdsc = it->second;
it_match = it;
// check for ambiguous substring match
if (name != it->first) {
155,7 → 165,7
}
RtclArgs args(interp, objc, objv, 2);
return (*pmdsc)(args);
return (it_match->second)(args);
}
 
//------------------------------------------+-----------------------------------
/trunk/tools/src/librtcltools/RtclProxyBase.hpp
1,4 → 1,4
// $Id: RtclProxyBase.hpp 365 2011-02-28 07:28:26Z mueller $
// $Id: RtclProxyBase.hpp 401 2011-07-31 21:02:33Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,6 → 13,9
//
// Revision History:
// Date Rev Version Comment
// 2011-07-31 401 1.2 add ctor(type,interp,name) for direct usage
// 2011-04-23 380 1.1 use boost/function instead of RmethDsc
// use boost::noncopyable (instead of private dcl's)
// 2011-02-20 363 1.0 Initial version
// 2011-02-11 360 0.1 First draft
// ---------------------------------------------------------------------------
19,7 → 22,7
 
/*!
\file
\version $Id: RtclProxyBase.hpp 365 2011-02-28 07:28:26Z mueller $
\version $Id: RtclProxyBase.hpp 401 2011-07-31 21:02:33Z mueller $
\brief Declaration of class RtclProxyBase.
*/
 
31,24 → 34,28
#include <string>
#include <map>
 
#include "boost/utility.hpp"
#include "boost/function.hpp"
 
#include "RtclArgs.hpp"
#include "librtools/RmethDscBase.hpp"
 
namespace Retro {
 
class RtclProxyBase {
class RtclProxyBase : private boost::noncopyable {
public:
static const int kOK = TCL_OK;
static const int kERR = TCL_ERROR;
 
typedef std::map<std::string, RmethDscBase<RtclArgs>*> mmap_t;
typedef boost::function<int(RtclArgs&)> methfo_t;
 
typedef std::map<std::string, methfo_t> mmap_t;
typedef mmap_t::iterator mmap_it_t;
typedef mmap_t::const_iterator mmap_cit_t;
typedef mmap_t::value_type mmap_val_t;
 
typedef RmethDscBase<RtclArgs> mdsc_t;
 
explicit RtclProxyBase(const std::string& type = std::string());
RtclProxyBase(const std::string& type, Tcl_Interp* interp,
const char* name);
virtual ~RtclProxyBase();
 
virtual int ClassCmdConfig(Tcl_Interp* interp, int objc,
60,9 → 67,8
protected:
void SetType(const std::string& type);
 
void AddMeth(const std::string& name,
RmethDscBase<RtclArgs>* pmeth);
 
void AddMeth(const std::string& name, const methfo_t& methfo);
void CreateObjectCmd(Tcl_Interp* interp, const char* name);
 
int TclObjectCmd(Tcl_Interp* interp, int objc,
78,11 → 84,6
mmap_t fMapMeth; //!< map for named methods
Tcl_Interp* fInterp; //!< tcl interpreter
Tcl_Command fCmdToken; //!< cmd token for object command
 
// RtclProxyBase is not copy or assignable
private:
RtclProxyBase(const RtclProxyBase& rhs);
RtclProxyBase& operator=(const RtclProxyBase& rhs);
};
} // end namespace Retro
/trunk/tools/src/librtcltools/RtclContext.hpp
1,4 → 1,4
// $Id: RtclContext.hpp 368 2011-03-12 09:58:53Z mueller $
// $Id: RtclContext.hpp 380 2011-04-25 18:14:52Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,6 → 13,7
//
// Revision History:
// Date Rev Version Comment
// 2011-04-24 380 1.0.2 use boost::noncopyable (instead of private dcl's)
// 2011-03-12 368 1.0.1 drop fExitSeen, get exit handling right
// 2011-02-18 362 1.0 Initial version
// 2011-02-18 362 0.1 First draft
20,7 → 21,7
 
/*!
\file
\version $Id: RtclContext.hpp 368 2011-03-12 09:58:53Z mueller $
\version $Id: RtclContext.hpp 380 2011-04-25 18:14:52Z mueller $
\brief Declaration of class RtclContext.
*/
 
33,12 → 34,14
#include <set>
#include <map>
 
#include "boost/utility.hpp"
 
#include "RtclClassBase.hpp"
#include "RtclProxyBase.hpp"
 
namespace Retro {
 
class RtclContext {
class RtclContext : private boost::noncopyable {
public:
typedef std::set<RtclClassBase*> cset_t;
typedef cset_t::iterator cset_it_t;
73,12 → 76,6
pset_t fSetProxy; //!< set for Proxy objects
 
static xmap_t fMapContext; //!< map of contexts
 
// RtclContext is not copy or assignable nor default constructable
private:
RtclContext();
RtclContext(const RtclContext& rhs);
RtclContext& operator=(const RtclContext& rhs);
};
} // end namespace Retro
/trunk/tools/src/librtcltools/RtclClassBase.hpp
1,4 → 1,4
// $Id: RtclClassBase.hpp 365 2011-02-28 07:28:26Z mueller $
// $Id: RtclClassBase.hpp 380 2011-04-25 18:14:52Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
13,6 → 13,7
//
// Revision History:
// Date Rev Version Comment
// 2011-04-24 380 1.0.1 use boost::noncopyable (instead of private dcl's)
// 2011-02-20 363 1.0 Initial version
// 2011-02-11 360 0.1 First draft
// ---------------------------------------------------------------------------
19,7 → 20,7
 
/*!
\file
\version $Id: RtclClassBase.hpp 365 2011-02-28 07:28:26Z mueller $
\version $Id: RtclClassBase.hpp 380 2011-04-25 18:14:52Z mueller $
\brief Declaration of class RtclClassBase.
*/
 
26,11 → 27,13
#ifndef included_Retro_RtclClassBase
#define included_Retro_RtclClassBase 1
 
#include "boost/utility.hpp"
 
#include "tcl.h"
 
namespace Retro {
 
class RtclClassBase {
class RtclClassBase : private boost::noncopyable {
public:
static const int kOK = TCL_OK;
static const int kERR = TCL_ERROR;
64,13 → 67,6
std::string fType; //!< classed type name
Tcl_Interp* fInterp; //!< tcl interpreter
Tcl_Command fCmdToken; //!< cmd token for class command
 
// RtclClassBase is not copy or assignable
private:
RtclClassBase(const RtclClassBase& rhs);
RtclClassBase& operator=(const RtclClassBase& rhs);
 
 
};
} // end namespace Retro
/trunk/tools/src/librtcltools/Makefile
1,7 → 1,9
# $Id: Makefile 370 2011-03-14 18:33:43Z mueller $
# $Id: Makefile 401 2011-07-31 21:02:33Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-07-31 401 1.1 rename realclean->distclean
# 2011-07-01 386 1.0.1 add BOOSTINC
# 2011-02-11 360 1.0 Initial version
#---
#
13,7 → 15,7
#
# Compile and Link search paths
#
INCLFLAGS = -I/usr/include/tcl8.4 -I${RETROBASE}/tools/src
INCLFLAGS = -I/usr/include/tcl8.4 -I${RETROBASE}/tools/src -I${BOOSTINC}
LDLIBS = -L${RETROBASE}/tools/lib -lrtools
#
# Object files to be included
39,7 → 41,7
#
# cleanup phonies:
#
.PHONY : clean cleandep realclean
.PHONY : clean cleandep distclean
clean :
@ rm -f $(OBJ_all)
@ echo "Object files removed"
48,7 → 50,7
@ rm -f $(DEP_all)
@ echo "Dependency files removed"
#
realclean : clean cleandep
distclean : clean cleandep
@ rm -f $(SOPATH)/lib$(SONAME).a $(SOPATH)/lib$(SONAME).so*
@ echo "Libraries removed"
#
/trunk/tools/src/Makefile
1,4 → 1,4
# $Id: Makefile 372 2011-03-20 22:48:11Z mueller $
# $Id: Makefile 401 2011-07-31 21:02:33Z mueller $
#
# Top level makefile, using the recipe found in
# http://www.lackof.org/taggart/hacking/make-example/
5,6 → 5,7
#
# Revision History:
# Date Rev Version Comment
# 2011-07-31 401 1.2 rename realclean->distclean
# 2011-03-20 372 1.1.1 renamed ..tcl -> ..tpp
# 2011-03-14 370 1.1.0 rename librtoolstcl -> librtcltools
# 2011-02-13 361 1.1 add realclean rule; add dirs and dependencies
18,9 → 19,9
#
BUILDDIRS = $(DIRS:%=build-%)
CLEANDIRS = $(DIRS:%=clean-%)
REALCDIRS = $(DIRS:%=realc-%)
REALCDIRS = $(DIRS:%=distc-%)
#
.PHONY: all clean realclean
.PHONY: all clean distclean
.PHONY: $(DIRS)
.PHONY: $(BUILDDIRS)
.PHONY: $(CLEANDIRS)
44,8 → 45,8
$(CLEANDIRS):
$(MAKE) -C $(@:clean-%=%) clean
#
# realclean rule
# distclean rule
#
realclean: $(REALCDIRS)
distclean: $(REALCDIRS)
$(REALCDIRS):
$(MAKE) -C $(@:realc-%=%) realclean
$(MAKE) -C $(@:distc-%=%) distclean
trunk/tools/bin/impact_wrapper Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/tools/bin/ti_rri =================================================================== --- trunk/tools/bin/ti_rri (revision 11) +++ trunk/tools/bin/ti_rri (revision 12) @@ -1,6 +1,6 @@ #! /usr/bin/env tclsh # -*- tcl -*- -# $Id: ti_rri 376 2011-04-17 12:24:07Z mueller $ +# $Id: ti_rri 386 2011-07-01 17:31:03Z mueller $ # # Copyright 2011- by Walter F.J. Mueller # @@ -15,6 +15,7 @@ # # Revision History: # Date Rev Version Comment +# 2011-04-22 379 1.0.1 check for RETROBASE; proper exit handling; help text # 2011-04-17 376 1.0 Initial version # 2011-03-19 371 0.1 First draft # @@ -49,7 +50,30 @@ set clist {} set optsendseen 0 +set runpid {} +# +# cleanup handler +# must be in a proc so that it can be called from tclreadline +# must be defined before ::tclreadline::Loop called (all after ignored...) +# +proc exit_cleanup {} { + global opts + global runpid + + # now close rlink connection + if { $opts(fifo) || $opts(term) } { + rlc close + } + + # FIXME_code: should sync here with -run process run-down + # but no wait available in tcl (grr...) + if { "$runpid" ne "" } { + after 100; # currently just wait 100ms + } + return +} + foreach arg $argv { if { $optsendseen } { lappend clist $arg @@ -74,10 +98,56 @@ } if { $opts(help) } { - puts "usage: ti_rri" + # use {} as defimiter here to avoid that escaping of all [] + puts {usage: ti_rri [OPTION]... [COMMAND]...} + puts {} + puts {Options:} + puts { --run=CMD exec's CMD as subprocess before the rlink port opened} + puts { useful to start test benches, usually via 'tbw'} + puts { --fifo[=ARGS] open fifo type rlink port. Optional arguments are:} + puts { --fifo=[NAME[,KEEP]]} + puts { NAME fifo name prefix, default 'rlink_cext_fifo'} + puts { KEEP if non-empty the fifo is kept open on exit} + puts { --term[=ARGS] open term type rlink port. Optional arguments are:} + puts { --term=[NAME,[BAUD,[BREAK]]]} + puts { NAME tty device name, default 'USB0'} + puts { if not starting with '/' the name is} + puts { prefixed with '/dev/tty'} + puts { BAUD serial port baud rate, default '115k'} + puts { allowed baud rate settings are:} + puts { 9600, 19200, 19k, 38400, 38k, 57600, 57k} + puts { 115200, 115k, 230400, 230k, 460800, 460k} + puts { 500000, 500k, 921600, 921k, 1000000, 1M} + puts { 2000000, 2M, 3000000, 3M} + puts { --log=FILE set log file name. Default is to write to stdout.} + puts { --logl=LVL set log level, default is '2' allowed values:} + puts { 0 no logging} + puts { 1 log rlink commands with communication errors} + puts { 2 log rlink commands with failed checks} + puts { 3 log all rlink commands} + puts { --dmpl=LVL set dump level, default is '0', values like logl} + puts { --tiol=LVL set i/o trace level, default is '0', allowed values:} + puts { 0 no i/o trace} + puts { 1 trace buffer activities} + puts { 2 trace character activities} + puts { --int enter interactive mode even when commands given} + puts { --help display this help and exit} + puts { -- all following arguments are treated as tcl commands} + puts {} + puts {Command handling:} + puts { For arguments of the form '@.tcl' the respective file is} + puts { sourced. All other arguments are treated as Tcl commands and executed} + puts { with eval.} + puts {} + puts {For further details consults the ti_rri man page.} return 0 } +if {![info exists env(RETROBASE)]} { + puts "-E: RETROBASE environment variable not defined" + return 1 +} + if { $opts(fifo) && $opts(term) } { puts "-E: both --fifo and --term given, only one allowed" return 1 @@ -100,8 +170,7 @@ rlc config -logdumplevel $opts(dmpl_) rlc config -logtracelevel $opts(tiol_) -# first start, if specified with -run, the test bench -set runpid {} +# first start, if specified with --run, the test bench if { $opts(run_) ne "" } { if { [catch {eval "exec $opts(run_) &" } runpid] } { puts "-E: failed to execute \"$opts(run_)\" with error message\n $runpid" @@ -130,7 +199,7 @@ set brk [lindex $nlist 2] if {$dev eq ""} {set dev "USB0"} if {$baud eq ""} {set baud "115k"} - if {! [regexp -- {^/dev} $dev]} { + if {! [regexp -- {^/} $dev]} { set dev "/dev/tty$dev" } set url "term:$dev?baud=$baud" @@ -187,21 +256,11 @@ return "ti_rri > " } } + ::tclreadline::readline eofchar {::exit_cleanup; puts {}; exit} ::tclreadline::Loop } +} else { + exit_cleanup } -# -# now close rlink connection -# -if { $opts(fifo) || $opts(term) } { - rlc close -} - -# FIXME_code: should sync here with -run process run-down -# but no wait available in tcl (grr...) -if { $runpid } { - after 100; # currently just wait 100ms -} - return 0
/trunk/tools/bin/vbomconv
1,7 → 1,7
#!/usr/bin/perl -w
# $Id: vbomconv 314 2010-07-09 17:38:41Z mueller $
# $Id: vbomconv 405 2011-08-14 08:16:28Z mueller $
#
# Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
14,6 → 14,11
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.9.1 always write 'vhdl' into xst prj files again; for
# -xst_export: remove opt file export, add ucf_cpp
# handling
# 2011-06-26 385 1.9 add --ise_path, pass it to vbomconv --xst_prj
# 2011-06-09 383 1.8.6 fix xst_vhdl.opt logic (use rtl/vlib now)
# 2010-07-03 312 1.8.5 add --flist action
# 2010-06-03 299 1.8.4 generate ucf->ncd dependencies in dep_xst
# 2010-04-26 284 1.8.3 add _[sft]sim support for ISim
46,7 → 51,7
 
my %opts = ();
 
GetOptions(\%opts, "help", "trace",
GetOptions(\%opts, "help", "trace", "ise_path=s",
"dep_xst", "dep_ghdl", "dep_isim",
"xst_prj", "isim_prj",
"ghdl_a", "ghdl_a_cmd",
87,7 → 92,15
my $is_tsim;
my $do_trace = exists $opts{trace};
my $level;
my $xst_writevhdl = 1;
 
# now using '-ifmt mixed', so language always needed (2011-08-13)
#if (defined $opts{ise_path}) {
# if ($opts{ise_path} =~ /^xc6s/) {
# $xst_writevhdl = 0;
# }
#}
 
autoflush STDOUT 1; # autoflush, so noting lost on exec later
 
if (exists $opts{help}) {
106,7 → 119,7
# check that only one action is defined, mark xst, gdhl, or isim class
 
foreach (keys %opts) {
$nactions += 1 unless ($_ eq "trace");
$nactions += 1 unless ($_ eq "trace" || $_ eq "ise_path");
$is_xst = 1 if ($_ eq "dep_xst");
$is_ghdl = 1 if ($_ eq "dep_ghdl");
$is_isim = 1 if ($_ eq "dep_isim");
307,8 → 320,11
 
if (exists $opts{xst_prj}) {
foreach (@file_list) {
print "vhdl work $_\n";
# print "work $_\n"; # for ISE 11.2 S-6/V-6 compilations
if ($xst_writevhdl) {
print "vhdl work $_\n";
} else {
print "work $_\n"; # for ISE S-6/V-6 compilations with '-ifmt VHDL'
}
}
}
 
484,17 → 500,18
 
close(PFILE);
 
# Note: currently no xflow opt files exported !!
if (exists $opts{xst_export}) {
copy_edir($ENV{RETROBASE}."/vlib/xst_vhdl.opt", $edir)
if (defined $ENV{RETROBASE} || -r $ENV{RETROBASE}."/vlib/xst_vhdl.opt");
 
copy_edir("xst_vhdl.opt", $edir) if (-r "xst_vhdl.opt");
 
open(XFILE, ">$edir/$stem.xcf") or
die "can't write open $edir/$stem.xcf: $!";
close(XFILE);
 
foreach(glob("*.xcf")) { copy_edir($_, $edir); }
 
if (-r "$stem.ucf_cpp") {
system "/bin/sh", "-c", "make $stem.ucf";
}
 
foreach(glob("*.ucf")) { copy_edir($_, $edir); }
}
 
/trunk/tools/bin/isemsg_filter
0,0 → 1,200
#!/usr/bin/perl -w
# $Id: isemsg_filter 406 2011-08-14 21:06:44Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 2, or at your option any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
# Revision History:
# Date Rev Version Comment
# 2011-08-14 406 1.0 Initial version
#
 
use 5.005; # require Perl 5.005 or higher
use strict; # require strict checking
use FileHandle;
 
use Getopt::Long;
 
my %opts = ();
 
GetOptions(\%opts, "help", "pack") || exit 1;
 
sub print_help;
sub read_mfs;
sub read_log;
 
my $type = shift @ARGV;
my $mfsnam = shift @ARGV;
my $lognam = shift @ARGV;
my @flist;
my @mlist;
my $nackcnt = 0;
my $ackcnt = 0;
my $misscnt = 0;
 
 
autoflush STDOUT 1; # autoflush, so noting lost on exec later
 
if (exists $opts{help}) {
print_help;
exit 0;
}
 
if (!defined $type || !defined $mfsnam || !defined $lognam) {
print STDERR "%isemsg_filter-E: one of 'type mfs log' missing \n\n";
print_help;
exit 1;
}
 
if ($type !~ m{^(xst|tra|map|par|twr|bgn)$}) {
print STDERR "%isemsg_filter-E: type must be xst,tra,map,par,twr, or bgn\n";
exit 1;
}
 
if (read_mfs()) {exit 1;}
if (read_log()) {exit 1;}
 
foreach (@mlist) {
my $msgorig = $_->[0];
my $msgflat = $_->[1];
my $msgmatch = 0;
foreach (@flist) {
my $filt = $_->[0];
if ($msgflat =~ m{$filt}) {
$_->[1] += 1;
$msgmatch = 1;
last;
}
}
if ($msgmatch) {
$_->[2] += 1;
} else {
$nackcnt += 1;
}
}
 
if ($nackcnt) {
print "Non-acknowledged messages of type [$type] from $lognam:\n";
foreach (@mlist) {
next if $_->[2];
print $_->[0] . "\n";
}
print "\n";
}
 
foreach (@flist) {
if ($_->[1]) {
$ackcnt += 1;
} else {
$misscnt += 1;
}
}
 
if ($ackcnt && exists $opts{pack}) {
print "Acknowledged messages of type [$type] from $lognam:\n";
foreach (@flist) {
next if $_->[1] == 0;
printf "%4d: %s\n", $_->[1], $_->[0];
}
print "\n";
}
 
if ($misscnt) {
print "Missed acknowledged messages of type [$type] from $lognam:\n";
foreach (@flist) {
next if $_->[1] != 0;
printf "%4d: %s\n", $_->[1], $_->[0];
}
print "\n";
}
 
#-------------------------------------------------------------------------------
sub read_mfs {
if (not -r $mfsnam) {
print STDERR "%isemsg_filter-E: \'$mfsnam\' not existing or readable\n";
return 1;
}
 
open (FFILE, $mfsnam) or die "can't open for read $mfsnam: $!";
 
my $intyp = 0;
 
while (<FFILE>) {
chomp;
next if /^\s*#/; # drop comments
next if /^\s*$/; # drop empty lines
 
if (m{^\[([a-z]{3})\]$}) {
if ($1 eq $type) {
$intyp = 1;
} else {
$intyp = 0;
}
} else {
if ($intyp) {
push @flist, [$_, 0];
}
}
}
 
close (FFILE);
return 0;
}
 
#-------------------------------------------------------------------------------
sub read_log {
if (not -r $lognam) {
print STDERR "%isemsg_filter-E: \'$lognam\' not existing or readable\n";
return 1;
}
 
open (LFILE, $lognam) or die "can't open for read $lognam: $!";
 
my $msgorig = "";
my $msgflat = "";
my $inmsg = 0;
 
while (<LFILE>) {
chomp;
if (m{^(INFO|WARNING|ERROR):}) {
if ($inmsg) {push @mlist, [$msgorig, $msgflat, 0];}
$inmsg = 1;
$msgorig = $_;
$msgflat = $_;
} elsif ($inmsg && m{^\s\s\s\S}) {
$msgorig .= "\n" . $_;
my $txt = $_;
$txt =~ s{\s\s}{}; # replace 3 leading blanks by one !
$msgflat .= $txt;
} else {
if ($inmsg) {push @mlist, [$msgorig, $msgflat, 0];}
$inmsg = 0;
}
}
 
if ($inmsg) {push @mlist, [$msgorig, $msgflat, 0];}
 
close (LFILE);
 
return 0;
}
 
#-------------------------------------------------------------------------------
 
sub print_help {
print "usage: isemsg_filter [options] type mfs log\n";
print " type log file type: xst,tra,map,par,twr, or bgn\n";
print " mfs message filter setup file\n";
print " log log file\n";
print " Options:\n";
print " --pack print summary of acknowledged messages\n";
print " --help this message\n";
}
trunk/tools/bin/isemsg_filter Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/tools/bin/config_wrapper =================================================================== --- trunk/tools/bin/config_wrapper (nonexistent) +++ trunk/tools/bin/config_wrapper (revision 12) @@ -0,0 +1,246 @@ +#!/usr/bin/perl -w +# $Id: config_wrapper 402 2011-08-05 18:56:44Z mueller $ +# +# Copyright 2010-2011 by Walter F.J. Mueller +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +# +# Revision History: +# Date Rev Version Comment +# 2011-08-04 402 1.1.4 add atlys support; +# 2011-07-25 399 1.1.3 add nexys2-500 support; bsdl path for sp605 +# 2011-07-18 395 1.1.2 cleanup bsdl path creation for jtag +# 2011-07-17 394 1.1.1 add bit->svf conversion and config with jtag +# 2011-07-11 393 1.1 renamed from impact_wrapper; add function parameter, +# old action with 'iconfig' +# 2011-07-01 386 1.0.3 support sp605/xc6slx45t +# 2010-05-24 294 1.0.2 support nexys2/xc3s1200e +# 2010-04-24 282 1.0.1 proper error exit for GetOptions() +# 2010-04-24 281 1.0 Initial version +# + +use 5.005; # require Perl 5.005 or higher +use strict; # require strict checking +use FileHandle; + +use Getopt::Long; + +my %opts = (); + +GetOptions(\%opts, "help", "dry_run", "board=s", "path=s") or exit 1; + +# setup defaults for board and path +if (not defined $opts{board}) { + $opts{board} = "s3board"; +} +if (not defined $opts{path}) { + $opts{path} = "xc3s1000" if $opts{board} eq "s3board"; + $opts{path} = "xc3s1200e" if $opts{board} eq "nexys2"; + $opts{path} = "xc6slx45" if $opts{board} eq "atlys"; + $opts{path} = "xc6slx45t" if $opts{board} eq "sp605"; +} + +sub print_help; +sub run_command; + + +autoflush STDOUT 1 if (-p STDOUT); # autoflush if output into pipe + +if (exists $opts{help}) { + print_help; + exit 0; +} + +my $board = $opts{board}; +my $ipath = $opts{path}; + +$ipath =~ s/-.*$//; # trim all after first '-' + +# now setup JTAG chain config + +my @plist; +my $pfpga; + +# +# Note: when new targets are added update also the blist logic below +# +if ($board eq "s3board" && $ipath eq "xc3s200") { # S3BOARD-200 + @plist = ($ipath, "xcf02s"); + $pfpga = 1; +} elsif ($board eq "s3board" && $ipath eq "xc3s1000") { # S3BOARD-1200 + @plist = ($ipath, "xcf04s"); + $pfpga = 1; + +} elsif ($board eq "nexys2" && $ipath eq "xc3s1200e") { # nexys2-1200 + @plist = ($ipath, "xcf04s"); + $pfpga = 1; +} elsif ($board eq "nexys2" && $ipath eq "xc3s500e") { # nexys2-500 + @plist = ($ipath, "xcf04s"); + $pfpga = 1; + +} elsif ($board eq "atlys" && $ipath eq "xc6slx45") { # atlys + @plist = ($ipath); + $pfpga = 1; + +} elsif ($board eq "sp605" && $ipath eq "xc6slx45t") { # sp605 + @plist = ("xccace", $ipath); + $pfpga = 2; +} else { + print STDERR "config_wrapper-E: only s3board/nexys2/sp605 supported\n"; + exit 1; +} + +my @blist; +foreach my $part (@plist) { + if ($part =~ m/^xcf/) { push @blist, "xcf/data" } # proms + elsif ($part =~ m/^xc3s\d*$/) { push @blist, "spartan3/data" } # s-3 + elsif ($part =~ m/^xc3s\d*e$/) { push @blist, "spartan3e/data" } # s-3e + elsif ($part =~ m/^xc6slx\d*t?$/) { push @blist, "spartan6/data" }# s-6 lx + elsif ($part =~ m/^xccace$/) { push @blist, "acempm/data" } # sys-ace + else { + print STDERR "config_wrapper-E: no bsdl path known for $part\n"; + exit 1; + } +} + +my $cmd = shift @ARGV; +my $file = shift @ARGV; + +if (! defined $cmd) { + print STDERR "config_wrapper-E: no command specified\n"; + exit 1; +} + +if (! defined $file) { + print STDERR "config_wrapper-E: no bit or svf file specified\n"; + exit 1; +} +if (! -r $file) { + print STDERR "config_wrapper-E: input file not found or readable\n"; + exit 1; +} + +my $xilpath = $ENV{XILINX}; +if (! defined $xilpath) { + print STDERR "config_wrapper-E: XILINX environment variable not defined\n"; + exit 1; +} + +# ----- iconfig action -------------------------------------------------------- +if ($cmd eq "iconfig") { + + my $tmpfile = "tmp_config_wrapper.cmd"; + open (OFILE, ">$tmpfile") or die "Couldn't open tmp cmd file: $!"; + + print OFILE "setMode -bs\n"; + print OFILE "setCable -p auto\n"; + for (my $i = 0; $i<=$#plist; $i++) { + printf OFILE "addDevice -p %d -part %s\n", $i+1, $plist[$i]; + } + printf OFILE "assignFile -p %d -file %s\n", $pfpga, $file; + printf OFILE "program -p %d -verify\n", $pfpga; + print OFILE "quit\n"; + + close (OFILE) or die "Couldn't close tmp cmd file: $!"; + + my $rc = run_command("impact -batch", $tmpfile); + exit $rc; + +# ----- jconfig action -------------------------------------------------------- +} elsif ($cmd eq "jconfig") { + + my $bpath = join ";", map "$xilpath/$_",@blist; + + my $tmpfile = "tmp_config_wrapper.cmd"; + open (OFILE, ">$tmpfile") or die "Couldn't open tmp cmd file: $!"; + + # the UrJtag and Xilinx impact have different chain and part number schemes + # impact: 1-based, 1 is first in chain; + # UrJtag: 0-based, 0 is last in chain; + # e.g. on Digilent Nexys2: + # impact: (1) FPGA (2) PROM + # UrJtag: (1) FPGA (0) PROM + + my $jtag_part = $#plist + 1 - $pfpga; + + print OFILE "cable usbblaster\n"; + printf OFILE "bsdl path %s\n", $bpath; + print OFILE "detect\n"; + printf OFILE "part %d\n", $jtag_part; + printf OFILE "svf %s\n", $file; + + close (OFILE) or die "Couldn't close tmp cmd file: $!"; + + my $rc = run_command("jtag", $tmpfile); + exit $rc; + +# ----- bit2svf action -------------------------------------------------------- +} elsif ($cmd eq "bit2svf") { + my $ofile = $file; + $ofile =~ s/\.bit/\.svf/; + + my $tmpfile = "tmp_config_wrapper.cmd"; + open (OFILE, ">$tmpfile") or die "Couldn't open tmp cmd file: $!"; + + print OFILE "setMode -bs\n"; + printf OFILE "setCable -port svf -file %s\n", $ofile; + printf OFILE "addDevice -p 1 -file %s\n", $file; + print OFILE "program -p 1\n"; + print OFILE "quit\n"; + + close (OFILE) or die "Couldn't close tmp cmd file: $!"; + + my $rc = run_command("impact -batch", $tmpfile); + exit $rc; +} + +print STDERR "config_wrapper-E: command must be bit2svf, iconfig or jconfig\n"; +exit 1; + +#------------------------------------------------------------------------------- + +sub run_command { + + my ($cmd, $tmpfile) = @_; + + my $wrc; + if (defined $opts{dry_run}) { + print STDOUT "$cmd\n"; + $wrc = system "/bin/sh", "-c", "cat $tmpfile"; + } else { + $wrc = system "/bin/sh", "-c", "$cmd $tmpfile"; + } + + my $rc = 0; + if ($wrc != 0) { + my $rc = int($wrc/256); + if ($rc == 0) { + my $sig = $wrc % 256; + print STDERR "config_wrapper-I $cmd aborted by signal $sig\n"; + $rc = 1; + } else { + print STDERR "config_wrapper-I $cmd failed (rc=$rc) $?\n"; + } + } + + unlink $tmpfile or die "Couldn't delete tmp cmd file: $!"; + return $rc; +} + +#------------------------------------------------------------------------------- + +sub print_help { + print "usage: config_wrapper [--help] [--board=b] [--path=p] cmd file\n"; + print " cmd bit2svf or iconfig or jconfig\n"; + print " --help this message\n"; + print " --dry_run print impact command list\n"; + print " --board=b type of board\n"; + print " --path=p type of fpga\n"; +}
trunk/tools/bin/config_wrapper Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/tools/bin/.cvsignore =================================================================== --- trunk/tools/bin/.cvsignore (nonexistent) +++ trunk/tools/bin/.cvsignore (revision 12) @@ -0,0 +1 @@ +cycfx2prog Index: trunk/tools/bin =================================================================== --- trunk/tools/bin (revision 11) +++ trunk/tools/bin (revision 12)
trunk/tools/bin Property changes : Modified: svn:ignore ## -30,3 +30,4 ## *_svn.log *_sum.log *_[dsft]sim.log +cycfx2prog Index: trunk/tools/dox/w11.Doxyfile =================================================================== --- trunk/tools/dox/w11.Doxyfile (revision 11) +++ trunk/tools/dox/w11.Doxyfile (revision 12) @@ -1,4 +1,4 @@ -# $Id: $ +# $Id: w11.Doxyfile 403 2011-08-06 17:36:22Z mueller $ # Revision History: # Date Rev Version Comment # 2011-01-09 354 1.0 Initial version Index: trunk/rtl/ibus/Makefile =================================================================== --- trunk/rtl/ibus/Makefile (revision 11) +++ trunk/rtl/ibus/Makefile (revision 12) @@ -1,13 +1,14 @@ -# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $ +# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $ # # Revision History: # Date Rev Version Comment +# 2011-08-13 405 1.1 use includes from rtl/make # 2008-08-22 161 1.0 Initial version # VBOM_all = $(wildcard *.vbom) NGC_all = $(VBOM_all:.vbom=.ngc) # -.phony : all clean +.PHONY : all clean # all : $(NGC_all) # @@ -15,7 +16,7 @@ # #---- # -include $(RETROBASE)/rtl/vlib/Makefile.xflow +include $(RETROBASE)/rtl/make/generic_xflow.mk # include $(VBOM_all:.vbom=.dep_xst) # Index: trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.mfset =================================================================== --- trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.mfset (nonexistent) +++ trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.mfset (revision 12) @@ -0,0 +1,63 @@ +# $Id: sys_tst_rlink_n2.mfset 406 2011-08-14 21:06:44Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected + +Unconnected output port 'LOCKED' of component 'dcm_sp_sfs' +Unconnected output port 'OFIFO_SIZE' of component 'rlink_base' +Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' +Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen' + +Input is never used +Input > is never used +Input is never used +Input is never used +Input is never used + +Signal > is assigned but never used +Signal is assigned but never used +Signal > is assigned but never used +ignal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal > is assigned but never used +Signal > is assigned but never used +Signal > is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent + +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +The signal is incomplete +Logical network I_MEM_WAIT_IBUF has no load +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +The signal I_MEM_WAIT_IBUF has no load +There are 1 loadless signals in this design +# +# ---------------------------------------------------------------------------- +[bgn] +Spartan-3 1200E and 1600E devices do not support bitstream +The signal is incomplete \ No newline at end of file Index: trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.ucf_cpp =================================================================== --- trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.ucf_cpp (revision 11) +++ trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.ucf_cpp (revision 12) @@ -1,4 +1,4 @@ -## $Id: mueller $ +## $Id: sys_tst_rlink_n2.ucf_cpp 403 2011-08-06 17:36:22Z mueller $ ## ## Revision History: ## Date Rev Version Comment Index: trunk/rtl/sys_gen/tst_rlink/nexys2/tb/Makefile =================================================================== --- trunk/rtl/sys_gen/tst_rlink/nexys2/tb/Makefile (revision 11) +++ trunk/rtl/sys_gen/tst_rlink/nexys2/tb/Makefile (revision 12) @@ -1,7 +1,8 @@ -# $Id: Makefile 351 2010-12-30 21:50:54Z mueller $ +# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $ # # Revision History: # Date Rev Version Comment +# 2011-08-13 405 1.1 use includes from rtl/make # 2010-12-29 351 1.0 Initial version # EXE_all = tb_tst_rlink_n2 @@ -8,7 +9,7 @@ # ISE_PATH = xc3s1200e-fg320-4 # -.phony : all all_ssim all_tsim clean +.PHONY : all all_ssim all_tsim clean # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) @@ -19,8 +20,8 @@ # #----- # -include $(RETROBASE)/rtl/vlib/Makefile.ghdl -include $(RETROBASE)/rtl/vlib/Makefile.xflow +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk # VBOM_all = $(wildcard *.vbom) # Index: trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd =================================================================== --- trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd (revision 11) +++ trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd (revision 12) @@ -1,4 +1,4 @@ --- $Id: sys_tst_rlink_n2.vhd 375 2011-04-02 07:56:47Z mueller $ +-- $Id: sys_tst_rlink_n2.vhd 406 2011-08-14 21:06:44Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -17,7 +17,9 @@ -- -- Dependencies: vlib/xlib/dcm_sp_sfs -- vlib/genlib/clkdivce --- bplib/s3board/s3_rs232_iob_int_ext +-- bplib/bpgen/bp_rs232_2l4l_iob +-- bplib/bpgen/sn_humanio_rbus +-- tst_rlink -- vlib/nexys2/n2_cram_dummy -- -- Test bench: tb/tb_tst_rlink_n2 @@ -27,14 +29,34 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-06-26 385 12.1 M53d xc3s1200e-4 688 1500 68 993 t 16.2 -- 2011-04-02 375 12.1 M53d xc3s1200e-4 688 1572 68 994 t 13.8 -- 2010-12-29 351 12.1 M53d xc3s1200e-4 604 1298 68 851 t 14.7 -- -- Revision History: -- Date Rev Version Comment +-- 2011-07-09 391 1.1.2 use now bp_rs232_2l4l_iob +-- 2011-07-08 390 1.1.1 use now sn_humanio +-- 2011-06-26 385 1.1 move s3_humanio_rbus from tst_rlink to top level -- 2010-12-29 351 1.0 Initial version ------------------------------------------------------------------------------ +-- Usage of Nexys 2 Switches, Buttons, LEDs: -- +-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob +-- 1 -> Pmod B/top RS232 port / +-- (1:7): no function (only connected to s3_humanio_rbus) +-- +-- LED(0): timer 0 busy +-- LED(1): timer 1 busy +-- LED(2:6): no function (only connected to s3_humanio_rbus) +-- LED(7): RL_SER_MONI.abact +-- +-- DSP: RL_SER_MONI.clkdiv (from auto bauder) +-- DP(0): RL_SER_MONI.rxact +-- DP(1): RTS_N (shows rx back preasure) +-- DP(2): RL_SER_MONI.txact +-- DP(3): CTS_N (shows tx back preasure) +-- library ieee; use ieee.std_logic_1164.all; @@ -43,7 +65,9 @@ use work.slvtypes.all; use work.xlib.all; use work.genlib.all; -use work.s3boardlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; use work.nexys2lib.all; use work.sys_conf.all; @@ -90,16 +114,28 @@ signal SWI : slv8 := (others=>'0'); signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); signal RESET : slbit := '0'; signal CE_USEC : slbit := '0'; signal CE_MSEC : slbit := '0'; + signal RB_MREQ_TOP : rb_mreq_type := rb_mreq_init; + signal RB_SRES_TOP : rb_sres_type := rb_sres_init; + signal RL_SER_MONI : rl_ser_moni_type := rl_ser_moni_init; + signal STAT : slv8 := (others=>'0'); + + constant rbaddr_hio : slv8 := "11000000"; -- 110000xx + begin assert (sys_conf_clksys mod 1000000) = 0 report "assert sys_conf_clksys on MHz grid" severity failure; + + RESET <= '0'; -- so far not used DCM : dcm_sp_sfs generic map ( @@ -125,9 +161,10 @@ CE_MSEC => CE_MSEC ); - IOB_RS232 : s3_rs232_iob_int_ext + IOB_RS232 : bp_rs232_2l4l_iob port map ( CLK => CLK, + RESET => '0', SEL => SWI(0), RXD => RXD, TXD => TXD, @@ -141,21 +178,21 @@ O_RTS1_N => O_FUSP_RTS_N ); - RLTEST : entity work.tst_rlink + HIO : sn_humanio_rbus generic map ( DEBOUNCE => sys_conf_hio_debounce, - CDINIT => sys_conf_ser2rri_cdinit) + RB_ADDR => rbaddr_hio) port map ( CLK => CLK, RESET => RESET, - CE_USEC => CE_USEC, CE_MSEC => CE_MSEC, - RXD => RXD, - TXD => TXD, - CTS_N => CTS_N, - RTS_N => RTS_N, + RB_MREQ => RB_MREQ_TOP, + RB_SRES => RB_SRES_TOP, SWI => SWI, BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, I_SWI => I_SWI, I_BTN => I_BTN, O_LED => O_LED, @@ -163,6 +200,24 @@ O_SEG_N => O_SEG_N ); + RLTEST : entity work.tst_rlink + generic map ( + CDINIT => sys_conf_ser2rri_cdinit) + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ_TOP => RB_MREQ_TOP, + RB_SRES_TOP => RB_SRES_TOP, + RL_SER_MONI => RL_SER_MONI, + STAT => STAT + ); + SRAM_PROT : n2_cram_dummy -- connect CRAM to protection dummy port map ( O_MEM_CE_N => O_MEM_CE_N, @@ -177,5 +232,16 @@ O_MEM_ADDR => O_MEM_ADDR, IO_MEM_DATA => IO_MEM_DATA ); - + + DSP_DAT <= RL_SER_MONI.clkdiv; + DSP_DP(0) <= RL_SER_MONI.rxact; + DSP_DP(1) <= RTS_N; + DSP_DP(2) <= RL_SER_MONI.txact; + DSP_DP(3) <= CTS_N; + + LED(7) <= RL_SER_MONI.abact; + LED(6 downto 2) <= (others=>'0'); + LED(1) <= STAT(1); + LED(0) <= STAT(0); + end syn;
/trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom
2,7 → 2,9
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/s3board/s3boardlib.vbom
../../../vlib/rbus/rblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/nexys2/nexys2lib.vhd
sys_conf : sys_conf.vhd
# components
9,7 → 11,8
[xst,isim]../../../vlib/xlib/dcm_sp_sfs_unisim.vbom
[ghdl]../../../vlib/xlib/dcm_sp_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/s3board/s3_rs232_iob_int_ext.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom
../tst_rlink.vbom
../../../bplib/nexys2/n2_cram_dummy.vbom
# design
/trunk/rtl/sys_gen/tst_rlink/nexys2/.cvsignore
1,3 → 1,4
_impactbatch.log
sys_tst_rlink_n2.ucf
*.dep_ucf_cpp
*.svf
/trunk/rtl/sys_gen/tst_rlink/nexys2/Makefile
1,7 → 1,8
# $Id: Makefile 351 2010-12-30 21:50:54Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-12-29 351 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
10,7 → 11,7
ISE_BOARD = nexys2
ISE_PATH = xc3s1200e-fg320-4
#
.phony : all clean
.PHONY : all clean
#
all : $(BIT_all)
#
24,8 → 25,8
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
trunk/rtl/sys_gen/tst_rlink/nexys2 Property changes : Modified: svn:ignore ## -33,3 +33,4 ## _impactbatch.log sys_tst_rlink_n2.ucf *.dep_ucf_cpp +*.svf Index: trunk/rtl/sys_gen/tst_rlink/tst_rlink.vhd =================================================================== --- trunk/rtl/sys_gen/tst_rlink/tst_rlink.vhd (revision 11) +++ trunk/rtl/sys_gen/tst_rlink/tst_rlink.vhd (revision 12) @@ -1,6 +1,6 @@ --- $Id: tst_rlink.vhd 375 2011-04-02 07:56:47Z mueller $ +-- $Id: tst_rlink.vhd 385 2011-06-26 22:10:57Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -21,7 +21,6 @@ -- rbus/rbd_rbmon -- rbus/rbd_eyemon -- rbus/rbd_timer --- s3board/s3_humanio_rbus -- rbus/rb_sres_or_4 -- -- Test bench: nexys2/tb/tb_tst_rlink_n2 @@ -31,24 +30,15 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-06-26 385 1.1 remove s3_humanio_rbus (will be in board design); +-- remove hio interface ports, add rbus ports -- 2011-04-02 375 1.0.1 add rbd_eyemon and two timer -- 2010-12-29 351 1.0 Initial version (inspired by sys_tst_rri) ------------------------------------------------------------------------------ --- Usage of Nexys 2 Switches, Buttons, LEDs: --- --- SWI(0): 0 -> main board RS232 port - implemented in sys_tst_rlink_* --- 1 -> Pmod B/top RS232 port / --- (1:7): no function (only connected to s3_humanio_rbus) --- --- LED(0): timer 0 busy --- LED(1): timer 1 busy --- LED(2:7): no function (only connected to s3_humanio_rbus) --- --- DSP: RL_SER_MONI.clkdiv (from auto bauder) --- DP(0): RXSD (inverted to signal activity) --- DP(1): RTS_N (shows rx back preasure) --- DP(2): TXSD (inverted to signal activity) --- DP(3): CTS_N (shows tx back preasure) +-- Usage of STAT signal: +-- STAT(0): timer 0 busy +-- STAT(1): timer 1 busy +-- STAT(2:7): unused library ieee; use ieee.std_logic_1164.all; @@ -58,13 +48,11 @@ use work.rblib.all; use work.rbdlib.all; use work.rlinklib.all; -use work.s3boardlib.all; -- ---------------------------------------------------------------------------- entity tst_rlink is -- tester for rlink generic ( - DEBOUNCE : boolean := true; CDINIT : natural := 15); port ( CLK : in slbit; -- clock @@ -75,26 +63,15 @@ TXD : out slbit; -- transmit data (board view) CTS_N : in slbit; -- rs232 cts_n RTS_N : out slbit; -- rs232 rts_n - SWI : out slv8; -- switches (for top cntl) - BTN : out slv4; -- buttons (for top cntl) - I_SWI : in slv8; -- s3 switches - I_BTN : in slv4; -- s3 buttons - O_LED : out slv8; -- s3 leds - O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) - O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + RB_MREQ_TOP : out rb_mreq_type; -- rbus: request to top + RB_SRES_TOP : in rb_sres_type; -- rbus: response from top + RL_SER_MONI: out rl_ser_moni_type; -- rlink monitor + STAT : out slv8 -- status flags ); end tst_rlink; architecture syn of tst_rlink is - signal RTS_N_L : slbit := '0'; - signal DSP_DAT : slv16 := (others=>'0'); - signal DSP_DP : slv4 := (others=>'0'); - - signal SWI_L : slv8 := (others=>'0'); - signal BTN_L : slv4 := (others=>'0'); - signal LED : slv8 := (others=>'0'); - signal RB_MREQ : rb_mreq_type := rb_mreq_init; signal RB_SRES : rb_sres_type := rb_sres_init; signal RB_SRES_TEST : rb_sres_type := rb_sres_init; @@ -103,7 +80,6 @@ signal RB_SRES_EMON : rb_sres_type := rb_sres_init; signal RB_SRES_TIM0 : rb_sres_type := rb_sres_init; signal RB_SRES_TIM1 : rb_sres_type := rb_sres_init; - signal RB_SRES_HIO : rb_sres_type := rb_sres_init; signal RB_SRES_SUM1 : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); @@ -117,7 +93,7 @@ signal TIM1_BUSY : slbit := '0'; signal RL_MONI : rl_moni_type := rl_moni_init; - signal RL_SER_MONI : rl_ser_moni_type := rl_ser_moni_init; + signal RL_SER_MONI_L : rl_ser_moni_type := rl_ser_moni_init; constant rbaddr_mon : slv8 := "11111100"; -- 111111xx constant rbaddr_emon : slv8 := "11111000"; -- 111110xx @@ -125,7 +101,6 @@ constant rbaddr_test : slv8 := "11110000"; -- 111100xx constant rbaddr_tim1 : slv8 := "11100001"; -- 11100001 constant rbaddr_tim0 : slv8 := "11100000"; -- 11100000 - constant rbaddr_hio : slv8 := "11000000"; -- 110000xx begin @@ -150,13 +125,13 @@ RXSD => RXD, TXSD => TXD, CTS_N => CTS_N, - RTS_N => RTS_N_L, + RTS_N => RTS_N, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES, RB_LAM => RB_LAM, RB_STAT => RB_STAT, RL_MONI => RL_MONI, - RL_SER_MONI => RL_SER_MONI + RL_SER_MONI => RL_SER_MONI_L ); RB_LAM(15 downto 2) <= RB_LAM_TEST(15 downto 2); @@ -207,7 +182,7 @@ RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_EMON, RXSD => RXD, - RXACT => RL_SER_MONI.rxact + RXACT => RL_SER_MONI_L.rxact ); TIM0 : rbd_timer @@ -236,34 +211,12 @@ BUSY => TIM1_BUSY ); - HIO : s3_humanio_rbus - generic map ( - DEBOUNCE => DEBOUNCE, - RB_ADDR => rbaddr_hio) - port map ( - CLK => CLK, - RESET => RESET, - CE_MSEC => CE_MSEC, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES_HIO, - SWI => SWI_L, - BTN => BTN_L, - LED => LED, - DSP_DAT => DSP_DAT, - DSP_DP => DSP_DP, - I_SWI => I_SWI, - I_BTN => I_BTN, - O_LED => O_LED, - O_ANO_N => O_ANO_N, - O_SEG_N => O_SEG_N - ); - RB_SRES_OR1 : rb_sres_or_4 port map ( RB_SRES_1 => RB_SRES_TEST, RB_SRES_2 => RB_SRES_BRAM, RB_SRES_3 => RB_SRES_MON, - RB_SRES_4 => RB_SRES_HIO, + RB_SRES_4 => RB_SRES_TOP, RB_SRES_OR => RB_SRES_SUM1 ); @@ -276,18 +229,11 @@ RB_SRES_OR => RB_SRES ); - DSP_DAT <= RL_SER_MONI.clkdiv; - DSP_DP(0) <= RL_SER_MONI.rxact; - DSP_DP(1) <= RTS_N_L; - DSP_DP(2) <= RL_SER_MONI.txact; - DSP_DP(3) <= CTS_N; + RB_MREQ_TOP <= RB_MREQ; + RL_SER_MONI <= RL_SER_MONI_L; - LED(0) <= TIM0_BUSY; - LED(1) <= TIM1_BUSY; - LED(7) <= RL_SER_MONI.abact; - - RTS_N <= RTS_N_L; - SWI <= SWI_L; - BTN <= BTN_L; - + STAT(0) <= TIM0_BUSY; + STAT(1) <= TIM1_BUSY; + STAT(7 downto 2) <= (others=>'0'); + end syn;
/trunk/rtl/sys_gen/tst_rlink/tst_rlink.vbom
3,7 → 3,6
../../vlib/rbus/rblib.vhd
../../vlib/rbus/rbdlib.vhd
../../vlib/rlink/rlinklib.vbom
../../bplib/s3board/s3boardlib.vhd
# components
../../vlib/rlink/rlink_base_serport.vbom
../../vlib/rbus/rbd_tester.vbom
11,7 → 10,6
../../vlib/rbus/rbd_rbmon.vbom
../../vlib/rbus/rbd_eyemon.vbom
../../vlib/rbus/rbd_timer.vbom
../../bplib/s3board/s3_humanio_rbus.vbom
../../vlib/rbus/rb_sres_or_4.vbom
# design
tst_rlink.vhd
/trunk/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.mfset
0,0 → 1,148
# $Id: sys_w11a_n2.mfset 406 2011-08-14 21:06:44Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
INFO:.*You can improve the performance of the multiplier
 
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_boot> of sequential type is unconnected
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_lock> of sequential type is unconnected
Node <CORE/VMBOX/R_REGS.ibcacc> of sequential type is unconnected
Node <HIO/R_REGS.swieff_\d*> of sequential type is unconnected
Node <HIO/R_REGS.btneff_\d*> of sequential type is unconnected
Node <HIO/R_REGS.swi_\d*> of sequential type is unconnected
Node <HIO/R_REGS.btn_\d*> of sequential type is unconnected
Node <MEM_SRAM.SRAM_CTL/R_REGS.addr0> of sequential type is unconnected
 
Unconnected output port 'LOCKED' of component 'dcm_sp_sfs'
Unconnected output port 'RL_MONI' of component 'rlink_base_serport'
Unconnected output port 'RL_SER_MONI' of component 'rlink_base_serport'
Unconnected output port 'ACK_W' of component 'n2_cram_memctl_as'
Unconnected output port 'OFIFO_SIZE' of component 'rlink_base'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen'
 
Input <CP_STAT.cpuwait> is never used
Input <CP_STAT.cmdbusy> is never used
Input <IB_MREQ.cacc> is never used
Input <IB_MREQ.rmw> is never used
Input <IB_MREQ.din<\d*:\d*>> is never used
Input <IB_MREQ.din<\d*>> is never used
Input <IB_MREQ.racc> is never used
Input <IB_MREQ.be0> is never used
Input <IB_MREQ.be1> is never used
Input <IB_MREQ.din> is never used
Input <IB_MREQ.re> is never used
Input <IB_MREQ.we> is never used
Input <IB_MREQ.addr<\d*:\d*>> is never used
Input <CCIN<2:1>> is never used
Input <EI_ACK> is never used
Input <IREG<\d*:\d*>> is never used
Input <MONI.idone> is never used
Input <MONI.trace_prev> is never used
Input <DIN<\d*:\d*>> is never used
Input <I_MEM_WAIT> is never used
Input <RB_MREQ.init> is never used
Input <RB_MREQ.din<\d*:\d*>> is never used
Input <RB_MREQ.aval> is never used
Input <RB_MREQ.re> is never used
Input <CNTL.trap_done> is never used
Input <VADDR<\d*:\d*>> is never used
 
Signal <R_VMSTAT.trap_ysv> is assigned but never used
Signal <R_VMSTAT.trap_mmu> is assigned but never used
Signal <R_VMSTAT.ack> is assigned but never used
Signal <R_IDSTAT.is_res> is assigned but never used
Signal <R_IDSTAT.fork_srcr> is assigned but never used
Signal <R_IDSTAT.fork_op> is assigned but never used
Signal <R_IDSTAT.force_srcsp> is assigned but never used
Signal <R_IDSTAT.do_pref_dec> is assigned but never used
Signal <R_IDSTAT.do_fork_srcr> is assigned but never used
Signal <R_IDSTAT.do_fork_opg> is assigned but never used
Signal <R_IDSTAT.do_fork_op> is assigned but never used
Signal <R_IDSTAT.do_fork_dsta> is assigned but never used
 
Signal <DM_STAT_VM.ibsres.dout> is assigned but never used
Signal <DM_STAT_VM.ibsres.busy> is assigned but never used
Signal <DM_STAT_VM.ibsres.ack> is assigned but never used
Signal <DM_STAT_VM.ibmreq.we> is assigned but never used
Signal <DM_STAT_VM.ibmreq.rmw> is assigned but never used
Signal <DM_STAT_VM.ibmreq.re> is assigned but never used
Signal <DM_STAT_VM.ibmreq.racc> is assigned but never used
Signal <DM_STAT_VM.ibmreq.din> is assigned but never used
Signal <DM_STAT_VM.ibmreq.cacc> is assigned but never used
Signal <DM_STAT_VM.ibmreq.be1> is assigned but never used
Signal <DM_STAT_VM.ibmreq.be0> is assigned but never used
Signal <DM_STAT_VM.ibmreq.aval> is assigned but never used
Signal <DM_STAT_VM.ibmreq.addr> is assigned but never used
Signal <DM_STAT_DP.psw.tflag> is assigned but never used
Signal <DM_STAT_DP.psw.rset> is assigned but never used
Signal <DM_STAT_DP.psw.pmode> is assigned but never used
Signal <DM_STAT_DP.psw.cc> is assigned but never used
Signal <DM_STAT_DP.pc> is assigned but never used
Signal <DM_STAT_DP.ireg_we> is assigned but never used
Signal <DM_STAT_DP.ireg> is assigned but never used
Signal <DM_STAT_DP.gpr_we> is assigned but never used
Signal <DM_STAT_DP.gpr_mode> is assigned but never used
Signal <DM_STAT_DP.gpr_bytop> is assigned but never used
Signal <DM_STAT_DP.gpr_adst> is assigned but never used
Signal <DM_STAT_DP.dtmp> is assigned but never used
Signal <DM_STAT_DP.dsrc> is assigned but never used
Signal <DM_STAT_DP.dres> is assigned but never used
Signal <DM_STAT_DP.ddst> is assigned but never used
Signal <DM_STAT_CO.cpuhalt> is assigned but never used
Signal <DM_STAT_CO.cpugo> is assigned but never used
 
Signal <IIST_MREQ.lock> is assigned but never used
Signal <IIST_MREQ.boot> is assigned but never used
 
Signal <EI_ACK_RL11> is assigned but never used
Signal <EI_ACK_KW11P> is assigned but never used
Signal <EI_ACK_DZ11TX> is assigned but never used
Signal <EI_ACK_DZ11RX> is assigned but never used
Signal <EI_ACK<\d*>> is assigned but never used
 
Signal <SIZE<\d*:\d*>> is assigned but never used
Signal <SWI<\d*:\d*>> is assigned but never used
Signal <BTN> is assigned but never used
 
FF/Latch <R_REGS.dcf_brk_1> in Unit <ibd_iist> is equivalent
FF/Latch <R_REGS.paddr_iopage_\d*> in Unit <pdp11_vmbox> is equivalent
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent
FF/Latch <MEM_SRAM.SRAM_CTL/R_REGS.memdi_\d*> in Unit <sys_w11a_n2> is equivalent
FF/Latch <CORE/SEQ/R_IDSTAT.aunit_srcmod_\d*> in Unit <sys_w11a_n2> is equivalent
FF/Latch <CORE/SEQ/R_IDSTAT.fork_dsta_\d*> in Unit <sys_w11a_n2> is equivalent
FF/Latch <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.dcf_brk_\d*> in Unit <sys_w11a_n2> is equivalent
 
FF/Latch <R_SSR0.inst_compl> has a constant value of 0
FF/Latch <MEM_SRAM.SRAM_CTL/R_REGS.cntdly_\d*> has a constant value of 0
FF/Latch <RLINK/BASE/RL/R_REGS.attn_\d*> has a constant value
FF/Latch <MEM_SRAM.SRAM_CTL/IOB_MEM_ADDRH/R_DO_\d*> has a constant value of 0
FF/Latch <CORE/SEQ/R_STATUS.intvect_8> has a constant value of 0
FF/Latch <CORE/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0
 
#
# ----------------------------------------------------------------------------
[tra]
INFO:.*TNM.*used in period specification.*was traced into DCM_SP
 
#
# ----------------------------------------------------------------------------
[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
Logical network I_MEM_WAIT_IBUF has no load
There is a dangling output parity pin
INFO:.*
 
#
# ----------------------------------------------------------------------------
[par]
The signal I_MEM_WAIT_IBUF has no load
There are 1 loadless signals in this design
#
# ----------------------------------------------------------------------------
[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
The signal <I_MEM_WAIT_IBUF> is incomplete
There is a dangling output parity pin
INFO:.*To achieve optimal frequency synthesis performance
/trunk/rtl/sys_gen/w11a/nexys2/tb/Makefile
1,7 → 1,8
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-26 295 1.0 Initial version
#
EXE_all = tb_w11a_n2
9,7 → 10,7
ISE_PATH = xc3s1200e-fg320-4
#
#
.phony : all all_ssim all_tsim clean
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
19,8 → 20,8
#
#-----
#
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
/trunk/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
1,6 → 1,6
-- $Id: sys_w11a_n2.vhd 351 2010-12-30 21:50:54Z mueller $
-- $Id: sys_w11a_n2.vhd 404 2011-08-07 22:00:25Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
17,8 → 17,8
--
-- Dependencies: vlib/xlib/dcm_sp_sfs
-- vlib/genlib/clkdivce
-- bplib/s3board/s3_rs232_iob_int_ext
-- bplib/s3board/s3_humanio_rbus
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_base_serport
-- vlib/rri/rb_sres_or_3
-- w11a/pdp11_core_rbus
33,7 → 33,7
-- ibus/ibdr_maxisys
-- w11a/pdp11_tmu_sb [sim only]
--
-- Test bench: tb/tb_s3board_w11a_n2
-- Test bench: tb/tb_sys_w11a_n2
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1; ghdl 0.26-0.29
62,6 → 62,8
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-09 391 1.2.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.2.1 use now sn_humanio
-- 2010-12-30 351 1.2 ported to rbv3
-- 2010-11-27 341 1.1.8 add DCM; new sys_conf consts for mem and clkdiv
-- 2010-11-13 338 1.1.7 add O_CLKSYS (for DCM derived system clock)
116,7 → 118,7
use work.genlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.s3boardlib.all;
use work.bpgenlib.all;
use work.nexys2lib.all;
use work.iblib.all;
use work.ibdlib.all;
263,9 → 265,10
CE_MSEC => CE_MSEC
);
 
IOB_RS232 : s3_rs232_iob_int_ext
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
279,7 → 282,7
O_RTS1_N => O_FUSP_RTS_N
);
 
HIO : s3_humanio_rbus
HIO : sn_humanio_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
/trunk/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom
4,7 → 4,7
../../../vlib/genlib/genlib.vhd
../../../vlib/rbus/rblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/s3board/s3boardlib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/nexys2/nexys2lib.vhd
../../../ibus/iblib.vhd
../../../ibus/ibdlib.vhd
14,8 → 14,8
[xst,isim]../../../vlib/xlib/dcm_sp_sfs_unisim.vbom
[ghdl]../../../vlib/xlib/dcm_sp_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/s3board/s3_rs232_iob_int_ext.vbom
../../../bplib/s3board/s3_humanio_rbus.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom
../../../vlib/rlink/rlink_base_serport.vbom
../../../vlib/rbus/rb_sres_or_3.vbom
../../../w11a/pdp11_core_rbus.vbom
/trunk/rtl/sys_gen/w11a/nexys2/Makefile
1,7 → 1,8
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-28 295 1.0 Initial version (derived from _s3 version)
#
VBOM_all = $(wildcard *.vbom)
10,7 → 11,7
ISE_BOARD = nexys2
ISE_PATH = xc3s1200e-fg320-4
#
.phony : all clean
.PHONY : all clean
#
all : $(BIT_all)
#
24,8 → 25,8
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
/trunk/rtl/sys_gen/w11a/s3board/tb/Makefile
1,7 → 1,8
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.3 use includes from rtl/make
# 2010-05-26 295 1.2 rename tb_s3board_pdp11core -> tb_w11a_s3
# 2007-11-26 98 1.1 add all_ssim and all_tsim targets
# 2007-09-23 84 1.0 Initial version
11,7 → 12,7
ISE_PATH = xc3s1000-ft256-4
#
#
.phony : all all_ssim all_tsim clean
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
21,8 → 22,8
#
#-----
#
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
/trunk/rtl/sys_gen/w11a/s3board/sys_w11a_s3.mfset
0,0 → 1,133
# $Id: sys_w11a_s3.mfset 406 2011-08-14 21:06:44Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
 
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_boot> of sequential type is unconnected
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_lock> of sequential type is unconnected
Node <CORE/VMBOX/R_REGS.ibcacc> of sequential type is unconnected
Node <CORE/SEQ/R_STATUS.cpuwait> of sequential type is unconnected
 
Unconnected output port 'RL_MONI' of component 'rlink_base_serport'
Unconnected output port 'RL_SER_MONI' of component 'rlink_base_serport'
Unconnected output port 'OFIFO_SIZE' of component 'rlink_base'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen'
Unconnected output port 'ACK_W' of component 's3_sram_memctl'
Unconnected output port 'ACT_R' of component 's3_sram_memctl'
Unconnected output port 'ACT_W' of component 's3_sram_memctl'
 
Input <CP_STAT.cpuwait> is never used
Input <CP_STAT.cmdbusy> is never used
Input <IB_MREQ.cacc> is never used
Input <IB_MREQ.rmw> is never used
Input <IB_MREQ.din<\d*:\d*>> is never used
Input <IB_MREQ.din<\d*>> is never used
Input <IB_MREQ.racc> is never used
Input <IB_MREQ.be0> is never used
Input <IB_MREQ.be1> is never used
Input <IB_MREQ.din> is never used
Input <IB_MREQ.re> is never used
Input <IB_MREQ.we> is never used
Input <IB_MREQ.addr<\d*:\d*>> is never used
Input <CCIN<2:1>> is never used
Input <EI_ACK> is never used
Input <IREG<\d*:\d*>> is never used
Input <MONI.idone> is never used
Input <MONI.trace_prev> is never used
Input <DIN<\d*:\d*>> is never used
Input <RB_MREQ.din<\d*:\d*>> is never used
Input <RB_MREQ.aval> is never used
Input <RB_MREQ.re> is never used
Input <CNTL.trap_done> is never used
Input <VADDR<\d*:\d*>> is never used
 
Signal <R_VMSTAT.trap_ysv> is assigned but never used
Signal <R_VMSTAT.trap_mmu> is assigned but never used
Signal <R_VMSTAT.ack> is assigned but never used
Signal <R_IDSTAT.is_res> is assigned but never used
Signal <R_IDSTAT.fork_srcr> is assigned but never used
Signal <R_IDSTAT.fork_op> is assigned but never used
Signal <R_IDSTAT.force_srcsp> is assigned but never used
Signal <R_IDSTAT.do_pref_dec> is assigned but never used
Signal <R_IDSTAT.do_fork_srcr> is assigned but never used
Signal <R_IDSTAT.do_fork_opg> is assigned but never used
Signal <R_IDSTAT.do_fork_op> is assigned but never used
Signal <R_IDSTAT.do_fork_dsta> is assigned but never used
 
Signal <DM_STAT_VM.ibsres.dout> is assigned but never used
Signal <DM_STAT_VM.ibsres.busy> is assigned but never used
Signal <DM_STAT_VM.ibsres.ack> is assigned but never used
Signal <DM_STAT_VM.ibmreq.we> is assigned but never used
Signal <DM_STAT_VM.ibmreq.rmw> is assigned but never used
Signal <DM_STAT_VM.ibmreq.re> is assigned but never used
Signal <DM_STAT_VM.ibmreq.racc> is assigned but never used
Signal <DM_STAT_VM.ibmreq.din> is assigned but never used
Signal <DM_STAT_VM.ibmreq.cacc> is assigned but never used
Signal <DM_STAT_VM.ibmreq.be1> is assigned but never used
Signal <DM_STAT_VM.ibmreq.be0> is assigned but never used
Signal <DM_STAT_VM.ibmreq.aval> is assigned but never used
Signal <DM_STAT_VM.ibmreq.addr> is assigned but never used
Signal <DM_STAT_DP.psw.tflag> is assigned but never used
Signal <DM_STAT_DP.psw.rset> is assigned but never used
Signal <DM_STAT_DP.psw.pmode> is assigned but never used
Signal <DM_STAT_DP.psw.cc> is assigned but never used
Signal <DM_STAT_DP.pc> is assigned but never used
Signal <DM_STAT_DP.ireg_we> is assigned but never used
Signal <DM_STAT_DP.ireg> is assigned but never used
Signal <DM_STAT_DP.gpr_we> is assigned but never used
Signal <DM_STAT_DP.gpr_mode> is assigned but never used
Signal <DM_STAT_DP.gpr_bytop> is assigned but never used
Signal <DM_STAT_DP.gpr_adst> is assigned but never used
Signal <DM_STAT_DP.dtmp> is assigned but never used
Signal <DM_STAT_DP.dsrc> is assigned but never used
Signal <DM_STAT_DP.dres> is assigned but never used
Signal <DM_STAT_DP.ddst> is assigned but never used
Signal <DM_STAT_DP.psw.pri> is assigned but never used
Signal <DM_STAT_DP.psw.cmode> is assigned but never used
Signal <DM_STAT_CO.cpuhalt> is assigned but never used
Signal <DM_STAT_CO.cpugo> is assigned but never used
 
Signal <IIST_MREQ.lock> is assigned but never used
Signal <IIST_MREQ.boot> is assigned but never used
 
Signal <EI_ACK_RL11> is assigned but never used
Signal <EI_ACK_KW11P> is assigned but never used
Signal <EI_ACK_DZ11TX> is assigned but never used
Signal <EI_ACK_DZ11RX> is assigned but never used
Signal <EI_ACK<\d*>> is assigned but never used
 
Signal <SIZE<\d*:\d*>> is assigned but never used
Signal <MEM_ADDR<\d*:\d*>> is assigned but never used
 
FF/Latch <R_REGS.dcf_brk_1> in Unit <ibd_iist> is equivalent
FF/Latch <R_REGS.paddr_iopage_\d*> in Unit <pdp11_vmbox> is equivalent
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent
FF/Latch <CORE/SEQ/R_IDSTAT.fork_dsta_\d*> in Unit <sys_w11a_s3> is equivalent
FF/Latch <CORE/SEQ/R_IDSTAT.aunit_srcmod_\d*> in Unit <sys_w11a_s3> is equivalent
FF/Latch <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.dcf_brk_\d*> in Unit <sys_w11a_s3> is equivalent
 
FF/Latch <R_SSR0.inst_compl> has a constant value of 0
FF/Latch <RLINK/BASE/RL/R_REGS.attn_\d*> has a constant value
FF/Latch <CORE/SEQ/R_STATUS.intvect_8> has a constant value of 0
FF/Latch <CORE/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0
 
#
# ----------------------------------------------------------------------------
[tra]
 
#
# ----------------------------------------------------------------------------
[map]
There is a dangling output parity pin
INFO:.*
 
#
# ----------------------------------------------------------------------------
[par]
 
#
# ----------------------------------------------------------------------------
[bgn]
There is a dangling output parity pin
/trunk/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
1,6 → 1,6
-- $Id: sys_w11a_s3.vhd 351 2010-12-30 21:50:54Z mueller $
-- $Id: sys_w11a_s3.vhd 404 2011-08-07 22:00:25Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
16,8 → 16,8
-- Description: w11a test design for s3board
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/s3board/s3_rs232_iob_int_ext
-- bplib/s3board/s3_humanio
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio
-- vlib/rlink/rlink_base_serport
-- vlib/rbus/rb_sres_or_2
-- w11a/pdp11_core_rbus
32,7 → 32,7
-- ibus/ibdr_maxisys
-- w11a/pdp11_tmu_sb [sim only]
--
-- Test bench: tb/tb_s3board_w11a_s3
-- Test bench: tb/tb_sys_w11a_s3
--
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 11.4, 12.1; ghdl 0.18-0.29
71,6 → 71,8
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-09 391 1.4.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.4.1 use now sn_humanio
-- 2010-12-30 351 1.4 ported to rbv3
-- 2010-11-06 336 1.3.7 rename input pin CLK -> I_CLK50
-- 2010-10-23 335 1.3.3 rename RRI_LAM->RB_LAM;
133,6 → 135,7
use work.genlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.s3boardlib.all;
use work.iblib.all;
use work.ibdlib.all;
253,9 → 256,10
CE_MSEC => CE_MSEC
);
 
IOB_RS232 : s3_rs232_iob_int_ext
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
269,7 → 273,7
O_RTS1_N => O_FUSP_RTS_N
);
 
HIO : s3_humanio
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
/trunk/rtl/sys_gen/w11a/s3board/Makefile
1,7 → 1,8
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.2 use includes from rtl/make
# 2010-05-28 295 1.1.4 rename sys_pdp11core -> sys_w11a_s3
# 2010-04-24 282 1.1.3 use %.impact rule, all=BIT_all now
# 2009-11-20 251 1.1.2 add .mcs rule
15,7 → 16,7
ISE_BOARD = s3board
ISE_PATH = xc3s1000-ft256-4
#
.phony : all clean
.PHONY : all clean
#
all : $(BIT_all)
#
29,8 → 30,8
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
/trunk/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom
3,6 → 3,7
../../../vlib/genlib/genlib.vhd
../../../vlib/rbus/rblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/s3board/s3boardlib.vbom
../../../ibus/iblib.vhd
../../../ibus/ibdlib.vhd
10,8 → 11,8
sys_conf = sys_conf.vhd
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/s3board/s3_rs232_iob_int_ext.vbom
../../../bplib/s3board/s3_humanio.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio.vbom
../../../vlib/rlink/rlink_base_serport.vbom
../../../vlib/rbus/rb_sres_or_2.vbom
../../../w11a/pdp11_core_rbus.vbom
/trunk/rtl/bplib/issi/Makefile
1,17 → 1,18
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2007-12-14 101 1.0 Initial version
#
#
.phony : clean
.PHONY : clean
#
clean : ghdl_clean
#
#-----
#
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
VBOM_all = $(wildcard *.vbom)
#
/trunk/rtl/bplib/nexys2/nexys2lib.vhd
1,4 → 1,4
-- $Id: nexys2lib.vhd 338 2010-11-13 22:19:25Z mueller $
-- $Id: nexys2lib.vhd 389 2011-07-07 21:59:00Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
54,7 → 54,7
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
138,4 → 138,4
);
end component;
 
end nexys2lib;
end package nexys2lib;
/trunk/rtl/bplib/nexys2/tb/Makefile
1,7 → 1,8
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-30 297 1.0.2 use tb_n2_cram_memctl_as now
# 2010-05-28 295 1.0.1 add tb_.._dummy's
# 2007-09-23 84 1.0 Initial version
10,7 → 11,7
#
ISE_PATH = xc3s1200e-fg320-4
#
.phony : all all_ssim all_tsim clean
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
20,9 → 21,9
#
#-----
#
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
include $(RETROBASE)/rtl/vlib/Makefile.isim
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_isim.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
/trunk/rtl/bplib/nexys2/Makefile
1,7 → 1,8
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-23 293 1.0 Initial version (cloned..)
#
VBOM_all = $(wildcard *.vbom)
9,7 → 10,7
#
ISE_PATH = xc3s1200e-fg320-4
#
.phony : all clean
.PHONY : all clean
#
all : $(NGC_all)
#
17,7 → 18,7
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#
/trunk/rtl/bplib/nexys2/nexys2_pins.ucf
1,9 → 1,9
## $Id: nexys2_pins.ucf 338 2010-11-13 22:19:25Z mueller $
## $Id: nexys2_pins.ucf 402 2011-08-05 18:56:44Z mueller $
##
## Pin locks for Nexys 2 core functionality (for 1200k FPGA)
## internal RS232
## human I/O (switches, buttons, leds, display)
## cram
## - internal RS232
## - human I/O (switches, buttons, leds, display)
## - cram
##
## Revision History:
## Date Rev Version Comment
/trunk/rtl/bplib/bpgen/bp_rs232_2line_iob.vbom
0,0 → 1,8
# libs
../../vlib/slvtypes.vhd
../../vlib/xlib/xlib.vhd
# components
../../vlib/xlib/iob_reg_i.vbom
../../vlib/xlib/iob_reg_o.vbom
# design
bp_rs232_2line_iob.vhd
/trunk/rtl/bplib/bpgen/sn_humanio.vhd
0,0 → 1,118
-- $Id: sn_humanio.vhd 403 2011-08-06 17:36:22Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio - syn
-- Description: All BTN, SWI, LED and DSP handling for s3board, nexys2/3
--
-- Dependencies: xlib/iob_reg_o_gen
-- bpgen/bp_swibtnled
-- bpgen/sn_4x7segctl
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-07-02 387 12.1 M53d xc3s1000-4 48 87 0 53 s 5.1 ns
-- 2010-04-10 275 11.4 L68 xc3s1000-4 48 87 0 53 s 5.2 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-30 400 1.2.1 use CDWIDTH=7 for sn_4x7segctl (for 100 MHz)
-- 2011-07-08 390 1.2 renamed from s3_humanio, add BWIDTH generic
-- 2011-07-02 387 1.1.2 use bp_swibtnled
-- 2010-04-17 278 1.1.1 rename dispdrv -> s3_dispdrv
-- 2010-04-11 276 1.1 instantiate BTN/SWI debouncers via DEBOUNCE generic
-- 2010-04-10 275 1.0 Initial version
------------------------------------------------------------------------------
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.xlib.all;
use work.bpgenlib.all;
 
-- ----------------------------------------------------------------------------
 
entity sn_humanio is -- human i/o handling: swi,btn,led,dsp
generic (
BWIDTH : positive := 4; -- BTN port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end sn_humanio;
 
architecture syn of sn_humanio is
signal N_ANO_N : slv4 := (others=>'0');
signal N_SEG_N : slv8 := (others=>'0');
begin
 
IOB_ANO_N : iob_reg_o_gen
generic map (DWIDTH => 4)
port map (CLK => CLK, CE => '1', DO => N_ANO_N, PAD => O_ANO_N);
IOB_SEG_N : iob_reg_o_gen
generic map (DWIDTH => 8)
port map (CLK => CLK, CE => '1', DO => N_SEG_N, PAD => O_SEG_N);
 
HIO : bp_swibtnled
generic map (
SWIDTH => 8,
BWIDTH => BWIDTH,
LWIDTH => 8,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
 
DRV : sn_4x7segctl
generic map (
CDWIDTH => 7) -- 7 good for 100 MHz on nexys2
port map (
CLK => CLK,
DIN => DSP_DAT,
DP => DSP_DP,
ANO_N => N_ANO_N,
SEG_N => N_SEG_N
);
end syn;
/trunk/rtl/bplib/bpgen/bp_rs232_4line_iob.vbom
0,0 → 1,8
# libs
../../vlib/slvtypes.vhd
../../vlib/xlib/xlib.vhd
# components
../../vlib/xlib/iob_reg_i.vbom
../../vlib/xlib/iob_reg_o.vbom
# design
bp_rs232_4line_iob.vhd
/trunk/rtl/bplib/bpgen/bpgenlib.vbom
0,0 → 1,4
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
bpgenlib.vhd
/trunk/rtl/bplib/bpgen/bp_rs232_2l4l_iob.vbom
0,0 → 1,8
# libs
../../vlib/slvtypes.vhd
bpgenlib.vbom
# components
bp_rs232_2line_iob.vbom
bp_rs232_4line_iob.vbom
# design
bp_rs232_2l4l_iob.vhd
/trunk/rtl/bplib/bpgen/sn_4x7segctl.vbom
0,0 → 1,5
# libs
../../vlib/slvtypes.vhd
# components
# design
sn_4x7segctl.vhd
/trunk/rtl/bplib/bpgen/bp_swibtnled.vhd
0,0 → 1,117
-- $Id: bp_swibtnled.vhd 403 2011-08-06 17:36:22Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: bp_swibtnled - syn
-- Description: Generic SWI, BTN and LED handling
--
-- Dependencies: xlib/iob_reg_i_gen
-- xlib/iob_reg_o_gen
-- genlib/debounce_gen
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-01 386 1.0 Initial version, extracted from s3_humanio
------------------------------------------------------------------------------
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
 
-- ----------------------------------------------------------------------------
 
entity bp_swibtnled is -- generic SWI, BTN and LED handling
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
);
end bp_swibtnled;
 
architecture syn of bp_swibtnled is
signal RI_SWI : slv(SWIDTH-1 downto 0) := (others=>'0');
signal RI_BTN : slv(BWIDTH-1 downto 0) := (others=>'0');
 
begin
 
IOB_SWI : iob_reg_i_gen
generic map (DWIDTH => SWIDTH)
port map (CLK => CLK, CE => '1', DI => RI_SWI, PAD => I_SWI);
IOB_BTN : iob_reg_i_gen
generic map (DWIDTH => BWIDTH)
port map (CLK => CLK, CE => '1', DI => RI_BTN, PAD => I_BTN);
IOB_LED : iob_reg_o_gen
generic map (DWIDTH => LWIDTH)
port map (CLK => CLK, CE => '1', DO => LED, PAD => O_LED);
DEB: if DEBOUNCE generate
 
DEB_SWI : debounce_gen
generic map (
CWIDTH => 2,
CEDIV => 3,
DWIDTH => SWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CE_INT => CE_MSEC,
DI => RI_SWI,
DO => SWI
);
 
DEB_BTN : debounce_gen
generic map (
CWIDTH => 2,
CEDIV => 3,
DWIDTH => BWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CE_INT => CE_MSEC,
DI => RI_BTN,
DO => BTN
);
end generate DEB;
 
NODEB: if not DEBOUNCE generate
SWI <= RI_SWI;
BTN <= RI_BTN;
end generate NODEB;
end syn;
/trunk/rtl/bplib/bpgen/sn_humanio_rbus.vbom
0,0 → 1,8
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
bpgenlib.vbom
# components
sn_humanio.vbom
# design
sn_humanio_rbus.vhd
/trunk/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd
0,0 → 1,63
-- $Id: bp_rs232_2line_iob.vhd 387 2011-07-03 17:24:52Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_2line_iob - syn
-- Description: iob's for 2 line rs232 (RXD,TXD only)
--
-- Dependencies: xlib/iob_reg_i
-- xlib/iob_reg_o
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-01 386 1.1 Moved and renamed to bpgen
-- 2010-04-17 278 1.0 Initial version (as s3_rs232_iob_int)
------------------------------------------------------------------------------
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.xlib.all;
 
-- ----------------------------------------------------------------------------
 
entity bp_rs232_2line_iob is -- iob's for 2 line rs232 (RXD,TXD)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit -- pad-o: transmit data (board view)
);
end bp_rs232_2line_iob;
 
architecture syn of bp_rs232_2line_iob is
begin
 
IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD);
IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD);
 
end syn;
/trunk/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd
0,0 → 1,73
-- $Id: bp_rs232_4line_iob.vhd 391 2011-07-09 17:25:02Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_4line_iob - syn
-- Description: iob's for 4 line rs232 (RXD,TXD and RTS,CTS)
--
-- Dependencies: xlib/iob_reg_i
-- xlib/iob_reg_o
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-01 386 1.1 moved and renamed to bpgen
-- 2010-04-17 278 1.0 Initial version (as s3_rs232_iob_ext)
------------------------------------------------------------------------------
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.xlib.all;
 
-- ----------------------------------------------------------------------------
 
entity bp_rs232_4line_iob is -- iob's for 4 line rs232 (w/ RTS,CTS)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit; -- pad-o: transmit data (board view)
I_CTS_N : in slbit; -- pad-i: clear to send (act. low)
O_RTS_N : out slbit -- pad-o: request to send (act. low)
);
end bp_rs232_4line_iob;
 
architecture syn of bp_rs232_4line_iob is
begin
 
IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD);
IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD);
 
IOB_CTS : iob_reg_i
port map (CLK => CLK, CE => '1', DI => CTS_N, PAD => I_CTS_N);
IOB_RTS : iob_reg_o
port map (CLK => CLK, CE => '1', DO => RTS_N, PAD => O_RTS_N);
end syn;
/trunk/rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd
0,0 → 1,187
-- $Id: bp_rs232_2l4l_iob.vhd 406 2011-08-14 21:06:44Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_2l4l_iob - syn
-- Description: iob's for internal + external rs232, with select
--
-- Dependencies: bp_rs232_2line_iob
-- bp_rs232_4line_iob
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.2.2 fix mistake in tx and rts relay
-- 2011-08-07 404 1.2.1 add RELAY generic and a relay stage towards IOB's
-- 2011-08-06 403 1.2 add pipeline flops; add RESET signal
-- 2011-07-09 391 1.1 moved and renamed to bpgen
-- 2011-07-02 387 1.0.1 use bp_rs232_[24]line_iob now
-- 2010-04-17 278 1.0 Initial version
------------------------------------------------------------------------------
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.bpgenlib.all;
 
-- ----------------------------------------------------------------------------
 
entity bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end bp_rs232_2l4l_iob;
 
architecture syn of bp_rs232_2l4l_iob is
signal RXD0 : slbit := '0';
signal RXD1 : slbit := '0';
signal CTS1_N : slbit := '0';
 
signal R_RXD : slbit := '1';
signal R_CTS_N : slbit := '0';
signal R_TXD0 : slbit := '1';
signal R_TXD1 : slbit := '1';
signal R_RTS1_N : slbit := '0';
 
signal RR_RXD0 : slbit := '1';
signal RR_TXD0 : slbit := '1';
signal RR_RXD1 : slbit := '1';
signal RR_TXD1 : slbit := '1';
signal RR_CTS1_N : slbit := '0';
signal RR_RTS1_N : slbit := '0';
 
begin
 
-- On Digilent Atlys bords the IOBs for P0 and P1 are on diagonally opposide
-- corners of the die, which causes very long (7-8ns) routing delays to a LUT
-- in the middle. The RELAY generic allows to add 'relay flops' between IOB
-- flops and the mux implented in proc_regs_mux.
--
-- The data flow is
-- iob-flop relay-flop if-flop port
-- RXD0 -> RR_RXD0 -> R_RXD -> RXD
-- TXD0 <- RR_TXD0 <- R_TXD0 <- TXD
-- RXD1 -> RR_RXD1 -> R_RXD -> RXD
-- TXD1 <- RR_TXD1 <- R_TXD1 <- TXD
-- CTS1_N -> RR_CTS1_N -> R_CTS_N -> CTS
-- RTS1_N <- RR_RTS1_N <- R_RTS1_N <- RTS
P0 : bp_rs232_2line_iob
port map (
CLK => CLK,
RXD => RXD0,
TXD => RR_TXD0,
I_RXD => I_RXD0,
O_TXD => O_TXD0
);
 
P1 : bp_rs232_4line_iob
port map (
CLK => CLK,
RXD => RXD1,
TXD => RR_TXD1,
CTS_N => CTS1_N,
RTS_N => RR_RTS1_N,
I_RXD => I_RXD1,
O_TXD => O_TXD1,
I_CTS_N => I_CTS1_N,
O_RTS_N => O_RTS1_N
);
 
DORELAY : if RELAY generate
proc_regs_pipe: process (CLK)
begin
if CLK'event and CLK='1' then
if RESET = '1' then
RR_RXD0 <= '1';
RR_TXD0 <= '1';
RR_RXD1 <= '1';
RR_TXD1 <= '1';
RR_CTS1_N <= '0';
RR_RTS1_N <= '0';
else
RR_RXD0 <= RXD0;
RR_TXD0 <= R_TXD0;
RR_RXD1 <= RXD1;
RR_TXD1 <= R_TXD1;
RR_CTS1_N <= CTS1_N;
RR_RTS1_N <= R_RTS1_N;
end if;
end if;
end process proc_regs_pipe;
end generate DORELAY;
 
NORELAY : if not RELAY generate
RR_RXD0 <= RXD0;
RR_TXD0 <= R_TXD0;
RR_RXD1 <= RXD1;
RR_TXD1 <= R_TXD1;
RR_CTS1_N <= CTS1_N;
RR_RTS1_N <= R_RTS1_N;
end generate NORELAY;
 
proc_regs_mux: process (CLK)
begin
 
if CLK'event and CLK='1' then
if RESET = '1' then
R_RXD <= '1';
R_CTS_N <= '0';
R_TXD0 <= '1';
R_TXD1 <= '1';
R_RTS1_N <= '0';
else
if SEL = '0' then -- use 2-line rs232, no flow cntl
R_RXD <= RR_RXD0; -- get port 0 inputs
R_CTS_N <= '0';
R_TXD0 <= TXD; -- set port 0 output
R_TXD1 <= '1'; -- port 1 outputs to idle state
R_RTS1_N <= '0';
else -- otherwise use 4-line rs232
R_RXD <= RR_RXD1; -- get port 1 inputs
R_CTS_N <= RR_CTS1_N;
R_TXD0 <= '1'; -- port 0 output to idle state
R_TXD1 <= TXD; -- set port 1 outputs
R_RTS1_N <= RTS_N;
end if;
end if;
end if;
 
end process proc_regs_mux;
RXD <= R_RXD;
CTS_N <= R_CTS_N;
end syn;
/trunk/rtl/bplib/bpgen/sn_humanio.vbom
0,0 → 1,11
# libs
../../vlib/slvtypes.vhd
../../vlib/xlib/xlib.vhd
bpgenlib.vbom
## sys_conf : sys_conf.vhd
# components
../../vlib/xlib/iob_reg_o_gen.vbom
bp_swibtnled.vbom
sn_4x7segctl.vbom
# design
sn_humanio.vhd
/trunk/rtl/bplib/bpgen/bpgenlib.vhd
0,0 → 1,180
-- $Id: bpgenlib.vhd 404 2011-08-07 22:00:25Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: bpliblib
-- Description: Generic Board/Part components
--
-- Dependencies: -
-- Tool versions: 12.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-07 404 1.0.4 add RELAY generic for bp_rs232_2l4l_iob
-- 2011-08-06 403 1.0.3 add RESET port for bp_rs232_2l4l_iob
-- 2011-07-09 391 1.0.2 move in bp_rs232_2l4l_iob from s3boardlib
-- 2011-07-08 390 1.0.1 move in sn_(4x7segctl|humanio*) from s3boardlib
-- 2011-07-01 386 1.0 Initial version (with rs232_iob's and bp_swibtnled)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.rblib.all;
 
package bpgenlib is
 
component bp_rs232_2line_iob is -- iob's for 2 line rs232 (RXD,TXD)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit -- pad-o: transmit data (board view)
);
end component;
 
component bp_rs232_4line_iob is -- iob's for 4 line rs232 (w/ RTS,CTS)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit; -- pad-o: transmit data (board view)
I_CTS_N : in slbit; -- pad-i: clear to send (act. low)
O_RTS_N : out slbit -- pad-o: request to send (act. low)
);
end component;
 
component bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end component;
 
component bp_swibtnled is -- generic SWI, BTN and LED handling
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
);
end component;
 
component bp_swibtnled_rbus is -- swi,btn,led handling /w rbus icept
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
);
end component;
 
component sn_4x7segctl is -- Quad 7 segment display controller
generic (
CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
port (
CLK : in slbit; -- clock
DIN : in slv16; -- data
DP : in slv4; -- decimal points
ANO_N : out slv4; -- anodes (act.low)
SEG_N : out slv8 -- segements (act.low)
);
end component;
 
component sn_humanio is -- human i/o handling: swi,btn,led,dsp
generic (
BWIDTH : positive := 4; -- BTN port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end component;
 
component sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
BWIDTH : positive := 4; -- BTN port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv8; -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end component;
 
end package bpgenlib;
/trunk/rtl/bplib/bpgen/sn_4x7segctl.vhd
0,0 → 1,155
-- $Id: sn_4x7segctl.vhd 400 2011-07-31 09:02:16Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_4x7segctl - syn
-- Description: Quad 7 segment display controller (for s3board and nexys2/3)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-30 400 1.2 digit dark in last quarter (not 16 clocks)
-- 2011-07-08 390 1.1.2 renamed from s3_dispdrv
-- 2010-04-17 278 1.1.1 renamed from dispdrv
-- 2010-03-29 272 1.1 add all ANO off time to allow to driver turn-off
-- delay and to avoid cross talk between digits
-- 2007-12-16 101 1.0.1 use _N for active low
-- 2007-09-16 83 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
 
entity sn_4x7segctl is -- Quad 7 segment display controller
generic (
CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
port (
CLK : in slbit; -- clock
DIN : in slv16; -- data
DP : in slv4; -- decimal points
ANO_N : out slv4; -- anodes (act.low)
SEG_N : out slv8 -- segements (act.low)
);
end sn_4x7segctl;
 
architecture syn of sn_4x7segctl is
 
type regs_type is record
cdiv : std_logic_vector(CDWIDTH-1 downto 0); -- clock divider counter
dcnt : slv2; -- digit counter
end record regs_type;
 
constant regs_init : regs_type := (
conv_std_logic_vector(0,CDWIDTH),
(others=>'0')
);
 
type hex2segtbl_type is array (0 to 15) of slv7;
 
constant hex2segtbl : hex2segtbl_type :=
("0111111", -- 0: "0000"
"0000110", -- 1: "0001"
"1011011", -- 2: "0010"
"1001111", -- 3: "0011"
"1100110", -- 4: "0100"
"1101101", -- 5: "0101"
"1111101", -- 6: "0110"
"0000111", -- 7: "0111"
"1111111", -- 8: "1000"
"1101111", -- 9: "1001"
"1110111", -- a: "1010"
"1111100", -- b: "1011"
"0111001", -- c: "1100"
"1011110", -- d: "1101"
"1111001", -- e: "1110"
"1110001" -- f: "1111"
);
 
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
begin
 
assert CDWIDTH >= 5
report "assert(CDWIDTH >= 5): CDWIDTH too small"
severity FAILURE;
 
proc_regs: process (CLK)
begin
 
if CLK'event and CLK='1' then
R_REGS <= N_REGS;
end if;
 
end process proc_regs;
 
 
proc_next: process (R_REGS, DIN, DP)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable cano : slv4 := "0000";
variable chex : slv4 := "0000";
variable cdp : slbit := '0';
begin
 
r := R_REGS;
n := R_REGS;
 
n.cdiv := unsigned(r.cdiv) - 1;
if unsigned(r.cdiv) = 0 then
n.dcnt := unsigned(r.dcnt) + 1;
end if;
 
chex := "0000";
cdp := '0';
case r.dcnt is
when "00" => chex := DIN( 3 downto 0); cdp := DP(0);
when "01" => chex := DIN( 7 downto 4); cdp := DP(1);
when "10" => chex := DIN(11 downto 8); cdp := DP(2);
when "11" => chex := DIN(15 downto 12); cdp := DP(3);
when others => chex := "----"; cdp := '-';
end case;
 
-- the logic below ensures that the anode PNP driver transistor is switched
-- off in the last quarter of the digit cycle.This prevents 'cross talk'
-- between digits due to transistor turn off delays.
-- For a nexys2 board at 50 MHz observed:
-- no or 4 cycles gap well visible cross talk
-- with 8 cycles still some weak cross talk
-- with 16 cycles none is visible.
-- --> The turn-off delay of the anode driver PNP's this therefore
-- larger 160 ns and below 320 ns.
-- As consquence CDWIDTH should be at least 6 for 50 MHz and 7 for 100 MHz.
 
cano := "1111";
if r.cdiv(CDWIDTH-1 downto CDWIDTH-2) /= "00" then
cano(conv_integer(unsigned(r.dcnt))) := '0';
end if;
N_REGS <= n;
 
ANO_N <= cano;
SEG_N <= not (cdp & hex2segtbl(conv_integer(unsigned(chex))));
 
end process proc_next;
end syn;
/trunk/rtl/bplib/bpgen/sn_humanio_rbus.vhd
0,0 → 1,316
-- $Id: sn_humanio_rbus.vhd 406 2011-08-14 21:06:44Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio_rbus - syn
-- Description: sn_humanio with rbus interceptor
--
-- Dependencies: bpgen/sn_humanio
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-08-14 406 12.1 M53d xc3s1000-4 142 156 0 123 s 5.1 ns
-- 2011-08-07 404 12.1 M53d xc3s1000-4 142 157 0 124 s 5.1 ns
-- 2010-12-29 351 12.1 M53d xc3s1000-4 93 138 0 111 s 6.8 ns
-- 2010-06-03 300 11.4 L68 xc3s1000-4 92 137 0 111 s 6.7 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.2 common register layout with bp_swibtnled_rbus
-- 2011-08-07 404 1.3 add pipeline regs ledin,(swi,btn,led,dp,dat)eff
-- 2011-07-08 390 1.2 renamed from s3_humanio_rbus, add BWIDTH generic
-- 2010-12-29 351 1.1 renamed from s3_humanio_rri; ported to rbv3
-- 2010-06-18 306 1.0.1 rename rbus data fields to _rbf_
-- 2010-06-03 300 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbbbbb00 cntl r/w/- Control register and BTN access
-- x:08 btn r/w/- r: return hio BTN status
-- w: ored with hio BTN to drive BTN
-- 3 dsp_en r/w/- if 1 display data will be driven by rbus
-- 2 dp_en r/w/- if 1 display dp's will be driven by rbus
-- 1 led_en r/w/- if 1 LED will be driven by rri
-- 0 swi_en r/w/- if 1 SWI will be driven by rri
--
-- bbbbbb01 7:00 swi r/w/- r: return hio SWI status
-- w: will drive SWI when swi_en=1
--
-- bbbbbb10 led r/w/- Interface to LED and DSP_DP
-- 15:12 dp r/w/- r: returns DSP_DP status
-- w: will drive display dp's when dp_en=1
-- 7:00 led r/w/- r: returns LED status
-- w: will drive led's when led_en=1
--
-- bbbbbb11 15:00 dsp r/w/- r: return hio DSP_DAT status
-- w: will drive DSP_DAT when dsp_en=1
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.rblib.all;
use work.bpgenlib.all;
 
-- ----------------------------------------------------------------------------
 
entity sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
BWIDTH : positive := 4; -- BTN port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv8; -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end sn_humanio_rbus;
 
architecture syn of sn_humanio_rbus is
type regs_type is record
rbsel : slbit; -- rbus select
swi : slv8; -- rbus swi
btn : slv(BWIDTH-1 downto 0); -- rbus btn
led : slv8; -- rbus led
dsp_dat : slv16; -- rbus dsp_dat
dsp_dp : slv4; -- rbus dsp_dp
ledin : slv8; -- led from design
swieff : slv8; -- effective swi
btneff : slv(BWIDTH-1 downto 0); -- effective btn
ledeff : slv8; -- effective led
dpeff : slv4; -- effective dsp_dp
dateff : slv16; -- effective dsp_dat
swi_en : slbit; -- enable: swi from rbus
led_en : slbit; -- enable: led from rbus
dsp_en : slbit; -- enable: dsp_dat from rbus
dp_en : slbit; -- enable: dsp_dp from rbus
end record regs_type;
 
constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
'0', -- rbsel
(others=>'0'), -- swi
btnzero, -- btn
(others=>'0'), -- led
(others=>'0'), -- dsp_dat
(others=>'0'), -- dsp_dp
(others=>'0'), -- ledin
(others=>'0'), -- swieff
btnzero, -- btneff
(others=>'0'), -- ledeff
(others=>'0'), -- dpeff
(others=>'0'), -- dateff
'0','0','0','0' -- (swi|led|dsp|dp)_en
);
 
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
subtype cntl_rbf_btn is integer range BWIDTH+8-1 downto 8;
constant cntl_rbf_dsp_en: integer := 3;
constant cntl_rbf_dp_en: integer := 2;
constant cntl_rbf_led_en: integer := 1;
constant cntl_rbf_swi_en: integer := 0;
subtype led_rbf_dp is integer range 15 downto 12;
subtype led_rbf_led is integer range 7 downto 0;
 
constant rbaddr_cntl: slv2 := "00"; -- 0 r/w/-
constant rbaddr_swi: slv2 := "01"; -- 1 r/w/-
constant rbaddr_led: slv2 := "10"; -- 2 r/w/-
constant rbaddr_dsp: slv2 := "11"; -- 3 r/w/-
 
signal HIO_SWI : slv8 := (others=>'0');
signal HIO_BTN : slv(BWIDTH-1 downto 0) := (others=>'0');
signal HIO_LED : slv8 := (others=>'0');
signal HIO_DSP_DAT : slv16 := (others=>'0');
signal HIO_DSP_DP : slv4 := (others=>'0');
 
begin
 
HIO : sn_humanio
generic map (
BWIDTH => BWIDTH,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => HIO_SWI,
BTN => HIO_BTN,
LED => HIO_LED,
DSP_DAT => HIO_DSP_DAT,
DSP_DP => HIO_DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
proc_regs: process (CLK)
begin
 
if CLK'event and CLK='1' then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
 
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP,
HIO_SWI, HIO_BTN, HIO_DSP_DAT, HIO_DSP_DP)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
begin
 
r := R_REGS;
n := R_REGS;
 
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
 
irbena := RB_MREQ.re or RB_MREQ.we;
 
-- input register for LED signal
n.ledin := LED;
 
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
n.rbsel := '1';
end if;
 
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
 
case RB_MREQ.addr(1 downto 0) is
 
when rbaddr_cntl =>
irb_dout(cntl_rbf_btn) := HIO_BTN;
irb_dout(cntl_rbf_dsp_en) := r.dsp_en;
irb_dout(cntl_rbf_dp_en) := r.dp_en;
irb_dout(cntl_rbf_led_en) := r.led_en;
irb_dout(cntl_rbf_swi_en) := r.swi_en;
if RB_MREQ.we = '1' then
n.btn := RB_MREQ.din(cntl_rbf_btn);
n.dsp_en := RB_MREQ.din(cntl_rbf_dsp_en);
n.dp_en := RB_MREQ.din(cntl_rbf_dp_en);
n.led_en := RB_MREQ.din(cntl_rbf_led_en);
n.swi_en := RB_MREQ.din(cntl_rbf_swi_en);
end if;
when rbaddr_swi =>
irb_dout(HIO_SWI'range) := HIO_SWI;
if RB_MREQ.we = '1' then
n.swi := RB_MREQ.din(n.swi'range);
end if;
when rbaddr_led =>
irb_dout(led_rbf_dp) := HIO_DSP_DP;
irb_dout(led_rbf_led) := r.ledin;
if RB_MREQ.we = '1' then
n.dsp_dp := RB_MREQ.din(led_rbf_dp);
n.led := RB_MREQ.din(led_rbf_led);
end if;
when rbaddr_dsp =>
irb_dout := HIO_DSP_DAT;
if RB_MREQ.we = '1' then
n.dsp_dat := RB_MREQ.din;
end if;
 
when others => null;
end case;
 
end if;
 
n.btneff := HIO_BTN or r.btn;
if r.swi_en = '0' then
n.swieff := HIO_SWI;
else
n.swieff := r.swi;
end if;
 
if r.led_en = '0' then
n.ledeff := r.ledin;
else
n.ledeff := r.led;
end if;
if r.dp_en = '0' then
n.dpeff := DSP_DP;
else
n.dpeff := r.dsp_dp;
end if;
if r.dsp_en = '0' then
n.dateff := DSP_DAT;
else
n.dateff := r.dsp_dat;
end if;
N_REGS <= n;
 
BTN <= R_REGS.btneff;
SWI <= R_REGS.swieff;
HIO_LED <= R_REGS.ledeff;
HIO_DSP_DP <= R_REGS.dpeff;
HIO_DSP_DAT <= R_REGS.dateff;
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
 
end process proc_next;
 
end syn;
/trunk/rtl/bplib/bpgen/Makefile
0,0 → 1,25
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2007-12-09 100 1.0.1 drop ISE_p definition
# 2007-09-16 83 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
ISE_PATH = xc3s1000-ft256-4
#
.PHONY : all clean
#
all : $(NGC_all)
#
clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#
/trunk/rtl/bplib/bpgen/bp_swibtnled.vbom
0,0 → 1,12
# libs
../../vlib/slvtypes.vhd
../../vlib/genlib/genlib.vhd
../../vlib/xlib/xlib.vhd
bpgenlib.vbom
## sys_conf : sys_conf.vhd
# components
../../vlib/xlib/iob_reg_i_gen.vbom
../../vlib/xlib/iob_reg_o_gen.vbom
../../vlib/genlib/debounce_gen.vbom
# design
bp_swibtnled.vhd
trunk/rtl/bplib/bpgen Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: trunk/rtl/bplib/s3board/s3_rs232_iob_int_ext.vbom =================================================================== --- trunk/rtl/bplib/s3board/s3_rs232_iob_int_ext.vbom (revision 11) +++ trunk/rtl/bplib/s3board/s3_rs232_iob_int_ext.vbom (nonexistent) @@ -1,8 +0,0 @@ -# libs -../../vlib/slvtypes.vhd -s3boardlib.vbom -# components -s3_rs232_iob_int.vbom -s3_rs232_iob_ext.vbom -# design -s3_rs232_iob_int_ext.vhd Index: trunk/rtl/bplib/s3board/s3_rs232_iob_ext.vhd =================================================================== --- trunk/rtl/bplib/s3board/s3_rs232_iob_ext.vhd (revision 11) +++ trunk/rtl/bplib/s3board/s3_rs232_iob_ext.vhd (nonexistent) @@ -1,72 +0,0 @@ --- $Id: s3_rs232_iob_ext.vhd 314 2010-07-09 17:38:41Z mueller $ --- --- Copyright 2010- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: s3_rs232_iob_ext - syn --- Description: iob's for external rs232 (PMod) --- --- Dependencies: xlib/iob_reg_i --- xlib/iob_reg_o --- --- Test bench: - --- --- Target Devices: generic --- Tool versions: xst 11.4; ghdl 0.26 --- --- Revision History: --- Date Rev Version Comment --- 2010-04-17 278 1.0 Initial version ------------------------------------------------------------------------------- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -use work.slvtypes.all; -use work.xlib.all; - --- ---------------------------------------------------------------------------- - -entity s3_rs232_iob_ext is -- iob's for external rs232 (PMod) - port ( - CLK : in slbit; -- clock - RXD : out slbit; -- receive data (board view) - TXD : in slbit; -- transmit data (board view) - CTS_N : out slbit; -- clear to send (act. low) - RTS_N : in slbit; -- request to send (act. low) - I_RXD : in slbit; -- pad-i: receive data (board view) - O_TXD : out slbit; -- pad-o: transmit data (board view) - I_CTS_N : in slbit; -- pad-i: clear to send (act. low) - O_RTS_N : out slbit -- pad-o: request to send (act. low) - ); -end s3_rs232_iob_ext; - -architecture syn of s3_rs232_iob_ext is -begin - - IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1 - generic map (INIT => '1') - port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD); - - IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1 - generic map (INIT => '1') - port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD); - - IOB_CTS : iob_reg_i - port map (CLK => CLK, CE => '1', DI => CTS_N, PAD => I_CTS_N); - - IOB_RTS : iob_reg_o - port map (CLK => CLK, CE => '1', DO => RTS_N, PAD => O_RTS_N); - -end syn; Index: trunk/rtl/bplib/s3board/s3_humanio.vbom =================================================================== --- trunk/rtl/bplib/s3board/s3_humanio.vbom (revision 11) +++ trunk/rtl/bplib/s3board/s3_humanio.vbom (nonexistent) @@ -1,13 +0,0 @@ -# libs -../../vlib/slvtypes.vhd -../../vlib/genlib/genlib.vhd -../../vlib/xlib/xlib.vhd -s3boardlib.vbom -## sys_conf : sys_conf.vhd -# components -../../vlib/xlib/iob_reg_i_gen.vbom -../../vlib/xlib/iob_reg_o_gen.vbom -../../vlib/genlib/debounce_gen.vbom -s3_dispdrv.vbom -# design -s3_humanio.vhd Index: trunk/rtl/bplib/s3board/s3_rs232_iob_int.vbom =================================================================== --- trunk/rtl/bplib/s3board/s3_rs232_iob_int.vbom (revision 11) +++ trunk/rtl/bplib/s3board/s3_rs232_iob_int.vbom (nonexistent) @@ -1,8 +0,0 @@ -# libs -../../vlib/slvtypes.vhd -../../vlib/xlib/xlib.vhd -# components -../../vlib/xlib/iob_reg_i.vbom -../../vlib/xlib/iob_reg_o.vbom -# design -s3_rs232_iob_int.vhd Index: trunk/rtl/bplib/s3board/s3_humanio_rbus.vbom =================================================================== --- trunk/rtl/bplib/s3board/s3_humanio_rbus.vbom (revision 11) +++ trunk/rtl/bplib/s3board/s3_humanio_rbus.vbom (nonexistent) @@ -1,8 +0,0 @@ -# libs -../../vlib/slvtypes.vhd -../../vlib/rbus/rblib.vhd -s3boardlib.vbom -# components -s3_humanio.vbom -# design -s3_humanio_rbus.vhd Index: trunk/rtl/bplib/s3board/s3_dispdrv.vbom =================================================================== --- trunk/rtl/bplib/s3board/s3_dispdrv.vbom (revision 11) +++ trunk/rtl/bplib/s3board/s3_dispdrv.vbom (nonexistent) @@ -1,5 +0,0 @@ -# libs -../../vlib/slvtypes.vhd -# components -# design -s3_dispdrv.vhd Index: trunk/rtl/bplib/s3board/s3_rs232_iob_ext.vbom =================================================================== --- trunk/rtl/bplib/s3board/s3_rs232_iob_ext.vbom (revision 11) +++ trunk/rtl/bplib/s3board/s3_rs232_iob_ext.vbom (nonexistent) @@ -1,8 +0,0 @@ -# libs -../../vlib/slvtypes.vhd -../../vlib/xlib/xlib.vhd -# components -../../vlib/xlib/iob_reg_i.vbom -../../vlib/xlib/iob_reg_o.vbom -# design -s3_rs232_iob_ext.vhd Index: trunk/rtl/bplib/s3board/s3_humanio.vhd =================================================================== --- trunk/rtl/bplib/s3board/s3_humanio.vhd (revision 11) +++ trunk/rtl/bplib/s3board/s3_humanio.vhd (nonexistent) @@ -1,147 +0,0 @@ --- $Id: s3_humanio.vhd 314 2010-07-09 17:38:41Z mueller $ --- --- Copyright 2010- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: s3_humanio - syn --- Description: All BTN, SWI, LED and DSP handling for s3board --- --- Dependencies: xlib/iob_reg_i_gen --- xlib/iob_reg_o_gen --- genlib/debounce_gen --- s3board/s3_dispdrv --- --- Test bench: - --- --- Target Devices: generic --- Tool versions: xst 11.4; ghdl 0.26 --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri --- 2010-04-10 275 11.4 L68 xc3s1000-4 80 87 0 53 s 5.2 ns --- --- Revision History: --- Date Rev Version Comment --- 2010-04-17 278 1.1.1 rename dispdrv -> s3_dispdrv --- 2010-04-11 276 1.1 instantiate BTN/SWI debouncers via DEBOUNCE generic --- 2010-04-10 275 1.0 Initial version ------------------------------------------------------------------------------- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -use work.slvtypes.all; -use work.xlib.all; -use work.genlib.all; -use work.s3boardlib.all; - --- ---------------------------------------------------------------------------- - -entity s3_humanio is -- human i/o handling: swi,btn,led,dsp - generic ( - DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - CE_MSEC : in slbit; -- 1 ms clock enable - SWI : out slv8; -- switch settings, debounced - BTN : out slv4; -- button settings, debounced - LED : in slv8; -- led data - DSP_DAT : in slv16; -- display data - DSP_DP : in slv4; -- display decimal points - I_SWI : in slv8; -- pad-i: switches - I_BTN : in slv4; -- pad-i: buttons - O_LED : out slv8; -- pad-o: leds - O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low) - O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low) - ); -end s3_humanio; - -architecture syn of s3_humanio is - - signal RI_SWI : slv8 := (others=>'0'); - signal RI_BTN : slv4 := (others=>'0'); - - signal N_ANO_N : slv4 := (others=>'0'); - signal N_SEG_N : slv8 := (others=>'0'); - -begin - - IOB_SWI : iob_reg_i_gen - generic map (DWIDTH => 8) - port map (CLK => CLK, CE => '1', DI => RI_SWI, PAD => I_SWI); - - IOB_BTN : iob_reg_i_gen - generic map (DWIDTH => 4) - port map (CLK => CLK, CE => '1', DI => RI_BTN, PAD => I_BTN); - - IOB_LED : iob_reg_o_gen - generic map (DWIDTH => 8) - port map (CLK => CLK, CE => '1', DO => LED, PAD => O_LED); - - IOB_ANO_N : iob_reg_o_gen - generic map (DWIDTH => 4) - port map (CLK => CLK, CE => '1', DO => N_ANO_N, PAD => O_ANO_N); - - IOB_SEG_N : iob_reg_o_gen - generic map (DWIDTH => 8) - port map (CLK => CLK, CE => '1', DO => N_SEG_N, PAD => O_SEG_N); - - DEB: if DEBOUNCE generate - - DEB_SWI : debounce_gen - generic map ( - CWIDTH => 2, - CEDIV => 3, - DWIDTH => 8) - port map ( - CLK => CLK, - RESET => RESET, - CE_INT => CE_MSEC, - DI => RI_SWI, - DO => SWI - ); - - DEB_BTN : debounce_gen - generic map ( - CWIDTH => 2, - CEDIV => 3, - DWIDTH => 4) - port map ( - CLK => CLK, - RESET => RESET, - CE_INT => CE_MSEC, - DI => RI_BTN, - DO => BTN - ); - - end generate DEB; - - NODEB: if not DEBOUNCE generate - SWI <= RI_SWI; - BTN <= RI_BTN; - end generate NODEB; - - DRV : s3_dispdrv - generic map ( - CDWIDTH => 6) - port map ( - CLK => CLK, - DIN => DSP_DAT, - DP => DSP_DP, - ANO_N => N_ANO_N, - SEG_N => N_SEG_N - ); - -end syn; Index: trunk/rtl/bplib/s3board/s3_rs232_iob_int_ext.vhd =================================================================== --- trunk/rtl/bplib/s3board/s3_rs232_iob_int_ext.vhd (revision 11) +++ trunk/rtl/bplib/s3board/s3_rs232_iob_int_ext.vhd (nonexistent) @@ -1,106 +0,0 @@ --- $Id: s3_rs232_iob_int_ext.vhd 314 2010-07-09 17:38:41Z mueller $ --- --- Copyright 2010- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: s3_rs232_iob_int_ext - syn --- Description: iob's for internal + external rs232, with select --- --- Dependencies: s3_rs232_iob_int --- s3_rs232_iob_ext --- --- Test bench: - --- --- Target Devices: generic --- Tool versions: xst 11.4; ghdl 0.26 --- --- Revision History: --- Date Rev Version Comment --- 2010-04-17 278 1.0 Initial version ------------------------------------------------------------------------------- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -use work.slvtypes.all; -use work.s3boardlib.all; - --- ---------------------------------------------------------------------------- - -entity s3_rs232_iob_int_ext is -- iob's for int+ext rs232, with select - port ( - CLK : in slbit; -- clock - SEL : in slbit; -- select, '0' for port 0 - RXD : out slbit; -- receive data (board view) - TXD : in slbit; -- transmit data (board view) - CTS_N : out slbit; -- clear to send (act. low) - RTS_N : in slbit; -- request to send (act. low) - I_RXD0 : in slbit; -- pad-i: p0: receive data (board view) - O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view) - I_RXD1 : in slbit; -- pad-i: p1: receive data (board view) - O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view) - I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low) - O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low) - ); -end s3_rs232_iob_int_ext; - -architecture syn of s3_rs232_iob_int_ext is - signal RXD0 : slbit := '0'; - signal TXD0 : slbit := '0'; - signal RXD1 : slbit := '0'; - signal TXD1 : slbit := '0'; - signal CTS1_N : slbit := '0'; - signal RTS1_N : slbit := '0'; -begin - - P0 : s3_rs232_iob_int - port map ( - CLK => CLK, - RXD => RXD0, - TXD => TXD0, - I_RXD => I_RXD0, - O_TXD => O_TXD0 - ); - - P1 : s3_rs232_iob_ext - port map ( - CLK => CLK, - RXD => RXD1, - TXD => TXD1, - CTS_N => CTS1_N, - RTS_N => RTS1_N, - I_RXD => I_RXD1, - O_TXD => O_TXD1, - I_CTS_N => I_CTS1_N, - O_RTS_N => O_RTS1_N - ); - - proc_port_mux: process (SEL, RXD0, TXD, RXD1, CTS1_N, RTS_N) - begin - if SEL = '0' then -- use main board rs232, no flow cntl - RXD <= RXD0; -- get port 0 inputs - CTS_N <= '0'; - TXD0 <= TXD; -- set port 0 output - TXD1 <= '1'; -- port 1 outputs to idle state - RTS1_N <= '0'; - else -- otherwise use pmod1 rs232 - RXD <= RXD1; -- get port 1 inputs - CTS_N <= CTS1_N; - TXD1 <= TXD; -- set port 1 outputs - RTS1_N <= RTS_N; - TXD0 <= '1'; -- port 0 output to idle state - end if; - end process proc_port_mux; - -end syn; Index: trunk/rtl/bplib/s3board/s3_dispdrv.vhd =================================================================== --- trunk/rtl/bplib/s3board/s3_dispdrv.vhd (revision 11) +++ trunk/rtl/bplib/s3board/s3_dispdrv.vhd (nonexistent) @@ -1,151 +0,0 @@ --- $Id: s3_dispdrv.vhd 314 2010-07-09 17:38:41Z mueller $ --- --- Copyright 2007-2010 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: s3_dispdrv - syn --- Description: s3board: 7 segment display driver --- --- Dependencies: - --- Test bench: - --- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 --- Revision History: --- Date Rev Version Comment --- 2010-04-17 278 1.1.1 renamed from dispdrv --- 2010-03-29 272 1.1 add all ANO off time to allow to driver turn-off --- delay and to avoid cross talk between digits --- 2007-12-16 101 1.0.1 use _N for active low --- 2007-09-16 83 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -use work.slvtypes.all; - -entity s3_dispdrv is -- 7 segment display driver - generic ( - CDWIDTH : positive := 6); -- clk divider width (must be >= 5) - port ( - CLK : in slbit; -- clock - DIN : in slv16; -- data - DP : in slv4; -- decimal points - ANO_N : out slv4; -- anodes (act.low) - SEG_N : out slv8 -- segements (act.low) - ); -end s3_dispdrv; - -architecture syn of s3_dispdrv is - - type regs_type is record - cdiv : std_logic_vector(CDWIDTH-1 downto 0); -- clock divider counter - dcnt : slv2; -- digit counter - end record regs_type; - - constant regs_init : regs_type := ( - conv_std_logic_vector(0,CDWIDTH), - (others=>'0') - ); - - type hex2segtbl_type is array (0 to 15) of slv7; - - constant hex2segtbl : hex2segtbl_type := - ("0111111", -- 0: "0000" - "0000110", -- 1: "0001" - "1011011", -- 2: "0010" - "1001111", -- 3: "0011" - "1100110", -- 4: "0100" - "1101101", -- 5: "0101" - "1111101", -- 6: "0110" - "0000111", -- 7: "0111" - "1111111", -- 8: "1000" - "1101111", -- 9: "1001" - "1110111", -- a: "1010" - "1111100", -- b: "1011" - "0111001", -- c: "1100" - "1011110", -- d: "1101" - "1111001", -- e: "1110" - "1110001" -- f: "1111" - ); - - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - -begin - - assert CDWIDTH >= 5 - report "assert(CDWIDTH >= 5): CDWIDTH too small" - severity FAILURE; - - proc_regs: process (CLK) - begin - - if CLK'event and CLK='1' then - R_REGS <= N_REGS; - end if; - - end process proc_regs; - - - proc_next: process (R_REGS, DIN, DP) - - variable r : regs_type := regs_init; - variable n : regs_type := regs_init; - variable cano : slv4 := "0000"; - variable chex : slv4 := "0000"; - variable cdp : slbit := '0'; - - begin - - r := R_REGS; - n := R_REGS; - - n.cdiv := unsigned(r.cdiv) - 1; - if unsigned(r.cdiv) = 0 then - n.dcnt := unsigned(r.dcnt) + 1; - end if; - - chex := "0000"; - cdp := '0'; - - case r.dcnt is - when "00" => chex := DIN( 3 downto 0); cdp := DP(0); - when "01" => chex := DIN( 7 downto 4); cdp := DP(1); - when "10" => chex := DIN(11 downto 8); cdp := DP(2); - when "11" => chex := DIN(15 downto 12); cdp := DP(3); - when others => chex := "----"; cdp := '-'; - end case; - - -- the logic below ensures that the anode PNP driver transistor is switched - -- off 16 cycles before the cathode drivers change. This prevents 'cross - -- talk' between digits due to transistor turn off delays. With no or 4 - -- cycles gap one gets well visible cross talk, with 8 cycles still some - -- weak cross talk. With 16 cycles (at 50MHz) none is visible. The - -- turn-off delay of the anode driver PNP's this therefore larger 160 ns - -- and below 320 ns. - -- As consquence CDWIDTH should be at least 5, better 6. - - cano := "1111"; - if unsigned(r.cdiv) >= 16 then - cano(conv_integer(unsigned(r.dcnt))) := '0'; - end if; - - N_REGS <= n; - - ANO_N <= cano; - SEG_N <= not (cdp & hex2segtbl(conv_integer(unsigned(chex)))); - - end process proc_next; - -end syn; Index: trunk/rtl/bplib/s3board/s3_rs232_iob_int.vhd =================================================================== --- trunk/rtl/bplib/s3board/s3_rs232_iob_int.vhd (revision 11) +++ trunk/rtl/bplib/s3board/s3_rs232_iob_int.vhd (nonexistent) @@ -1,62 +0,0 @@ --- $Id: s3_rs232_iob_int.vhd 314 2010-07-09 17:38:41Z mueller $ --- --- Copyright 2010- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: s3_rs232_iob_int - syn --- Description: iob's for internal rs232 --- --- Dependencies: xlib/iob_reg_i --- xlib/iob_reg_o --- --- Test bench: - --- --- Target Devices: generic --- Tool versions: xst 11.4; ghdl 0.26 --- --- Revision History: --- Date Rev Version Comment --- 2010-04-17 278 1.0 Initial version ------------------------------------------------------------------------------- --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -use work.slvtypes.all; -use work.xlib.all; - --- ---------------------------------------------------------------------------- - -entity s3_rs232_iob_int is -- iob's for internal rs232 - port ( - CLK : in slbit; -- clock - RXD : out slbit; -- receive data (board view) - TXD : in slbit; -- transmit data (board view) - I_RXD : in slbit; -- pad-i: receive data (board view) - O_TXD : out slbit -- pad-o: transmit data (board view) - ); -end s3_rs232_iob_int; - -architecture syn of s3_rs232_iob_int is -begin - - IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1 - generic map (INIT => '1') - port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD); - - IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1 - generic map (INIT => '1') - port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD); - -end syn; Index: trunk/rtl/bplib/s3board/s3_humanio_rbus.vhd =================================================================== --- trunk/rtl/bplib/s3board/s3_humanio_rbus.vhd (revision 11) +++ trunk/rtl/bplib/s3board/s3_humanio_rbus.vhd (nonexistent) @@ -1,286 +0,0 @@ --- $Id: s3_humanio_rbus.vhd 352 2011-01-02 13:01:37Z mueller $ --- --- Copyright 2010- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: s3_humanio_rbus - syn --- Description: s3_humanio with rbus interceptor --- --- Dependencies: s3board/s3_humanio --- --- Test bench: - --- --- Target Devices: generic --- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29 --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri --- 2010-12-29 300 12.1 M53d xc3s1000-4 93 138 0 111 s 6.8 ns --- 2010-06-03 300 11.4 L68 xc3s1000-4 92 137 0 111 s 6.7 ns --- --- Revision History: --- Date Rev Version Comment --- 2010-12-29 351 1.1 renamed from s3_humanio_rri; ported to rbv3 --- 2010-06-18 306 1.0.1 rename rbus data fields to _rbf_ --- 2010-06-03 300 1.0 Initial version ------------------------------------------------------------------------------- --- --- rbus registers: --- --- Address Bits Name r/w/f Function --- bbbbbb00 cntl r/w/- Control register and BTN access --- 11 dat_en r/w/- if 1 display data will be driven by rri --- 10 dp_en r/w/- if 1 display dp's will be driven by rri --- 9 led_en r/w/- if 1 LED will be driven by rri --- 8 swi_en r/w/- if 1 SWI will be driven by rri --- 3:00 btn r/w/- r: return hio BTN status --- w: BTN is hio BTN ored with this fields --- --- bbbbbb01 7:00 swi r/w/- r: return hio SWI status --- w: will drive SWI when swi_en=1 --- --- bbbbbb10 leddp r/w/- Interface to LED and DSP_DP --- 11:09 dsp_dp r/w/- r: returns DSP_DP status --- w: will drive display dp's when dp_en=1 --- 7:00 led r/w/- r: returns LED status --- w: will drive led's when led_en=1 --- --- bbbbbb11 15:00 dsp_dat r/w/- r: return hio DSP_DAT status --- w: will drive DSP_DAT when dat_en=1 --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - -use work.slvtypes.all; -use work.rblib.all; -use work.s3boardlib.all; - --- ---------------------------------------------------------------------------- - -entity s3_humanio_rbus is -- human i/o handling /w rbus intercept - generic ( - DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN - RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8)); - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - CE_MSEC : in slbit; -- 1 ms clock enable - RB_MREQ : in rb_mreq_type; -- rbus: request - RB_SRES : out rb_sres_type; -- rbus: response - SWI : out slv8; -- switch settings, debounced - BTN : out slv4; -- button settings, debounced - LED : in slv8; -- led data - DSP_DAT : in slv16; -- display data - DSP_DP : in slv4; -- display decimal points - I_SWI : in slv8; -- pad-i: switches - I_BTN : in slv4; -- pad-i: buttons - O_LED : out slv8; -- pad-o: leds - O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low) - O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low) - ); -end s3_humanio_rbus; - -architecture syn of s3_humanio_rbus is - - type regs_type is record - rbsel : slbit; -- rbus select - swi : slv8; -- rbus swi - btn : slv4; -- rbus btn - led : slv8; -- rbus led - dsp_dat : slv16; -- rbus dsp_dat - dsp_dp : slv4; -- rbus dsp_dp - swi_en : slbit; -- enable: swi from rri - led_en : slbit; -- enable: led from rri - dat_en : slbit; -- enable: dsp_dat from rri - dp_en : slbit; -- enable: dsp_dp from rri - end record regs_type; - - constant regs_init : regs_type := ( - '0', -- rbsel - (others=>'0'), -- swi - (others=>'0'), -- btn - (others=>'0'), -- led - (others=>'0'), -- dsp_dat - (others=>'0'), -- dsp_dp - '0','0','0','0' -- (swi|led|dat|dp)_en - ); - - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - - constant cntl_rbf_dat_en: integer := 11; - constant cntl_rbf_dp_en: integer := 10; - constant cntl_rbf_led_en: integer := 9; - constant cntl_rbf_swi_en: integer := 8; - subtype cntl_rbf_btn is integer range 3 downto 0; - subtype leddp_rbf_dsp_dp is integer range 11 downto 8; - subtype leddp_rbf_led is integer range 7 downto 0; - - constant rbaddr_cntl: slv2 := "00"; -- 0 -/r/w - constant rbaddr_swi: slv2 := "01"; -- 1 -/r/w - constant rbaddr_leddp: slv2 := "10"; -- 2 -/r/w - constant rbaddr_dsp: slv2 := "11"; -- 3 -/r/w - - signal HIO_SWI : slv8 := (others=>'0'); - signal HIO_BTN : slv4 := (others=>'0'); - signal HIO_LED : slv8 := (others=>'0'); - signal HIO_DSP_DAT : slv16 := (others=>'0'); - signal HIO_DSP_DP : slv4 := (others=>'0'); - -begin - - HIO : s3_humanio - generic map ( - DEBOUNCE => DEBOUNCE) - port map ( - CLK => CLK, - RESET => RESET, - CE_MSEC => CE_MSEC, - SWI => HIO_SWI, - BTN => HIO_BTN, - LED => HIO_LED, - DSP_DAT => HIO_DSP_DAT, - DSP_DP => HIO_DSP_DP, - I_SWI => I_SWI, - I_BTN => I_BTN, - O_LED => O_LED, - O_ANO_N => O_ANO_N, - O_SEG_N => O_SEG_N - ); - - proc_regs: process (CLK) - begin - - if CLK'event and CLK='1' then - if RESET = '1' then - R_REGS <= regs_init; - else - R_REGS <= N_REGS; - end if; - end if; - - end process proc_regs; - - proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP, - HIO_SWI, HIO_BTN, HIO_LED, HIO_DSP_DAT, HIO_DSP_DP) - - variable r : regs_type := regs_init; - variable n : regs_type := regs_init; - - variable irb_ack : slbit := '0'; - variable irb_busy : slbit := '0'; - variable irb_err : slbit := '0'; - variable irb_dout : slv16 := (others=>'0'); - variable irbena : slbit := '0'; - - begin - - r := R_REGS; - n := R_REGS; - - irb_ack := '0'; - irb_busy := '0'; - irb_err := '0'; - irb_dout := (others=>'0'); - - irbena := RB_MREQ.re or RB_MREQ.we; - - -- rbus address decoder - n.rbsel := '0'; - if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then - n.rbsel := '1'; - end if; - - -- rbus transactions - if r.rbsel = '1' then - irb_ack := irbena; -- ack all accesses - - case RB_MREQ.addr(1 downto 0) is - - when rbaddr_cntl => - irb_dout(cntl_rbf_dat_en) := r.dat_en; - irb_dout(cntl_rbf_dp_en) := r.dp_en; - irb_dout(cntl_rbf_led_en) := r.led_en; - irb_dout(cntl_rbf_swi_en) := r.swi_en; - irb_dout(cntl_rbf_btn) := HIO_BTN; - if RB_MREQ.we = '1' then - n.dat_en := RB_MREQ.din(cntl_rbf_dat_en); - n.dp_en := RB_MREQ.din(cntl_rbf_dp_en); - n.led_en := RB_MREQ.din(cntl_rbf_led_en); - n.swi_en := RB_MREQ.din(cntl_rbf_swi_en); - n.btn := RB_MREQ.din(cntl_rbf_btn); - end if; - - when rbaddr_swi => - irb_dout(HIO_SWI'range) := HIO_SWI; - if RB_MREQ.we = '1' then - n.swi := RB_MREQ.din(n.swi'range); - end if; - - when rbaddr_leddp => - irb_dout(leddp_rbf_dsp_dp) := HIO_DSP_DP; - irb_dout(leddp_rbf_led) := HIO_LED; - if RB_MREQ.we = '1' then - n.dsp_dp := RB_MREQ.din(leddp_rbf_dsp_dp); - n.led := RB_MREQ.din(leddp_rbf_led); - end if; - - when rbaddr_dsp => - irb_dout := HIO_DSP_DAT; - if RB_MREQ.we = '1' then - n.dsp_dat := RB_MREQ.din; - end if; - - when others => null; - end case; - - end if; - - BTN <= HIO_BTN or r.btn; - - if r.swi_en = '0' then - SWI <= HIO_SWI; - else - SWI <= r.swi; - end if; - - if r.led_en = '0' then - HIO_LED <= LED; - else - HIO_LED <= r.led; - end if; - - if r.dp_en = '0' then - HIO_DSP_DP <= DSP_DP; - else - HIO_DSP_DP <= r.dsp_dp; - end if; - - if r.dat_en = '0' then - HIO_DSP_DAT <= DSP_DAT; - else - HIO_DSP_DAT <= r.dsp_dat; - end if; - - N_REGS <= n; - - RB_SRES <= rb_sres_init; - RB_SRES.ack <= irb_ack; - RB_SRES.busy <= irb_busy; - RB_SRES.err <= irb_err; - RB_SRES.dout <= irb_dout; - - end process proc_next; - -end syn; Index: trunk/rtl/bplib/s3board/s3board_pins.ucf =================================================================== --- trunk/rtl/bplib/s3board/s3board_pins.ucf (revision 11) +++ trunk/rtl/bplib/s3board/s3board_pins.ucf (revision 12) @@ -1,9 +1,9 @@ -## $Id: s3board_pins.ucf 336 2010-11-06 18:28:27Z mueller $ +## $Id: s3board_pins.ucf 402 2011-08-05 18:56:44Z mueller $ ## ## Pin locks for S3BOARD core functionality: -## internal RS232 -## human I/O (switches, buttons, leds, display) -## sram +## - internal RS232 +## - human I/O (switches, buttons, leds, display) +## - sram ## ## Revision History: ## Date Rev Version Comment Index: trunk/rtl/bplib/s3board/s3boardlib.vhd =================================================================== --- trunk/rtl/bplib/s3board/s3boardlib.vhd (revision 11) +++ trunk/rtl/bplib/s3board/s3boardlib.vhd (revision 12) @@ -1,6 +1,6 @@ --- $Id: s3boardlib.vhd 351 2010-12-30 21:50:54Z mueller $ +-- $Id: s3boardlib.vhd 391 2011-07-09 17:25:02Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,6 +19,9 @@ -- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-07-09 391 1.3.5 move s3_rs232_iob_int_ext to bpgenlib +-- 2011-07-08 390 1.3.4 move s3_(dispdrv|humanio*) to bpgenlib +-- 2011-07-03 387 1.3.3 move s3_rs232_iob_(int|ext) to bpgenlib -- 2010-12-30 351 1.3.2 use rblib; rename human s3_humanio_rri -> _rbus -- 2010-11-06 336 1.3.1 rename input pin CLK -> I_CLK50 -- 2010-06-03 300 1.3 add s3_humanio_rri (now needs rrilib) @@ -41,7 +44,6 @@ use ieee.std_logic_arith.all; use work.slvtypes.all; -use work.rblib.all; package s3boardlib is @@ -87,102 +89,6 @@ ); end component; -component s3_dispdrv is -- 7 segment display driver - generic ( - CDWIDTH : positive := 6); -- clk divider width (must be >= 5) - port ( - CLK : in slbit; -- clock - DIN : in slv16; -- data - DP : in slv4; -- decimal points - ANO_N : out slv4; -- anodes (act.low) - SEG_N : out slv8 -- segements (act.low) - ); -end component; - -component s3_humanio is -- human i/o handling: swi,btn,led,dsp - generic ( - DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - CE_MSEC : in slbit; -- 1 ms clock enable - SWI : out slv8; -- switch settings, debounced - BTN : out slv4; -- button settings, debounced - LED : in slv8; -- led data - DSP_DAT : in slv16; -- display data - DSP_DP : in slv4; -- display decimal points - I_SWI : in slv8; -- pad-i: switches - I_BTN : in slv4; -- pad-i: buttons - O_LED : out slv8; -- pad-o: leds - O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low) - O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low) - ); -end component; - -component s3_humanio_rbus is -- human i/o handling /w rbus intercept - generic ( - DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN - RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8)); - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - CE_MSEC : in slbit; -- 1 ms clock enable - RB_MREQ : in rb_mreq_type; -- rbus: request - RB_SRES : out rb_sres_type; -- rbus: response - SWI : out slv8; -- switch settings, debounced - BTN : out slv4; -- button settings, debounced - LED : in slv8; -- led data - DSP_DAT : in slv16; -- display data - DSP_DP : in slv4; -- display decimal points - I_SWI : in slv8; -- pad-i: switches - I_BTN : in slv4; -- pad-i: buttons - O_LED : out slv8; -- pad-o: leds - O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low) - O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low) - ); -end component; - -component s3_rs232_iob_int is -- iob's for internal rs232 - port ( - CLK : in slbit; -- clock - RXD : out slbit; -- receive data (board view) - TXD : in slbit; -- transmit data (board view) - I_RXD : in slbit; -- pad-i: receive data (board view) - O_TXD : out slbit -- pad-o: transmit data (board view) - ); -end component; - -component s3_rs232_iob_ext is -- iob's for external rs232 (Pmod) - port ( - CLK : in slbit; -- clock - RXD : out slbit; -- receive data (board view) - TXD : in slbit; -- transmit data (board view) - CTS_N : out slbit; -- clear to send (act. low) - RTS_N : in slbit; -- request to send (act. low) - I_RXD : in slbit; -- pad-i: receive data (board view) - O_TXD : out slbit; -- pad-o: transmit data (board view) - I_CTS_N : in slbit; -- pad-i: clear to send (act. low) - O_RTS_N : out slbit -- pad-o: request to send (act. low) - ); -end component; - -component s3_rs232_iob_int_ext is -- iob's for int+ext rs232, with select - port ( - CLK : in slbit; -- clock - SEL : in slbit; -- select, '0' for port 0 - RXD : out slbit; -- receive data (board view) - TXD : in slbit; -- transmit data (board view) - CTS_N : out slbit; -- clear to send (act. low) - RTS_N : in slbit; -- request to send (act. low) - I_RXD0 : in slbit; -- pad-i: p0: receive data (board view) - O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view) - I_RXD1 : in slbit; -- pad-i: p1: receive data (board view) - O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view) - I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low) - O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low) - ); -end component; - component s3_sram_dummy is -- SRAM protection dummy port ( O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) @@ -218,4 +124,4 @@ ); end component; -end s3boardlib; +end package s3boardlib;
/trunk/rtl/bplib/s3board/tb/Makefile
1,7 → 1,8
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.3 use includes from rtl/make
# 2010-05-16 291 1.2.2 rename tb_memctl_s3sram->tb_s3_sram_memctl
# 2010-05-01 286 1.2.1 add tb_s3board_usp_dummy
# 2009-11-21 252 1.2 add ISim support
12,7 → 13,7
#
ISE_PATH = xc3s1000-ft256-4
#
.phony : all all_ssim all_tsim clean
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
22,9 → 23,9
#
#-----
#
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
include $(RETROBASE)/rtl/vlib/Makefile.isim
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_isim.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
/trunk/rtl/bplib/s3board/s3boardlib.vbom
1,4 → 1,3
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
s3boardlib.vhd
/trunk/rtl/bplib/s3board/Makefile
1,7 → 1,8
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2007-12-09 100 1.0.1 drop ISE_p definition
# 2007-09-16 83 1.0 Initial version
#
10,7 → 11,7
#
ISE_PATH = xc3s1000-ft256-4
#
.phony : all clean
.PHONY : all clean
#
all : $(NGC_all)
#
18,7 → 19,7
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#
/trunk/rtl/w11a/tb/Makefile
1,7 → 1,8
# $Id: Makefile 351 2010-12-30 21:50:54Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.4 use includes from rtl/make
# 2010-12-30 351 1.3 retire tb_rripdp_pdp11core tb_rriext_pdp11core
# 2009-11-22 252 1.2 add ISim support
# 2007-09-16 83 1.1.1 add include *.o.dep_ghdl
11,7 → 12,7
EXE_all = tb_pdp11core tb_rlink_tba_pdp11core
#
#
.phony : all all_ssim all_tsim clean
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
21,9 → 22,9
#
#-----
#
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
include $(RETROBASE)/rtl/vlib/Makefile.isim
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_isim.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
/trunk/rtl/w11a/Makefile
1,7 → 1,8
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2007-12-09 100 1.0.1 drop ISE_p def
# 2007-07-08 65 1.0 Initial version
#
8,7 → 9,7
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
.phony : all clean
.PHONY : all clean
#
all : $(NGC_all)
#
16,7 → 17,7
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#
/trunk/rtl/vlib/rlink/rlinklib.vhd
1,4 → 1,4
-- $Id: rlinklib.vhd 348 2010-12-26 15:23:44Z mueller $
-- $Id: rlinklib.vhd 389 2011-07-07 21:59:00Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
305,4 → 305,4
);
end component;
 
end rlinklib;
end package rlinklib;
/trunk/rtl/vlib/rlink/tb/rlink_cext_vhpi.vhd
1,4 → 1,4
-- $Id: rlink_cext_vhpi.vhd 351 2010-12-30 21:50:54Z mueller $
-- $Id: rlink_cext_vhpi.vhd 389 2011-07-07 21:59:00Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
37,7 → 37,7
attribute foreign of rlink_cext_putbyte :
function is "VHPIDIRECT rlink_cext_putbyte";
 
end rlink_cext_vhpi;
end package rlink_cext_vhpi;
 
package body rlink_cext_vhpi is
 
55,4 → 55,4
report "rlink_cext_getbyte not vhpi'ed" severity failure;
end rlink_cext_putbyte;
 
end rlink_cext_vhpi;
end package body rlink_cext_vhpi;
/trunk/rtl/vlib/rlink/tb/rlinktblib.vhd
1,4 → 1,4
-- $Id: rlinktblib.vhd 351 2010-12-30 21:50:54Z mueller $
-- $Id: rlinktblib.vhd 389 2011-07-07 21:59:00Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
174,4 → 174,4
);
end component;
 
end rlinktblib;
end package rlinktblib;
/trunk/rtl/vlib/rlink/tb/Makefile
1,7 → 1,8
# $Id: Makefile 349 2010-12-28 14:02:13Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.4 use includes from rtl/make
# 2010-12-28 349 1.3.1 add tb_rlink_tba_eyemon
# 2010-12-05 343 1.3 rri->rlink renames
# 2009-11-21 252 1.2 add ISim support
14,7 → 15,7
tb_rlink_tba_ttcombo tb_rlink_tba_eyemon
#
#
.phony : all all_ssim all_tsim clean
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
24,9 → 25,9
#
#-----
#
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
include $(RETROBASE)/rtl/vlib/Makefile.isim
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_isim.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
/trunk/rtl/vlib/rlink/Makefile
1,7 → 1,8
# $Id: Makefile 343 2010-12-05 21:24:38Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2007-12-09 100 1.0.1 drop ISE_p definition
# 2007-07-06 64 1.0 Initial version
#
8,7 → 9,7
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
.phony : all clean
.PHONY : all clean
#
all : $(NGC_all)
#
16,7 → 17,7
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#
/trunk/rtl/vlib/rlink/rlink_serport.vhd
1,6 → 1,6
-- $Id: rlink_serport.vhd 350 2010-12-28 16:40:11Z mueller $
-- $Id: rlink_serport.vhd 406 2011-08-14 21:06:44Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
20,7 → 20,7
-- Test bench: tb/tb_rlink_serport
--
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
28,6 → 28,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 3.1.1 cleaner code for RL_SER_MONI.clkdiv assignment
-- 2010-12-25 348 3.1 re-written, is now a serial to rlink_base adapter
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-04 343 3.0 renamed rri_ -> rlink_
110,7 → 111,7
signal TXBUSY : slbit := '0';
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal ABCLKDIV : slv16 := (others=>'0');
signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0');
 
begin
 
230,6 → 231,11
RL_SER_MONI.txact <= TXBUSY;
RL_SER_MONI.abact <= ABACT;
RL_SER_MONI.abdone <= ABDONE;
RL_SER_MONI.clkdiv <= ABCLKDIV;
proc_clkdiv: process (ABCLKDIV)
begin
RL_SER_MONI.clkdiv <= (others=>'0');
RL_SER_MONI.clkdiv(ABCLKDIV'range) <= ABCLKDIV;
end process proc_clkdiv;
 
end syn;
/trunk/rtl/vlib/genlib/genlib.vhd
1,4 → 1,4
-- $Id: genlib.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: genlib.vhd 389 2011-07-07 21:59:00Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
153,4 → 153,4
);
end component;
 
end genlib;
end package genlib;
/trunk/rtl/vlib/genlib/Makefile
1,7 → 1,8
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.2 use includes from rtl/make
# 2007-12-09 100 1.1.1 drop ISE_p definition
# 2007-06-03 47 1.1 use Makefile.xflow
# 2007-06-03 45 1.0 Initial version
9,7 → 10,7
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
.phony : all clean
.PHONY : all clean
#
all : $(NGC_all)
#
17,7 → 18,7
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#
/trunk/rtl/vlib/memlib/memlib.vhd
1,4 → 1,4
-- $Id: memlib.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: memlib.vhd 389 2011-07-07 21:59:00Z mueller $
--
-- Copyright 2006-2007 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
235,4 → 235,4
);
end component;
 
end memlib;
end package memlib;
/trunk/rtl/vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd
1,6 → 1,6
-- $Id: ram_1swsr_xfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ram_1swsr_xfirst_gen_unisim.vhd 406 2011-08-14 21:06:44Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
19,9 → 19,10
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.0.2 cleaner code for L_DI initialization
-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
-- 2008-03-08 123 1.0 Initial version
------------------------------------------------------------------------------
71,6 → 72,9
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/36-1 downto 0 generate
122,7 → 126,10
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
 
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/18-1 downto 0 generate
175,6 → 182,9
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/9-1 downto 0 generate
227,6 → 237,9
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/4-1 downto 0 generate
256,6 → 269,9
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/2-1 downto 0 generate
/trunk/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd
1,6 → 1,6
-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 406 2011-08-14 21:06:44Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
19,9 → 19,10
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.0.2 cleaner code for L_DI(A|B) initialization
-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
-- 2008-03-08 123 1.0 Initial version (merged from _rfirst/_wfirst)
------------------------------------------------------------------------------
79,6 → 80,10
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
159,6 → 164,10
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
239,6 → 248,10
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
319,6 → 332,10
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
362,6 → 379,10
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
/trunk/rtl/vlib/memlib/Makefile
1,7 → 1,8
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2007-12-09 100 1.0.1 drop ISE_p definition
# 2007-06-03 45 1.0 Initial version
#
8,7 → 9,7
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
.phony : all clean
.PHONY : all clean
#
all : $(NGC_all)
#
16,7 → 17,7
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#
/trunk/rtl/vlib/comlib/crc8.vhd
1,6 → 1,6
-- $Id: crc8.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: crc8.vhd 406 2011-08-14 21:06:44Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
31,9 → 31,10
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.0.1 remove superfluous variable r
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
 
78,13 → 79,9
end process proc_regs;
 
proc_next: process (R_CRC, DI, ENA)
 
variable r : slv8 := INIT;
variable n : slv8 := INIT;
 
begin
 
r := R_CRC;
n := R_CRC;
 
if ENA = '1' then
/trunk/rtl/vlib/comlib/comlib.vhd
1,6 → 1,6
-- $Id: comlib.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: comlib.vhd 400 2011-07-31 09:02:16Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
16,9 → 16,10
-- Description: communication components
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-30 400 1.3 added byte2word, word2byte
-- 2007-10-12 88 1.2.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.2 added procedure crc8_update_tbl
-- 2007-06-29 61 1.1.1 rename for crc8 SALT->INIT
34,6 → 35,34
 
package comlib is
 
component byte2word is -- 2 byte -> 1 word stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data (byte)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv16; -- output data (word)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end component;
 
component word2byte is -- 1 word -> 2 byte stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv16; -- input data (word)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data (byte)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end component;
 
component cdata2byte is -- 9bit comma,data -> byte stream
generic (
CPREF : slv4 := "1000"; -- comma prefix
83,7 → 112,7
procedure crc8_update_tbl (crc : inout slv8;
data : in slv8);
 
end comlib;
end package comlib;
 
-- ----------------------------------------------------------------------------
 
/trunk/rtl/vlib/comlib/misc/Makefile
1,13 → 1,14
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2007-11-26 98 1.0 Initial version
#
EXE_all = gen_crc8_tbl gen_crc8_tbl_check
#
#
.phony : all clean
.PHONY : all clean
#
all : $(EXE_all)
#
15,7 → 16,7
#
#-----
#
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
VBOM_all = $(wildcard *.vbom)
#
/trunk/rtl/vlib/comlib/Makefile
1,7 → 1,8
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.2 use includes from rtl/make
# 2007-07-06 64 1.1 use Makefile.xflow
# 2007-06-03 45 1.0 Initial version
#
8,7 → 9,7
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
.phony : all clean
.PHONY : all clean
#
all : $(NGC_all)
#
16,7 → 17,7
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#
/trunk/rtl/vlib/rbus/rbd_rbmon.vhd
1,4 → 1,4
-- $Id: rbd_rbmon.vhd 374 2011-03-27 17:02:47Z mueller $
-- $Id: rbd_rbmon.vhd 387 2011-07-03 17:24:52Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
33,17 → 33,17
-- 2010-12-27 349 1.0 Initial version
------------------------------------------------------------------------------
--
-- address layout:
-- bbbbbb00 : cntl
-- 00 : go/halt (writing 1 clears addr)
-- bbbbbb01 : alim: read-write register
-- 15:08 : hilim: upper address limit (def: ff)
-- 7:00 : lolim: lower address limit (def: 00)
-- bbbbbb10 : addr: read-write register
-- 15 : wrap: line address wrapped (read-only, cleared on write)
-- xx:02 : laddr: line address
-- 01:00 : waddr: word address
-- bbbbbb11 : data: read-write register
-- Address Bits Name r/w/f Function
-- bbbbbb00 cntl r/w/f Control register
-- 00 go r/w/f writing 1 clears add
-- bbbbbb01 alim r/w/- Address limit register
-- 15:08 hilim r/w/- upper address limit (def: ff)
-- 07:00 lolim r/w/- lower address limit (def: 00)
-- bbbbbb10 addr r/w/- Address register
-- 15 wrap r/0/- line address wrapped (cleared on write)
-- *:02 laddr r/w/- line address
-- 01:00 waddr r/w/- word address
-- bbbbbb11 data r/w/- Data register
--
-- data format:
-- word 3 15 : ack
/trunk/rtl/vlib/rbus/rbd_eyemon.vhd
1,4 → 1,4
-- $Id: rbd_eyemon.vhd 375 2011-04-02 07:56:47Z mueller $
-- $Id: rbd_eyemon.vhd 406 2011-08-14 21:06:44Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
137,6 → 137,8
begin
 
BRAM_DIA <= (others=>'0'); -- always 0, no writes on this port
BRAM : ram_2swsr_wfirst_gen
generic map (
AWIDTH => 9,
/trunk/rtl/vlib/rbus/rblib.vhd
1,6 → 1,6
-- $Id: rblib.vhd 349 2010-12-28 14:02:13Z mueller $
-- $Id: rblib.vhd 405 2011-08-14 08:16:28Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
20,6 → 20,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-13 405 3.0.3 add in direction for FADDR,SEL ports
-- 2010-12-26 349 3.0.2 add rb_sel
-- 2010-12-22 346 3.0.1 add rb_mon and rb_mon_sb;
-- 2010-12-04 343 3.0 extracted from rrilib and rritblib;
113,8 → 114,8
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
FADDR : slv3; -- field address
SEL : slbit; -- select
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : out slv(DWIDTH-1 downto 0); -- data
RB_MREQ : in rb_mreq_type; -- rbus request
RB_SRES : out rb_sres_type -- rbus response
127,8 → 128,8
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
FADDR : slv3; -- field address
SEL : slbit; -- select
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : out slv(DWIDTH-1 downto 0); -- data
RB_MREQ : in rb_mreq_type; -- rbus request
RB_SRES : out rb_sres_type -- rbus response
139,8 → 140,8
generic (
DWIDTH : positive := 16);
port (
FADDR : slv3; -- field address
SEL : slbit; -- select
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : in slv(DWIDTH-1 downto 0); -- data
RB_SRES : out rb_sres_type -- rbus response
);
189,5 → 190,4
);
end component;
 
 
end rblib;
end package rblib;
/trunk/rtl/vlib/rbus/Makefile
1,7 → 1,8
# $Id: Makefile 343 2010-12-05 21:24:38Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2007-12-09 100 1.0.1 drop ISE_p definition
# 2007-07-06 64 1.0 Initial version
#
8,7 → 9,7
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
.phony : all clean
.PHONY : all clean
#
all : $(NGC_all)
#
16,7 → 17,7
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#
/trunk/rtl/vlib/xlib/Makefile
1,13 → 1,14
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version omment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2007-12-08 100 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
.phony : all clean
.PHONY : all clean
#
all : $(NGC_all)
#
15,7 → 16,7
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#
/trunk/rtl/vlib/xlib/xlib.vhd
1,4 → 1,4
-- $Id: xlib.vhd 338 2010-11-13 22:19:25Z mueller $
-- $Id: xlib.vhd 389 2011-07-07 21:59:00Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
164,4 → 164,4
);
end component;
 
end xlib;
end package xlib;
/trunk/rtl/vlib/serport/tb/Makefile
1,7 → 1,8
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.3 use includes from rtl/make
# 2009-11-21 252 1.2 add ISim support
# 2007-11-26 98 1.1 use make includes
# 2007-06-03 48 1.0 Initial version
8,7 → 9,7
#
EXE_all = tb_serport_uart_rx tb_serport_uart_rxtx tb_serport_autobaud
#
.phony : all all_ssim all_tsim clean
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
18,9 → 19,9
#
#-----
#
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
include $(RETROBASE)/rtl/vlib/Makefile.isim
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_isim.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
/trunk/rtl/vlib/serport/Makefile
1,7 → 1,8
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2007-12-09 100 1.0.1 drop ISE_p definition
# 2007-07-03 45 1.0 Initial version
#
8,7 → 9,7
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
.phony : all clean
.PHONY : all clean
#
all : $(NGC_all)
#
16,7 → 17,7
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
include $(VBOM_all:.vbom=.dep_xst)
#
/trunk/rtl/vlib/serport/serport.vhd
1,4 → 1,4
-- $Id: serport.vhd 348 2010-12-26 15:23:44Z mueller $
-- $Id: serport.vhd 389 2011-07-07 21:59:00Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
134,4 → 134,4
);
end component;
 
end serport;
end package serport;
/trunk/rtl/make/syn_s3_speed.opt
0,0 → 1,40
FLOWTYPE = FPGA_SYNTHESIS;
#
# $Id: syn_s3_speed.opt 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 renamed, moved to rtl/make;
# 2007-07-20 67 1.0 Initial version
#
# Derived from ISE xst_vhdl.opt
#
# ----------------------------------------------------------------------------
# Options for XST
#
Program xst
-ifn <design>_xst.scr; # input XST script file
-ofn <design>_xst.log; # output XST log file
-intstyle xflow; # Message Reporting Style
#
# ParamFile lists the XST Properties that can be set by the user.
#
ParamFile: <design>_xst.scr
"run";
#
# Global Synthesis Options
#
"-ifn <synthdesign>"; # Input/Project File Name
"-ifmt VHDL"; # Input Format (Verilog or VHDL)
"-ofn <design>"; # Output File Name
"-ofmt ngc"; # Output File Format
"-p <partname>"; # Target Device
"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
"-opt_level 2"; # Optimization Effort Criteria: 2=High
"-uc <design>.xcf"; # Constraint File name
#
# The following are HDL Options
#
End ParamFile
End Program xst
#
/trunk/rtl/make/generic_ghdl.mk
0,0 → 1,48
# $Id: generic_ghdl.mk 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.3 renamed, moved to rtl/make;
# 2007-11-04 95 1.2.2 fix find statement in ghdl_tmp_clean
# 2007-11-02 94 1.2.1 don't delete cext_*.o in ghdl_tmp_clean
# 2007-07-08 65 1.2 support now autobuilding of _fsim and _tsim models
# 2007-06-16 57 1.1 cleanup ghdl_clean handling
# 2007-06-10 52 1.0 Initial version
#
GHDLIEEE = --ieee=synopsys
GHDLUNISIM = -P$(XILINX)/ghdl/unisim
GHDLSIMPRIM = -P$(XILINX)/ghdl/simprim
GHDL = ghdl
COMPILE.vhd = $(GHDL) -a $(GHDLIEEE)
LINK.vhd = $(GHDL) -e $(GHDLIEEE)
#
% : %.vbom
vbomconv --ghdl_i $<
vbomconv --ghdl_m $<
#
# rules for _[ft]sim to use 'virtual' [ft]sim vbom's (derived from _ssim)
#
%_fsim : %_ssim.vbom
vbomconv --ghdl_i $*_fsim.vbom
vbomconv --ghdl_m $*_fsim.vbom
#
%_tsim : %_ssim.vbom
vbomconv --ghdl_i $*_tsim.vbom
vbomconv --ghdl_m $*_tsim.vbom
#
%.dep_ghdl: %.vbom
vbomconv --dep_ghdl $< > $@
#
.PHONY: ghdl_clean ghdl_tmp_clean
#
ghdl_clean: ghdl_tmp_clean
rm -f $(EXE_all)
rm -f $(EXE_all:%=%_[sft]sim)
rm -f $(EXE_all:%=%.exe)
rm -f $(EXE_all:%=%_[sft]sim.exe)
rm -f cext_*.o
#
ghdl_tmp_clean:
find -maxdepth 1 -name "*.o" | grep -v "^\./cext_" | xargs rm -f
rm -f work-obj93.cf
#
/trunk/rtl/make/imp_s3_speed_maptd.opt
0,0 → 1,92
FLOWTYPE = FPGA;
#
# $Id: imp_s3_speed_maptd.opt 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 renamed, moved to rtl/make;
# 2007-07-20 67 1.0 Initial version
#
# Derived from ISE balanced.opt
# Uses timing driven map like 'mapphyssynthesis' SmartExplorer strategy
#
# ----------------------------------------------------------------------------
# Options for Translator
#
# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
#
Program ngdbuild
-p <partname>; # Partname to use - picked from xflow commandline
-nt timestamp; # NGO File generation. Regenerate only when
# source netlist is newer than existing
# NGO file (default)
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
<userdesign>; # User design - pick from xflow command line
<design>.ngd; # Name of NGD file. Filebase same as design filebase
End Program ngdbuild
 
#
# ----------------------------------------------------------------------------
# Options for Mapper
#
# Type "map -h <arch>" for a detailed list of map command line options
#
Program map
-o <design>_map.ncd; # Output Mapped ncd file
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-timing; # Perform a timing-driven packing
-ol high; # Effort level
-xe n; # Extra effort level for timing-driven packing (normal)
-register_duplication on;# Duplicate registers/luts during timing-driven packing
-logic_opt on; # Perform physical synthesis combinatorial logic opt.
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
 
#
# ----------------------------------------------------------------------------
# Options for Post Map Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_map_trce
-v 3; # Produce verbose timing report
#-e 3; # Produce error report (limit 3 items/constraint)
-xml <design>_map.twx; # Output XML version of the timing report
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
<inputdir><design>_map.ncd; # Input mapped ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_map_trce
 
#
# ----------------------------------------------------------------------------
# Options for Place and Route
#
# Type "par -h" for a detailed list of par command line options
#
Program par
-w; # Overwrite existing placed and routed ncd
-ol high; # Overall effort level
-xe n; # Extra effort level
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
<design>_map.ncd; # Input mapped NCD file
<inputdir><design>.ncd; # Output placed and routed NCD
<inputdir><design>.pcf; # Input physical constraints file
END Program par
 
#
# ----------------------------------------------------------------------------
# Options for Post Par Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_par_trce
-v 3; # Produce verbose timing report
#-e 3; # Produce error report (limit 3 items/constraint)
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-xml <design>.twx; # Output XML version of the timing report
<inputdir><design>.ncd; # Input placed and routed ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_par_trce
 
 
/trunk/rtl/make/generic_xflow.mk
0,0 → 1,287
# $Id: generic_xflow.mk 406 2011-08-14 21:06:44Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-14 406 1.7.1 use isemsg_filter; new %.mfsum target
# 2011-08-13 405 1.7 renamed, moved to rtl/make;
# 2011-07-17 394 1.6.2 add rm *.svf to ise_clean rule
# 2011-07-11 392 1.6.1 use config_wrapper, support jtag via svf generation
# 2011-06-26 385 1.6 use ISE_PATH for vbomconv -xst_prj
# 2010-11-26 340 1.5.8 fix path for .opt defaults (now rtl/vlib)
# 2010-05-06 289 1.5.7 add xilinx_tsim_xon support
# 2010-04-24 282 1.5.6 add %.impact rule to run impact_wrapper
# 2010-04-17 278 1.4.5 add '|| true' after grep in diag summary to prevent
# a make abort in case no diags are seen
# 2010-04-02 273 1.4.4 add -I{RETROBASE} to ucf_cpp processing rules
# 2010-03-14 268 1.4.3 add XFLOWOPT_SYN and XFLOWOPT_IMP
# 2009-11-21 252 1.4.2 use bitgen directly, use ISE_USERID
# 2007-12-17 102 1.4.1 fix %.dep_ucf_cpp : %.ucf_cpp rule
# 2007-12-16 101 1.4 add ucf_cpp rules
# 2007-12-09 100 1.3.7 ifndef define ISE_PATH to xc3s1000-ft256-4
# 2007-11-02 94 1.3.6 use .SECONDARY to keep intermediate files
# 2007-10-28 93 1.3.5 call xst_count_bels -xsts when _ssim is generated
# 2007-10-12 88 1.3.4 support <design>.xcf files, if provided
# 2007-10-06 87 1.3.3 remove *_twr.log in clean
# 2007-07-20 67 1.3.2 handle local/global xst_vhdl.opt
# 2007-07-15 66 1.3.1 add rule "%.ngc: ../%.vbom" to support _*sim in ./tb
# add XST diagnostics summary at end of listing
# 2007-07-06 64 1.3 all vbom based now
# 2007-06-16 57 1.2.1 cleanup ghdl_clean handling (rm _[sft]sim)
# 2007-06-10 52 1.2 reorganized svn directory structure
# 2007-06-10 51 1.1 consolidate test bench generation
# 2007-06-03 45 1.0 Initial version
#---
#
# setup default board (for impact), device and userid (for bitgen)
#
ifndef ISE_BOARD
ISE_BOARD = s3board
endif
#
ifndef ISE_PATH
ISE_PATH = xc3s1000-ft256-4
endif
#
ifndef ISE_USERID
ISE_USERID = 0xffffffff
endif
#
# setup defaults for xflow option files for synthesis and implementation
#
ifndef XFLOWOPT_SYN
XFLOWOPT_SYN = syn_s3_speed.opt
endif
#
ifndef XFLOWOPT_IMP
XFLOWOPT_IMP = imp_s3_speed.opt
endif
#
XFLOW = xflow -p ${ISE_PATH}
#
# $@ first target
# $< first dependency
# $* stem in rule match
#
# when chaining, don't delete 'expensive' intermediate files:
.SECONDARY :
#
# Synthesize (xst)
# input: %.vbom vbom project description
# output: %.ngc
# %_xst.log xst log file
#
%.ngc: %.vbom
if [ ! -d ./ise ]; then mkdir ./ise; fi
(cd ./ise; vbomconv --ise_path=${ISE_PATH} --xst_prj ../$< > $*.prj)
(cd ./ise; touch $*.xcf)
if [ -r $*.xcf ]; then cp $*.xcf ./ise; fi
if [ -r ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ]; then \
cp ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ./ise; fi
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi
if [ -r ./ise/$*_xst.log ]; then cp -p ./ise/$*_xst.log .; fi
@ echo "==============================================================="
@ echo "* XST Diagnostic Summary *"
@ echo "==============================================================="
@ if [ -r $*.mfset ]; then isemsg_filter xst $*.mfset $*_xst.log; fi
@ if [ ! -r $*.mfset ]; then grep -i -A 1 ":.*:" $*_xst.log || true; fi
@ echo "==============================================================="
#
# the following rule needed to generate an %_*sim.vhd in a ./tb sub-directory
# it will look for a matching vbom in the parent directory
%.ngc: ../%.vbom
if [ ! -d ./ise ]; then mkdir ./ise; fi
(cd ./ise; vbomconv --xst_prj ../$< > $*.prj)
(cd ./ise; touch $*.xcf)
if [ -r $*.xcf ]; then cp $*.xcf ./ise; fi
if [ -r ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ]; then \
cp ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ./ise; fi
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi
if [ -r ./ise/$*_xst.log ]; then cp -p ./ise/$*_xst.log .; fi
@ echo "==============================================================="
@ echo "* XST Diagnostic Summary *"
@ echo "==============================================================="
@ if [ -r $*.mfset ]; then isemsg_filter xst $*.mfset $*_xst.log; fi
@ if [ ! -r $*.mfset ]; then grep -i -A 1 ":.*:" $*_xst.log || true; fi
@ echo "==============================================================="
#
# Implement 1 (map+par)
# input: %.ngc
# %.ucf constraint file (if available)
# output: %.ncd
# %.pcf
# %_tra.log translate (ngdbuild) log file (renamed %.bld)
# %_map.log map log file (renamed %_map.mrp)
# %_par.log par log file (renamed %.par)
# %_pad.log pad file (renamed %_pad.txt)
# %_twr.log trce log file (renamed %.twr)
#
%.ncd %.pcf: %.ngc
if [ ! -d ./ise ]; then mkdir ./ise; fi
if [ -r $*.ngc ]; then cp -p $*.ngc ./ise; fi
if [ -r $*.ucf ]; then cp -p $*.ucf ./ise; fi
if [ -r ${RETROBASE}/rtl/make/${XFLOWOPT_IMP} ]; then \
cp ${RETROBASE}/rtl/make/${XFLOWOPT_IMP} ./ise; fi
if [ -r ${XFLOWOPT_IMP} ]; then cp -p ${XFLOWOPT_IMP} ./ise; fi
${XFLOW} -wd ise -implement ${XFLOWOPT_IMP} $<
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ncd ]; then cp -p ./ise/$*.ncd .; fi
if [ -r ./ise/$*.pcf ]; then cp -p ./ise/$*.pcf .; fi
if [ -r ./ise/$*.bld ]; then cp -p ./ise/$*.bld ./$*_tra.log; fi
if [ -r ./ise/$*_map.mrp ]; then cp -p ./ise/$*_map.mrp ./$*_map.log; fi
if [ -r ./ise/$*.par ]; then cp -p ./ise/$*.par ./$*_par.log; fi
if [ -r ./ise/$*_pad.txt ]; then cp -p ./ise/$*_pad.txt ./$*_pad.log; fi
if [ -r ./ise/$*.twr ]; then cp -p ./ise/$*.twr ./$*_twr.log; fi
#
# Implement 2 (bitgen)
# input: %.ncd
# output: %.bit
# %.msk
# %_bgn.log bitgen log file (renamed %.bgn)
#
%.bit: %.ncd
if [ ! -d ./ise ]; then mkdir ./ise; fi
if [ -r $*.ncd ]; then cp -p $*.ncd ./ise; fi
(cd ./ise; bitgen -l -w -m -g ReadBack -g UserId:${ISE_USERID} -intstyle xflow $*.ncd)
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.bit ]; then cp -p ./ise/$*.bit .; fi
if [ -r ./ise/$*.msk ]; then cp -p ./ise/$*.msk .; fi
if [ -r ./ise/$*.bgn ]; then cp -p ./ise/$*.bgn ./$*_bgn.log; fi
#
# Create svf from bitstream
# input: %.bit
# output: %.svf
#
%.svf: %.bit
config_wrapper --board=${ISE_BOARD} --path=${ISE_PATH} bit2svf $*.bit
 
#
# Configure FPGA with impact
# input: %.bit
# output: .PHONY
#
%.iconfig: %.bit
config_wrapper --board=${ISE_BOARD} --path=${ISE_PATH} iconfig $*.bit
 
#
# Configure FPGA with jtag
# input: %.svf
# output: .PHONY
#
%.jconfig: %.svf
config_wrapper --board=${ISE_BOARD} --path=${ISE_PATH} jconfig $*.svf
 
#
# Print log file summary
# input: %_*.log (not depended)
# output: .PHONY
%.mfsum: %.mfset
@ echo "=== XST summary ============================================="
@ if [ -r $*_xst.log ]; then isemsg_filter xst $*.mfset $*_xst.log; fi
@ echo "=== Translate summary ======================================="
@ if [ -r $*_tra.log ]; then isemsg_filter tra $*.mfset $*_tra.log; fi
@ echo "=== MAP summary ============================================="
@ if [ -r $*_map.log ]; then isemsg_filter map $*.mfset $*_map.log; fi
@ echo "=== PAR summary ============================================="
@ if [ -r $*_par.log ]; then isemsg_filter par $*.mfset $*_par.log; fi
@ echo "=== Bitgen summary =========================================="
@ if [ -r $*_bgn.log ]; then isemsg_filter bgn $*.mfset $*_bgn.log; fi
 
#
#
#
# Post-XST simulation model (netgen -sim; UNISIM based)
# input: %.ngc
# output: %_ssim.vhd
# %_ngn_ssim.log netgen log file (renamed %.nlf)
#
%_ssim.vhd: %.ngc
if [ ! -d ./ise ]; then mkdir ./ise; fi
if [ -r $*.ngc ]; then cp -p $*.ngc ./ise; fi
(cd ise; netgen -sim -intstyle xflow -ofmt vhdl -w $*.ngc)
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.vhd ]; then cp -p ./ise/$*.vhd ./$*_ssim.vhd; fi
if [ -r ./ise/$*.nlf ]; then cp -p ./ise/$*.nlf ./$*_ngn_ssim.log; fi
if [ -r $*_ssim.vhd ]; then xst_count_bels -xsts $*_ssim.vhd; fi
#
# Post-XST simulation model (netgen -sim; SIMPRIM based)
# input: %.ngc
# output: %_fsim.vhd
# %_ngn_fsim.log netgen log file (renamed %.nlf)
#
%_fsim.vhd: %.ngc
if [ ! -d ./ise ]; then mkdir ./ise; fi
if [ -r $*.ngc ]; then cp -p $*.ngc ./ise; fi
(cd ise; ngdbuild -p ${ISE_PATH} -nt timestamp -intstyle xflow \
$*.ngc $*.ngd)
(cd ise; netgen -sim -intstyle xflow -ofmt vhdl -w $*.ngd)
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.vhd ]; then cp -p ./ise/$*.vhd ./$*_fsim.vhd; fi
if [ -r ./ise/$*.nlf ]; then cp -p ./ise/$*.nlf ./$*_ngn_fsim.log; fi
#
# Post-par timing simulation model (netgen -sim)
# input: %.ncd
# output: %_tsim.vhd
# %_ngn_tsim.log netgen log file (renamed time_sim.nlf)
#
#!! use netgen directly because xflow 8.1 goes mad when -tsim used a 2nd time
#!! see blog_xilinx_webpack.txt 2007-06-10
#
%_tsim.vhd %_tsim.sdf: %.ncd
if [ ! -d ./ise ]; then mkdir ./ise; fi
if [ -r $*.ncd ]; then cp -p $*.ncd ./ise; fi
if [ -r $*.pcf ]; then cp -p $*.pcf ./ise; fi
(cd ise; netgen -ofmt vhdl -sim -w -intstyle xflow -pcf \
$*.pcf $*.ncd $*_tsim.vhd )
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*_tsim.vhd ]; then cp -p ./ise/$*_tsim.vhd .; fi
if [ -r ./ise/$*_tsim.sdf ]; then cp -p ./ise/$*_tsim.sdf .; fi
if [ -r ./ise/$*_tsim.nlf ]; then cp -p ./ise/$*_tsim.nlf ./$*_ngn_tsim.log; fi
if [ -r $*_tsim.vhd -a -r $*.tsim_xon_dat ]; then xilinx_tsim_xon $*; fi
#
# generate dep_xst files from vbom
#
%.dep_xst: %.vbom
vbomconv --dep_xst $< > $@
#
# generate cpp'ed ucf files from ucf_cpp
#
%.ucf : %.ucf_cpp
cpp -I${RETROBASE}/rtl $*.ucf_cpp $*.ucf
#
# generate nested dependency rules for cpp'ed ucf files from ucf_cpp
#
%.dep_ucf_cpp : %.ucf_cpp
cpp -I${RETROBASE}/rtl -MM $*.ucf_cpp |\
sed 's/\.o:/\.ucf:/' > $*.dep_ucf_cpp
#
.PHONY : ise_clean ise_tmp_clean
#
ise_clean: ise_tmp_clean
rm -rf *.ngc
rm -rf *.ncd
rm -rf *.pcf
rm -rf *.bit
rm -rf *.msk
rm -rf *.svf
rm -rf *_[sft]sim.vhd
rm -rf *_tsim.sdf
rm -rf *_xst.log
rm -rf *_tra.log
rm -rf *_map.log
rm -rf *_par.log
rm -rf *_pad.log
rm -rf *_twr.log
rm -rf *_bgn.log
rm -rf *_ngn_[sft]sim.log
rm -rf *_svn.log
rm -rf *_sum.log
#
ise_tmp_clean:
rm -rf ./ise
#
/trunk/rtl/make/syn_s6_speed.opt
0,0 → 1,40
FLOWTYPE = FPGA_SYNTHESIS;
#
# $Id: syn_s6_speed.opt 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.0 Initial version
#
# Derived from ISE xst_mixed.opt
#
# ----------------------------------------------------------------------------
# Options for XST
#
Program xst
-ifn <design>_xst.scr; # input XST script file
-ofn <design>_xst.log; # output XST log file
-intstyle xflow; # Message Reporting Style
#
# ParamFile lists the XST Properties that can be set by the user.
#
ParamFile: <design>_xst.scr
"run";
#
# Global Synthesis Options
#
"-ifn <synthdesign>"; # Input/Project File Name
"-ifmt mixed"; # Input Format (Verilog and VHDL)
"-ofn <design>"; # Output File Name
"-ofmt ngc"; # Output File Format
"-top <design>"; # Top Design Name
"-p <partname>"; # Target Device
"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
"-opt_level 2"; # Optimization Effort Criteria: 2=High
"-uc <design>.xcf"; # Constraint File name
#
# The following are HDL Options
#
End ParamFile
End Program xst
#
/trunk/rtl/make/generic_isim.mk
0,0 → 1,50
# $Id: generic_isim.mk 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.2 renamed, moved to rtl/make;
# 2010-04-26 284 1.1 add _[sft]sim support
# 2009-11-22 252 1.0 Initial version
#
FUSE = fuse
#
%_ISim : %.vbom
vbomconv -isim_prj $< > $*_isim.prj
$(FUSE) $* -prj $*_isim.prj -o $*_ISim
rm -rf $*_isim.prj
#
# rule for _ssim to call FUSE with right top level name
#
%_ISim_ssim : %_ssim.vbom
vbomconv -isim_prj $*_ssim.vbom > $*_isim_ssim.prj
$(FUSE) $* -prj $*_isim_ssim.prj -o $*_ISim_ssim
rm -rf $*_isim_ssim.prj
#
# rule for _[ft]sim to use 'virtual' _[ft]sim vbom's (derived from _ssim)
#
%_ISim_fsim : %_ssim.vbom
vbomconv -isim_prj $*_fsim.vbom > $*_isim_fsim.prj
$(FUSE) $* -prj $*_isim_fsim.prj -o $*_ISim_fsim
rm -rf $*_isim_fsim.prj
#
%_ISim_tsim : %_ssim.vbom
vbomconv -isim_prj $*_tsim.vbom > $*_isim_tsim.prj
$(FUSE) $* -prj $*_isim_tsim.prj -o $*_ISim_tsim
rm -rf $*_isim_tsim.prj
#
%.dep_isim: %.vbom
vbomconv --dep_isim $< > $@
#
.PHONY: isim_clean isim_tmp_clean
#
isim_clean: isim_tmp_clean
rm -f $(EXE_all:%=%_ISim)
rm -f $(EXE_all:%=%_ISim_ssim)
rm -f $(EXE_all:%=%_ISim_fsim)
rm -f $(EXE_all:%=%_ISim_tsim)
#
isim_tmp_clean:
rm -f isim.log isim.wdb
rm -f fuse.log
rm -rf isim
#
/trunk/rtl/make/generic_xflow_cpld.mk
0,0 → 1,130
# $Id: generic_xflow_cpld.mk 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 renamed, moved to rtl/make;
# 2010-03-13 268 1.0 Initial version, cloned from .xflow Rev 252
#---
#
# setup default device
#
ifndef ISE_PATH
ISE_PATH = xc2c64a-7-vq44
endif
#
# setup defaults for xflow option files for synthesis and implementation
#
ifndef XFLOWOPT_SYN
XFLOWOPT_SYN = xst_vhdl.opt
endif
#
ifndef XFLOWOPT_IMP
XFLOWOPT_IMP = balanced.opt
endif
#
XFLOW = xflow -p ${ISE_PATH}
#
# $@ first target
# $< first dependency
# $* stem in rule match
#
# when chaining, don't delete 'expensive' intermediate files:
.SECONDARY :
#
# Synthesize (xst)
# input: %.prj project file
# output: %.ngc
# %_xst.log xst log file
#
# Note: removed "cp ${RETROBASE}/vlib/${XFLOWOPT_SYN} ./ise" option
#
%.ngc: %.vbom
if [ ! -d ./ise ]; then mkdir ./ise; fi
(cd ./ise; vbomconv --xst_prj ../$< > $*.prj)
(cd ./ise; touch $*.xcf)
if [ -r $*.xcf ]; then cp $*.xcf ./ise; fi
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi
if [ -r ./ise/$*_xst.log ]; then cp -p ./ise/$*_xst.log .; fi
@ echo "==============================================================="
@ echo "* Makefile.xflow: XST Diagnostic Summary *"
@ echo "==============================================================="
@ grep -i -A 1 ":.*:" $*_xst.log
@ echo "==============================================================="
#
# the following rule needed to generate an %_*sim.vhd in a ./tb sub-directory
# it will look for a matching vbom in the parent directory
%.ngc: ../%.vbom
if [ ! -d ./ise ]; then mkdir ./ise; fi
(cd ./ise; vbomconv --xst_prj ../$< > $*.prj)
(cd ./ise; touch $*.xcf)
if [ -r $*.xcf ]; then cp $*.xcf ./ise; fi
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi
if [ -r ./ise/$*_xst.log ]; then cp -p ./ise/$*_xst.log .; fi
@ echo "==============================================================="
@ echo "* Makefile.xflow: XST Diagnostic Summary *"
@ echo "==============================================================="
@ grep -i -A 1 ":.*:" $*_xst.log
@ echo "==============================================================="
#
# Fit (map + cpldfit +
# input: %.ngc project file
# output: %.ncd
# %.jed
# %_tra.log translate (ngdbuild) log file (renamed %.bld)
# %_fit.log cpldfit log file (renamed %.rpt)
# %_tim.log timing analyser log file (renamed %.tim)
# %_pad.log pad file (renamed %.pad)
#
# Note: removed "cp ${RETROBASE}/vlib/balanced.opt" option
# currently ise 'density.opt' as steering file
#
%.ncd %.jed: %.ngc
if [ ! -d ./ise ]; then mkdir ./ise; fi
if [ -r $*.ngc ]; then cp -p $*.ngc ./ise; fi
if [ -r $*.ucf ]; then cp -p $*.ucf ./ise; fi
if [ -r ${XFLOWOPT_IMP} ]; then cp -p ${XFLOWOPT_IMP} ./ise; fi
${XFLOW} -wd ise -fit ${XFLOWOPT_IMP} $<
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ncd ]; then cp -p ./ise/$*.ncd .; fi
if [ -r ./ise/$*.jed ]; then cp -p ./ise/$*.jed .; fi
if [ -r ./ise/$*.bld ]; then cp -p ./ise/$*.bld ./$*_tra.log; fi
if [ -r ./ise/$*.rpt ]; then cp -p ./ise/$*.rpt ./$*_fit.log; fi
if [ -r ./ise/$*.tim ]; then cp -p ./ise/$*.tim ./$*_tim.log; fi
if [ -r ./ise/$*.pad ]; then cp -p ./ise/$*.pad ./$*_pad.log; fi
#
# generate dep_xst files from vbom
#
%.dep_xst: %.vbom
vbomconv --dep_xst $< > $@
#
# generate cpp'ed ucf files from ucf_cpp
#
%.ucf : %.ucf_cpp
cpp $*.ucf_cpp $*.ucf
#
# generate nested dependency rules for cpp'ed ucf files from ucf_cpp
#
%.dep_ucf_cpp : %.ucf_cpp
cpp -MM $*.ucf_cpp | sed 's/\.o:/\.ucf:/' > $*.dep_ucf_cpp
#
.PHONY : ise_clean ise_tmp_clean
#
ise_clean: ise_tmp_clean
rm -rf *.ngc
rm -rf *.ncd
rm -rf *.jed
rm -rf *_xst.log
rm -rf *_tra.log
rm -rf *_fit.log
rm -rf *_tim.log
rm -rf *_pad.log
#
ise_tmp_clean:
rm -rf ./ise
#
/trunk/rtl/make/imp_s3_speed.opt
0,0 → 1,86
FLOWTYPE = FPGA;
#
# $Id: imp_s3_speed.opt 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 renamed, moved to rtl/make;
# 2007-07-20 67 1.0 Initial version
#
# Derived from ISE balanced.opt
#
# ----------------------------------------------------------------------------
# Options for Translator
#
# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
#
Program ngdbuild
-p <partname>; # Partname to use - picked from xflow commandline
-nt timestamp; # NGO File generation. Regenerate only when
# source netlist is newer than existing
# NGO file (default)
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
<userdesign>; # User design - pick from xflow command line
<design>.ngd; # Name of NGD file. Filebase same as design filebase
End Program ngdbuild
 
#
# ----------------------------------------------------------------------------
# Options for Mapper
#
# Type "map -h <arch>" for a detailed list of map command line options
#
Program map
-o <design>_map.ncd; # Output Mapped ncd file
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
 
#
# ----------------------------------------------------------------------------
# Options for Post Map Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_map_trce
-v 3; # Produce verbose timing report
#-e 3; # Produce error report (limit 3 items/constraint)
-xml <design>_map.twx; # Output XML version of the timing report
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
<inputdir><design>_map.ncd; # Input mapped ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_map_trce
 
#
# ----------------------------------------------------------------------------
# Options for Place and Route
#
# Type "par -h" for a detailed list of par command line options
#
Program par
-w; # Overwrite existing placed and routed ncd
-ol high; # Overall effort level
-xe n; # extra effort level
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
<design>_map.ncd; # Input mapped NCD file
<inputdir><design>.ncd; # Output placed and routed NCD
<inputdir><design>.pcf; # Input physical constraints file
END Program par
 
#
# ----------------------------------------------------------------------------
# Options for Post Par Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_par_trce
-v 3; # Produce verbose timing report
#-e 3; # Produce error report (limit 3 items/constraint)
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-xml <design>.twx; # Output XML version of the timing report
<inputdir><design>.ncd; # Input placed and routed ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_par_trce
 
 
/trunk/rtl/make/imp_s6_speed.opt
0,0 → 1,92
FLOWTYPE = FPGA;
#
# $Id: imp_s6_speed.opt 405 2011-08-14 08:16:28Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.0 Initial version
#
# Derived from ISE balanced.opt
# Uses uses settings like 'mapgloboptlogoptregdup' SmartExplorer strategy
#
# ----------------------------------------------------------------------------
# Options for Translator
#
# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
#
Program ngdbuild
-p <partname>; # Partname to use - picked from xflow commandline
-nt timestamp; # NGO File generation. Regenerate only when
# source netlist is newer than existing
# NGO file (default)
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
<userdesign>; # User design - pick from xflow command line
<design>.ngd; # Name of NGD file. Filebase same as design filebase
End Program ngdbuild
 
#
# ----------------------------------------------------------------------------
# Options for Mapper
#
# Type "map -h <arch>" for a detailed list of map command line options
#
Program map
-o <design>_map.ncd; # Output Mapped ncd file
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-ol high; # Effort level
-xe n; # Extra effort level for timing-driven packing (normal)
-global_opt speed; # Perform global optimization before mapping
-logic_opt on; # Perform physical synthesis combinatorial logic opt.
-register_duplication on;# Duplicate registers/luts during timing-driven packing
-w; # Always overwrite any existing output files
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
 
#
# ----------------------------------------------------------------------------
# Options for Post Map Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_map_trce
-v 3; # Produce verbose timing report
#-e 3; # Produce error report (limit 3 items/constraint)
-xml <design>_map.twx; # Output XML version of the timing report
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
<inputdir><design>_map.ncd; # Input mapped ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_map_trce
 
#
# ----------------------------------------------------------------------------
# Options for Place and Route
#
# Type "par -h" for a detailed list of par command line options
#
Program par
-w; # Overwrite existing placed and routed ncd
-ol high; # Overall effort level
-xe n; # extra effort level
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
<design>_map.ncd; # Input mapped NCD file
<inputdir><design>.ncd; # Output placed and routed NCD
<inputdir><design>.pcf; # Input physical constraints file
END Program par
 
#
# ----------------------------------------------------------------------------
# Options for Post Par Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_par_trce
-v 3; # Produce verbose timing report
#-e 3; # Produce error report (limit 3 items/constraint)
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-xml <design>.twx; # Output XML version of the timing report
<inputdir><design>.ncd; # Input placed and routed ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_par_trce
 
 
trunk/rtl/make Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: trunk/doc/INSTALL.txt =================================================================== --- trunk/doc/INSTALL.txt (revision 11) +++ trunk/doc/INSTALL.txt (revision 12) @@ -1,4 +1,4 @@ -# $Id: INSTALL.txt 376 2011-04-17 12:24:07Z mueller $ +# $Id: INSTALL.txt 408 2011-09-12 19:48:36Z mueller $ Guide to install and build w11a systems, test benches and support software @@ -40,9 +40,12 @@ (Xilinx xst based) as well as the support software (mainly the rlink backend server) requires - - the definition of the environment variable RETROBASE + - the definition of the environment variables: + - RETROBASE: must refer to the installation root directory + - BOOSTINC: pathname for includes of boost library - that the tools binary directory is in the path - that the tools library directory is in the library path + For bash and alike use @@ -50,6 +53,11 @@ export PATH=$PATH:$RETROBASE/tools/bin export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RETROBASE/tools/lib + In most cases the boost library version coming with the distribution will + work, in those cases simply use + + export BOOSTINC=/usr/include + After that building functional model based test benches will work. If you want to also build post-xst or post-par test benches read next section. @@ -79,6 +87,14 @@ 4a. Compile sharable libraries --------------------------------------- + Required tools and libraries: + g++ >= 4.3 (decltype support assumed in usage of boost::bind) + boost >= 1.35 (boost::thread api changed, new one is used) + + Build was tested under: + ubuntu lucid (10.04 LTS): gcc 4.4.3 boost 1.40.0 + debian lenny (5.0.8): gcc 4.3.2 boost 1.xx.x (t.b.c.) + To build all sharable libraries cd $RETROBASE/tools/src @@ -191,7 +207,7 @@ To load the bitfile with WebPack impact into the target board use - make .impact + make .iconfig If only the xst or par output is wanted just use
/trunk/doc/README.txt
1,4 → 1,4
# $Id: README.txt 376 2011-04-17 12:24:07Z mueller $
# $Id: README.txt 408 2011-09-12 19:48:36Z mueller $
 
Release notes for w11a
 
60,6 → 60,34
 
3. Change Log ----------------------------------------------------------------
 
- trunk (2011-09-11: svn rev 12(oc) 408(wfjm); untagged w11a_V0.531) +++++++++
 
- Summary
- Many small changes to prepare upcoming support for
- Spartan-6 boards (nexys3 and atlys)
- usage of Cypress FX2 USB interface on nexys2/3 and atlys boards
- no functional change of w11a CPU core or any test systems
 
- Changes
- use boost libraries instead of custom coding:
- boost/function and /bind for callbacks, retire RmethDscBase and RmethDsc
- boost/foreach for some iterator loops
Note: boost 1.35 and gcc 4.3 or newer is required, see INSTALL.txt
- module renames:
bplib/s3board/s3_rs232_iob_int -> bplib/bpgen/bp_rs232_2line_iob
bplib/s3board/s3_rs232_iob_ext -> bplib/bpgen/bp_rs232_4line_iob
bplib/s3board/s3_dispdrv -> bplib/bpgen/sn_4x7segctl
bplib/s3board/s3_humanio -> bplib/bpgen/sn_humanio
bplib/s3board/s3_humanio_rbus -> bplib/bpgen/sn_humanio_rbus
- other renames:
tools/bin/impact_wrapper -> tools/bin/config_wrapper
- reorganize Makefile includes and xflow option files
rtl/vlib/Makefile.ghdl -> rtl/make/generic_ghdl.mk
rtl/vlib/Makefile.isim -> rtl/make/generic_isim.mk
rtl/vlib/Makefile.xflow -> rtl/make/generic_xflow.mk
rtl/vlib/xst_vhdl.opt -> rtl/make/syn_s3_speed.opt
rtl/vlib/balanced.opt -> rtl/make/imp_s3_speed.opt
 
- trunk (2011-04-17: svn rev 11(oc) 376(wfjm); untagged w11a_V0.53) ++++++++++
 
- Summary

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