OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

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Rev 36 → Rev 37

/trunk/Makefile
1,4 → 1,4
# $Id: Makefile 772 2016-06-05 12:55:11Z mueller $
# $Id: Makefile 810 2016-10-02 16:51:12Z mueller $
#
# 'Meta Makefile' for whole retro project
# allows to make all synthesis targets
6,8 → 6,11
#
# Revision History:
# Date Rev Version Comment
# 2016-10-01 810 1.2.6 move component tests to SIM_viv when vivado used
# 2016-07-10 785 1.2.5 re-enable rtl/sys_gen/tst_sram/nexys4 (ok in 2016.2)
# 2016-06-05 772 1.2.4 add vmfsum,imfsum targets
# 2016-03-19 748 1.2.3 comment out legacy designs and tests
# 2016-02-19 733 1.2.2 disable rtl/sys_gen/tst_sram/nexys4 (fails in 2015.4)
# 2016-02-19 732 1.2.1 remove dispunit syn and sim entries
# 2015-02-01 640 1.2 add vivado targets, separate from ise targets
# 2015-01-25 638 1.1 drop as type fx2 targets
29,6 → 32,7
SYN_ise += rtl/sys_gen/tst_rlink/s3board
SYN_ise += rtl/sys_gen/tst_serloop/s3board
SYN_ise += rtl/sys_gen/tst_snhumanio/s3board
SYN_ise += rtl/sys_gen/tst_sram/s3board
SYN_ise += rtl/sys_gen/w11a/s3board
 
# Nexys2 -------------------------------------
39,6 → 43,7
#SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3
SYN_ise += rtl/sys_gen/tst_serloop/nexys2
SYN_ise += rtl/sys_gen/tst_snhumanio/nexys2
SYN_ise += rtl/sys_gen/tst_sram/nexys2
SYN_ise += rtl/sys_gen/w11a/nexys2
 
# Nexys3 -------------------------------------
48,6 → 53,7
SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic
SYN_ise += rtl/sys_gen/tst_serloop/nexys3
SYN_ise += rtl/sys_gen/tst_snhumanio/nexys3
SYN_ise += rtl/sys_gen/tst_sram/nexys3
SYN_ise += rtl/sys_gen/w11a/nexys3
 
# Vivado based targets, by board type --------------------
61,6 → 67,7
SYN_viv += rtl/sys_gen/tst_rlink/nexys4
SYN_viv += rtl/sys_gen/tst_serloop/nexys4
SYN_viv += rtl/sys_gen/tst_snhumanio/nexys4
SYN_viv += rtl/sys_gen/tst_sram/nexys4
SYN_viv += rtl/sys_gen/w11a/nexys4
 
# Arty ---------------------------------------
71,15 → 78,11
# ISE flow -----------------------------------------------
 
# Component tests ----------------------------
SIM_ise += rtl/bplib/nxcramlib/tb
SIM_ise += rtl/vlib/comlib/tb
SIM_ise += rtl/vlib/rlink/tb
SIM_ise += rtl/vlib/serport/tb
SIM_ise += rtl/w11a/tb
 
# S3board ------------------------------------
SIM_ise += rtl/sys_gen/tst_rlink/s3board/tb
SIM_ise += rtl/sys_gen/tst_serloop/s3board/tb
SIM_ise += rtl/sys_gen/tst_sram/s3board/tb
SIM_ise += rtl/sys_gen/w11a/s3board/tb
 
# Nexys2 -------------------------------------
86,6 → 89,7
SIM_ise += rtl/sys_gen/tst_rlink/nexys2/tb
SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
SIM_ise += rtl/sys_gen/tst_serloop/nexys2/tb
SIM_ise += rtl/sys_gen/tst_sram/nexys2/tb
SIM_ise += rtl/sys_gen/w11a/nexys2/tb
 
# Nexys3 -------------------------------------
92,9 → 96,20
SIM_ise += rtl/sys_gen/tst_rlink/nexys3/tb
SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
SIM_ise += rtl/sys_gen/tst_serloop/nexys3/tb
SIM_ise += rtl/sys_gen/tst_sram/nexys3/tb
SIM_ise += rtl/sys_gen/w11a/nexys3/tb
 
# Vivado flow --------------------------------------------
 
# Component tests ----------------------------
SIM_viv += rtl/bplib/issi/tb
SIM_viv += rtl/bplib/micron/tb
SIM_viv += rtl/bplib/nxcramlib/tb
SIM_viv += rtl/vlib/comlib/tb
SIM_viv += rtl/vlib/rlink/tb
SIM_viv += rtl/vlib/serport/tb
SIM_viv += rtl/w11a/tb
 
# Basys3 -------------------------------------
SIM_viv += rtl/sys_gen/tst_rlink/basys3/tb
#SIM_viv += rtl/sys_gen/tst_serloop/basys3/tb
103,6 → 118,7
# Nexys4 -------------------------------------
SIM_viv += rtl/sys_gen/tst_rlink/nexys4/tb
SIM_viv += rtl/sys_gen/tst_serloop/nexys4/tb
SIM_viv += rtl/sys_gen/tst_sram/nexys4/tb
SIM_viv += rtl/sys_gen/w11a/nexys4/tb
 
# Arty ---------------------------------------
/trunk/doc/README.txt
1,4 → 1,4
$Id: README.txt 779 2016-06-26 15:37:16Z mueller $
$Id: README.txt 811 2016-10-03 07:24:02Z mueller $
 
Release notes for w11a
 
22,6 → 22,156
 
2. Change Log ----------------------------------------------------------------
 
- trunk (2016-10-02: svn rev 37(oc) 811(wfjm); untagged w11a_V0.74) +++++++++
- Preface
- the current version of the memory controller for the micron mt45w8mw16b
'cellular ram' used on nexys2, nexys3, and nexys4 uses the asynchronous
access mode. The device supports a 'page mode' to speed up read access to
subsequent addresses. Even though prepared in the controller logic this
feature was simply forgotten. This is now properly implemented and
results in a bit faster cache line load times. The overall performance
of a w11a design is measurably, but marginally better.
- many unit tests still used a ISE environment. All board independent
tests were converted now to a vivado environment, only tests which
really depend a FPGA not supported by vivado stay with ISE.
- a total of 82 unit or system tests are currently available. Many of them
can be executed by different simulation engines, ghdl or the ISE/vivado
build-in simulators, and for different stages of the implementation flow,
from initial behavioral simulation over post-synthesis functional to final
post-routing timing simulation. This results in a large number of possible
tests. All test benches are all self-checking, but the execution of them
was so far not sufficiently automatized.
This was addressed with 'tbrun', a test bench driver, which obtains a
list of all available test benches from configuration files, selects
a subset given by selection criteria, and executes them. It can handle
the parallel execution of tests so multi-core systems can be very
easily exploited. Running all tests is now a single shell command.
- a new tool 'tbfilt' simplifies the logic of self-checking test benches
and can also be used as a tool to analyze the full log files produced
by the test benches
- several test benches have been added to this release, most notably the
memory tester sys_tst_sram_* which was originally developed to verify
the s3board SRAM controller and later ported to verify the nexys* CRAM
controller.
- the system test benches with SRAM and CRAM now include the PCB trace
delay between FPGA and memory chip. The new entity simbididly models a
bi-directional bus delay.
- so far test benches ended by stopping the clock, all processes were
written such that they enter a permanent wait, which causes the simulation
to stop. Worked for fine behavioral simulations, but fails when Xilinx
MMCMs are involved in post-synthesis simulations. The UNISIM models
apparently have timed waits. The test benches were modified to stop via a
report with severity failure, the test environment detects this specific
assertion/report failure and accepts it as successful termination of
the simulation.
- the configuration of the board switches in system test benches was done
in a sub-optimal way which could lead to startup problems. tbrun_tbwrri
uses now a different mechanism which ensures that all board and test
bench configuration is done in the first ns of the simulation and has
thus completed well before all other activities.
- finally a caveat: post-synthesis simulations work fine with ISE, but
currently not with vivado, even in case of almost identical designs,
like sys_tst_rlink_n3 vs sys_tst_rlink_n4. Is under investigation.
 
- Summary
- upgraded CRAM controller, now with 'page mode' support
- new test bench driver tbrun, give automatized test bench execution
 
- New features
- new modules
- rtl/bplib/issi/tb/* - added unit test for is61lv25616al model
- rtl/bplib/micron/tb/* - added unit test for mt45w8mw16b model
- rtl/sys_gen/tst_serloop - add serloop2 (2 clock) designs for n3,n4
- nexys3/sys_tst_serloop2_n3.vhd
- nexys4/sys_tst_serloop2_n4.vhd
- rtl/sys_gen/tst_sram - add sram test design for
- nexys2/*
- nexys3/*
- nexys4/*
- s3board/*
- rtl/vlib/genlib/tb
- clkdivce_tb.vhd - copy for tb usage of clkdivce
- rtl/vlib/rlink/tb
- rlink_tba.vhd - rlink test bench adapter
- tb_rlink_tba.vhd - test bench for rbus devices
- tbd_tba_ttcombo.vhd - tba tester for ttcombo
- rtl/vlib/simlib
- simbididly.vhd - bi-di bus delay model
- rtl/vlib/xlib
- gsr_pulse.vhd - pulse GSR at startup
- gsr_pulse_dummy.vhd - no-action dummy (for bsim models)
- rtl/w11a/tb
- tb_rlink_tba_pdp11core.vhd - tba tester for w11a
 
- new files
- doc/man/man1 - added tbrun,tbfilt man pages
- */tbrun.yml - test bench descriptors for tbrun
- rtl/sys_gen/w11a/tb
- tb_w11a_mem70*.dat - stim files for additional tests
- rtl/w11a/tb
- tb_pdp11core_ubmap.dat - stim files for additional test
- tools/bin
- njobihtm - determine #jobs
- tbfilt - test bench output filter
- tbrun - test bench driver
- ticonv_rri - converts old 'mode rri' for ti_rri
- tools/tcl/tst_sram/*.tcl - support for sys_tst_sram
 
- Changes
- rtl/bplib
- arty/tb/tb_arty.vhd - add gsr_pulse (provisional....)
- */tb/tb_*.vhd - tbcore_rlink without CLK_STOP now
- fx2lib/tb/fx2_2fifo_core.vhd - proc_ifclk: remove clock stop
- nexys2/tb/tb_nexys2_core.vhd - use simbididly
- nexys3/tb/tb_nexys3_core.vhd - use simbididly
- nexys4/tb/tb_nexys4_cram.vhd - use simbididly
- nxcramlib
- nx_cram_memctl_as.vhd - add page mode support
- nxcramlib.vhd - add cram_*delay functions
- s3board
- s3_sram_memctl.vhd - drop "KEEP" for data (better for dbg)
- tb/tb_s3board_core.vhd - use simbididly
- rtl/make_ise
- generic_ghdl.mk - ghdl_clean: remove also gcov files
- rtl/make_viv
- generic_ghdl.mk - ghdl_clean: remove also gcov files
- generic_vivado.mk - viv_clean: rm only vivado logs
- generic_xsim.mk - xsim work dir now xsim.<mode>.<stem>
- rtl/sys_gen/tst_serloop
- */tb/tb_tst_serloop*.vhd - remove CLK_STOP logic
- tb/tb_tst_serloop.vhd - remove CLK_STOP logic
- rtl/sys_gen/w11a/nexys*
- sys_conf.vhd - use cram_*delay functions
- rtl/vlib/rlink
- rlink_core.vhd - remove 'assert false' from report stmts
- tb/tb_rlink.vhd - use clkdivce_tb
- tbcore/tbcore_rlink.vhd - conf: add .wait, CONF_DONE; drop CLK_STOP
- rtl/vlib/simlib
- simbus.vhd - rename SB_CLKSTOP > SB_SIMSTOP
- simclk.vhd - CLK_STOP now optional port
- rtl/vlib/xlib
- */s*_cmt_sfs_*.vhd - remove 'assert false' from report stmts
- tools/bin
- tbrun_tbwrri - add --r(l|b)mon,(b|s)wait; configure
now via _conf={...}
- tbw - use {} as delimiter for immediate mode
- vbomconv - add VBOMCONV_GHDL_OPTS and .._GHDL_GCOV
- xise_ghdl_* - add ghdlopts as 1st option; def is -O2
 
- removed files
- tools/bin/ghdl_assert_filter - obsolete (use tbfilt now)
- renames
- rtl/make_viv/viv_*.tcl -> tools/vivado - separate make and tools
 
- Bug fixes
- tools/bin
- tbw - xsim: append -R to ARGV (was prepended...)
- xtwi - add ":." to PATH even under BARE_PATH
 
- Known issues
- all issues: see README_known_issues.txt
- no resolved or new issues in this release
 
- trunk (2016-06-26: svn rev 36(oc) 779(wfjm); untagged w11a_V0.73) +++++++++
- Preface
- the 'basic vivado support' added with V0.64 was a minimal effort port of
120,7 → 270,7
- serport_2clock2.vhd - like serport_2clock, use fifo_2c_dram2
- rtl/vlib/xlib
- usr_access_unisim.vhd - Wrapper for USR_ACCESS* entities
- new files
- new files
- tools/bin
- xise_msg_summary - list all filtered ISE messages
- xviv_msg_filter - message filter for vivado
/trunk/doc/man/man1/njobihtm.1
0,0 → 1,75
.\" -*- nroff -*-
.\" $Id: njobihtm.1 810 2016-10-02 16:51:12Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH NJOBIHTM 1 2016-10-01 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
njobihtm \- number of jobs considering hyper-threading and memory
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY njobihtm
.OP -v
.OP -m nnn[MG]
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
\fBnjobihtm\fP determines the number of CPU-intensive jobs based on the
number of CPU and memory resources. The 'ihtm' stands for 'intelligent
hyper-threading and memory'. The script
 
.RS 2
.PD 0
.IP "-" 2
determines the number of physical cores and the number of threads per core
.IP "-"
assumes that only a quarter of the additional hyper-threads are useful
.IP "-"
if \fB-m\fP is given. determines the memory size, assumes that at least
one GB should be available for general usage, and limits the number of
jobs accordingly.
.PD
.RE
.PP
The number of jobs is written to STDOUT, and can be used like `njobs`.
.
.\" ------------------------------------------------------------------
.SH OPTIONS
.
.\" -- --mem -------------------------------------
.IP \fB\-m\ \fIsize\fR
gives the required physical memory per job.
\fIsize\fP must be given as integer with either a 'M' or 'G', indicating MB
or GB.
.
.\" -- --verbose ---------------------------------
.IP \fB\-v\fP
if given the found system parameters and the reasoning is printed to STDERR.
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBmake -j `njobihtm` all\fR" 4
Start \fBmake\fR(1) with a reasonable number of jobs.
.IP "\fBnjobihtm -v -m=2G\fR" 4
Determines the number of jobs with 2 GB memory per job. On a system with 4 cores
and hyper-threading and 8 GB installed memory one gets due to the '-v' the
output
.EX
#cpus: 8
#thread/cpu: 2
#cores: 4
mem(MB): 7961
#job (cpus): 5
#job (mem): 3
3
.EE
Note that the '-v' output goes to STDERR, only the answer '3' to STDOUT.
 
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
/trunk/doc/man/man1/tbfilt.1
0,0 → 1,307
.\" -*- nroff -*-
.\" $Id: tbfilt.1 803 2016-08-28 12:39:00Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBFILT 1 2016-08-27 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbfilt \- filter for and analysis of test bench log files
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY tbfilt
.B \-\-tee
.I OFILE
.OP OPTIONS
.
.SY tbfilt
.OP OPTIONS
.RI [ FILES ]...
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
.SS Principle of Operation
\fBtbfilt\fP is the central tool to analyze the log files created by the test
benches. It scans the test bench output for messages which indicate a test
failure and based on this marks a test as \fBPASS\fPed or \fBFAIL\fPed.
It can be used in two modes:
 
.RS 2
.IP "-" 2
as filter during test bench execution, typically in a setup like
.EX
tbw <test_bench> 2>&1 | tbfilt --tee=<log_file>
.EE
tbfilt reads the output from the test bench via stdin and a pipe, filters
out the messages indicating a failure and shows them on stdout, and saves
the full test bench output to the file given in the \fB\-\-tee\fP option.
In this mode tbfilt works similar to a
.EX
tee ... | egrep ...
.EE
pipeline with a very involved egrep selection expression.
The exit status of tbfilt is 1 in case the test is considered as \fBFAIL\fPed.
.
.IP "-" 2
as log file analysis tool. In this case the test bench log files are either
specified explicitly as arguments or determined via the \fB\-\-find\fP or
\fB\-\-all\fP options.
If the \fB\-\-summary\fP option is specified a one line summary for each
test log file is displayed. The format of this summary is configurable via
the \fB\-\-format\fP, \fB\-\-wide\fP, and \fB\-\-compact\fP options and via
the \fB\TBFILT_FORMAT\fP environment variable.
The exit status of tbfilt is 1 in case any of the tests is considered as
\fBFAIL\fPed.
.
.RE
.PP
.
.SS Filter Criteria
A line which contains any of the following strings is considered as an
indication of a \fBFAIL\fPed test:
.RS 2
.PD 0
.IP "\fB-E:\fR"
.IP "\fB-F:\fR"
.IP "\fBERROR\fR"
.IP "\fBFAIL\fR"
.IP "\fB:(assertion warning):\fR"
.IP "\fB:(assertion error):\fR"
.IP "\fB:(assertion failure):\fR"
.PD
.RE
 
As excption to the general rules above the following assertion messages
are accepted:
Assertion warnings from IEEE libraries at startup (t=0) are ignored. They are
hard to avoid in complex models and in general don't indicate a real issue.
.RS 2
.PD 0
.IP "-" 2
assertion warnings from IEEE libraries at startup (t=0). They are hard to
avoid in complex models and in general don't indicate a real issue. Best
is to suppress them in \fBghdl\fP(1) with the
option '--ieee-asserts=disable-at-0'.
.IP "-" 2
assertion failure with the text 'Simulation Finished'. It is used to end
simulations in \fBghdl\fP(1) in some test benches.
.PD
.RE
 
tbfilt also expects a line in one of the formats
.EX
xxx ns: DONE -- tb'swithout clock
xxx.x ns xxx: DONE -- single clock tb's
xxx.x ns xxx: DONE-xxx -- multiclock tb's (max taken)
.EE
and considers a test \fBFAIL\fPed if it is missing.
 
In addition lines containing
.RS 4
.PD 0
.IP "\fB-W:\fR"
.IP "\fBPASS\fR"
.PD
.RE
will be displayed. If the \fB\-\-pcom\fP option is specified also all lines
starting with 'C'.
 
Finally, tbfilt checks for a line of the format
.EX
real xmx.xxxs user xmx.xxxs sys xmx.xxxs
.EE
and extracts the test bench execution times from this. It can be generated
by a \fBbash\fP(1) 'time' command when
.EX
export TIMEFORMAT=$'real %3lR user %3lU sys %3lS'
.EE
is set. The wrapper scripts \fB\tbrun_tbw\fP(1) or \fBtbrun_tbwrri\fP(1)
are in general used to set this up correctly.
.
.\" ------------------------------------------------------------------
.SH OPTIONS
.
.\" --------------------------------------------------------
.SS Filter Options
.
.\" -- --tee -------------------------------------
.IP "\fB\-\-tee=\fIofile\fR"
All log file input is written to \fIofile\fP. Typically used to save the
test bench output in a file when tbfilt is used in filter mode in a pipeline
and reads from stdin.
.
.\" -- --pcom ------------------------------------
.IP \fB\-\-pcom\fP
Enables that lines starting with "C" are also displayed.
.
.\" --------------------------------------------------------
.SS File Selection Options
.
.\" -- --find ------------------------------------
.IP "\fB\-\-find=\fIpatt\fR"
When given the input files are determined with a \fBfind\fP(1) command.
The selection pattern \fIpatt\fR is used with a find -regex in egrep mode.
This is functionally similar to a
.EX
find -regextype egrep -regex '\fIpatt\fR' | sort | tbfilt ....
.EE
pipeline.
 
When no '*' wildcard is found in \fIpatt\fR it is assumed to be a mode
specification and the pattern is prefixed by
.EX
.*/tb_.*_
.EE
and suffixed by
.EX
.*\\.log
.EE
to select all log files of a given mode (e.g. 'bsim').
.
.\" -- --all -------------------------------------
.IP \fB\-\-all\fP
When given uses as input files all test bench files which conform the
naming convention. Is equivalent to the option
.EX
--find '.*/tb_.*_[bfsorept]sim(_.*)?\\.log'
.EE
.
.\" --------------------------------------------------------
.SS Summary Options
.
.\" -- --summary----------------------------------
.IP \fB\-\-summary\fP
Selects summary mode. Only a single summary line per input file is written.
The format is configurable via the \fB\-\-format\fP, \fB\-\-wide\fP, and
\fB\-\-compact\fP options and via the \fBTBFILT_FORMAT\fP environment variable.
The precedence is (in increasing priority):
.RS
.PD 0
.IP " -" 4
build default ('%ec %pf %nf')
.IP " -"
\fBTBFILT_FORMAT\fP option
.IP " -"
\fB\-\-wide\fP option
.IP " -"
\fB\-\-compact\fP option
.IP " -"
\fB\-\-format\fP option
.PD
.RE
.
.\" -- --wide ------------------------------------
.IP \fB\-\-wide\fP
Selects a wide format for summary outputs, designed to give the most pertinent
information. Uses a format of "%fd %fs %tr %tc %sc %ec %pf %nf".
.
.\" -- --compact ---------------------------------
.IP \fB\-\-compact\fP
Selects a compact format for summary outputs, designed to give the key info
on a 80 character wide line. Uses a format of "%fa %tg %sg %ec %pf %ns".
.
.\" -- --nohead ----------------------------------
.IP \fB\-\-nohead\fP
Suppresses the head line of summary outputs. Useful of summary output is
piped into sort or other tools.
.
.\" -- --format ----------------------------------
.IP "\fB\-\-format=\fIfmt\fR"
Defined the format of the summary lines.
The format specification \fIfmt\fR string is a sequence of conversion
specifications of the form '%xx', which will be replaces by the respective
values and other characters which are simply copied (usually a blank as
delimiter).
The supported conversion specifications are:
.RS
.PD 0
.IP \fB%fd\fP 5
modification date of input file (as yyyy-mm-dd)
.IP \fB%ft\fP
modification time of input file (as hh:mm:ss)
.IP \fB%fs\fP
modification time of input file short format (as hh:mm)
.IP \fB%fa\fP
age of input file in seconds, minutes, hours or days
.IP \fB%tr\fP
real (wall clock) time of test bench run
.IP \fB%tu\fP
user time of test bench run
.IP \fB%ts\fP
system time of test bench run
.IP \fB%tc\fP
total cpu (user+system) time of test bench run
.IP \fB%tg\fP
show '%tc c' if cpu time significant, otherwise '%tr r'
.IP \fB%st\fP
simulation time in ns
.IP \fB%ss\fP
simulation time short format (in usec, msec, or sec)
.IP \fB%sc\fP
main system clock cycles till DONE
.IP \fB%sg\fP
use %sc, if available, otherwise %ss
.IP \fB%sp\fP
cpu time per simulation clock cycle (in usec or msec)
.IP \fB%sm\fP
estimate of system clock rate (in MHz)
.IP \fB%ec\fP
error count
.IP \fB%pf\fP
PASS or FAIL, derived from error count
.IP \fB%nf\fP
full file name (with path)
.IP \fB%ns\fP
short file name (without path)
.PD
.RE
.
.\" ------------------------------------------------------------------
.SH EXIT STATUS
In case the test bench is considered FAILed an exit status 1 is returned.
In case of an error at startup, e.g. no input files or invalid format
specification, an error message to stderr or printed and an exit status
of 2 is returned.
.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT
.IP "\fBTBFILT_FORMAT\fR" 4
Defines the default summary format and overwrites the build-in default of
"%ec %pf %nf".
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.SS As Filter
Usually used together with \fBtbw\fP(1) in pipelines like
.EX
tbw <test_bench> 2>&1 | tbfilt --tee=<log_file>
.EE
Since tbfilt expects also the output of a \fBbash\fP(1) 'time' command
in the input stream the setup of the pipeline is more involved.
In general the wrapper scripts \fB\tbrun_tbw\fP(1) or \fBtbrun_tbwrri\fP(1)
are used.
.
.SS As Analysis Tool
To generate a compact overview of all test bench outputs use
.EX
cd $RETROBASE
tbfilt -all -summary -compact
.EE
To generate a report indicating all \fBFAIL\fPed test use
.EX
cd $RETROBASE
tbfilt -all -summary -nohead | grep FAIL
.EE
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR tbw (1),
.BR tbrun_tbw (1),
.BR tbrun_tbwrri (1)
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
/trunk/doc/man/man1/tbrun.1
0,0 → 1,239
.\" -*- nroff -*-
.\" $Id: tbrun.1 812 2016-10-03 18:39:50Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBRUN 1 2016-10-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbrun \- test bench driver
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY tbrun
.OP OPTIONS
.OP DSCFILE
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
\fBtbrun\fP organizes the execution of large sets of test benches. It will
 
.RS 2
.PD 0
.IP "-" 2
read the file \fIDSCFILE\fP, which describes the full set of test benches.
The top level \fIDSCFILE\fP typically includes other files which allows to
organize the description in a well structured manner. If no \fIDSCFILE\fP
is specified the file \fItbrun.yml\fP in the current working directory is
used.
.IP "-"
selects based on the given \fB\-\-tag\fP and \fB\-\-exclude\fP options the
tests to be executed in a given run.
.IP "-"
determines based on the \fB\-\-mode\fP option the simulation engine and
the simulation type, behavioral or post-synthesis or later. See section
MODES for details.
.IP "-"
executes the tests which as much parallelism as possible. The \fB\-\-jobs\fP
option specifies the maximal number of jobs, and a locking logic prevents that
more than one test is run in one working directory.
.PD
.RE
.PP
.
.\" ------------------------------------------------------------------
.SH OPTIONS
.
.\" -- --tag -------------------------------------
.IP \fB\-\-tag=\fItlist\fR
specifies the tags a test must match to be selected for execution.
\fItlist\fR can be a comma separated list of tags, a test must match
all tags given in \fItlist\fR to be selected.
.br
\fB\-\-tag\fP can be specified multiple times, the selections are ored.
In effect, a test must match all tags in the \fItlist\fR of one of the
specified \fB\-\-tag\fP options.
.br
If no \fB\-\-tag\fP option is given an implicit \fI\-\-tag=default\fP is
assumed, so all tests with the tag 'default' are executed.
.
.\" -- --exclude ---------------------------------
.IP \fB\-\-exclude=\fItlist\fR
specifies the tags a test must not match. \fItlist\fR can again be a comma
separated list, a test which matches all the tags given is excluded.
.br
\fB\-\-exclude\fP can be specified multiple times, the rejections are ored.
In effect, a test is rejected if it matches all tags in the \fItlist\fR of
one of the specified \fB\-\-exclude\fP options.
.
.\" -- --mode ------------------------------------
.IP \fB\-\-mode=\fImlist\fR
determines the simulation engine and the type of simulation. Can be a
comma separated list, if several modes are specified all of them will
be executed.
.br
If no \fB\-\-mode\fP is given the default value 'bsim' is used.
Note that unlike \fB\-\-tag\fP and \fB\-\-exclude\fP only a single
\fB\-\-mode\fP option is processed, if multiple are present only the
last one will be used.
 
.RS
Each mode specification has the format '[\fIengine\fP]_[\fItype\fP]'
and follows the model name suffix rules of the build system.
 
If the \fIengine\fP part is omitted \fBghdl\fP(1) is assumed as default.
If the \fItype\fP part is omitted 'bsim' is assumed as default.
Other supported values for \fIengine\fP are
.RS 2
.PD 0
.IP \fBISim\fP 6
the Xilinx ISE build-in simulator
.IP \fBXSim\fP
the Xilinx vivado build-in simulator
.PD
.RE
 
The \fItype\fP part has the following supported values
.RS 2
.PD 0
.IP \fBbsim\fP 6
behavioral simulation
.IP \fBssim\fP
post-synthesis functional simulation
.IP \fBfsim\fP
post-map simulation (only ISE)
.IP \fBosim\fP
post-optimize functional simulation (only vivado)
.IP \fBrsim\fP
post-routing functional simulation (only vivado)
.IP \fBesim\fP
post-synthesis timing simulation (only vivado)
.IP \fBpsim\fP
post-optimize timing simulation (only vivado)
.IP \fBtsim\fP
post-routing timing simulation
.PD
.RE
.RE
.
.\" -- --jobs ------------------------------------
.IP \fB\-\-jobs=\fInjob\fR
.RS
specifies the maximal number of parallel jobs.
Without \fB\-\-jobs\fP option the tests are executed sequentially and
the test output is forwarded immediately to stdout.
 
With \fB\-\-jobs\fP option a task dispatcher is used which starts the jobs,
received and buffers the test output, and forwards it to stdout when the
job completes. The test outputs are always in the original selection order,
thus not affected by the completion order.
 
The task dispatcher displays also a progress line when stdout is a terminal
device of the format
.EX
#-I: t047: 5l 35.6s; t053: 5l 20.2s (26t,2w,31o)
.EE
where
.RS 2
.PD 0
.IP "t***:" 6
specifies the current task number
.IP "**l"
number of output lines collected for this task
.IP "*.*s"
run time (as real time) of the task (running since time)
.IP "**t"
number of tasks still waiting for execution
.IP "*w"
number of tasks currently running
.IP "*o"
number of tasks in pending output queue
.PD
.RE
 
Note that \fB\-\-jobs\fP enables the task dispatcher and thus output
buffering and progress line output even when \fInjob\fP is '1' !
.RE
.
.\" -- --tee -------------------------------------
.IP \fB\-\-tee=\fIoutfile\fR
if specified the all output send to stdout with the exception of the
progress line updates is also written in the file \fIoutfile\fR.
This is very convenient in conjunction with the \fB\-\-jobs\fP option
which generates progress line output only when stdout is a terminal
device.
Using shell pipes and \fBtee\fP(1) will therefore prevent progress lines,
use the \fB\-\-tee\fP instead to save the output into a file.
.
.\" -- --dry -------------------------------------
.IP \fB\-\-dry\fP
dry run, prints the generated commands, but doesn't execute.
When used without \f\-\-jobs\fP option a commented list of shell commands
is printed which describes the linear execution of the selected tests.
.br
When used together with \f\-\-jobs\fP this option mainly serves to debug
the task dispatcher. A random wait of 0.2 to 1.8 sec is generated for each
selected test.
.
\" -- --trace -----------------------------------
.IP \fB\-\-trace\fP
prints additional information on job control
.
.\" -- --nomake ----------------------------------
.IP \fB\-\-nomake\fP
don't execute make step of test bench.
Will be forwarded to \fBtbrun_tbw\fP(1) and \fBtbrun_tbwrri\fP(1)
based test benches.
.
\" -- --norun -----------------------------------
.IP \fB\-\-norun\fP
don't execute run step of test bench, useful to only execute make step.
Will be forwarded to \fBtbrun_tbw\fP(1) and \fBtbrun_tbwrri\fP(1)
based test benches.
.
\" -- --rlmon -----------------------------------
.IP \fB\-\-rlmon\fP
enable the rlink monitor, will be forwarded to \fBtbrun_tbwrri\fP(1)
based test benches.
.
\" -- --rbmon -----------------------------------
.IP \fB\-\-rbmon\fP
enable the rbus monitor, will be forwarded to \fBtbrun_tbwrri\fP(1)
based test benches
.
.\" -- --bwait ----------------------------------
.IP \fB\-\-bwait=\fItwait\fR
specifies startup wait for behavioral simulations.
\fItwait\fR must be an integer, time unit is 1 ns. Will be forwarded
to \fBtbrun_tbwrri\fP(1) based test benches.
.
.\" -- --swait ----------------------------------
.IP \fB\-\-swait=\fItwait\fR
specifies startup wait for post-synthesis and higher simulations.
\fItwait\fR must be an integer, time unit is 1 ns. Will be forwarded
to \fBtbrun_tbwrri\fP(1) based test benches.
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBtbrun" 4
Simplest default case, will use the \fItbrun.yml\fP file in the current
working directory, assume \fI\-\-tag=default\fP and \fI\-\-mode=bsim\fP
and this select all tests tagged with 'default' and run the behavioral
simulation with \fBghdl\fP(1). Done in simple sequential mode.
.IP "\fBtbrun --jobs=2 --tag=viv,sys_w11a --mode=XSim" 4
Will select all tests which have a 'viv' and a 'sys_w11a' tag,
use XSim as simulation engine and run the behavioral simulation.
Will use the task dispatcher and will try to run 2 tests in parallel.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR tbrun_tbw (1),
.BR tbrun_tbwrri (1),
.BR tbfilt (1)
 
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
/trunk/doc/man/man1/tbrun_tbw.1
1,11 → 1,11
.\" -*- nroff -*-
.\" $Id: tbrun_tbw.1 774 2016-06-12 17:08:47Z mueller $
.\" $Id: tbrun_tbw.1 800 2016-08-21 22:02:49Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBRUN_TBW 1 2016-03-18 "Retro Project" "Retro Project Manual"
.TH TBRUN_TBW 1 2016-08-21 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbrun_tbw \- \fBtbw\fP based test bench starter
30,15 → 30,8
.IP "-"
build a \fBtbw\fP(1) command, using \fISTIMFILE\fP if specified.
.IP "-"
create a shell pipe to which runs tbw and handles the output with
.IP " -" 4
\fBghdl_assert_filter\fP(1) to suppress irrelevant diagnostics
created by \fBghdl\fP(1) and it's IEEE libs
.IP " -"
\fBtee\fP(1) to save the output to a log file. The log file
name is build as "<TBENCH>_<lsuf>.log"
.IP " -"
\fBegrep\fP(1) to filter out only essential lines to stdout
create a shell pipe to which runs tbw and handles the test bench output with
\fBtbfilt\fP(1) to determine success of failure.
.PD
.RE
.PP
53,6 → 46,14
.IP \fB\-\-dry\fP
dry run, prints the commands but doesn't execute
.
.\" -- --nomake ----------------------------------
.IP \fB\-\-nomake\fP
don't execute make step (\fITBENCH\fP neither build nor updated)
.
\" -- --norun -----------------------------------
.IP \fB\-\-norun\fP
don't execute test bench (useful to only execute make step)
.
.\" -- --lsuf ------------------------------------
.IP \fB\-\-lsuf\ \fIsuff\fR
use '_\fIsuff\fR.log' as suffix for log file. Default is '_bsim.log'
68,23 → 69,25
.\" -- --tbw opts --------------------------------
.IP \fB\-\-tbw\ \fIopts\fR
append \fIopts\fP to the \fBtbw\fP(1) command
.\" -- --pcom ------------------------------------
.IP \fB\-\-pcom\fR
enables that test bench comments are passed to stdout.
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBtbrun_tbw tb_serport_uart_rx" 4
Simplest default case, will execute
Simplest default case, will execute in essence
.EX
make tb_serport_uart_rx
time tbw tb_serport_uart_rx 2>&1 |\\
ghdl_assert_filter |\\
tee tb_serport_uart_rx_bsim.log |\\
egrep "(-[EFW]:|ERROR|FAIL|PASS|DONE)"
tbw tb_serport_uart_rx 2>&1 | tbfilt
.EE
The issued command is more involved, defines TIMEFORMAT, adds a bash 'time',
and some redirects to ensure that the 'time' output ends up un the log file.
 
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR tbw (1),
.BR ghdl_assert_filter (1),
.BR tbfilt (1),
.BR ghdl (1)
 
.\" ------------------------------------------------------------------
/trunk/doc/man/man1/tbrun_tbwrri.1
1,11 → 1,11
.\" -*- nroff -*-
.\" $Id: tbrun_tbwrri.1 774 2016-06-12 17:08:47Z mueller $
.\" $Id: tbrun_tbwrri.1 808 2016-09-17 13:02:46Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBRUN_TBWRRI 1 2016-03-18 "Retro Project" "Retro Project Manual"
.TH TBRUN_TBWRRI 1 2016-09-17 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbrun_tbw \- \fBti_rri\fP plus \fBtbw\fP based test bench starter
38,15 → 38,8
.IP " -"
all optional \fICOMMANDS\fP
.IP "-" 2
create shell pipes to filter the output with
.IP " -" 4
\fBghdl_assert_filter\fP(1) to suppress irrelevant diagnostics
created by \fBghdl\fP(1) and it's IEEE libs
.IP " -"
\fBtee\fP(1) to save the output to a log file. The log file
name is build as "<TBENCH>_<lsuf>.log"
.IP " -"
\fBegrep\fP(1) to filter out only essential lines to stdout
create shell pipe to filter the output with \fBtbfilt\fP(1) to determine
success of failure.
.PD
.RE
.PP
61,6 → 54,14
.IP \fB\-\-dry\fP
dry run, prints the commands but doesn't execute
.
.\" -- --nomake ----------------------------------
.IP \fB\-\-nomake\fP
don't execute make step (\fITBENCH\fP neither build nor updated)
.
.\" -- --norun -----------------------------------
.IP \fB\-\-norun\fP
don't execute test bench (useful to only execute make step)
.
.\" -- --lsuf ------------------------------------
.IP \fB\-\-lsuf\ \fIsuff\fR
use '_\fIsuff\fR.log' as suffix for log file. Default is '_bsim.log'
110,6 → 111,27
.IP \fB\-\-pcom\fR
enables that test bench comments are passed to stdout.
.
.\" -- --rlmon -----------------------------------
.IP \fB\-\-rlmon\fR
configures the test bench to enable rlmon (rlink communication monitor, logs
all characters read and send by the rlink core).
Done in UUT, thus useful only for behavioral simulations.
.
.\" -- --rbmon -----------------------------------
.IP \fB\-\-rbmon\fR
configures the test bench to enable rbmon (rbus monitor, logs all rbus
transactions).
Done in UUT, thus useful only for behavioral simulations.
.
.\" -- --bwait -----------------------------------
.IP \fB\-\-bwait\fR\ \fItime\fR
add additional \fItime\fR ns startup waiting time for behavioral models.
.
.\" -- --swait -----------------------------------
.IP \fB\-\-bwait\fR\ \fItime\fR
add additional \fItime\fR ns startup waiting time for post-synthesis and
later models.
 
.\" -- --help ------------------------------------
.IP \fB\-\-help\fR
print help message and quit.
118,7 → 140,7
.SH "SEE ALSO"
.BR tbw (1),
.BR ti_rri (1),
.BR ghdl_assert_filter (1),
.BR tbfilt (1),
.BR ghdl (1)
 
.\" ------------------------------------------------------------------
/trunk/doc/man/man1/tbw.1
1,11 → 1,11
.\" -*- nroff -*-
.\" $Id: tbw.1 774 2016-06-12 17:08:47Z mueller $
.\" $Id: tbw.1 810 2016-10-02 16:51:12Z mueller $
.\"
.\" Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBW 1 2016-04-17 "Retro Project" "Retro Project Manual"
.TH TBW 1 2016-10-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbw \- wrapper script to start ghdl based VHDL test benches
113,6 → 113,23
display process name before each cycle.
.
.\" ------------------------------------------------------------------
.
.SH ENVIRONMENT
.IP \fBTBW_GHDL_OPTS\fP 4
Additional options which are passed to ghdl based simulations.
Of particular value are
.RS
.IP "\fB\-\-ieee\-asserts=disable\-at\-0\fP" 4
suppresses assertion warnings from the ieee libraries at startup time (t=0ns).
.IP "\fB\-\-unbuffered\fP"
sets output at all files (stdout, stderr, and files opened for write) to
unbuffered mode. This is very helpful to keep output from the ghdl
simulation and other programs in a co-simulation environment in synch.
Note: only available for ghdl 0.34dev after merge of Jonsba/master #100 on
2016-06-26.
.RE
.
.\" ------------------------------------------------------------------
.SH FILES
.IP "\fI./tbw.dat\fR" 4
This configuration file is searched for in the directory of the test bench
168,7 → 185,7
These test benches are usually run like
 
.EX
tbw <testbenchname> [stimfile] | tee <logfile> | egrep "(FAIL|DONE)"
tbw <testbenchname> [stimfile] | tbfilt --tee <logfile>
.EE
 
where
177,10 → 194,8
.IP "\-" 2
\fBtbw\fP sets up the stimulus file and runs the test bench executable
.IP "\-"
\fBtee\fP ensures that the full log is saved
.IP "\-"
\fBegrep\fP filters \fIFAIL\fP and \fIDONE\fP lines, a successful run will
produce a single \fIDONE\fP line
\fBtbfilt\fP ensures that the full log is saved and the PASS/FAIL criteria
are extracted
.PD
.RE
 
190,14 → 205,13
.SS Test benches controlled with \fBti_rri\fP
In these cases the test bench is started via \fBti_rri\fP using the
\fB\-\-run\fP and \fB\-\-fifo\fP options. Also here usually a pipe with
\fBtee\fP and \fBegrep\fP is used, a typical example is
\fBtbfilt\fP(1) is used, a typical example is
 
.EX
ti_rri \-\-run="tbw tb_tst_rlink_n3" \-\-fifo \-\-logl=3 \-\- \\
"package require tst_rlink" \\
"tst_rlink::setup" "tst_rlink::test_all" |\\
tee tb_tst_rlink_n3_bsim.log |\\
egrep "(\-[EFW]:|FAIL|PEND|DONE)"
tbfilt --tee=tb_tst_rlink_n3_bsim.log
.EE
 
The convenience script \fBtbrun_tbwrri\fP(1) can be used in many cases to
206,8 → 220,9
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR tbrun_tbw (1),
.BR tbfilt (1),
.BR ti_rri (1),
.BR tbrun_tbw (1),
.BR tbrun_tbwrri (1),
.BR gtkwave (1),
.BR symlink (7),
/trunk/doc/man/man1/vbomconv.1
1,5 → 1,5
.\" -*- nroff -*-
.\" $Id: vbomconv.1 779 2016-06-26 15:37:16Z mueller $
.\" $Id: vbomconv.1 783 2016-07-03 21:14:57Z mueller $
.\"
.\" Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
6,7 → 6,7
.\"
.\" ------------------------------------------------------------------
.
.TH VBOMCONV 1 2016-03-19 "Retro Project" "Retro Project Manual"
.TH VBOMCONV 1 2016-07-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
vbomconv \- generate files and actions from vbom manifest files
446,7 → 446,7
.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT
.IP \fBVBOMCONV_XSIM_LANG\fP
.IP \fBVBOMCONV_XSIM_LANG\fP 4
Controls the language for the generated models used by xsim. Can be set to
\fIverilog\fP or to \fIvhdl\fP. If not defined \fIverilog\fP is used.
It affects \fB\-\-vsim_prj\fP but also \fB\-\-dep_vsim\fP.
453,6 → 453,26
Use \fBrm_dep\fP(1) to force regeneration of dependency files when this
environment variable is set, unset or changed.
.
.IP \fBVBOMCONV_GHDL_OPTS\fP
Extra options for the ghdl compile stage. If not specified "\fB-O2 -g\fP" is
taken to enable optimization (is not default for gcc backend!) and debug
symbols (needed for assertion failure backtrace).
.
.IP \fBVBOMCONV_GHDL_GCOV\fP
If defined and set to '1' \fBghdl\fP(1) models will be compiled with
\fBgcov\fP(1) coverage support. This option is only available when ghdl
was compiled with gcc backend, the llvm and mcode backend do not support
coverage analysis. The generated ghdl options will be appended after the
ones given by \fBVBOMCONV_GHDL_OPTS\fP. Note that no default options are
assume, so -Ox or -g options must be explicitly given via
\fBVBOMCONV_GHDL_OPTS\fP.
The additional ghdl options are
.EX
-Wc,-ftest-coverage
-Wc,-fprofile-arcs
-Wl,-lgcov
.EE
.
.\" ------------------------------------------------------------------
.SH BUGS
.IP \(bu 2
/trunk/doc/man/man1/xise_ghdl_simprim.1
1,11 → 1,11
.\" -*- nroff -*-
.\" $Id: xise_ghdl_simprim.1 779 2016-06-26 15:37:16Z mueller $
.\" $Id: xise_ghdl_simprim.1 782 2016-07-03 08:09:36Z mueller $
.\"
.\" Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH XISE_GHDL_SIMPRIM 1 2015-01-29 "Retro Project" "Retro Project Manual"
.TH XISE_GHDL_SIMPRIM 1 2016-07-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xise_ghdl_simprim \- compile Xilinx ISE SIMPRIM libraries for ghdl
12,7 → 12,9
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.B xise_ghdl_simprim
.SY xise_ghdl_simprim
.RI [ GHDL-OPTIONS ]...
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
45,6 → 47,12
tools but not by \fBghdl\fP.
The \fBxilinx_vhdl_memcolltype_fix\fP
helper script simply removes them, no further problems seen so far.
.
.\" ------------------------------------------------------------------
.SH OPTIONS
Options added after the xise_ghdl_simprim command are simply forwarded to
the 'ghdl -a' commands. In general used to specify the optimize level.
If no options given \fI-O2 -g\fP is used.
 
.\" ------------------------------------------------------------------
.SH ENVIRONMENT
64,7 → 72,7
.SH "SEE ALSO"
.BR xtwi (1),
.BR ghdl (1),
.BR xilinx_ghdl_unisim (1)
.BR xise_ghdl_unisim (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR
/trunk/doc/man/man1/xise_ghdl_unisim.1
1,11 → 1,11
.\" -*- nroff -*-
.\" $Id: xise_ghdl_unisim.1 779 2016-06-26 15:37:16Z mueller $
.\" $Id: xise_ghdl_unisim.1 782 2016-07-03 08:09:36Z mueller $
.\"
.\" Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH XISE_GHDL_UNISIM 1 2015-02-04 "Retro Project" "Retro Project Manual"
.TH XISE_GHDL_UNISIM 1 2016-07-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xise_ghdl_unisim \- compile Xilinx ISE UNISIM and UNIMACRO libraries for ghdl
12,7 → 12,9
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.B xise_ghdl_unisim
.SY xise_ghdl_unisim
.RI [ GHDL-OPTIONS ]...
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
39,6 → 41,12
tools but not by \fBghdl\fP.
The \fBxilinx_vhdl_memcolltype_fix\fP
helper script simply removes them, no further problems seen so far.
.
.\" ------------------------------------------------------------------
.SH OPTIONS
Options added after the xise_ghdl_unisim command are simply forwarded to
the 'ghdl -a' commands. In general used to specify the optimize level.
If no options given \fI-O2 -g\fP is used.
 
.\" ------------------------------------------------------------------
.SH ENVIRONMENT
/trunk/doc/man/man1/xviv_ghdl_unisim.1
1,11 → 1,11
.\" -*- nroff -*-
.\" $Id: xviv_ghdl_unisim.1 779 2016-06-26 15:37:16Z mueller $
.\" $Id: xviv_ghdl_unisim.1 782 2016-07-03 08:09:36Z mueller $
.\"
.\" Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH XVIV_GHDL_UNISIM 1 2015-02-04 "Retro Project" "Retro Project Manual"
.TH XVIV_GHDL_UNISIM 1 2016-07-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xviv_ghdl_unisim \- compile Xilinx Vivado UNISIM and UNIMACRO libraries for ghdl
12,7 → 12,9
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.B xviv_ghdl_unisim
.SY xviv_ghdl_unisim
.RI [ GHDL-OPTIONS ]...
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
40,8 → 42,14
tools but not by \fBghdl\fP.
The \fBxilinx_vhdl_memcolltype_fix\fP
helper script simply removes them, no further problems seen so far.
 
.
.\" ------------------------------------------------------------------
.SH OPTIONS
Options added after the xviv_ghdl_unisim command are simply forwarded to
the 'ghdl -a' commands. In general used to specify the optimize level.
If no options given \fI-O2 -g\fP is used.
.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT
.IP \fBXTWV_PATH\fP
points to the root of the currently active Vivado installation.
/trunk/doc/man/man5/vbom.5
1,11 → 1,11
.\" -*- nroff -*-
.\" $Id: vbom.5 779 2016-06-26 15:37:16Z mueller $
.\" $Id: vbom.5 782 2016-07-03 08:09:36Z mueller $
.\"
.\" Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH VBOM 2016-03-19 "Retro Project" "Retro Project Manual"
.TH VBOM 2016-07-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
vbom \- vhdl manifest file format - 'vhdl bill of material'
48,13 → 48,15
.B "\fB.v\fP"
.TQ
.B "\fB.sv\fP"
refers to a verilog or system-verilog source file. Accepted by the vivado
refers to a verilog or system verilog source file. Accepted by the vivado
xsim simulator. Typically used for DPI wrappers or simprim based models
in vivado.
.
.IP "\fB.c\fP"
refers to the C source which implements a \fIvhdl\fP function or procedure
via the \fIvhpi\fP mechanism. Supported only in conjunction with \fBghdl\fP.
refers to the C sources which implement either a vhdl function or
procedure via the VHPI mechanism or a system verilog functions
via the DPI mechanism. Supported only in conjunction with ghdl
and vivado simulator.
.
.RE
.
/trunk/doc/w11a_tb_guide.txt
1,4 → 1,4
# $Id: w11a_tb_guide.txt 779 2016-06-26 15:37:16Z mueller $
# $Id: w11a_tb_guide.txt 810 2016-10-02 16:51:12Z mueller $
 
Note: - Ghdl is used for all behavioral simulations
- Optionally Vivado xsim can be used
7,22 → 7,25
- For timing simulations only Vivado xsim can be used.
- ISE isim is also available, but considered legacy support
 
Guide to running w11a test benches
Guide to running test benches
 
Table of content:
1. Unit tests benches
2. Available unit tests benches
3. System tests benches
4. Available system tests benches
1. Tests bench environment
2. Unit test benches
3. System test benches
4. Test bench driver
5. Execute all available tests
6. Available unit tests benches
7. Available system tests benches
 
 
1. Unit tests benches -----------------------------------------------------
1. Tests bench environment ------------------------------------------------
 
All unit test benches have the same simple structure:
All test benches have the same simple structure:
 
- a stimulus process reads test patterns as well as the expected
responses from a stimulus file
- the test benches are 'self-checking'. For unit tests a stimulus process
reads test patterns as well as the expected responses from a stimulus file
 
- the responses are checked in very simple cases by the stimulus process,
in general by a monitoring process
35,121 → 38,41
 
- at the end a line with the word "DONE" is printed.
 
- the test bench is run like
- Most tests can be run as
- bsim: the behavioral model
- ssim: post-synthesis functional
- osim: post-optimization functional
- rsim: post-routing functional
- esim: post-synthesis timing
- psim: post-optimization timing
- tsim: post-routing timing
 
tbw <testbenchname> [stimfile] | tee <logfile> | egrep "(FAIL|DONE)"
 
where
- 'tbw' is a small perl script setting up a symbolic link to the
stimulus file, the default extracted from the file tbw.dat, if
an optional file name is give this one will be used instead.
- 'tee' ensures that the full log is saved
- 'egrep' filters FAIL and DONE lines, a successful run will
produce a single DONE line
 
- Most tests can be run against
- the behavioral model
- post-synthesis functional
- post-optimization functional
- post-routing functional
- post-synthesis timing
- post-optimization timing
- post-routing timing
 
Building the simulation models is handled by the build environment. See
README_buildsystem_Vivado.txt for details of the vivado flow and
README_buildsystem_ISE.txt for the ISE flow.
 
An example of a post-synthesis model is given for the w11a core test.
2. Unit test benches ------------------------------------------------------
 
- for convenience a wrapper script 'tbrun_tbw' is used to generate the
tbw|tee|egrep pipe. This script also checks with 'make' whether the
test bench is up-to-date or must be (re)-compiled.
All unit test are executed via 'tbw' (test bench warpper) script.
 
2. Available unit tests benches -------------------------------------------
- the test bench is run like
 
In the following the available tests are listed with their tbrun_tbw which
- will call 'make' to build them
- and create the pipe setup to run them
and the expected output (the run time measured on a 3 GHz system)
tbw <testbenchname> [stimfile] | tbfilt --tee <logfile>
 
- serport receiver test
cd $RETROBASE/rtl/vlib/serport/tb
tbrun_tbw tb_serport_uart_rx
-> 1269955.0 ns 63488: DONE
-> real 0m0.531s user 0m0.392s sys 0m0.014s
where
- tbw sets up the environment of the test bench and starts it.
It generates required symbolic links, e.g. to the stimulus file,
the defaults extracted from the file tbw.dat, if an optional file
name is give this one will be used instead.
- tbfilt saves the full test bench output to a logfile and filters
the output for PASS/FAIL criteria
 
- serport receiver/transmitter test
tbrun_tbw tb_serport_uart_rxtx
-> 52335.0 ns 2607: DONE
-> real 0m0.120s user 0m0.065s sys 0m0.013s
- for convenience a wrapper script 'tbrun_tbw' is used to generate the
tbw|tbfilt pipe. This script also checks with 'make' whether the
test bench is up-to-date or must be (re)-compiled.
 
- serport autobauder test
tbrun_tbw tb_serport_autobaud
-> 367475.0 ns 18364: DONE
-> real 0m0.343s user 0m0.316s sys 0m0.003s
3. System test benches ----------------------------------------------------
 
- 9 bit comma,data to Byte stream converter test
cd $RETROBASE/rtl/vlib/comlib/tb
tbrun_tbw tb_cdata2byte
-> 7261.0 ns 354: DONE
-> real 0m0.088s user 0m0.057s sys 0m0.013s
 
- rlink core test
 
cd $RETROBASE/rtl/vlib/rlink/tb
tbrun_tbw tb_rlink_direct
-> 78975.0 ns 3939: DONE
-> real 0m0.270s user 0m0.222s sys 0m0.026s
 
- rlink core test via serial port interface
 
cd $RETROBASE/rtl/vlib/rlink/tb
tbrun_tbw --lsuf stim2_bsim tb_rlink_sp1c tb_rlink_sp1c_stim.dat
-> 27595.0 ns 1370: DONE
-> real 0m0.184s user 0m0.145s sys 0m0.011s
 
tbrun_tbw --lsuf stim1_bsim tb_rlink_sp1c tb_rlink_stim.dat
-> 420295.0 ns 21005: DONE
-> real 0m0.939s user 0m0.945s sys 0m0.026s
 
- w11a core test
- using behavioral model
 
cd $RETROBASE/rtl/w11a/tb
tbrun_tbw tb_pdp11core
-> 225355.0 ns 61258: DONE
-> real 0m6.446s user 0m6.387s sys 0m0.024s
 
- using Vivado post-synthesis vhdl model and ghdl
 
tbrun_tbw tb_pdp11core_ssim
-> 1225355.0 ns 61258: DONE
-> real 1m40.446s user 1m40.344s sys 0m0.075s
 
- using Vivado post-synthesis verilog model and xsim
 
tbrun_tbw tb_pdp11core_XSim_ssim
-> 1225355.0 ns 61258: DONE
-> real 1m14.835s user 1m13.997s sys 0m1.011s
 
- s3board sram controller test
 
cd $RETROBASE/rtl/bplib/s3board/tb
tbrun_tbw tb_s3_sram_memctl
-> 5015.0 ns 241: DONE
-> real 0m0.075s user 0m0.045s sys 0m0.022s
 
- nexys2/nexys3 cram controller test
 
cd $RETROBASE/rtl/bplib/nxcramlib/tb
tbrun_tbw tb_nx_cram_memctl_as
-> 24272.5 ns 1204: DONE
-> real 0m0.337s user 0m0.147s sys 0m0.146s
 
3. System tests benches ---------------------------------------------------
 
The system tests allow to verify to verify a full system design.
In this case vhdl test bench code contains
- (simple) models of the memories used on the FPGA boards
163,183 → 86,93
simulation, or via a serial port to a FPGA board. This way the same tests
can be executed in simulation and on real hardware.
 
4. Available system tests benches -----------------------------------------
In general the script 'tbrun_tbwrri' is used to generate the quite lengthy
ommand to properly setup the tbw|tbfilt pipe. This script also checks
with 'make' whether the test bench is up-to-date or must be (re)-compiled.
 
4a. serport tester ---------------------------------------------------
4. Test bench driver ------------------------------------------------------
 
The sys_tst_serloop design is a test target for validating the serial
link UART stack. Send and receive throughput as well as loop-back tests
are supported
All available tests (unit and system test benches) are described in a
set of descriptor files, usually called 'tbrun.yml'. The top level file
in $RETROBASE includes other descriptor files located in the source
directories of the tests.
 
- sys_tst_serloop_s3 test bench
The script 'tbrun' reads these descriptor files, selects tests based
on --tag and --exclude options, and executes the tests with the
simulation engine and simulation type given by the --mode option.
For full description of see 'man tbrun'.
 
cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb
tbrun_tbw tb_tst_serloop_s3
-> 301353.3 ns 18068: DONE
-> real 0m0.832s user 0m0.765s sys 0m0.036s
The low level drivers 'tbrun_tbw' and 'tbrun_tbwrri' will automatically
build the model if it is not available or outdated. This is very convenient
when working with a single test bench during development.
 
- sys_tst_serloop_n2 test bench
When executing a large number of them it's in general better to separate
the model building (make phase) made model execution (run phase). Both
the low level drivers as well as 'tbrun' support this via the options
--nomake and --norun.
 
cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb
tbrun_tbw tb_tst_serloop1_n2
-> 361560.0 ns 18068: DONE
-> real 0m0.799s user 0m0.758s sys 0m0.021s
The individial test benches are simplest started via tbrun and a proper
selection via --tag. Very helpful is
 
tbrun_tbw tb_tst_serloop2_n2
-> 304353.3 ns 18248: DONE
-> real 0m1.274s user 0m1.236s sys 0m0.017s
cd $RETROBASE
tbrun --dry --tag=.*
 
- sys_tst_serloop_n3 test bench
which gives a listing of all available test. The tag list as well as
the shell commands to execute the test are shown.
 
cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb
tbrun_tbw tb_tst_serloop1_n3
-> 361560.0 ns 18068: DONE
-> real 0m0.841s user 0m0.820s sys 0m0.014s
5. Execute all available tests --------------------------------------------
 
4b. rlink tester -----------------------------------------------------
As stated above it is in general better to to separate the model building
(make phase) made model execution (run phase). The currently recommended
way to execute all test benches is given below.
The run time is measured on a 3 GHz dual core system.
 
The sys_tst_rlink design is a test target for validating the rlink and
rbus functionality at all levels.
cd $RETROBASE
# build all behavioral models
# first all with ISE work flow
time nice tbrun -j 2 -norun -tag=ise -tee=tbrun_make_ise_bsim.log
# --> real 3m41.732s user 6m3.381s sys 0m24.224s
 
- Artix based systems
# than all with vivado work flow
time nice tbrun -j 2 -norun -tag=viv -tee=tbrun_make_viv_bsim.log
# --> real 3m36.532s user 5m58.319s sys 0m25.235s
# than execute all behavioral models
time nice tbrun -j 2 -nomake -tag=ise -tee=tbrun_run_ise_bsim.log
# --> real 3m19.799s user 5m45.060s sys 0m6.625s
time nice tbrun -j 2 -nomake -tag=viv -tee=tbrun_run_viv_bsim.log
#--> real 3m49.193s user 5m44.063s sys 0m5.332s
 
- sys_tst_rlink_arty test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/arty/tb
tbrun_tbwrri --hxon --pack tst_rlink tb_tst_rlink_arty \
"tst_rlink::setup" "tst_rlink::test_all"
-> 1028590.0 ns 102838: DONE
-> real 0m14.163s user 0m12.637s sys 0m0.152s
All test create an individual logfile. 'tbfilt' can be used to scan
these logfiles and create a summary with
 
- sys_tst_rlink_b3 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/basys3/tb
tbrun_tbwrri --hxon --pack tst_rlink tb_tst_rlink_b3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 1028820.0 ns 102861: DONE
-> real 0m9.275s user 0m9.041s sys 0m0.094s
tbfilt -all -sum -comp
It should look like
76m 0m00.034s c 0.92u 0 PASS tb_is61lv25616al_bsim.log
76m 0m00.153s c 4.00u 0 PASS tb_mt45w8mw16b_bsim.log
76m 0m00.168s c 1146 0 PASS tb_nx_cram_memctl_as_bsim.log
...
...
76m 0m03.729s c 61258 0 PASS tb_pdp11core_bsim_base.log
76m 0m00.083s c 1121 0 PASS tb_pdp11core_bsim_ubmap.log
76m 0m00.068s c 1031 0 PASS tb_rlink_tba_pdp11core_bsim_ibdr.log
 
- sys_tst_rlink_n4 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys4/tb
tbrun_tbwrri --pack tst_rlink tb_tst_rlink_n4 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 1020240.0 ns 102003: DONE
-> real 0m9.751s user 0m9.544s sys 0m0.081s
6. Available unit tests benches -------------------------------------------
 
tbrun --tag=comlib # comlib unit tests
tbrun --tag=serport # serport unit tests
tbrun --tag=rlink # rlink unit tests
tbrun --tag=issi # SRAM model unit tests
tbrun --tag=micron # CRAM model unit tests
tbrun --tag=sram_memctl # SRAM controller unit tests
tbrun --tag=cram_memctl # CRAM controller unit tests
tbrun --tag=w11a # w11a unit tests
 
- Spartan based systems
7. Available system tests benches -----------------------------------------
 
- sys_tst_rlink_n3 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb
tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_n3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 1024980.0 ns 102477: DONE
-> real 0m8.081s user 0m7.904s sys 0m0.106s
 
- sys_tst_rlink_n2 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_n2 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 2049320.0 ns 102455: DONE
-> real 0m7.934s user 0m7.748s sys 0m0.114s
 
- sys_tst_rlink_s3 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb
tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_s3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 2049720.0 ns 102476: DONE
-> real 0m7.612s user 0m7.437s sys 0m0.075s
 
4c. rlink tester, Cypress FX2 based version --------------------------
 
The sys_tst_rlink_cuff design is a test target for validating the rlink and
rbus functionality at all levels over the Cypress FX2 USB interface which
is provided by the Nexys2 abd Nexys3 boards.
 
- sys_tst_rlink_cuff_ic_n3 test bench
 
cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
tbrun_tbwrri --cuff --pack tst_rlink tb_tst_rlink_cuff_ic_n3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 558770.0 ns 55856: DONE
-> real 0m7.679s user 0m7.433s sys 0m0.185s
 
- sys_tst_rlink_cuff_ic_n2 test bench
 
cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
tbrun_tbwrri --cuff --pack tst_rlink tb_tst_rlink_cuff_ic_n2 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 596300.0 ns 29804: DONE
-> real 0m3.741s user 0m3.542s sys 0m0.127s
 
4d. w11a systems -----------------------------------------------------
 
The stimulus file used in the w11a core test can be executed in the full
system context with the following commands. Note that the cycle number
printed in the DONE line can now vary slightly because the response time of
the rlink backend process and thus scheduling of backend vs. ghdl process
can affect the result.
 
For convenience a wrapper script 'tbrun_tbwrri' is used to generate the
required quite long ti_rri command. Like for 'tbrun_tbw' the script also
checks with 'make' whether the test bench is up-to-date or must be
(re)-compiled.
 
- Artix based systems
 
cd $RETROBASE/rtl/sys_gen/w11a/nexys4/tb
tbrun_tbwrri --pack rw11 tb_w11a_n4 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 4812818.3 ns 577513: DONE
-> real 1m11.139s user 1m10.726s sys 0m0.545s
 
- Spartan based systems
- sys_w11a_n3 test bench
cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb
tbrun_tbwrri --cuff --pack rw11 tb_w11a_n3 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 3612428.7 ns 231182: DONE
-> real 0m47.454s user 0m47.241s sys 0m0.456s
 
- sys_w11a_n2 test bench
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
tbrun_tbwrri --cuff --pack rw11 tb_w11a_n2 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 4009900.0 ns 200484: DONE
-> real 0m45.429s user 0m45.215s sys 0m0.480s
 
- sys_w11a_s3 test bench
cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
tbrun_tbwrri --fusp --pack rw11 tb_w11a_s3 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 10528880.0 ns 526434: DONE
-> real 1m13.706s user 1m13.483s sys 0m0.470s
 
 
A new, modular w11a test bench is under construction. So far it is very
incomplete. This very preliminary version can be executed with
 
- sys_w11a_n2 test bench
 
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
tbrun_tbwrri --cuff --lsuf tbench_bsim --pack rw11 tb_w11a_n2 \
"rw11::setup_cpu" "rw11::tbench @cpu_all.dat"
-> 3268940.0 ns 163436: DONE
-> real 0m30.761s user 0m31.576s sys 0m0.502s
 
tbrun_tbwrri --cuff --lsuf tbench_bsim --pack rw11 tb_w11a_n2 \
"rw11::setup_cpu" "rw11::tbench @dev_all.dat"
-> 1376360.0 ns 68807: DONE
-> real 0m16.991s user 0m17.049s sys 0m0.235s
 
tbrun --tag=sys_tst_serloop.* # all sys_tst_serloop designs
tbrun --tag=sys_tst_rlink # all sys_tst_rlink designs
tbrun --tag=sys_tst_rlink_cuff # all sys_tst_rlink_cuff designs
tbrun --tag=sys_tst_sram # all sys_tst_sram designs
tbrun --tag=sys_w11a # all w11a designs
/trunk/rtl/bplib/arty/tb/sys_conf_sim.vhd
0,0 → 1,54
-- $Id: sys_conf_sim.vhd 726 2016-01-31 23:02:31Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_arty_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2015.4; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-31 726 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package sys_conf is
 
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
 
-- derived constants
 
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
 
end package sys_conf;
 
/trunk/rtl/bplib/arty/tb/tb_arty.vbom
11,6 → 11,7
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
${gsr_pulse := ../../../vlib/xlib/gsr_pulse_dummy.vbom}
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
/trunk/rtl/bplib/arty/tb/tb_arty.vhd
1,4 → 1,4
-- $Id: tb_arty.vhd 748 2016-03-20 15:18:50Z mueller $
-- $Id: tb_arty.vhd 809 2016-09-18 19:49:14Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
26,10 → 26,12
-- To test: generic, any arty_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.33
-- Tool versions: viv 2015.4-2016.2; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-18 809 1.3 add gsr_pulse (provisional....)
-- 2016-09-02 805 1.2.1 tbcore_rlink without CLK_STOP now
-- 2016-03-20 748 1.2 BUGFIX: add PORTSEL_XON logic
-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config
-- 2016-02-20 734 1.0.2 use s7_cmt_sfs_tb to avoid xsim conflict
59,7 → 61,6
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
86,10 → 87,12
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
 
begin
 
GINIT : entity work.gsr_pulse;
CLKGEN : simclk
generic map (
96,8 → 99,7
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
CLKGEN_COM : entity work.s7_cmt_sfs_tb
120,7 → 122,6
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
/trunk/rtl/bplib/basys3/tb/basys3_dummy.vbom
0,0 → 1,5
# libs
../../../vlib/slvtypes.vhd
# components
# design
basys3_dummy.vhd
/trunk/rtl/bplib/basys3/tb/basys3_dummy.vhd
0,0 → 1,59
-- $Id: basys3_dummy.vhd 726 2016-01-31 23:02:31Z mueller $
--
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: basys3_dummy - syn
-- Description: basys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_basys3
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2014.4; ghdl 0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-31 726 1.0.1 fix typos
-- 2015-01-15 634 1.0 Initial version (derived from nexys4_dummy)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
entity basys3_dummy is -- BASYS 3 dummy (base; loopback)
-- implements basys3_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv16; -- b3 switches
I_BTN : in slv5; -- b3 buttons
O_LED : out slv16; -- b3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end basys3_dummy;
 
architecture syn of basys3_dummy is
begin
 
O_TXD <= I_RXD; -- loop back serport
 
O_LED <= I_SWI; -- mirror SWI on LED
 
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
end syn;
/trunk/rtl/bplib/basys3/tb/sys_conf_sim.vhd
0,0 → 1,54
-- $Id: sys_conf_sim.vhd 810 2016-10-02 16:51:12Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_basys3_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-10-01 810 1.0 Initial version (cloned from nexys4)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package sys_conf is
 
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
 
-- derived constants
 
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
 
end package sys_conf;
 
/trunk/rtl/bplib/basys3/tb/tb_basys3.vhd
1,4 → 1,4
-- $Id: tb_basys3.vhd 748 2016-03-20 15:18:50Z mueller $
-- $Id: tb_basys3.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
26,10 → 26,11
-- To test: generic, any basys3_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33
-- Tool versions: viv 2014.4-2016.2; ghdl 0.31-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.1.4 tbcore_rlink without CLK_STOP now
-- 2016-02-20 734 1.1.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.1.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.1.1 use serport/tb/serport_master_tb
59,7 → 60,6
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
84,8 → 84,8
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
 
begin
94,8 → 94,7
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
CLKGEN_COM : entity work.s7_cmt_sfs_tb
118,7 → 117,6
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
/trunk/rtl/bplib/bpgen/Makefile
0,0 → 1,37
# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-20 749 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#
/trunk/rtl/bplib/fx2lib/tb/fx2_2fifo_core.vhd
1,6 → 1,6
-- $Id: fx2_2fifo_core.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: fx2_2fifo_core.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
18,9 → 18,10
-- Dependencies: memlib/fifo_2c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.0.1 proc_ifclk: remove clock stop (not needed anymore)
-- 2013-01-04 469 1.0 Initial version
------------------------------------------------------------------------------
 
131,15 → 132,15
);
 
proc_ifclk: process
constant offset : time := 200 ns;
constant halfperiod_7 : time := 16700 ps;
constant halfperiod_6 : time := 16600 ps;
constant offset : Delay_length := 200 ns;
constant halfperiod_7 : Delay_length := 16700 ps;
constant halfperiod_6 : Delay_length := 16600 ps;
begin
 
CLK30 <= '0';
wait for offset;
 
clk_loop: loop
loop
CLK30 <= '1';
wait for halfperiod_7;
CLK30 <= '0';
152,11 → 153,8
wait for halfperiod_7;
CLK30 <= '0';
wait for halfperiod_6;
exit clk_loop when to_x01(SB_CLKSTOP) = '1';
end loop;
wait; -- endless wait, simulator will stop
end process proc_ifclk;
 
proc_state: process (CLK30)
/trunk/rtl/bplib/issi/is61lv25616al.vhd
1,4 → 1,4
-- $Id: is61lv25616al.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: is61lv25616al.vhd 790 2016-07-20 18:52:44Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
126,18 → 126,18
 
architecture sim of is61lv25616al_bank is
 
constant T_rc : time := 10 ns; -- read cycle time (min)
constant T_aa : time := 10 ns; -- address access time (max)
constant T_oha : time := 2 ns; -- output hold time (min)
constant T_ace : time := 10 ns; -- ce access time (max)
constant T_doe : time := 4 ns; -- oe access time (max)
constant T_hzoe : time := 4 ns; -- oe to high-Z output (max)
constant T_lzoe : time := 0 ns; -- oe to low-Z output (min)
constant T_hzce : time := 4 ns; -- ce to high-Z output (min=0,max=4)
constant T_lzce : time := 3 ns; -- ce to low-Z output (min)
constant T_ba : time := 4 ns; -- lb,ub access time (max)
constant T_hzb : time := 3 ns; -- lb,ub to high-Z output (min=0,max=3)
constant T_lzb : time := 0 ns; -- lb,ub low-Z output (min)
constant T_rc : Delay_length := 10 ns; -- read cycle time (min)
constant T_aa : Delay_length := 10 ns; -- address access time (max)
constant T_oha : Delay_length := 2 ns; -- output hold time (min)
constant T_ace : Delay_length := 10 ns; -- ce access time (max)
constant T_doe : Delay_length := 4 ns; -- oe access time (max)
constant T_hzoe : Delay_length := 4 ns; -- oe to high-Z output (max)
constant T_lzoe : Delay_length := 0 ns; -- oe to low-Z output (min)
constant T_hzce : Delay_length := 4 ns; -- ce to high-Z output (min=0,max=4)
constant T_lzce : Delay_length := 3 ns; -- ce to low-Z output (min)
constant T_ba : Delay_length := 4 ns; -- lb,ub access time (max)
constant T_hzb : Delay_length := 3 ns; -- lb,ub to high-Z out (min=0,max=3)
constant T_lzb : Delay_length := 0 ns; -- lb,ub low-Z output (min)
 
constant memsize : positive := 2**(ADDR'length);
constant datzero : slv(DATA'range) := (others=>'0');
/trunk/rtl/bplib/issi/tb/.cvsignore
0,0 → 1,2
tb_is61lv25616al
tb_is61lv25616al_stim
/trunk/rtl/bplib/issi/tb/Makefile
0,0 → 1,46
# $Id: Makefile 804 2016-08-28 17:33:50Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-28 804 1.3 remove ISim, add XSim support
# 2011-08-13 405 1.2 use includes from rtl/make
# 2009-11-21 252 1.1 add ISim support
# 2007-12-14 101 1.0 Initial version
#
EXE_all = tb_is61lv25616al
 
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_osim clean
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_osim : $(EXE_all:=_osim)
#
all_XSim : $(EXE_all:=_XSim)
all_XSim_ssim : $(EXE_all:=_XSim_ssim)
all_XSim_osim : $(EXE_all:=_XSim_osim)
all_XSim_tsim : $(EXE_all:=_XSim_tsim)
#
clean : viv_clean ghdl_clean xsim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsim)
endif
#
/trunk/rtl/bplib/issi/tb/tb_is61lv25616al.vbom
0,0 → 1,7
#
# libs
../../../vlib/simlib/simlib.vhd
# components
../is61lv25616al.vbom
# design
tb_is61lv25616al.vhd
/trunk/rtl/bplib/issi/tb/tb_is61lv25616al.vhd
0,0 → 1,193
-- $Id: tb_is61lv25616al.vhd 790 2016-07-20 18:52:44Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_is61lv25616al - sim
-- Description: Test bench for is61lv25616al memory model
--
-- Dependencies: is61lv25616al [UUT]
--
-- To test: is61lv25616al
--
-- Verified (with tb_is61lv25616al_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2010-05-16 291 - 0.26 - - c:ok
-- 2007-12-15 101 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-21 432 1.1.1 now numeric_std clean
-- 2010-05-16 291 1.1 initial values for all act.low signals now '1'
-- 2007-12-14 101 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.simlib.all;
 
entity tb_is61lv25616al is
end tb_is61lv25616al;
 
architecture sim of tb_is61lv25616al is
signal CE_N : slbit := '1';
signal OE_N : slbit := '1';
signal WE_N : slbit := '1';
signal UB_N : slbit := '1';
signal LB_N : slbit := '1';
signal ADDR : slv18 := (others=>'0');
signal DATA : slv16 := (others=>'0');
begin
 
UUT : entity work.is61lv25616al
port map (
CE_N => CE_N,
OE_N => OE_N,
WE_N => WE_N,
UB_N => UB_N,
LB_N => LB_N,
ADDR => ADDR,
DATA => DATA
);
 
proc_stim: process
file fstim : text open read_mode is "tb_is61lv25616al_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idtime : Delay_length := 0 ns;
variable imatch : boolean := false;
variable ival : slbit := '0';
variable ival2 : slv2 := (others=>'0');
variable ival16 : slv16 := (others=>'0');
variable ival18 : slv18 := (others=>'0');
variable ice : slbit := '0';
variable ioe : slbit := '0';
variable iwe : slbit := '0';
variable ibe : slv2 := "00";
variable iaddr : slv18 := (others=>'0');
variable idata : slv16 := (others=>'0');
variable ide : slbit := '0';
variable idchk : slv16 := (others=>'0');
 
begin
 
file_loop: while not endfile(fstim) loop
 
readline (fstim, iline);
 
readcomment(iline, ok);
next file_loop when ok;
 
readword(iline, dname, ok);
if ok then
case dname is
when "wdo " => -- wdo
read_ea(iline, idtime);
wait for idtime;
 
readtagval_ea(iline, "ce", imatch, ival);
if imatch then ice := ival; end if;
readtagval_ea(iline, "oe", imatch, ival);
if imatch then ioe := ival; end if;
readtagval_ea(iline, "we", imatch, ival);
if imatch then iwe := ival; end if;
readtagval_ea(iline, "be", imatch, ival2, 2);
if imatch then ibe := ival2; end if;
readtagval_ea(iline, "a", imatch, ival18, 16);
if imatch then iaddr := ival18; end if;
readtagval_ea(iline, "de", imatch, ival);
if imatch then ide := ival; end if;
readtagval_ea(iline, "d", imatch, ival16, 16);
if imatch then idata := ival16; end if;
 
CE_N <= not ice;
OE_N <= not ioe;
WE_N <= not iwe;
LB_N <= not ibe(0);
UB_N <= not ibe(1);
ADDR <= iaddr;
if ide = '1' then
DATA <= idata;
else
DATA <= (others=>'Z');
end if;
 
write(oline, now, right, 12);
write(oline, string'(": wdo "));
write(oline, string'(" ce="));
write(oline, ice);
write(oline, string'(" oe="));
write(oline, ioe);
write(oline, string'(" we="));
write(oline, iwe);
write(oline, string'(" be="));
write(oline, ibe, right, 2);
write(oline, string'(" a="));
writegen(oline, iaddr, right, 5, 16);
write(oline, string'(" de="));
write(oline, ide);
if ide = '1' then
write(oline, string'(" d="));
writegen(oline, idata, right, 4, 16);
end if;
readtagval_ea(iline, "D", imatch, idchk, 16);
if imatch then
write(oline, string'(" D="));
writegen(oline, DATA, right, 4, 16);
write(oline, string'(" CHECK"));
if DATA = idchk then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL exp="));
writegen(oline, idchk, right, 4, 16);
end if;
end if;
 
writeline(output, oline);
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
 
else
report "failed to find command" severity failure;
end if;
 
testempty_ea(iline);
 
end loop;
 
write(oline, now, right, 12);
write(oline, string'(": DONE"));
writeline(output, oline);
 
wait; -- suspend proc_stim forever
-- no clock, sim will end
 
end process proc_stim;
 
end sim;
/trunk/rtl/bplib/issi/tb/tb_is61lv25616al_stim.dat
0,0 → 1,92
# $Id: tb_is61lv25616al_stim.dat 146 2008-05-16 19:17:42Z mueller $
#
C Write first 8 cells, full words
#
wdo 0 ns ce=1 be=11 a=00000 de=1 d=1000
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00001 de=1 d=1101
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00002 de=1 d=1202
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00003 de=1 d=1303
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00004 de=1 d=1404
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00005 de=1 d=1505
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00006 de=1 d=1606
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00007 de=1 d=1707
wdo 10 ns we=1
wdo 20 ns we=0
#
wdo 10 ns be=11 de=0
wdo 20 ns
#
C Read first 8 cells
#
wdo 20 ns oe=1 a=00000
wdo 20 ns D=1000
wdo 0 ns oe=1 a=00001
wdo 20 ns D=1101
wdo 0 ns oe=1 a=00002
wdo 20 ns D=1202
wdo 0 ns oe=1 a=00003
wdo 20 ns D=1303
wdo 0 ns oe=1 a=00004
wdo 20 ns D=1404
wdo 0 ns oe=1 a=00005
wdo 20 ns D=1505
wdo 0 ns oe=1 a=00006
wdo 20 ns D=1606
wdo 0 ns oe=1 a=00007
wdo 20 ns D=1707
#
wdo 0 ns oe=0
wdo 20 ns
#
C Byte write in last 4 cells
wdo 0 ns ce=1 be=00 a=00004 de=1 d=3414 -- no write
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=01 a=00005 de=1 d=3515 -- low byte write
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=10 a=00006 de=1 d=3616 -- high byte write
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00007 de=1 d=3717 -- full word write
wdo 10 ns we=1
wdo 20 ns we=0
#
wdo 10 ns be=11 de=0
wdo 20 ns
#
C Read again first 8 cells
#
wdo 20 ns oe=1 a=00000
wdo 20 ns D=1000
wdo 0 ns oe=1 a=00001
wdo 20 ns D=1101
wdo 0 ns oe=1 a=00002
wdo 20 ns D=1202
wdo 0 ns oe=1 a=00003
wdo 20 ns D=1303
wdo 0 ns oe=1 a=00004
wdo 20 ns D=1404
wdo 0 ns oe=1 a=00005
wdo 20 ns D=1515
wdo 0 ns oe=1 a=00006
wdo 20 ns D=3606
wdo 0 ns oe=1 a=00007
wdo 20 ns D=3717
#
wdo 20 ns
#
/trunk/rtl/bplib/issi/tb/tbrun.yml
0,0 → 1,13
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-00-10 806 1.1 use nossim because no _ssim support available
# 2016-08-12 797 1.0 Initial version
#
- default:
mode: ${viv_modes_nossim}
#
- tag: [default, viv, bplib, issi]
test: |
tbrun_tbw tb_is61lv25616al${ms}
/trunk/rtl/bplib/issi/tb
trunk/rtl/bplib/issi/tb Property changes : Added: svn:ignore ## -0,0 +1,44 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb +tb_is61lv25616al +tb_is61lv25616al_stim Index: trunk/rtl/bplib/micron/mt45w8mw16b.vhd =================================================================== --- trunk/rtl/bplib/micron/mt45w8mw16b.vhd (revision 36) +++ trunk/rtl/bplib/micron/mt45w8mw16b.vhd (revision 37) @@ -1,6 +1,6 @@ --- $Id: mt45w8mw16b.vhd 718 2015-12-26 15:59:48Z mueller $ +-- $Id: mt45w8mw16b.vhd 799 2016-08-21 09:20:19Z mueller $ -- --- Copyright 2010-2015 by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,7 +16,7 @@ -- Description: Micron MT45W8MW16B CellularRAM model -- Currently a much simplified model -- - only async accesses --- - ignores CLK and CRE +-- - ignores CLK -- - simple model for response of DATA lines, but no -- check for timing violations of control lines -- @@ -23,9 +23,11 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-08-18 799 1.4.1 remove 'assert false' from report statements +-- 2016-07-10 786 1.4 add RCR handling; page mode by default now off !! -- 2015-12-26 718 1.3.3 BUGFIX: initialize L_ADDR with all '1', see comment -- 2011-11-19 427 1.3.2 now numeric_std clean -- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa) @@ -82,19 +84,23 @@ architecture sim of mt45w8mw16b is -- timing constants for -701 speed grade (70 ns; 104 MHz) - constant T_aa : time := 70 ns; -- address access time (max) - constant T_apa : time := 20 ns; -- page acess time (max) - constant T_oh : time := 5 ns; -- output hold from addr change (max) - constant T_oe : time := 20 ns; -- output enable to valid output (max) - constant T_ohz : time := 8 ns; -- output disable to high-z output (max) - constant T_olz : time := 3 ns; -- output enable to low-z output (min) - constant T_lz : time := 10 ns; -- chip enable to low-z output (min) - constant T_hz : time := 8 ns; -- chip disable to high-z output (max) + constant T_aa : Delay_length := 70 ns; -- address access time (max) + constant T_apa : Delay_length := 20 ns; -- page access time (max) + constant T_oh : Delay_length := 5 ns; -- output hold from addr change (max) + constant T_oe : Delay_length := 20 ns; -- output enable to valid output (max) + constant T_ohz : Delay_length := 8 ns; -- output disable to high-z out (max) + constant T_olz : Delay_length := 3 ns; -- output enable to low-z output (min) + constant T_lz : Delay_length := 10 ns; -- chip enable to low-z output (min) + constant T_hz : Delay_length := 8 ns; -- chip disable to high-z output (max) constant memsize : positive := 2**(ADDR'length); constant datzero : slv(DATA'range) := (others=>'0'); type ram_type is array (0 to memsize-1) of slv(DATA'range); + subtype xcr_f_sel is integer range 19 downto 18; -- cre register select + constant xcr_sel_rcr : slv2 := "00"; + constant xcr_sel_bcr : slv2 := "10"; + constant bcr_f_mode : integer := 15; -- operating mode constant bcr_f_ilat : integer := 14; -- initial latency subtype bcr_f_lc is integer range 13 downto 11; -- latency counter @@ -103,6 +109,14 @@ subtype bcr_f_drive is integer range 5 downto 4; -- drive strength constant bcr_f_bw : integer := 3; -- burst wrap subtype bcr_f_bl is integer range 2 downto 0; -- burst length + + subtype rcr_f_res3 is integer range 22 downto 20; -- reserved - MBZ + subtype rcr_f_res2 is integer range 17 downto 8; -- reserved - MBZ + constant rcr_f_pmode : integer := 7; -- page mode (1=ena) + subtype rcr_f_res1 is integer range 6 downto 5; -- reserved - MBZ + constant rcr_f_dpd : integer := 4; -- dpd mode (1=dis) + constant rcr_f_res0 : integer := 3; -- reserved - MBZ + subtype rcr_f_par is integer range 2 downto 0; -- array conf (000=all) subtype f_byte1 is integer range 15 downto 8; subtype f_byte0 is integer range 7 downto 0; @@ -115,6 +129,7 @@ signal ADV : slbit := '0'; signal WE_L_EFF : slbit := '0'; signal WE_U_EFF : slbit := '0'; + signal WE_C_EFF : slbit := '0'; signal R_BCR_MODE : slbit := '1'; -- mode: def: async signal R_BCR_ILAT : slbit := '0'; -- ilat: def: variable @@ -124,7 +139,12 @@ signal R_BCR_DRIVE : slv2 := "01"; -- drive:def: 1/2 signal R_BCR_BW : slbit := '1'; -- bw: def: no wrap signal R_BCR_BL : slv3 := "111"; -- bl: def: continuous - + + signal R_RCR_PMODE : slbit := '0'; -- pmode:def: disabled (ena=1 !) + signal R_RCR_DPD : slbit := '1'; -- dpd: def: disabled (ena=0 !) + signal R_RCR_PAR : slv3 := "000"; -- par: def: full array + signal R_T_APA_EFF : Delay_length := T_aa; -- page mode disabled by default + signal L_ADDR : slv23 := (others=>'1'); -- all '1' for propper 1st access signal DOUT_VAL_EN : slbit := '0'; signal DOUT_VAL_AA : slbit := '0'; @@ -144,9 +164,11 @@ BE_U <= not UB_N; ADV <= not ADV_N; - WE_L_EFF <= CE and WE and BE_L; - WE_U_EFF <= CE and WE and BE_U; + WE_L_EFF <= CE and WE and BE_L and (not CRE); + WE_U_EFF <= CE and WE and BE_U and (not CRE); + WE_C_EFF <= CE and WE and CRE; + -- address valid logic, latch ADDR when ADV true proc_adv: process (ADV, ADDR) begin @@ -174,7 +196,7 @@ DOUT_VAL_EN <= '0', '1' after T_aa; end if; if L_ADDR'event then - DOUT_VAL_PA <= '0', '1' after T_apa; + DOUT_VAL_PA <= '0', '1' after R_T_APA_EFF; if L_ADDR(22 downto 4) /= addr_last(22 downto 4) then DOUT_VAL_AA <= '0', '1' after T_aa; end if; @@ -207,7 +229,7 @@ end if; end process proc_dout_lz; - proc_cram: process (CE, OE, WE, WE_L_EFF, WE_U_EFF, L_ADDR, DATA) + proc_cram: process (WE_L_EFF, WE_U_EFF, L_ADDR, DATA) variable ram : ram_type := (others=>datzero); begin @@ -224,6 +246,39 @@ end process proc_cram; + proc_cr: process (WE_C_EFF, L_ADDR) + begin + if falling_edge(WE_C_EFF) then + case L_ADDR(xcr_f_sel) is + + when xcr_sel_rcr => + R_RCR_PMODE <= L_ADDR(rcr_f_pmode); + if L_ADDR(rcr_f_pmode) = '1' then + R_T_APA_EFF <= T_apa; + else + R_T_APA_EFF <= T_aa; + end if; + assert L_ADDR(rcr_f_res3) = "000" + report "bad rcr write: 22:20 not zero" severity error; + assert L_ADDR(rcr_f_res2) = "0000000000" + report "bad rcr write: 17: 8 not zero" severity error; + assert L_ADDR(rcr_f_res1) = "00" + report "bad rcr write: 6: 5 not zero" severity error; + assert L_ADDR(rcr_f_dpd) = '1' + report "bad rcr write: dpd not '1'" severity error; + assert L_ADDR(rcr_f_res0) = '0' + report "bad rcr write: 3: 3 not zero" severity error; + assert L_ADDR(rcr_f_par) = "000" + report "bad rcr write: par not '000'" severity error; + + when xcr_sel_bcr => + report "bcr written - not supported" severity error; + when others => + report "bad select field" severity error; + end case; + end if; + end process proc_cr; + proc_data: process (DOUT, DOUT_VAL_EN, DOUT_VAL_AA, DOUT_VAL_PA, DOUT_VAL_OE, DOUT_LZ_CE, DOUT_LZ_OE) variable idout : slv16 := (others=>'0');
/trunk/rtl/bplib/micron/tb/.cvsignore
0,0 → 1,2
tb_mt45w8mw16b
tb_mt45w8mw16b_stim
/trunk/rtl/bplib/micron/tb/Makefile
0,0 → 1,46
# $Id: Makefile 804 2016-08-28 17:33:50Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-28 804 1.2 remove ISim, add XSim support
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-16 291 1.0 Initial version
#
EXE_all = tb_mt45w8mw16b
 
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_osim clean
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_osim : $(EXE_all:=_osim)
#
all_XSim : $(EXE_all:=_XSim)
all_XSim_ssim : $(EXE_all:=_XSim_ssim)
all_XSim_osim : $(EXE_all:=_XSim_osim)
all_XSim_tsim : $(EXE_all:=_XSim_tsim)
#
clean : viv_clean ghdl_clean xsim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsim)
endif
#
/trunk/rtl/bplib/micron/tb/tb_mt45w8mw16b.vbom
0,0 → 1,8
#
# libs
../../../vlib/simlib/simlib.vhd
# components
../mt45w8mw16b.vbom
../../../vlib/simlib/simbididly.vbom
# design
tb_mt45w8mw16b.vhd
/trunk/rtl/bplib/micron/tb/tb_mt45w8mw16b.vhd
0,0 → 1,247
-- $Id: tb_mt45w8mw16b.vhd 791 2016-07-21 22:01:10Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_mt45w8mw16b - sim
-- Description: Test bench for mt45w8mw16b memory model
--
-- Dependencies: mt45w8mw16b [UUT]
-- simlib/simbididly
--
-- To test: mt45w8mw16b
--
-- Verified (with tb_mt45w8mw16b_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2016-07-16 787 - 0.33 - - c:ok
-- 2010-05-16 291 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 787 1.2 test also CRE; use simbididly;
-- 2011-11-21 432 1.1.1 now numeric_std clean
-- 2010-05-16 291 1.0 Initial version (cloned from tb_is61lv25616al)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.simlib.all;
 
entity tb_mt45w8mw16b is
end tb_mt45w8mw16b;
 
architecture sim of tb_mt45w8mw16b is
 
constant pcb_delay : Delay_length := 1 ns;
signal MM_CE_N : slbit := '1';
signal MM_OE_N : slbit := '1';
signal MM_WE_N : slbit := '1';
signal MM_UB_N : slbit := '1';
signal MM_LB_N : slbit := '1';
signal MM_CRE : slbit := '0';
signal MM_MWAIT : slbit := '0';
signal MM_ADDR : slv23 := (others=>'0');
signal MM_DATA : slv16 := (others=>'Z');
signal TB_CE_N : slbit := '1';
signal TB_OE_N : slbit := '1';
signal TB_WE_N : slbit := '1';
signal TB_UB_N : slbit := '1';
signal TB_LB_N : slbit := '1';
signal TB_CRE : slbit := '0';
signal TB_MWAIT : slbit := '0';
signal TB_ADDR : slv23 := (others=>'0');
signal TB_DATA : slv16 := (others=>'Z');
 
begin
 
UUT : entity work.mt45w8mw16b
port map (
CLK => '0',
CE_N => MM_CE_N,
OE_N => MM_OE_N,
WE_N => MM_WE_N,
UB_N => MM_UB_N,
LB_N => MM_LB_N,
ADV_N => '0',
CRE => MM_CRE,
MWAIT => MM_MWAIT,
ADDR => MM_ADDR,
DATA => MM_DATA
);
 
MM_CE_N <= TB_CE_N after pcb_delay;
MM_OE_N <= TB_OE_N after pcb_delay;
MM_WE_N <= TB_WE_N after pcb_delay;
MM_UB_N <= TB_UB_N after pcb_delay;
MM_LB_N <= TB_LB_N after pcb_delay;
MM_CRE <= TB_CRE after pcb_delay;
MM_ADDR <= TB_ADDR after pcb_delay;
TB_MWAIT <= MM_MWAIT after pcb_delay;
 
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 16)
port map (
A => TB_DATA,
B => MM_DATA);
proc_stim: process
file fstim : text open read_mode is "tb_mt45w8mw16b_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idtime : Delay_length := 0 ns;
variable imatch : boolean := false;
variable ival : slbit := '0';
variable ival2 : slv2 := (others=>'0');
variable ival16 : slv16 := (others=>'0');
variable ival23 : slv23 := (others=>'0');
variable ice : slbit := '0';
variable ioe : slbit := '0';
variable iwe : slbit := '0';
variable ibe : slv2 := "00";
variable icre : slbit := '0';
variable iaddr : slv23 := (others=>'0');
variable idata : slv16 := (others=>'0');
variable ide : slbit := '0';
variable idchk : slv16 := (others=>'0');
 
begin
 
-- initial signal driver settings
TB_CE_N <= '1';
TB_OE_N <= '1';
TB_WE_N <= '1';
TB_UB_N <= '1';
TB_LB_N <= '1';
TB_CRE <= '0';
TB_ADDR <= (others=>'0');
TB_DATA <= (others=>'Z');
file_loop: while not endfile(fstim) loop
 
readline (fstim, iline);
 
readcomment(iline, ok);
next file_loop when ok;
 
readword(iline, dname, ok);
if ok then
case dname is
when "wdo " => -- wdo
read_ea(iline, idtime);
wait for idtime;
 
readtagval_ea(iline, "ce", imatch, ival);
if imatch then ice := ival; end if;
readtagval_ea(iline, "cre", imatch, ival);
if imatch then icre := ival; end if;
readtagval_ea(iline, "oe", imatch, ival);
if imatch then ioe := ival; end if;
readtagval_ea(iline, "we", imatch, ival);
if imatch then iwe := ival; end if;
readtagval_ea(iline, "be", imatch, ival2, 2);
if imatch then ibe := ival2; end if;
readtagval_ea(iline, "a", imatch, ival23, 16);
if imatch then iaddr := ival23; end if;
readtagval_ea(iline, "de", imatch, ival);
if imatch then ide := ival; end if;
readtagval_ea(iline, "d", imatch, ival16, 16);
if imatch then idata := ival16; end if;
 
TB_CE_N <= not ice;
TB_OE_N <= not ioe;
TB_WE_N <= not iwe;
TB_LB_N <= not ibe(0);
TB_UB_N <= not ibe(1);
TB_CRE <= icre;
TB_ADDR <= iaddr;
if ide = '1' then
TB_DATA <= idata;
else
TB_DATA <= (others=>'Z');
end if;
 
write(oline, now, right, 12);
write(oline, string'(": wdo "));
write(oline, string'(" ce="));
write(oline, ice);
write(oline, string'(" oe="));
write(oline, ioe);
write(oline, string'(" we="));
write(oline, iwe);
if icre = '0' then
write(oline, string'(" be="));
write(oline, ibe, right, 2);
else
write(oline, string'(" cre=1"));
end if;
write(oline, string'(" a="));
writegen(oline, iaddr, right, 6, 16);
write(oline, string'(" de="));
write(oline, ide);
if ide = '1' then
write(oline, string'(" d="));
writegen(oline, idata, right, 4, 16);
end if;
readtagval_ea(iline, "D", imatch, idchk, 16);
if imatch then
write(oline, string'(" D="));
writegen(oline, TB_DATA, right, 4, 16);
write(oline, string'(" CHECK"));
if TB_DATA = idchk then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL exp="));
writegen(oline, idchk, right, 4, 16);
end if;
end if;
 
writeline(output, oline);
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
 
else
report "failed to find command" severity failure;
end if;
 
testempty_ea(iline);
 
end loop;
 
write(oline, now, right, 12);
write(oline, string'(": DONE"));
writeline(output, oline);
 
wait; -- suspend proc_stim forever
-- no clock, sim will end
 
end process proc_stim;
 
end sim;
/trunk/rtl/bplib/micron/tb/tb_mt45w8mw16b_stim.dat
0,0 → 1,141
# $Id: tb_mt45w8mw16b_stim.dat 787 2016-07-16 14:40:41Z mueller $
#
C Write first 8 cells, full words
#
wdo 100 ns ce=1 be=11 a=000000 de=1 d=1000
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000001 de=1 d=1101
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000002 de=1 d=1202
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000003 de=1 d=1303
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000004 de=1 d=1404
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000005 de=1 d=1505
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000006 de=1 d=1606
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000007 de=1 d=1707
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 0 ns be=11 de=0
wdo 20 ns
#
C Read first 8 cells (full cycle per read)
#
wdo 0 ns ce=1 oe=1 a=000000
wdo 100 ns ce=0 D=1000
wdo 20 ns ce=1 a=000001
wdo 100 ns ce=0 D=1101
wdo 20 ns ce=1 a=000002
wdo 100 ns ce=0 D=1202
wdo 20 ns ce=1 a=000003
wdo 100 ns ce=0 D=1303
wdo 20 ns ce=1 a=000004
wdo 100 ns ce=0 D=1404
wdo 20 ns ce=1 a=000005
wdo 100 ns ce=0 D=1505
wdo 20 ns ce=1 a=000006
wdo 100 ns ce=0 D=1606
wdo 20 ns ce=1 a=000007
wdo 100 ns ce=0 D=1707
wdo 0 ns oe=0
wdo 20 ns
#
C Read first 4 cells (all in one CE, page mode timing, will be expect XXXX)
#
wdo 0 ns ce=1 oe=1 a=000000
wdo 100 ns a=000001 D=1000
wdo 40 ns a=000002 D=XXXX
wdo 40 ns a=000003 D=XXXX
wdo 40 ns D=XXXX
wdo 0 ns oe=0
wdo 20 ns
#
C Enable page mode
# addr to set rcr with pmode=1
# a(19:18) = 00 select
# a( 7) = 1 pmode
# a( 4) = 1 dpd (disable)
# --> addr = 00090
wdo 0 ns ce=1 cre=1 we=1 a=000090
wdo 80 ns ce=0 cre=0 we=0
wdo 20 ns
#
C Read first 8 cells (page mode, all in one CE)
#
wdo 0 ns ce=1 oe=1 a=000000
wdo 100 ns a=000001 D=1000
wdo 40 ns a=000002 D=1101
wdo 40 ns a=000003 D=1202
wdo 40 ns a=000004 D=1303
wdo 40 ns a=000005 D=1404
wdo 40 ns a=000006 D=1505
wdo 40 ns a=000007 D=1606
wdo 40 ns ce=0 D=1707
#
wdo 0 ns oe=0
wdo 20 ns
#
C Byte write in last 4 cells
wdo 0 ns ce=1 be=00 a=000004 de=1 d=3414 -- no write
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=01 a=000005 de=1 d=3515 -- low byte write
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=10 a=000006 de=1 d=3616 -- high byte write
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000007 de=1 d=3717 -- full word write
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 0 ns be=11 de=0
wdo 20 ns
#
C Read again first 8 cells (page mode, all in one CE)
#
wdo 0 ns ce=1 oe=1 a=000000
wdo 100 ns a=000001 D=1000
wdo 40 ns a=000002 D=1101
wdo 40 ns a=000003 D=1202
wdo 40 ns a=000004 D=1303
wdo 40 ns a=000005 D=1404
wdo 40 ns a=000006 D=1515
wdo 40 ns a=000007 D=3606
wdo 40 ns ce=0 D=3717
#
wdo 20 ns
#
/trunk/rtl/bplib/micron/tb/tbrun.yml
0,0 → 1,13
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-00-10 806 1.1 use nossim because no _ssim support available
# 2016-08-22 800 1.0 Initial version
#
- default:
mode: ${viv_modes_nossim}
#
- tag: [default, viv, bplib, micron, cram]
test: |
tbrun_tbw tb_mt45w8mw16b${ms}
/trunk/rtl/bplib/micron/tb
trunk/rtl/bplib/micron/tb Property changes : Added: svn:ignore ## -0,0 +1,44 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb +tb_mt45w8mw16b +tb_mt45w8mw16b_stim Index: trunk/rtl/bplib/nexys2/tb/nexys2_dummy.vbom =================================================================== --- trunk/rtl/bplib/nexys2/tb/nexys2_dummy.vbom (nonexistent) +++ trunk/rtl/bplib/nexys2/tb/nexys2_dummy.vbom (revision 37) @@ -0,0 +1,7 @@ +# libs +../../../vlib/slvtypes.vhd +../../nxcramlib/nxcramlib.vhd +# components +../../nxcramlib/nx_cram_dummy.vbom +# design +nexys2_dummy.vhd Index: trunk/rtl/bplib/nexys2/tb/nexys2_dummy.vhd =================================================================== --- trunk/rtl/bplib/nexys2/tb/nexys2_dummy.vhd (nonexistent) +++ trunk/rtl/bplib/nexys2/tb/nexys2_dummy.vhd (revision 37) @@ -0,0 +1,86 @@ +-- $Id: nexys2_dummy.vhd 444 2011-12-25 10:04:58Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: nexys2_dummy - syn +-- Description: nexys2 minimal target (base; serport loopback) +-- +-- Dependencies: - +-- To test: tb_nexys2 +-- Target Devices: generic +-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.3 remove clksys output hack +-- 2011-11-26 433 1.2 use nxcramlib +-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy +-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock) +-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50 +-- 2010-05-23 294 1.0 Initial version (derived from s3board_dummy) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.nxcramlib.all; + +entity nexys2_dummy is -- NEXYS 2 dummy (base; loopback) + -- implements nexys2_aif + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit -- flash ce.. (act.low) + ); +end nexys2_dummy; + +architecture syn of nexys2_dummy is + +begin + + O_TXD <= I_RXD; -- loop back + + CRAM : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + +end syn; Index: trunk/rtl/bplib/nexys2/tb/nexys2_fusp_cuff_dummy.vbom =================================================================== --- trunk/rtl/bplib/nexys2/tb/nexys2_fusp_cuff_dummy.vbom (nonexistent) +++ trunk/rtl/bplib/nexys2/tb/nexys2_fusp_cuff_dummy.vbom (revision 37) @@ -0,0 +1,7 @@ +# libs +../../../vlib/slvtypes.vhd +../../nxcramlib/nxcramlib.vhd +# components +../../nxcramlib/nx_cram_dummy.vbom +# design +nexys2_fusp_cuff_dummy.vhd Index: trunk/rtl/bplib/nexys2/tb/nexys2_fusp_cuff_dummy.vhd =================================================================== --- trunk/rtl/bplib/nexys2/tb/nexys2_fusp_cuff_dummy.vhd (nonexistent) +++ trunk/rtl/bplib/nexys2/tb/nexys2_fusp_cuff_dummy.vhd (revision 37) @@ -0,0 +1,100 @@ +-- $Id: nexys2_fusp_cuff_dummy.vhd 509 2013-04-21 20:46:20Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: nexys2_fusp_cuff_dummy - syn +-- Description: nexys2 minimal target (base; serport loopback) +-- +-- Dependencies: - +-- To test: tb_nexys2 +-- Target Devices: generic +-- Tool versions: 13.3; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-01 467 1.0 Initial version (derived nexys2_fusp_dummy) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.nxcramlib.all; + +entity nexys2_fusp_cuff_dummy is -- NEXYS 2 dummy (+fusp+cuff; loopback) + -- implements nexys2_fusp_cuff_aif + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit; -- fusp: rs232 tx + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end nexys2_fusp_cuff_dummy; + +architecture syn of nexys2_fusp_cuff_dummy is + +begin + + O_TXD <= I_RXD; -- loop back + O_FUSP_TXD <= I_FUSP_RXD; + O_FUSP_RTS_N <= I_FUSP_CTS_N; + + O_FX2_SLRD_N <= '1'; -- keep fx2 iface quiet + O_FX2_SLWR_N <= '1'; + O_FX2_SLOE_N <= '1'; + O_FX2_PKTEND_N <= '1'; + + CRAM : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + +end syn; Index: trunk/rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vbom =================================================================== --- trunk/rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vbom (nonexistent) +++ trunk/rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vbom (revision 37) @@ -0,0 +1,7 @@ +# libs +../../../vlib/slvtypes.vhd +../../nxcramlib/nxcramlib.vhd +# components +../../nxcramlib/nx_cram_dummy.vbom +# design +nexys2_fusp_dummy.vhd Index: trunk/rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vhd =================================================================== --- trunk/rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vhd (nonexistent) +++ trunk/rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vhd (revision 37) @@ -0,0 +1,92 @@ +-- $Id: nexys2_fusp_dummy.vhd 467 2013-01-02 19:49:05Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: nexys2_fusp_dummy - syn +-- Description: nexys2 minimal target (base; serport loopback) +-- +-- Dependencies: - +-- To test: tb_nexys2 +-- Target Devices: generic +-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.3 remove clksys output hack +-- 2011-11-26 433 1.2 use nxcramlib +-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy +-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock) +-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50 +-- 2010-05-28 295 1.0 Initial version (derived from s3board_fusp_dummy) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.nxcramlib.all; + +entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback) + -- implements nexys2_fusp_aif + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end nexys2_fusp_dummy; + +architecture syn of nexys2_fusp_dummy is + +begin + + O_TXD <= I_RXD; -- loop back + O_FUSP_TXD <= I_FUSP_RXD; + O_FUSP_RTS_N <= I_FUSP_CTS_N; + + CRAM : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + +end syn; Index: trunk/rtl/bplib/nexys2/tb/sys_conf_sim.vhd =================================================================== --- trunk/rtl/bplib/nexys2/tb/sys_conf_sim.vhd (nonexistent) +++ trunk/rtl/bplib/nexys2/tb/sys_conf_sim.vhd (revision 37) @@ -0,0 +1,42 @@ +-- $Id: sys_conf_sim.vhd 444 2011-12-25 10:04:58Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for tb_nexys2_fusp_dummy (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkfx_divide : positive := 2; + constant sys_conf_clkfx_multiply : positive := 3; -- ==> 75 MHz + + -- derived constants + + constant sys_conf_clksys : integer := + (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; + Index: trunk/rtl/bplib/nexys2/tb/tb_nexys2.vbom =================================================================== --- trunk/rtl/bplib/nexys2/tb/tb_nexys2.vbom (nonexistent) +++ trunk/rtl/bplib/nexys2/tb/tb_nexys2.vbom (revision 37) @@ -0,0 +1,23 @@ +# Not meant for direct top level usage. Used with +# tb_nexys2_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/xlib/xlib.vhd +../nexys2lib.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +${sys_conf := sys_conf_sim.vhd} +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom +../../../vlib/xlib/dcm_sfs_gsim.vbom +tb_nexys2_core.vbom +../../../vlib/serport/tb/serport_master_tb.vbom +${nexys2_aif := nexys2_dummy.vbom} -UUT +# design +tb_nexys2.vhd +@top:tb_nexys2 Index: trunk/rtl/bplib/nexys2/tb/tb_nexys2.vhd =================================================================== --- trunk/rtl/bplib/nexys2/tb/tb_nexys2.vhd (nonexistent) +++ trunk/rtl/bplib/nexys2/tb/tb_nexys2.vhd (revision 37) @@ -0,0 +1,226 @@ +-- $Id: tb_nexys2.vhd 805 2016-09-03 08:09:52Z mueller $ +-- +-- Copyright 2010-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nexys2 - sim +-- Description: Test bench for nexys2 (base) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- rlink/tbcore/tbcore_rlink +-- xlib/dcm_sfs +-- tb_nexys2_core +-- nexys2_aif [UUT] +-- serport/tb/serport_master_tb +-- +-- To test: generic, any nexys2_aif target +-- +-- Target Devices: generic +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-09-02 805 3.2.3 tbcore_rlink without CLK_STOP now +-- 2016-02-13 730 3.2.2 direct instantiation of tbcore_rlink +-- 2016-01-03 724 3.2.1 use serport/tb/serport_master_tb +-- 2015-04-12 666 3.2 use serport_master instead of serport_uart_rxtx +-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface +-- 2011-11-26 433 3.0.2 remove O_FLA_CE_N from tb_nexys2_core +-- 2011-11-21 432 3.0.1 now numeric_std clean; update O_FLA_CE_N usage +-- 2010-12-30 351 3.0 use rlink/tb now +-- 2010-11-13 338 1.0.3 now dcm aware: add O_CLKSYS, use rritb_core_dcm +-- 2010-11-06 336 1.0.2 rename input pin CLK -> I_CLK50 +-- 2010-05-28 295 1.0.1 use serport_uart_rxtx +-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.xlib.all; +use work.nexys2lib.all; +use work.simlib.all; +use work.simbus.all; +use work.sys_conf.all; + +entity tb_nexys2 is +end tb_nexys2; + +architecture sim of tb_nexys2 is + + signal CLKOSC : slbit := '0'; + signal CLKCOM : slbit := '0'; + + signal CLKCOM_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv8 := (others=>'0'); + signal I_BTN : slv4 := (others=>'0'); + signal O_LED : slv8 := (others=>'0'); + signal O_ANO_N : slv4 := (others=>'0'); + signal O_SEG_N : slv8 := (others=>'0'); + signal O_MEM_CE_N : slbit := '1'; + signal O_MEM_BE_N : slv2 := (others=>'1'); + signal O_MEM_WE_N : slbit := '1'; + signal O_MEM_OE_N : slbit := '1'; + signal O_MEM_ADV_N : slbit := '1'; + signal O_MEM_CLK : slbit := '0'; + signal O_MEM_CRE : slbit := '0'; + signal I_MEM_WAIT : slbit := '0'; + signal O_MEM_ADDR : slv23 := (others=>'Z'); + signal IO_MEM_DATA : slv16 := (others=>'0'); + signal O_FLA_CE_N : slbit := '0'; + + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + + constant clock_period : Delay_length := 20 ns; + constant clock_offset : Delay_length := 200 ns; + +begin + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLKOSC + ); + + DCM_COM : dcm_sfs + generic map ( + CLKFX_DIVIDE => sys_conf_clkfx_divide, + CLKFX_MULTIPLY => sys_conf_clkfx_multiply, + CLKIN_PERIOD => 10.0) + port map ( + CLKIN => CLKOSC, + CLKFX => CLKCOM, + LOCKED => open + ); + + CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); + + TBCORE : entity work.tbcore_rlink + port map ( + CLK => CLKCOM, + RX_DATA => TXDATA, + RX_VAL => TXENA, + RX_HOLD => TXBUSY, + TX_DATA => RXDATA, + TX_ENA => RXVAL + ); + + N2CORE : entity work.tb_nexys2_core + port map ( + I_SWI => I_SWI, + I_BTN => I_BTN, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + UUT : nexys2_aif + port map ( + I_CLK50 => CLKOSC, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA, + O_FLA_CE_N => O_FLA_CE_N + ); + + SERMSTR : entity work.serport_master_tb + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLKCOM, + RESET => RESET, + CLKDIV => CLKDIV, + ENAXON => R_PORTSEL_XON, + ENAESC => '0', + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXOK => '1', + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXSD => O_TXD, + TXSD => I_RXD, + RXRTS_N => open, + TXCTS_N => '0' + ); + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLKCOM); + + if RXERR = '1' then + writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_portsel then + R_PORTSEL_XON <= to_x01(SB_DATA(1)); + end if; + end if; + end process proc_simbus; + +end sim; Index: trunk/rtl/bplib/nexys2/tb/tb_nexys2_core.vbom =================================================================== --- trunk/rtl/bplib/nexys2/tb/tb_nexys2_core.vbom (revision 36) +++ trunk/rtl/bplib/nexys2/tb/tb_nexys2_core.vbom (revision 37) @@ -1,7 +1,9 @@ # libs ../../../vlib/slvtypes.vhd +../../../vlib/simlib/simlib.vhd ../../../vlib/simlib/simbus.vhd # components +../../../vlib/simlib/simbididly.vhd ../../micron/mt45w8mw16b.vbom # design tb_nexys2_core.vhd Index: trunk/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd =================================================================== --- trunk/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd (revision 36) +++ trunk/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd (revision 37) @@ -1,6 +1,6 @@ --- $Id: tb_nexys2_core.vhd 724 2016-01-03 22:53:53Z mueller $ +-- $Id: tb_nexys2_core.vhd 791 2016-07-21 22:01:10Z mueller $ -- --- Copyright 2010-2011 by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -15,14 +15,16 @@ -- Module Name: tb_nexys2_core - sim -- Description: Test bench for nexys2 - core device handling -- --- Dependencies: vlib/parts/micron/mt45w8mw16b +-- Dependencies: simlib/simbididly +-- vlib/parts/micron/mt45w8mw16b -- -- To test: generic, any nexys2 target -- -- Target Devices: generic --- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-07-20 791 1.2 use simbididly -- 2011-11-26 433 1.1.1 remove O_FLA_CE_N from tb_nexys2_core -- 2011-11-21 432 1.1 update O_FLA_CE_N usage -- 2011-11-19 427 1.0.1 now numeric_std clean @@ -36,6 +38,7 @@ use std.textio.all; use work.slvtypes.all; +use work.simlib.all; use work.simbus.all; entity tb_nexys2_core is @@ -57,27 +60,57 @@ architecture sim of tb_nexys2_core is + signal MM_MEM_CE_N : slbit := '1'; + signal MM_MEM_BE_N : slv2 := (others=>'1'); + signal MM_MEM_WE_N : slbit := '1'; + signal MM_MEM_OE_N : slbit := '1'; + signal MM_MEM_ADV_N : slbit := '1'; + signal MM_MEM_CLK : slbit := '0'; + signal MM_MEM_CRE : slbit := '0'; + signal MM_MEM_WAIT : slbit := '0'; + signal MM_MEM_ADDR : slv23 := (others=>'Z'); + signal MM_MEM_DATA : slv16 := (others=>'0'); + signal R_SWI : slv8 := (others=>'0'); signal R_BTN : slv4 := (others=>'0'); constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8)); constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8)); + constant pcb_delay : Delay_length := 1 ns; begin + MM_MEM_CE_N <= O_MEM_CE_N after pcb_delay; + MM_MEM_BE_N <= O_MEM_BE_N after pcb_delay; + MM_MEM_WE_N <= O_MEM_WE_N after pcb_delay; + MM_MEM_OE_N <= O_MEM_OE_N after pcb_delay; + MM_MEM_ADV_N <= O_MEM_ADV_N after pcb_delay; + MM_MEM_CLK <= O_MEM_CLK after pcb_delay; + MM_MEM_CRE <= O_MEM_CRE after pcb_delay; + MM_MEM_ADDR <= O_MEM_ADDR after pcb_delay; + I_MEM_WAIT <= MM_MEM_WAIT after pcb_delay; + + BUSDLY: simbididly + generic map ( + DELAY => pcb_delay, + DWIDTH => 16) + port map ( + A => IO_MEM_DATA, + B => MM_MEM_DATA); + MEM : entity work.mt45w8mw16b port map ( - CLK => O_MEM_CLK, - CE_N => O_MEM_CE_N, - OE_N => O_MEM_OE_N, - WE_N => O_MEM_WE_N, - UB_N => O_MEM_BE_N(1), - LB_N => O_MEM_BE_N(0), - ADV_N => O_MEM_ADV_N, - CRE => O_MEM_CRE, - MWAIT => I_MEM_WAIT, - ADDR => O_MEM_ADDR, - DATA => IO_MEM_DATA + CLK => MM_MEM_CLK, + CE_N => MM_MEM_CE_N, + OE_N => MM_MEM_OE_N, + WE_N => MM_MEM_WE_N, + UB_N => MM_MEM_BE_N(1), + LB_N => MM_MEM_BE_N(0), + ADV_N => MM_MEM_ADV_N, + CRE => MM_MEM_CRE, + MWAIT => MM_MEM_WAIT, + ADDR => MM_MEM_ADDR, + DATA => MM_MEM_DATA ); proc_simbus: process (SB_VAL)
/trunk/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
1,4 → 1,4
-- $Id: tb_nexys2_fusp.vhd 730 2016-02-13 16:22:03Z mueller $
-- $Id: tb_nexys2_fusp.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
30,6 → 30,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 3.3.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 3.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 3.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 3.3 use serport_master instead of serport_uart_rxtx
65,7 → 66,6
signal CLKOSC : slbit := '0';
signal CLKCOM : slbit := '0';
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
116,8 → 116,8
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
 
begin
126,8 → 126,7
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
DCM_COM : dcm_sfs
146,7 → 145,6
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
/trunk/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd
1,4 → 1,4
-- $Id: tb_nexys2_fusp_cuff.vhd 730 2016-02-13 16:22:03Z mueller $
-- $Id: tb_nexys2_fusp_cuff.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
27,10 → 27,11
-- To test: generic, any nexys2_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.2.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
60,7 → 61,6
signal CLKOSC : slbit := '0';
signal CLKCOM : slbit := '0';
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
132,8 → 132,8
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
 
begin
142,12 → 142,9
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
 
SB_CLKSTOP <= CLK_STOP;
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
164,7 → 161,6
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TBC_RXDATA,
RX_VAL => TBC_RXVAL,
RX_HOLD => TBC_RXHOLD,
/trunk/rtl/bplib/nexys3/tb/nexys3_fusp_cuff_dummy.vbom
0,0 → 1,7
# libs
../../../vlib/slvtypes.vhd
../../nxcramlib/nxcramlib.vhd
# components
../../nxcramlib/nx_cram_dummy.vbom
# design
nexys3_fusp_cuff_dummy.vhd
/trunk/rtl/bplib/nexys3/tb/nexys3_fusp_cuff_dummy.vhd
0,0 → 1,102
-- $Id: nexys3_fusp_cuff_dummy.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys3_dummy - syn
-- Description: nexys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys3
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.0 Initial version (derived nexys3_fusp_dummy)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.nxcramlib.all;
 
entity nexys3_fusp_cuff_dummy is -- NEXYS 3 dummy (+fusp+cuff; loopback)
-- implements nexys3_fusp_cuff_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end nexys3_fusp_cuff_dummy;
 
architecture syn of nexys3_fusp_cuff_dummy is
begin
 
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
 
O_FX2_SLRD_N <= '1'; -- keep fx2 iface quiet
O_FX2_SLWR_N <= '1';
O_FX2_SLOE_N <= '1';
O_FX2_PKTEND_N <= '1';
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
 
end syn;
/trunk/rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vbom
0,0 → 1,7
# libs
../../../vlib/slvtypes.vhd
../../nxcramlib/nxcramlib.vhd
# components
../../nxcramlib/nx_cram_dummy.vbom
# design
nexys3_fusp_dummy.vhd
/trunk/rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vhd
0,0 → 1,90
-- $Id: nexys3_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys3_dummy - syn
-- Description: nexys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys3
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.1 use nxcramlib
-- 2011-11-25 432 1.0 Initial version (derived from nexys2_fusp_dummy)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.nxcramlib.all;
 
entity nexys3_fusp_dummy is -- NEXYS 3 dummy (base+fusp; loopback)
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end nexys3_fusp_dummy;
 
architecture syn of nexys3_fusp_dummy is
begin
 
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
 
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
 
end syn;
/trunk/rtl/bplib/nexys3/tb/sys_conf_sim.vhd
0,0 → 1,46
-- $Id: sys_conf_sim.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_nexys3_fusp_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2011-11-25 433 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package sys_conf is
 
constant sys_conf_clksys_vcodivide : positive := 4;
constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 75 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 75 MHz
constant sys_conf_clksys_gentype : string := "DCM";
 
-- derived constants
 
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
end package sys_conf;
 
/trunk/rtl/bplib/nexys3/tb/tb_nexys3_core.vbom
1,7 → 1,9
# libs
../../../vlib/slvtypes.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/simlib/simbididly.vhd
../../micron/mt45w8mw16b.vbom
# design
tb_nexys3_core.vhd
/trunk/rtl/bplib/nexys3/tb/tb_nexys3_core.vhd
1,6 → 1,6
-- $Id: tb_nexys3_core.vhd 724 2016-01-03 22:53:53Z mueller $
-- $Id: tb_nexys3_core.vhd 791 2016-07-21 22:01:10Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
15,14 → 15,16
-- Module Name: tb_nexys3_core - sim
-- Description: Test bench for nexys3 - core device handling
--
-- Dependencies: vlib/parts/micron/mt45w8mw16b
-- Dependencies: simlib/simbididly
-- vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys3 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-20 791 1.1 use simbididly
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)
------------------------------------------------------------------------------
 
33,6 → 35,7
use std.textio.all;
 
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
 
entity tb_nexys3_core is
54,27 → 57,57
 
architecture sim of tb_nexys3_core is
signal MM_MEM_CE_N : slbit := '1';
signal MM_MEM_BE_N : slv2 := (others=>'1');
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADV_N : slbit := '1';
signal MM_MEM_CLK : slbit := '0';
signal MM_MEM_CRE : slbit := '0';
signal MM_MEM_WAIT : slbit := '0';
signal MM_MEM_ADDR : slv23 := (others=>'Z');
signal MM_MEM_DATA : slv16 := (others=>'0');
 
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
 
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
constant pcb_delay : Delay_length := 1 ns;
 
begin
MM_MEM_CE_N <= O_MEM_CE_N after pcb_delay;
MM_MEM_BE_N <= O_MEM_BE_N after pcb_delay;
MM_MEM_WE_N <= O_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= O_MEM_OE_N after pcb_delay;
MM_MEM_ADV_N <= O_MEM_ADV_N after pcb_delay;
MM_MEM_CLK <= O_MEM_CLK after pcb_delay;
MM_MEM_CRE <= O_MEM_CRE after pcb_delay;
MM_MEM_ADDR <= O_MEM_ADDR after pcb_delay;
I_MEM_WAIT <= MM_MEM_WAIT after pcb_delay;
 
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 16)
port map (
A => IO_MEM_DATA,
B => MM_MEM_DATA);
 
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
CLK => MM_MEM_CLK,
CE_N => MM_MEM_CE_N,
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(1),
LB_N => MM_MEM_BE_N(0),
ADV_N => MM_MEM_ADV_N,
CRE => MM_MEM_CRE,
MWAIT => MM_MEM_WAIT,
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA
);
proc_simbus: process (SB_VAL)
/trunk/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd
1,4 → 1,4
-- $Id: tb_nexys3_fusp.vhd 730 2016-02-13 16:22:03Z mueller $
-- $Id: tb_nexys3_fusp.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
26,10 → 26,11
-- To test: generic, any nexys3_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.3.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
60,7 → 61,6
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
112,8 → 112,8
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
 
begin
122,8 → 122,7
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
CLKGEN_COM : s6_cmt_sfs
146,7 → 145,6
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
/trunk/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd
1,4 → 1,4
-- $Id: tb_nexys3_fusp_cuff.vhd 730 2016-02-13 16:22:03Z mueller $
-- $Id: tb_nexys3_fusp_cuff.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
27,10 → 27,11
-- To test: generic, any nexys3_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.2.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
61,7 → 62,6
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
133,8 → 133,8
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
 
begin
143,12 → 143,9
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
SB_CLKSTOP <= CLK_STOP;
 
CLKGEN_COM : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
169,7 → 166,6
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TBC_RXDATA,
RX_VAL => TBC_RXVAL,
RX_HOLD => TBC_RXHOLD,
/trunk/rtl/bplib/nexys4/tb/nexys4_cram_dummy.ucf_cpp
0,0 → 1,13
## $Id: nexys4_cram_dummy.ucf_cpp 643 2015-02-07 17:41:53Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2015-02-06 463 1.1 factor out memory
## 2013-09-21 534 1.0 Initial version
##
 
## std board
##
#include "bplib/nexys4/nexys4_pins.ucf"
#include "bplib/nexys4/nexys4_pins_cram.ucf"
##
/trunk/rtl/bplib/nexys4/tb/nexys4_cram_dummy.vbom
0,0 → 1,8
# libs
../../../vlib/slvtypes.vhd
../../nxcramlib/nxcramlib.vhd
# components
../../nxcramlib/nx_cram_dummy.vbom
# design
nexys4_cram_dummy.vhd
@ucf_cpp: nexys4_cram_dummy.ucf
/trunk/rtl/bplib/nexys4/tb/nexys4_cram_dummy.vhd
0,0 → 1,93
-- $Id: nexys4_cram_dummy.vhd 643 2015-02-07 17:41:53Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys4_cram_dummy - syn
-- Description: nexys4 target (base; serport loopback, cram protect)
--
-- Dependencies: -
-- To test: tb_nexys4_cram
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-21 534 1.0 Initial version (derived from nexys3_dummy)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.nxcramlib.all;
 
entity nexys4_cram_dummy is -- NEXYS 4 dummy (base+cram)
-- implements nexys4_cram_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end nexys4_cram_dummy;
 
architecture syn of nexys4_cram_dummy is
begin
 
O_TXD <= I_RXD; -- loop back serport
O_RTS_N <= I_CTS_N;
 
O_LED <= I_SWI; -- mirror SWI on LED
 
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED
O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3);
 
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
/trunk/rtl/bplib/nexys4/tb/nexys4_dummy.ucf_cpp
0,0 → 1,11
## $Id: nexys4_dummy.ucf_cpp 534 2013-09-22 21:37:24Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-09-21 534 1.0 Initial version
##
 
## std board
##
#include "bplib/nexys4/nexys4_pins.ucf"
##
/trunk/rtl/bplib/nexys4/tb/nexys4_dummy.vbom
0,0 → 1,5
# libs
../../../vlib/slvtypes.vhd
# design
nexys4_dummy.vhd
@ucf_cpp: nexys4_dummy.ucf
/trunk/rtl/bplib/nexys4/tb/nexys4_dummy.vhd
0,0 → 1,69
-- $Id: nexys4_dummy.vhd 643 2015-02-07 17:41:53Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys4_dummy - syn
-- Description: nexys4 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys4
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-06 643 1.3 factor out memory
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-21 534 1.0 Initial version (derived from nexys3_dummy)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
entity nexys4_dummy is -- NEXYS 4 dummy (base; loopback)
-- implements nexys4_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end nexys4_dummy;
 
architecture syn of nexys4_dummy is
begin
 
O_TXD <= I_RXD; -- loop back serport
O_RTS_N <= I_CTS_N;
 
O_LED <= I_SWI; -- mirror SWI on LED
 
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED
O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3);
 
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
end syn;
/trunk/rtl/bplib/nexys4/tb/sys_conf_sim.vhd
0,0 → 1,54
-- $Id: sys_conf_sim.vhd 641 2015-02-01 22:12:15Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_nexys4_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2012-09-21 534 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package sys_conf is
 
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
 
-- derived constants
 
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
 
end package sys_conf;
 
/trunk/rtl/bplib/nexys4/tb/tb_nexys4.vhd
1,4 → 1,4
-- $Id: tb_nexys4.vhd 734 2016-02-20 22:43:20Z mueller $
-- $Id: tb_nexys4.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
26,10 → 26,11
-- To test: generic, any nexys4_aif target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.3.4 tbcore_rlink without CLK_STOP now
-- 2016-02-20 734 1.3.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
62,7 → 63,6
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
92,8 → 92,8
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
 
begin
102,8 → 102,7
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
CLKGEN_COM : entity work.s7_cmt_sfs_tb
126,7 → 125,6
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
/trunk/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom
16,6 → 16,7
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom
tb_nexys4_core.vbom
../../../vlib/simlib/simbididly.vbom
../../micron/mt45w8mw16b.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
${nexys4_cram_aif := nexys4_cram_dummy.vbom} -UUT
/trunk/rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd
1,4 → 1,4
-- $Id: tb_nexys4_cram.vhd 734 2016-02-20 22:43:20Z mueller $
-- $Id: tb_nexys4_cram.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
22,15 → 22,18
-- tb_nexys4_core
-- serport/tb/serport_master_tb
-- nexys4_cram_aif [UUT]
-- simlib/simbididly
-- vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys4_cram_aif target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.3.1 tbcore_rlink without CLK_STOP now
-- 2016-07-20 791 1.3 use simbididly
-- 2016-02-20 734 1.2.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
62,7 → 65,6
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
87,23 → 89,36
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
 
signal TB_MEM_CE_N : slbit := '1';
signal TB_MEM_BE_N : slv2 := (others=>'1');
signal TB_MEM_WE_N : slbit := '1';
signal TB_MEM_OE_N : slbit := '1';
signal TB_MEM_ADV_N : slbit := '1';
signal TB_MEM_CLK : slbit := '0';
signal TB_MEM_CRE : slbit := '0';
signal TB_MEM_WAIT : slbit := '0';
signal TB_MEM_ADDR : slv23 := (others=>'Z');
signal TB_MEM_DATA : slv16 := (others=>'0');
 
signal MM_MEM_CE_N : slbit := '1';
signal MM_MEM_BE_N : slv2 := (others=>'1');
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADV_N : slbit := '1';
signal MM_MEM_CLK : slbit := '0';
signal MM_MEM_CRE : slbit := '0';
signal MM_MEM_WAIT : slbit := '0';
signal MM_MEM_ADDR : slv23 := (others=>'Z');
signal MM_MEM_DATA : slv16 := (others=>'0');
 
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant pcb_delay : Delay_length := 1 ns;
 
begin
112,8 → 127,7
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
CLKGEN_COM : entity work.s7_cmt_sfs_tb
136,7 → 150,6
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
166,31 → 179,49
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
O_MEM_CE_N => TB_MEM_CE_N,
O_MEM_BE_N => TB_MEM_BE_N,
O_MEM_WE_N => TB_MEM_WE_N,
O_MEM_OE_N => TB_MEM_OE_N,
O_MEM_ADV_N => TB_MEM_ADV_N,
O_MEM_CLK => TB_MEM_CLK,
O_MEM_CRE => TB_MEM_CRE,
I_MEM_WAIT => TB_MEM_WAIT,
O_MEM_ADDR => TB_MEM_ADDR,
IO_MEM_DATA => TB_MEM_DATA
);
MM_MEM_CE_N <= TB_MEM_CE_N after pcb_delay;
MM_MEM_BE_N <= TB_MEM_BE_N after pcb_delay;
MM_MEM_WE_N <= TB_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= TB_MEM_OE_N after pcb_delay;
MM_MEM_ADV_N <= TB_MEM_ADV_N after pcb_delay;
MM_MEM_CLK <= TB_MEM_CLK after pcb_delay;
MM_MEM_CRE <= TB_MEM_CRE after pcb_delay;
MM_MEM_ADDR <= TB_MEM_ADDR after pcb_delay;
TB_MEM_WAIT <= MM_MEM_WAIT after pcb_delay;
 
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 16)
port map (
A => TB_MEM_DATA,
B => MM_MEM_DATA);
 
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
CLK => MM_MEM_CLK,
CE_N => MM_MEM_CE_N,
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(1),
LB_N => MM_MEM_BE_N(0),
ADV_N => MM_MEM_ADV_N,
CRE => MM_MEM_CRE,
MWAIT => MM_MEM_WAIT,
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA
);
SERMSTR : entity work.serport_master_tb
/trunk/rtl/bplib/nxcramlib/Makefile
0,0 → 1,37
# $Id: Makefile 761 2016-04-17 08:53:48Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-04-15 761 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#
/trunk/rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd
1,4 → 1,4
-- $Id: nx_cram_memctl_as.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: nx_cram_memctl_as.vhd 789 2016-07-17 08:26:55Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
20,18 → 20,29
-- vlib/xlib/iob_reg_io_gen
-- Test bench: tb/tb_nx_cram_memctl_as
-- sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
-- sys_gen/tst_sram/nexys3/tb/tb_tst_sram_n3
-- sys_gen/tst_sram/nexys4/tb/tb_tst_sram_n4
-- Target Devices: generic
-- Tool versions: ise 11.4-14.7; viv 2014.4-2016.1; ghdl 0.26-0.33
-- Tool versions: ise 11.4-14.7; viv 2014.4-2016.2; ghdl 0.26-0.33
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2016-07-03 783 2016.3 xc7a100t-1 91 87 0 0 43
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 100 0 96 s 6.7
-- 2010-05-24 294 11.4 L68 xc3s1200e-4 91 99 0 95 s 6.7
-- 2010-05-23 293 11.4 L68 xc3s1200e-4 91 139 0 99 s 6.7
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2016-07-03 767 14.7 131013 xc6slx16-2 100 134 0 60 s 4.2
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 100 0 96 s 6.7
-- 2010-05-24 294 11.4 L68 xc3s1200e-4 91 99 0 95 s 6.7
-- 2010-05-23 293 11.4 L68 xc3s1200e-4 91 139 0 99 s 6.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.2.2 don't init N_REGS (vivado fix for fsm inference)
-- 2016-07-16 788 2.1 change *DELAY generics, now absolute delay cycles
-- add s_init1; drop "KEEP" for data (better for dbg)
-- 2016-07-10 786 2.0 add page mode support
-- 2016-05-22 767 1.2.2 don't init N_REGS (vivado fix for fsm inference)
-- 2015-12-26 718 1.2.1 BUGFIX: do_dispatch(): always define imem_oe
-- 2011-11-26 433 1.2 renamed from n2_cram_memctl_as
-- 2011-11-19 432 1.1 remove O_FLA_CE_N port
44,41 → 55,23
-- 2010-05-23 293 1.0 Initial version
--
-- Notes:
-- 1. READ1DELAY of 2 is needed even though the timing of the memory suggests
-- that 1 cycle is enough (T_apa is 20 ns, so 40 ns round trip is ok). A
-- short READ1 delay works in sim, but not on fpga where the data of the
-- ADDR(0)=0 cycle is re-read (see notes_tst_sram_n2.txt).
-- tb_n2_cram_memctl_as_ISim_tsim works with full sdf even when T_apa is
-- 40ns or 50 ns, only T_apa 60 ns fails !
-- Unclear what is wrong here, the timing of the memory model seems ok.
-- 2. There is no 'bus-turn-around' cycle needed for a write->read change
-- 1. There is no 'bus-turn-around' cycle needed for a write->read change
-- FPGA_OE goes 1->0 and MEM_OE goes 0->1 on the s_wrput1->s_rdinit
-- transition simultaneously. The FPGA will go high-Z quickly, the memory
-- low-Z delay by the IOB and internal memory delays. No clash.
-- 3. There is a hidden 'bus-turn-around' cycle for a read->write change.
-- 2. There is a hidden 'bus-turn-around' cycle for a read->write change.
-- MEM_OE goes 1->0 on s_rdget1->s_wrinit and the memory will go high-z with
-- some delay. FPGA_OE goes 0->1 in the next cycle at s_wrinit->s_wrwait0.
-- Again no clash due to the 1 cycle delay.
--
-- Nominal timings:
-- READ0/1 = N_rd_cycle - 2
-- WRITE = N_wr_cycle - 1
-- READ0 = (T_aa + ext_read_delay) in cycles
-- READ1 = (T_pa + ext_read_delay) in cycles
-- WRITE = (T_aa + ext_write_delay) in cycles
-- with
-- ext_read_delay: output_IOB + 2*PCB_delay + input_IOB + skew
-- ext_write_delay: skew
--
-- from notes_nexys2.txt (Rev 339):
-- clksys RD WR < use for > Test case
-- MHz div mul
-- <51.20 2 3 <-- 50 50 1 1
-- 51.20- 54.80 3 3 <-- 52,54 54 25 27
-- 54.80- 64.10 3 4 <-- 55,56,58,60,62,64 64 25 32
-- 64.10- 68.50 4 4 <-- 65 65 10 13
-- 68.50- 76.92 4 5 <-- 70,75 75 2 3
-- 76.92- 82.19 5 5 <-- 80 80 5 8
-- 82.19- 89.74 5 6 <-- 85 85 10 17
-- 89.74- 95.89 6 6 <-- 90,95 95 10 19
-- 95.89-102.56 6 7 <-- 100 100 1 2
-- remark added 2015-12-26
-- - for sys_w11a_n3 one gets in simulation errors for 72 MHz and RD=4 !!
-- - so far unclear whether controller or memory model is wrong !!
--
-- Timing of some signals:
--
126,9 → 119,9
 
entity nx_cram_memctl_as is -- CRAM driver (async+page mode)
generic (
READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
READ0DELAY : positive := 4; -- read word 0 delay in clock cycles
READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
WRITEDELAY : positive := 3); -- write delay in clock cycles
WRITEDELAY : positive := 4); -- write delay in clock cycles
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
160,6 → 153,13
architecture syn of nx_cram_memctl_as is
 
type state_type is (
s_init, -- s_init: startup state
s_init1, -- s_init1: reset released
s_wcinit, -- s_wcinit: write rcr init
s_wcwait, -- s_wcwait: write rcr wait
s_wcput, -- s_wcput: write rcr done
s_rainit, -- s_rainit: read array init
s_rawait, -- s_rawait: wait read array
s_idle, -- s_idle: wait for req
s_rdinit, -- s_rdinit: read init cycle
s_rdwait0, -- s_rdwait0: read wait low word
187,7 → 187,7
end record regs_type;
 
constant regs_init : regs_type := (
s_idle, -- state
s_init, -- state
'0', -- ackr
'0', -- addr0
"00", -- be2nd
197,7 → 197,16
(others=>'0'), -- memdo0
(others=>'0') -- memdi
);
 
constant c_addrh_rcr_setup : slv22 :=
"000" & -- 22:20 reserved MBZ
"00" & -- 19:18 reg sel 00=RCR
"0000000000" & -- 17: 8 reserved MBZ
'1' & -- 7 page mode enable (1=enable)
"00" & -- 6: 5 reserved MBZ
'1' & -- 4 dpd disaable (1=disable)
"000"; -- 3: 1 rest is reserved or PAR, which should be 0
 
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
206,9 → 215,11
signal MEM_BE_N : slv2 := "11";
signal MEM_WE_N : slbit := '1';
signal MEM_OE_N : slbit := '1';
signal MEM_CRE : slbit := '0';
signal BE_CE : slbit := '0';
signal ADDRH_CE : slbit := '0';
signal ADDR0_CE : slbit := '0';
signal ADDRH : slv22 := (others=>'0');
signal ADDR0 : slbit := '0';
signal DATA_CEI : slbit := '0';
signal DATA_CEO : slbit := '0';
216,17 → 227,23
signal MEM_DO : slv16 := (others=>'0');
signal MEM_DI : slv16 := (others=>'0');
 
-- these attributes aren't accepted by ghdl 0.26
-- attribute s : string;
-- attribute s of I_MEM_WAIT : signal is "true";
 
begin
 
assert READ0DELAY<=2**R_REGS.cntdly'length and
READ1DELAY<=2**R_REGS.cntdly'length and
WRITEDELAY<=2**R_REGS.cntdly'length
report "assert(READ0,READ1,WRITEDELAY <= 2**cntdly'length)"
-- Notes:
-- used READ0DELAY-2 and READ0DELAY-3
-- used READ1DELAY-2
-- used WRITEDELAY-2
assert READ0DELAY-2 < 2**R_REGS.cntdly'length and
READ1DELAY-2 < 2**R_REGS.cntdly'length and
WRITEDELAY-2 < 2**R_REGS.cntdly'length
report "assert( (READ0,READ1,WRITE)DELAY-2 < 2**cntdly'length)"
severity failure;
assert READ0DELAY >= 3 and
READ1DELAY >= 2 and
WRITEDELAY >= 2
report "assert( (READ0,READ1,WRITE)DELAY-2 >= 2 or 3)"
severity failure;
 
CLK_180 <= not CLK;
271,6 → 288,16
PAD => O_MEM_OE_N
);
IOB_MEM_CRE : iob_reg_o
generic map (
INIT => '0')
port map (
CLK => CLK,
CE => '1',
DO => MEM_CRE,
PAD => O_MEM_CRE
);
IOB_MEM_ADDRH : iob_reg_o_gen
generic map (
DWIDTH => 22)
277,7 → 304,7
port map (
CLK => CLK,
CE => ADDRH_CE,
DO => ADDR,
DO => ADDRH,
PAD => O_MEM_ADDR(22 downto 1)
);
292,7 → 319,7
IOB_MEM_DATA : iob_reg_io_gen
generic map (
DWIDTH => 16,
PULL => "KEEP")
PULL => "NONE")
port map (
CLK => CLK,
CEI => DATA_CEI,
305,7 → 332,6
 
O_MEM_ADV_N <= '0';
O_MEM_CLK <= '0';
O_MEM_CRE <= '0';
 
proc_regs: process (CLK)
begin
320,7 → 346,7
 
end process proc_regs;
 
proc_next: process (R_REGS, REQ, WE, BE, DI, MEM_DO)
proc_next: process (R_REGS, REQ, WE, BE, DI, ADDR, MEM_DO)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
328,13 → 354,15
variable iackw : slbit := '0';
variable iactr : slbit := '0';
variable iactw : slbit := '0';
variable imem_ce : slbit := '0';
variable imem_be : slv2 := "00";
variable imem_we : slbit := '0';
variable imem_oe : slbit := '0';
variable imem_ce : slbit := '0';
variable imem_be : slv2 := "00";
variable imem_we : slbit := '0';
variable imem_oe : slbit := '0';
variable imem_cre : slbit := '0';
variable ibe_ce : slbit := '0';
variable iaddrh_ce : slbit := '0';
variable iaddr0_ce : slbit := '0';
variable iaddrh : slv22 := (others=>'0');
variable iaddr0 : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
385,13 → 413,15
iactr := '0';
iactw := '0';
 
imem_ce := '0';
imem_be := "11";
imem_we := '0';
imem_oe := '0';
imem_ce := '0';
imem_be := "11";
imem_we := '0';
imem_oe := '0';
imem_cre := '0';
ibe_ce := '0';
iaddrh_ce := '0';
iaddr0_ce := '0';
iaddrh := ADDR;
iaddr0 := '0';
idata_cei := '0';
idata_ceo := '0';
402,6 → 432,54
end if;
 
case r.state is
when s_init => -- s_init: startup state
ibusy := '1'; -- signal busy, unable to handle req
n.state := s_init1;
 
when s_init1 => -- s_init1: reset released
ibusy := '1'; -- signal busy, unable to handle req
iaddrh := c_addrh_rcr_setup;
iaddr0 := '0';
iaddrh_ce := '1';
iaddr0_ce := '1';
imem_ce := '1'; -- ce CRAM next cycle
imem_cre := '1'; -- cre CRAM next cycle
n.state := s_wcinit;
 
when s_wcinit => -- s_wcinit: write rcr init
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
imem_cre := '1'; -- cre CRAM next cycle
imem_we := '1'; -- we CRAM next cycle
n.cntdly := slv(to_unsigned(WRITEDELAY-2, n.cntdly'length));
n.state := s_wcwait;
 
when s_wcwait => -- s_wcinit: write rcr wait
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM next cycle
imem_cre := '1'; -- cre CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_wcput; -- next: write rcr done
end if;
 
when s_wcput => -- s_wcput: write rcr done
ibusy := '1'; -- signal busy, unable to handle req
n.state := s_rainit; -- next: read array init
 
when s_rainit => -- s_rainit: read array init
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
n.cntdly:= slv(to_unsigned(READ0DELAY-2, n.cntdly'length));
n.state := s_rawait ; -- next: wait read array
 
when s_rawait => -- s_rawait: wait read array
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_idle; -- next: wait for req
end if;
 
when s_idle => -- s_idle: wait for req
if REQ = '1' then -- if IO requested
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
413,8 → 491,8
iactr := '1'; -- signal mem read
imem_ce := '1'; -- ce CRAM next cycle
imem_oe := '1'; -- oe CRAM next cycle
n.cntdly:= slv(to_unsigned(READ0DELAY-1, n.cntdly'length));
n.state := s_rdwait0; -- next: wait
n.cntdly:= slv(to_unsigned(READ0DELAY-3, n.cntdly'length));
n.state := s_rdwait0; -- next: wait low word
 
when s_rdwait0 => -- s_rdwait0: read wait low word
ibusy := '1'; -- signal busy, unable to handle req
433,7 → 511,7
idata_cei := '1'; -- latch input data
iaddr0_ce := '1'; -- latch address 0 bit
iaddr0 := '1'; -- now go for high word
n.cntdly:= slv(to_unsigned(READ1DELAY-1, n.cntdly'length));
n.cntdly:= slv(to_unsigned(READ1DELAY-2, n.cntdly'length));
n.state := s_rdwait1; -- next: wait high word
 
when s_rdwait1 => -- s_rdwait1: read wait high word
442,7 → 520,7
imem_ce := '1'; -- ce CRAM next cycle
imem_oe := '1'; -- oe CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_rdget1; -- next: get low word
n.state := s_rdget1; -- next: get high word
end if; --
 
when s_rdget1 => -- s_rdget1: read get high word
468,7 → 546,7
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM in half cycle
n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
n.cntdly:= slv(to_unsigned(WRITEDELAY-2, n.cntdly'length));
n.state := s_wrwait0; -- next: wait
 
when s_wrwait0 => -- s_rdput0: write wait 1st word
511,7 → 589,7
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM in half cycle
n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
n.cntdly:= slv(to_unsigned(WRITEDELAY-2, n.cntdly'length));
n.state := s_wrwait1; -- next: wait
 
when s_wrwait1 => -- s_wrwait1: write wait 2nd word
565,6 → 643,7
MEM_WE_N <= not imem_we;
MEM_BE_N <= not imem_be;
MEM_OE_N <= not imem_oe;
MEM_CRE <= imem_cre;
 
if r.addr0 = '0' then
MEM_DI <= r.memdi(15 downto 0);
575,6 → 654,7
BE_CE <= ibe_ce;
ADDRH_CE <= iaddrh_ce;
ADDR0_CE <= iaddr0_ce;
ADDRH <= iaddrh;
ADDR0 <= iaddr0;
DATA_CEI <= idata_cei;
DATA_CEO <= idata_ceo;
/trunk/rtl/bplib/nxcramlib/nxcramlib.vhd
1,6 → 1,6
-- $Id: nxcramlib.vhd 641 2015-02-01 22:12:15Z mueller $
-- $Id: nxcramlib.vhd 788 2016-07-16 22:23:23Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
16,10 → 16,11
-- Description: Nexys 2/3 CRAM drivers
--
-- Dependencies: -
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
-- Tool versions: ise 11.4-14.7; viv 2014.4-2016.2; ghdl 0.26-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.1 add cram_(read0|read1|write)delay functions
-- 2011-11-26 433 1.0 Initial version (extracted from nexys2lib)
------------------------------------------------------------------------------
 
29,7 → 30,17
use work.slvtypes.all;
 
package nxcramlib is
pure function cram_delay(clk_mhz : positive;
delay_ps : positive) return positive;
pure function cram_read0delay(clk_mhz : positive) return positive;
pure function cram_read1delay(clk_mhz : positive) return positive;
pure function cram_writedelay(clk_mhz : positive) return positive;
 
constant cram_read0delay_ps : positive := 80000; -- initial read delay
constant cram_read1delay_ps : positive := 30000; -- page read delay
constant cram_writedelay_ps : positive := 75000; -- write delay
 
component nx_cram_dummy is -- CRAM protection dummy
port (
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
47,9 → 58,9
 
component nx_cram_memctl_as is -- CRAM driver (async+page mode)
generic (
READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
READ0DELAY : positive := 4; -- read word 0 delay in clock cycles
READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
WRITEDELAY : positive := 3); -- write delay in clock cycles
WRITEDELAY : positive := 4); -- write delay in clock cycles
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
78,3 → 89,43
end component;
 
end package nxcramlib;
 
-- ----------------------------------------------------------------------------
package body nxcramlib is
 
-- -------------------------------------
pure function cram_delay( -- calculate delay in clock cycles
clk_mhz : positive; -- clock frequency in MHz
delay_ps : positive) -- delay in ps
return positive is
variable period_ps : natural := 0; -- clk period in ps
begin
period_ps := 1000000 / clk_mhz;
return (delay_ps + period_ps - 10) / period_ps;
end function cram_delay;
 
-- -------------------------------------
pure function cram_read0delay( -- read0 delay in clock cycles
clk_mhz : positive) -- clock frequency in MHz
return positive is
begin
return cram_delay(clk_mhz, cram_read0delay_ps);
end function cram_read0delay;
 
-- -------------------------------------
pure function cram_read1delay( -- read1 delay in clock cycles
clk_mhz : positive) -- clock frequency in MHz
return positive is
begin
return cram_delay(clk_mhz, cram_read1delay_ps);
end function cram_read1delay;
 
-- -------------------------------------
pure function cram_writedelay( -- write delay in clock cycles
clk_mhz : positive) -- clock frequency in MHz
return positive is
begin
return cram_delay(clk_mhz, cram_writedelay_ps);
end function cram_writedelay;
 
end package body nxcramlib;
/trunk/rtl/bplib/nxcramlib/tb/.cvsignore
1,2 → 1,3
tb_nx_cram_memctl_as
tb_nx_cram_memctl_stim
list_cram_delay
/trunk/rtl/bplib/nxcramlib/tb/Makefile
0,0 → 1,42
# $Id: Makefile 788 2016-07-16 22:23:23Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-04-17 761 1.0 Initial version
#
EXE_all = tb_nx_cram_memctl_as
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_osim clean
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_osim : $(EXE_all:=_osim)
#
all_XSim : $(EXE_all:=_XSim)
all_XSim_ssim : $(EXE_all:=_XSim_ssim)
all_XSim_osim : $(EXE_all:=_XSim_osim)
all_XSim_tsim : $(EXE_all:=_XSim_tsim)
#
clean : viv_clean ghdl_clean xsim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsim)
endif
#
/trunk/rtl/bplib/nxcramlib/tb/Makefile.ise
1,4 → 1,4
# $Id: Makefile.ise 761 2016-04-17 08:53:48Z mueller $
# $Id: Makefile.ise 788 2016-07-16 22:23:23Z mueller $
#
# Revision History:
# Date Rev Version Comment
6,7 → 6,8
# 2014-07-27 545 1.0.1 make reference board configurable via XTW_BOARD
# 2011-11-26 433 1.0 Initial version (cloned)
#
EXE_all = tb_nx_cram_memctl_as
EXE_all = tb_nx_cram_memctl_as
EXE_all += list_cram_delay
#
ifndef XTW_BOARD
XTW_BOARD=nexys3
/trunk/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd
1,4 → 1,4
-- $Id: tb_nx_cram_memctl.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: tb_nx_cram_memctl.vhd 802 2016-08-27 19:00:23Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
113,10 → 113,11
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 7.5 ns; -- compatible ucf for
constant c2out_time : time := 12.0 ns; -- tbd_nx_cram_memctl_as
constant clock_period : Delay_length := 20 ns; -- when changed update also
-- READ0DELAY ect delays !!
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 7.5 ns; -- compatible ucf for
constant c2out_time : Delay_length := 12.0 ns; -- tbd_nx_cram_memctl_as
 
begin
 
/trunk/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_as.vbom
1,6 → 1,8
# configure tb_nx_cram_memctl with tbd_nx_cram_memctl_as target;
# use vhdl configure file (tb_nx_cram_memctl_as.vhd) to allow
# that all configurations will co-exist in work library
# configure
uut = tbd_nx_cram_memctl_as.vbom
tb_nx_cram_memctl.vbom
# design
tb_nx_cram_memctl_as.vhd
/trunk/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_as_ssim.vbom
1,5 → 1,6
# configure for _*sim case
#
# configure
uut = tbd_nx_cram_memctl_as_ssim.vhd
# design
tb_nx_cram_memctl_as.vbom
@top:tb_nx_cram_memctl_as
/trunk/rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.ucf
0,0 → 1,40
## $Id: tbd_nx_cram_memctl_as.ucf 433 2011-11-27 22:04:39Z mueller $
##
## drive strength defs and timing defs for tbd_nx_cram_memctl_as test target
##
## Revision History:
## Date Rev Version Comment
## 2011-11-26 433 1.1 renamed from tbd_n2_cram_memctl_as.ucf
## 2010-05-30 297 1.0 Initial version
##
## Note: default is DRIVE=12 | SLEW=SLOW
##
## The OFFSET rules are compatible with the setup and c2out times
## used in the test bench tb_nx_cram_memctl.
##
NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
OFFSET = IN 7.5 ns BEFORE "CLK";
OFFSET = OUT 12.0 ns AFTER "CLK";
##
NET "O_MEM_WE_N" OFFSET = OUT 12.0 ns AFTER "CLK" FALLING;
##
## -- define defaults
##
INST "/" IOSTANDARD=LVCMOS33;
##
## CRAM ----------------------------------------------------------------------
NET "O_MEM_CE_N" IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_WE_N" IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_OE_N" IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_MEM_BE_N<*>" IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_MEM_ADV_N" IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_CLK" IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_CRE" IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "I_MEM_WAIT" IOSTANDARD=LVCMOS33 | PULLDOWN;
##
NET "O_MEM_ADDR<*>" IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=FAST;
NET "IO_MEM_DATA<*>" IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW | KEEPER;
##
/trunk/rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vhd
1,6 → 1,6
-- $Id: tbd_nx_cram_memctl_as.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: tbd_nx_cram_memctl_as.vhd 802 2016-08-27 19:00:23Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
30,6 → 30,7
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-08-27 802 1.2.1 use cram_read0delay ect
-- 2011-11-26 433 1.2 renamed from tbd_n2_cram_memctl_as
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_memctl
-- 2010-06-03 298 1.0.1 add hack to force IOB'FFs to O_MEM_ADDR
78,7 → 79,7
begin
 
-- Note: This is a HACk to ensure that the IOB flops are on the O_MEM_ADDR
-- Note: This is a hack to ensure that the IOB flops are on the O_MEM_ADDR
-- pins. Without par might choose to use IFF's on ADDR, causing varying
-- routing delays to O_MEM_ADDR. Didn't find a better way, setting
-- iob "false" attributes in ADDR didn't help.
87,11 → 88,11
ADDR_X <= ADDR when RESET='0' else (others=>'0');
MEMCTL : nx_cram_memctl_as
CRAMCTL : nx_cram_memctl_as
generic map (
READ0DELAY => 2,
READ1DELAY => 2,
WRITEDELAY => 3)
READ0DELAY => cram_read0delay(50), -- assume 50 MHz system clock. Must be
READ1DELAY => cram_read1delay(50), -- modified when clock_period is
WRITEDELAY => cram_writedelay(50)) -- changed in tb_nx_cram_memctl !!
port map (
CLK => CLK,
RESET => RESET,
/trunk/rtl/bplib/nxcramlib/tb/tbrun.yml
0,0 → 1,12
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-22 800 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [default, viv, bplib, cram_memctl_as]
test: |
tbrun_tbw tb_nx_cram_memctl_as${ms}
/trunk/rtl/bplib/nxcramlib/tb
trunk/rtl/bplib/nxcramlib/tb Property changes : Modified: svn:ignore ## -42,3 +42,4 ## *.wdb tb_nx_cram_memctl_as tb_nx_cram_memctl_stim +list_cram_delay Index: trunk/rtl/bplib/s3board/s3_sram_memctl.vhd =================================================================== --- trunk/rtl/bplib/s3board/s3_sram_memctl.vhd (revision 36) +++ trunk/rtl/bplib/s3board/s3_sram_memctl.vhd (revision 37) @@ -1,6 +1,6 @@ --- $Id: s3_sram_memctl.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: s3_sram_memctl.vhd 793 2016-07-23 19:38:55Z mueller $ -- --- Copyright 2007-2011 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -30,6 +30,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-07-23 793 1.0.7 drop "KEEP" for data (better for dbg) -- 2011-11-19 427 1.0.6 now numeric_std clean -- 2010-06-03 299 1.0.5 add "KEEP" for data iob; -- 2010-05-16 291 1.0.4 rename memctl_s3sram -> s3_sram_memctl @@ -200,7 +201,7 @@ IOB_MEM_DATA : iob_reg_io_gen generic map ( DWIDTH => 32, - PULL => "KEEP") + PULL => "NONE") port map ( CLK => CLK, CEI => DATA_CEI, Index: trunk/rtl/bplib/s3board/tb/Makefile =================================================================== --- trunk/rtl/bplib/s3board/tb/Makefile (revision 36) +++ trunk/rtl/bplib/s3board/tb/Makefile (revision 37) @@ -10,8 +10,6 @@ # 2007-11-26 98 1.1 use make includes # 2007-09-23 84 1.0 Initial version # -EXE_all = tb_s3board_dummy -EXE_all += tb_s3board_fusp_dummy EXE_all += tb_s3_sram_memctl # ifndef XTW_BOARD Index: trunk/rtl/bplib/s3board/tb/s3board_dummy.vbom =================================================================== --- trunk/rtl/bplib/s3board/tb/s3board_dummy.vbom (nonexistent) +++ trunk/rtl/bplib/s3board/tb/s3board_dummy.vbom (revision 37) @@ -0,0 +1,7 @@ +# libs +../../../vlib/slvtypes.vhd +../s3boardlib.vbom +# components +../s3_sram_dummy.vbom +# design +s3board_dummy.vhd Index: trunk/rtl/bplib/s3board/tb/s3board_dummy.vhd =================================================================== --- trunk/rtl/bplib/s3board/tb/s3board_dummy.vhd (nonexistent) +++ trunk/rtl/bplib/s3board/tb/s3board_dummy.vhd (revision 37) @@ -0,0 +1,73 @@ +-- $Id: s3board_dummy.vhd 336 2010-11-06 18:28:27Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: s3board_dummy - syn +-- Description: s3board minimal target (base; serport loopback) +-- +-- Dependencies: - +-- To test: tb_s3board +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Revision History: +-- Date Rev Version Comment +-- 2010-11-06 336 1.1.3 rename input pin CLK -> I_CLK50 +-- 2010-04-17 278 1.1.2 rename sram_dummy -> s3_sram_dummy +-- 2007-12-16 101 1.1.1 use _N for active low +-- 2007-12-09 100 1.1 add sram memory signals, dummy handle them +-- 2007-09-23 85 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.s3boardlib.all; + +entity s3board_dummy is -- S3BOARD dummy (base; loopback) + -- implements s3board_aif + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end s3board_dummy; + +architecture syn of s3board_dummy is + +begin + + O_TXD <= I_RXD; + + SRAM : s3_sram_dummy -- connect SRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + +end syn; Index: trunk/rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd =================================================================== --- trunk/rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd (revision 36) +++ trunk/rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd (revision 37) @@ -1,4 +1,4 @@ --- $Id: tb_s3_sram_memctl.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: tb_s3_sram_memctl.vhd 790 2016-07-20 18:52:44Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -90,10 +90,10 @@ signal CLK_STOP : slbit := '0'; signal CLK_CYCLE : integer := 0; - constant clock_period : time := 20 ns; - constant clock_offset : time := 200 ns; - constant setup_time : time := 5 ns; - constant c2out_time : time := 10 ns; + constant clock_period : Delay_length := 20 ns; + constant clock_offset : Delay_length := 200 ns; + constant setup_time : Delay_length := 5 ns; + constant c2out_time : Delay_length := 10 ns; begin
/trunk/rtl/bplib/s3board/tb/tb_s3_sram_memctl_ssim.vbom
1,4 → 1,6
# configure for _*sim case
# configure
uut = s3_sram_memctl_ssim.vhd
# design
tb_s3_sram_memctl.vbom
@top:tb_s3_sram_memctl
/trunk/rtl/bplib/s3board/tb/tb_s3board.vbom
0,0 → 1,20
# Not meant for direct top level usage. Used with
# tb_s3board_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../s3boardlib.vbom
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
tb_s3board_core.vbom
${s3board_aif := s3board_dummy.vbom} -UUT
../../../vlib/serport/tb/serport_master_tb.vbom
# design
tb_s3board.vhd
@top:tb_s3board
/trunk/rtl/bplib/s3board/tb/tb_s3board.vhd
0,0 → 1,205
-- $Id: tb_s3board.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_s3board - sim
-- Description: Test bench for s3board (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- tb_s3board_core
-- s3board_aif [UUT]
-- serport/tb/serport_master_tb
--
-- To test: generic, any s3board_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 3.2.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 3.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 3.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 3.2 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-21 432 3.0.1 now numeric_std clean
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-06 336 2.0.3 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 2.0.2 use serport_uart_rxtx
-- 2010-05-01 286 2.0.1 use rritb_core as component again (rriv1 is gone..)
-- 2010-04-25 283 2.0 factor out basic device handling to tb_s3board_core
-- and_conf/_stim file processing to rri/tb/rritb_core
-- 2010-04-24 281 1.3.2 use serport_uart_[tr]x directly again
-- 2007-12-16 101 1.3.1 use _N for active low, add sram memory model
-- 2007-12-09 100 1.3 add sram memory signals
-- 2007-11-23 97 1.2 use serport_uart_[tr]x_tb to allow that UUT is a
-- [sft]sim model compiled with keep hierarchy
-- 2007-10-26 92 1.1.1 use DONE timestamp at end of execution
-- 2007-10-19 90 1.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- use CLKDIV="00 --> sim with max. serport speed
-- 2007-09-23 85 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.rlinklib.all;
use work.s3boardlib.all;
use work.simlib.all;
use work.simbus.all;
 
entity tb_s3board is
end tb_s3board;
 
architecture sim of tb_s3board is
signal CLK : slbit := '0';
 
signal CLK_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
 
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slv2 := (others=>'1');
signal O_MEM_BE_N : slv4 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADDR : slv18 := (others=>'Z');
signal IO_MEM_DATA : slv32 := (others=>'0');
 
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
 
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLK,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
 
S3CORE : entity work.tb_s3board_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
 
UUT : s3board_aif
port map (
I_CLK50 => CLK,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
 
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
 
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
 
if RXERR = '1' then
writetimestamp(oline, CLK_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
 
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
 
end sim;
/trunk/rtl/bplib/s3board/tb/tb_s3board_core.vbom
1,7 → 1,9
# libs
../../../vlib/slvtypes.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/simlib/simbididly.vhd
../../issi/is61lv25616al.vbom
# design
tb_s3board_core.vhd
/trunk/rtl/bplib/s3board/tb/tb_s3board_core.vhd
1,4 → 1,4
-- $Id: tb_s3board_core.vhd 724 2016-01-03 22:53:53Z mueller $
-- $Id: tb_s3board_core.vhd 793 2016-07-23 19:38:55Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
15,14 → 15,16
-- Module Name: tb_s3board_core - sim
-- Description: Test bench for s3board - core device handling
--
-- Dependencies: vlib/parts/issi/is61lv25616al
-- Dependencies: simlib/simbididly
-- vlib/parts/issi/is61lv25616al
--
-- To test: generic, any s3board target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-23 793 1.1 use simbididly
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2010-05-02 287 1.0.1 add sbaddr_(swi|btn) defs, now sbus addr 16,17
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
35,6 → 37,7
use std.textio.all;
 
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
 
entity tb_s3board_core is
52,34 → 55,56
 
architecture sim of tb_s3board_core is
signal MM_MEM_CE_N : slv2 := (others=>'1');
signal MM_MEM_BE_N : slv4 := (others=>'1');
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADDR : slv18 := (others=>'Z');
signal MM_MEM_DATA : slv32 := (others=>'0');
 
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
 
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
constant pcb_delay : Delay_length := 1 ns;
 
begin
MM_MEM_CE_N <= O_MEM_CE_N after pcb_delay;
MM_MEM_BE_N <= O_MEM_BE_N after pcb_delay;
MM_MEM_WE_N <= O_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= O_MEM_OE_N after pcb_delay;
MM_MEM_ADDR <= O_MEM_ADDR after pcb_delay;
 
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 32)
port map (
A => IO_MEM_DATA,
B => MM_MEM_DATA);
 
MEM_L : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(0),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(15 downto 0)
CE_N => MM_MEM_CE_N(0),
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(1),
LB_N => MM_MEM_BE_N(0),
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA(15 downto 0)
);
MEM_U : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(1),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(3),
LB_N => O_MEM_BE_N(2),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(31 downto 16)
CE_N => MM_MEM_CE_N(1),
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(3),
LB_N => MM_MEM_BE_N(2),
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA(31 downto 16)
);
proc_simbus: process (SB_VAL)
/trunk/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
1,4 → 1,4
-- $Id: tb_s3board_fusp.vhd 730 2016-02-13 16:22:03Z mueller $
-- $Id: tb_s3board_fusp.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
25,9 → 25,10
-- To test: generic, any s3board_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.3.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
60,7 → 61,6
signal CLK : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
106,8 → 106,8
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
 
begin
 
116,8 → 116,7
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
CLK => CLK
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
125,7 → 124,6
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLK,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
/trunk/rtl/bplib/s3board/tb/tbrun.yml
0,0 → 1,12
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-27 802 1.0 Initial version
#
- default:
mode: ${ise_modes}
#
- tag: [default, ise, bplib, sram_memctl]
test: |
tbrun_tbw tb_s3_sram_memctl${ms}
/trunk/rtl/bplib/sysmon/sysmon_rbus_core.vhd
1,4 → 1,4
-- $Id: sysmon_rbus_core.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: sysmon_rbus_core.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
24,7 → 24,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-25 787 1.0.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-25 767 1.0.1 don't init N_REGS (vivado fix for fsm inference)
-- BUGFIX: use s_init in regs_init (was s_idle)
-- 2016-03-12 741 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
/trunk/rtl/ibus/Makefile
0,0 → 1,37
# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-20 749 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#
/trunk/rtl/ibus/ibd_iist.vhd
1,4 → 1,4
-- $Id: ibd_iist.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: ibd_iist.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2009-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
29,7 → 29,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 0.8.2 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 0.8.2 don't init N_REGS (vivado fix for fsm inference)
-- 2011-11-18 427 0.8.1 now numeric_std clean
-- 2010-10-17 333 0.8 use ibus V2 interface
-- 2009-06-07 224 0.7 send inverted stc_stp; remove pgc_err; honor msk_im
/trunk/rtl/ibus/ibdr_rhrp.vhd
1,4 → 1,4
-- $Id: ibdr_rhrp.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: ibdr_rhrp.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
28,7 → 28,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.0.4 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 1.0.4 don't init N_REGS (vivado fix for fsm inference)
-- 2015-06-20 692 1.0.3 BUGFIX: fix func-go when drive/init busy checks
-- 2015-06-05 690 1.0.2 use 'not unit' for lsb of rpsn to avoid SI detect
-- BUGFIX: set rmr only for write to busy unit
/trunk/rtl/ibus/ibdr_rk11.vhd
1,4 → 1,4
-- $Id: ibdr_rk11.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: ibdr_rk11.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2008-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
29,7 → 29,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.3.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 1.3.1 don't init N_REGS (vivado fix for fsm inference)
-- 2015-05-01 672 1.3 BUGFIX: interrupt after dreset,seek command start
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
/trunk/rtl/ibus/ibdr_rl11.vhd
1,4 → 1,4
-- $Id: ibdr_rl11.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: ibdr_rl11.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2014-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
27,7 → 27,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.0.2 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 1.0.2 don't init N_REGS (vivado fix for fsm inference)
-- 2015-03-04 655 1.0.1 seek: ignore da(6:5), don't check for 0 anymore
-- 2015-02-28 653 1.0 Initial verison
-- 2014-06-09 561 0.1 First draft
/trunk/rtl/ibus/sys_conf.vhd
0,0 → 1,47
-- $Id: sys_conf.vhd 683 2015-05-17 21:54:35Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Default definitions for ibdr_maxisys
--
-- Dependencies: -
-- Tool versions: xst 14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2015-03-14 658 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package sys_conf is
 
-- configure character and communication devices
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11
constant sys_conf_ibd_pc11 : boolean := true; -- PC11
constant sys_conf_ibd_lp11 : boolean := true; -- LP11
 
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
 
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
 
end package sys_conf;
 
/trunk/rtl/make_ise/generic_ghdl.mk
1,4 → 1,4
# $Id: generic_ghdl.mk 778 2016-06-25 15:18:01Z mueller $
# $Id: generic_ghdl.mk 781 2016-07-01 16:56:02Z mueller $
#
# Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
5,7 → 5,8
#
# Revision History:
# Date Rev Version Comment
# 2016-06-24 778 1.1 use ghdl.?sim as workdir
# 2016-07-01 781 1.5.1 ghdl_clean: remove also gcov files
# 2016-06-24 778 1.5 use ghdl.?sim as workdir
# 2015-02-14 646 1.4 use --xlpath for vbomconv; drop cygwin support;
# 2014-07-26 575 1.3.2 use XTWI_PATH now (ise/vivado switch done later)
# 2013-01-27 477 1.3.1 use dontincdep.mk to suppress .dep include on clean
43,6 → 44,7
ghdl_clean: ghdl_tmp_clean
rm -f $(EXE_all)
rm -f $(EXE_all:%=%_[sft]sim)
rm -f *.gcov *.gcda *.gcno
#
ghdl_tmp_clean:
rm -rf ghdl.[bsft]sim
/trunk/rtl/make_viv/viv_default_config.tcl File deleted
/trunk/rtl/make_viv/viv_tools_config.tcl File deleted
/trunk/rtl/make_viv/viv_tools_model.tcl File deleted
/trunk/rtl/make_viv/viv_default_build.tcl File deleted
/trunk/rtl/make_viv/viv_default_model.tcl File deleted
/trunk/rtl/make_viv/viv_init.tcl File deleted
/trunk/rtl/make_viv/viv_tools_build.tcl File deleted
/trunk/rtl/make_viv/generic_ghdl.mk
1,4 → 1,4
# $Id: generic_ghdl.mk 778 2016-06-25 15:18:01Z mueller $
# $Id: generic_ghdl.mk 781 2016-07-01 16:56:02Z mueller $
#
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
5,6 → 5,7
#
# Revision History:
# Date Rev Version Comment
# 2016-07-01 781 1.1.1 ghdl_clean: remove also gcov files
# 2016-06-24 778 1.1 add rsim model; use ghdl.?sim as workdir
# 2015-02-14 646 1.0 Initial version (cloned from make_ise)
#
35,6 → 36,7
ghdl_clean: ghdl_tmp_clean
rm -f $(EXE_all)
rm -f $(EXE_all:%=%_[sor]sim)
rm -f *.gcov *.gcda *.gcno
#
ghdl_tmp_clean:
rm -rf ghdl.[bsor]sim
/trunk/rtl/make_viv/generic_vivado.mk
1,4 → 1,4
# $Id: generic_vivado.mk 778 2016-06-25 15:18:01Z mueller $
# $Id: generic_vivado.mk 803 2016-08-28 12:39:00Z mueller $
#
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
5,6 → 5,8
#
# Revision History:
# Date Rev Version Comment
# 2016-08-27 802 1.4.1 viv_clean: rm only vivado logs
# 2016-07-22 792 1.4 relocate viv tcl code to tools/vivado
# 2016-06-24 778 1.3 add rsim.vhd and [sorep]sim.v targets
# 2016-06-11 774 1.2.1 call xviv_sim_vhdl_cleanup for %_[so]sim rules
# 2016-05-27 769 1.2 add xviv_msg_filter support
22,16 → 24,16
# ensure that default tools and flows are defined
#
ifndef VIV_INIT
VIV_INIT = ${RETROBASE}/rtl/make_viv/viv_init.tcl
VIV_INIT = ${RETROBASE}/tools/vivado/viv_init.tcl
endif
ifndef VIV_BUILD_FLOW
VIV_BUILD_FLOW = ${RETROBASE}/rtl/make_viv/viv_default_build.tcl
VIV_BUILD_FLOW = ${RETROBASE}/tools/vivado/viv_default_build.tcl
endif
ifndef VIV_CONFIG_FLOW
VIV_CONFIG_FLOW = ${RETROBASE}/rtl/make_viv/viv_default_config.tcl
VIV_CONFIG_FLOW = ${RETROBASE}/tools/vivado/viv_default_config.tcl
endif
ifndef VIV_MODEL_FLOW
VIV_MODEL_FLOW = ${RETROBASE}/rtl/make_viv/viv_default_model.tcl
VIV_MODEL_FLOW = ${RETROBASE}/tools/vivado/viv_default_model.tcl
endif
#
# $@ first target
247,7 → 249,9
rm -f *.bit
rm -f *.dcp
rm -f *.jou
rm -f *.log
rm -f *_bit.log
rm -f *_imp.log
rm -f *_syn.log
rm -f *.rpt
rm -f *_[sor]sim.vhd
rm -f *_[sorept]sim.v
/trunk/rtl/make_viv/generic_xsim.mk
1,4 → 1,4
# $Id: generic_xsim.mk 778 2016-06-25 15:18:01Z mueller $
# $Id: generic_xsim.mk 804 2016-08-28 17:33:50Z mueller $
#
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
5,6 → 5,7
#
# Revision History:
# Date Rev Version Comment
# 2016-08-28 804 1.1.1 xsim work dir now xsim.<mode>.<stem>
# 2016-06-24 778 1.1 add [rep]sim models; use xsim.?sim as workdir
# 2016-02-06 727 1.0 Initial version
#
77,7 → 78,7
rm -f $(EXE_all:%=%_XSim_esim)
rm -f $(EXE_all:%=%_XSim_psim)
rm -f $(EXE_all:%=%_XSim_tsim)
rm -rf xsim.[bsorept]sim
rm -rf xsim.[bsorept]sim.*
#
xsim_tmp_clean:
rm -f *.wdb
85,6 → 86,6
rm -f xsim.log xsim_*.backup.log
rm -f webtalk.jou webtalk_*.backup.jou
rm -f webtalk.log webtalk_*.backup.log
rm -rf xsim.[bsorept]sim/xsim.dir/xil_defaultlib
rm -f xsim.dir
rm -rf xsim.[bsorept]sim.*/xsim.dir/xil_defaultlib
rm -rf xsim.dir
#
/trunk/rtl/sys_gen/tst_rlink/Makefile
0,0 → 1,37
# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-20 749 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#
/trunk/rtl/sys_gen/tst_rlink/arty/tb/tb_tst_rlink_arty.vbom
1,7 → 1,9
# configure tb_arty with sys_tst_rlink_arty target;
# use vhdl configure file (tb_tst_rlink_arty.vhd) to allow
# that all configurations will co-exist in work library
${arty_aif := ../sys_tst_rlink_arty.vbom}
# configure
arty_aif = ../sys_tst_rlink_arty.vbom
sys_conf = sys_conf_sim.vhd
# design
../../../../bplib/arty/tb/tb_arty.vbom
tb_tst_rlink_arty.vhd
/trunk/rtl/sys_gen/tst_rlink/arty/tb/tb_tst_rlink_arty_ssim.vbom
1,6 → 1,9
# configure for _*sim case
# Note: this tb uses sys_tst_rlink_arty.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
# configure
gsr_pulse = ../../../../vlib/xlib/gsr_pulse.vbom
arty_aif = sys_tst_rlink_arty_ssim.vhd
# design
tb_tst_rlink_arty.vbom
@top:tb_tst_rlink_arty
/trunk/rtl/sys_gen/tst_rlink/arty/tb/tbrun.yml
0,0 → 1,18
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [default, viv, sys_tst_rlink, arty, base]
test: |
tbrun_tbwrri --hxon --lsuf base --pack tst_rlink tb_tst_rlink_arty${ms} \
"tst_rlink::setup" "tst_rlink::test_all"
#
- tag: [default, viv, sys_tst_rlink, arty, emon]
test: |
tbrun_tbwrri --hxon --lsuf emon --pack tst_rlink tb_tst_rlink_arty${ms} \
"tst_rlink::setup" "tst_rlink::test_all_emon"
/trunk/rtl/sys_gen/tst_rlink/basys3/tb/tb_tst_rlink_b3.vbom
1,7 → 1,9
# configure tb_basys3 with sys_tst_rlink_b3 target;
# use vhdl configure file (tb_tst_rlink_b3.vhd) to allow
# that all configurations will co-exist in work library
${basys3_aif := ../sys_tst_rlink_b3.vbom}
# configure
basys3_aif = ../sys_tst_rlink_b3.vbom
sys_conf = sys_conf_sim.vhd
# design
../../../../bplib/basys3/tb/tb_basys3.vbom
tb_tst_rlink_b3.vhd
/trunk/rtl/sys_gen/tst_rlink/basys3/tb/tb_tst_rlink_b3_ssim.vbom
1,6 → 1,8
# configure for _*sim case
# Note: this tb uses sys_tst_rlink_b3.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
# configure
basys3_aif = sys_tst_rlink_b3_ssim.vhd
# design
tb_tst_rlink_b3.vbom
@top:tb_tst_rlink_b3
/trunk/rtl/sys_gen/tst_rlink/basys3/tb/tbrun.yml
0,0 → 1,18
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [default, viv, sys_tst_rlink, b3, base]
test: |
tbrun_tbwrri --hxon --lsuf base --pack tst_rlink tb_tst_rlink_b3${ms} \
"tst_rlink::setup" "tst_rlink::test_all"
#
- tag: [default, viv, sys_tst_rlink, b3, emon]
test: |
tbrun_tbwrri --hxon --lsuf emon --pack tst_rlink tb_tst_rlink_b3${ms} \
"tst_rlink::setup" "tst_rlink::test_all_emon"
/trunk/rtl/sys_gen/tst_rlink/nexys2/tb/tb_tst_rlink_n2.vbom
1,7 → 1,9
# configure tb_nexsy2_fusp with sys_tst_rlink_n2 target;
# use vhdl configure file (tb_tst_rlink_n2.vhd) to allow
# that all configurations will co-exist in work library
${nexys2_fusp_aif := ../sys_tst_rlink_n2.vbom}
# configure
nexys2_fusp_aif = ../sys_tst_rlink_n2.vbom
sys_conf = sys_conf_sim.vhd
# design
../../../../bplib/nexys2/tb/tb_nexys2_fusp.vbom
tb_tst_rlink_n2.vhd
/trunk/rtl/sys_gen/tst_rlink/nexys2/tb/tb_tst_rlink_n2_ssim.vbom
1,6 → 1,8
# configure for _*sim case
# Note: this tb uses sys_tst_rlink_n2.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
# configure
nexys2_fusp_aif = sys_tst_rlink_n2_ssim.vhd
# design
tb_tst_rlink_n2.vbom
@top:tb_tst_rlink_n2
/trunk/rtl/sys_gen/tst_rlink/nexys2/tb/tbrun.yml
0,0 → 1,19
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-28 803 1.1 use ${ise_modes_noisim} when ISim can't be used
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${ise_modes_noisim}
#
- tag: [default, ise, sys_tst_rlink, n2, base]
test: |
tbrun_tbwrri --sxon --lsuf base --pack tst_rlink tb_tst_rlink_n2${ms} \
"tst_rlink::setup" "tst_rlink::test_all"
#
- tag: [default, ise, sys_tst_rlink, n2, emon]
test: |
tbrun_tbwrri --sxon --lsuf emon --pack tst_rlink tb_tst_rlink_n2${ms} \
"tst_rlink::setup" "tst_rlink::test_all_emon"
/trunk/rtl/sys_gen/tst_rlink/nexys3/tb/tb_tst_rlink_n3.vbom
1,7 → 1,9
# configure tb_nexsy3_fusp with sys_tst_rlink_n3 target;
# use vhdl configure file (tb_tst_rlink_n3.vhd) to allow
# that all configurations will co-exist in work library
${nexys3_fusp_aif := ../sys_tst_rlink_n3.vbom}
# configure
nexys3_fusp_aif = ../sys_tst_rlink_n3.vbom
sys_conf = sys_conf_sim.vhd
# design
../../../../bplib/nexys3/tb/tb_nexys3_fusp.vbom
tb_tst_rlink_n3.vhd
/trunk/rtl/sys_gen/tst_rlink/nexys3/tb/tb_tst_rlink_n3_ssim.vbom
1,6 → 1,8
# configure for _*sim case
# Note: this tb uses sys_tst_rlink_n3.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
# configure
nexys3_fusp_aif = sys_tst_rlink_n3_ssim.vhd
# design
tb_tst_rlink_n3.vbom
@top:tb_tst_rlink_n3
/trunk/rtl/sys_gen/tst_rlink/nexys3/tb/tbrun.yml
0,0 → 1,19
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-28 803 1.1 use ${ise_modes_noisim} when ISim can't be used
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${ise_modes_noisim}
#
- tag: [default, ise, sys_tst_rlink, n3, base]
test: |
tbrun_tbwrri --sxon --lsuf base --pack tst_rlink tb_tst_rlink_n3${ms} \
"tst_rlink::setup" "tst_rlink::test_all"
#
- tag: [default, ise, sys_tst_rlink, n3, emon]
test: |
tbrun_tbwrri --sxon --lsuf emon --pack tst_rlink tb_tst_rlink_n3${ms} \
"tst_rlink::setup" "tst_rlink::test_all_emon"
/trunk/rtl/sys_gen/tst_rlink/nexys4/tb/tb_tst_rlink_n4.vbom
1,7 → 1,9
# configure tb_nexsy4 with sys_tst_rlink_n4 target;
# use vhdl configure file (tb_tst_rlink_n4.vhd) to allow
# that all configurations will co-exist in work library
${nexys4_aif := ../sys_tst_rlink_n4.vbom}
# configure
nexys4_aif = ../sys_tst_rlink_n4.vbom
sys_conf = sys_conf_sim.vhd
# design
../../../../bplib/nexys4/tb/tb_nexys4.vbom
tb_tst_rlink_n4.vhd
/trunk/rtl/sys_gen/tst_rlink/nexys4/tb/tb_tst_rlink_n4_ssim.vbom
1,6 → 1,8
# configure for _*sim case
# Note: this tb uses sys_tst_rlink_n4.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
# configure
nexys4_aif = sys_tst_rlink_n4_ssim.vhd
# design
tb_tst_rlink_n4.vbom
@top:tb_tst_rlink_n4
/trunk/rtl/sys_gen/tst_rlink/nexys4/tb/tbrun.yml
0,0 → 1,18
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [default, viv, sys_tst_rlink, n4, base]
test: |
tbrun_tbwrri --lsuf base --pack tst_rlink tb_tst_rlink_n4${ms} \
"tst_rlink::setup" "tst_rlink::test_all"
#
- tag: [default, viv, sys_tst_rlink, n4, emon]
test: |
tbrun_tbwrri --lsuf emon --pack tst_rlink tb_tst_rlink_n4${ms} \
"tst_rlink::setup" "tst_rlink::test_all_emon"
/trunk/rtl/sys_gen/tst_rlink/s3board/tb/tb_tst_rlink_s3.vbom
1,7 → 1,9
# configure tb_s3board_fusp with sys_tst_rlink_s3 target;
# use vhdl configure file (tb_tst_rlink_s3.vhd) to allow
# that all configurations will co-exist in work library
${s3board_aif := ../sys_tst_rlink_s3.vbom}
# configure
s3board_fusp_aif = ../sys_tst_rlink_s3.vbom
sys_conf = sys_conf_sim.vhd
# design
../../../../bplib/s3board/tb/tb_s3board_fusp.vbom
tb_tst_rlink_s3.vhd
/trunk/rtl/sys_gen/tst_rlink/s3board/tb/tbrun.yml
0,0 → 1,19
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-28 803 1.1 no ISim and no ssim available --> only bsim left !
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: bsim
#
- tag: [default, ise, sys_tst_rlink, s3, base]
test: |
tbrun_tbwrri --sxon --lsuf base --pack tst_rlink tb_tst_rlink_s3${ms} \
"tst_rlink::setup" "tst_rlink::test_all"
#
- tag: [default, ise, sys_tst_rlink, s3, emon]
test: |
tbrun_tbwrri --sxon --lsuf emon --pack tst_rlink tb_tst_rlink_s3${ms} \
"tst_rlink::setup" "tst_rlink::test_all_emon"
/trunk/rtl/sys_gen/tst_rlink/tbrun.yml
0,0 → 1,12
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-13 798 1.0 Initial version
#
- include: s3board/tb/tbrun.yml
- include: nexys2/tb/tbrun.yml
- include: nexys3/tb/tbrun.yml
- include: nexys4/tb/tbrun.yml
- include: basys3/tb/tbrun.yml
- include: arty/tb/tbrun.yml
/trunk/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.vbom
1,4 → 1,4
# conf
# configure
sys_conf = sys_conf.vhd
# libs
# components
/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.vbom
1,4 → 1,4
# conf
# configure
sys_conf = sys_conf.vhd
# libs
# components
/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2.vbom
1,7 → 1,9
# configure tb_nexsy2_fusp_cuff with sys_tst_rlink_cuff_n2 target;
# use vhdl configure file (tb_tst_rlink_cuff_ic_n2.vhd) to allow
# that all configurations will co-exist in work library
${nexys2_fusp_cuff_aif := ../sys_tst_rlink_cuff_ic_n2.vbom}
# configure
nexys2_fusp_cuff_aif = ../sys_tst_rlink_cuff_ic_n2.vbom
sys_conf = sys_conf_sim.vhd
# design
../../../../../bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom
tb_tst_rlink_cuff_ic_n2.vhd
/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2_ssim.vbom
1,6 → 1,8
# configure for _*sim case
# Note: this tb uses sys_tst_rlink_n2.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
# configure
nexys2_fusp_cuff_aif = sys_tst_rlink_cuff_ic_n2_ssim.vhd
# design
tb_tst_rlink_cuff_ic_n2.vbom
@top:tb_tst_rlink_cuff_ic_n2
/trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tbrun.yml
0,0 → 1,27
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-28 803 1.1 use ${ise_modes_noisim} when ISim can't be used
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${ise_modes_noisim}
#
- tag: [default, ise, sys_tst_rlink_cuff, n2, basefx2]
test: |
tbrun_tbwrri --cuff --lsuf basefx2 --pack tst_rlink \
tb_tst_rlink_cuff_ic_n2${ms} \
"tst_rlink::setup" "tst_rlink::test_all"
#
- tag: [ise, sys_tst_rlink_cuff, n2, baseser]
test: |
tbrun_tbwrri --sxon --lsuf baseser --pack tst_rlink \
tb_tst_rlink_cuff_ic_n2${ms} \
"tst_rlink::setup" "tst_rlink::test_all"
 
- tag: [ise, sys_tst_rlink_cuff, n2, emon]
test: |
tbrun_tbwrri --sxon --lsuf emonser --pack tst_rlink \
tb_tst_rlink_cuff_ic_n2${ms} \
"tst_rlink::setup" "tst_rlink::test_all_emon"
/trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.vbom
1,4 → 1,4
# conf
# configure
sys_conf = sys_conf.vhd
# libs
# components
/trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/tb_tst_rlink_cuff_ic_n3.vbom
1,7 → 1,9
# configure tb_nexsy3_fusp_cuff with sys_tst_rlink_cuff_n3 target;
# use vhdl configure file (tb_tst_rlink_cuff_ic_n3.vhd) to allow
# that all configurations will co-exist in work library
${nexys3_fusp_cuff_aif := ../sys_tst_rlink_cuff_ic_n3.vbom}
# configure
nexys3_fusp_cuff_aif = ../sys_tst_rlink_cuff_ic_n3.vbom
sys_conf = sys_conf_sim.vhd
# design
../../../../../bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom
tb_tst_rlink_cuff_ic_n3.vhd
/trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/tb_tst_rlink_cuff_ic_n3_ssim.vbom
1,6 → 1,8
# configure for _*sim case
# Note: this tb uses sys_tst_rlink_n3.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
# configure
nexys3_fusp_cuff_aif = sys_tst_rlink_cuff_ic_n3_ssim.vhd
# design
tb_tst_rlink_cuff_ic_n3.vbom
@top:tb_tst_rlink_cuff_ic_n3
/trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/tbrun.yml
0,0 → 1,27
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-28 803 1.1 use ${ise_modes_noisim} when ISim can't be used
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${ise_modes_noisim}
#
- tag: [default, ise, sys_tst_rlink_cuff, n3, basefx2]
test: |
tbrun_tbwrri --cuff --lsuf basefx2 --pack tst_rlink \
tb_tst_rlink_cuff_ic_n3${ms} \
"tst_rlink::setup" "tst_rlink::test_all"
#
- tag: [ise, sys_tst_rlink_cuff, n3, baseser]
test: |
tbrun_tbwrri --sxon --lsuf baseser --pack tst_rlink \
tb_tst_rlink_cuff_ic_n3${ms} \
"tst_rlink::setup" "tst_rlink::test_all"
 
- tag: [ise, sys_tst_rlink_cuff, n3, emon]
test: |
tbrun_tbwrri --sxon --lsuf emonser --pack tst_rlink \
tb_tst_rlink_cuff_ic_n3${ms} \
"tst_rlink::setup" "tst_rlink::test_all_emon"
/trunk/rtl/sys_gen/tst_rlink_cuff/tbrun.yml
0,0 → 1,8
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-21 799 1.0 Initial version
#
- include: nexys2/ic/tb/tbrun.yml
- include: nexys3/ic/tb/tbrun.yml
/trunk/rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vbom
5,7 → 5,7
../../vlib/rlink/rlinklib.vbom
../../vlib/serport/serportlib.vbom
../../bplib/fx2lib/fx2lib.vhd
${sys_conf := nexys2/as/sys_conf.vhd}
${sys_conf := nexys2/ic/sys_conf.vhd}
# components
../../vlib/rlink/rlink_core8.vbom
../../vlib/rlink/rlink_rlbmux.vbom
/trunk/rtl/sys_gen/tst_serloop/Makefile
0,0 → 1,34
# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-20 749 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : all clean distclean
#
all : tst_serloop
#
distclean :
rm -f tst_serloop
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#
/trunk/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom
1,4 → 1,4
# conf
# configure
sys_conf = sys_conf1_sim.vhd
# libs
../../../../vlib/slvtypes.vhd
/trunk/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vhd
1,6 → 1,6
-- $Id: tb_tst_serloop1_n2.vhd 444 2011-12-25 10:04:58Z mueller $
-- $Id: tb_tst_serloop1_n2.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
25,6 → 25,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2 remove CLK_STOP logic (simstop via report)
-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack
-- 2011-12-16 439 1.0 Initial version
------------------------------------------------------------------------------
45,7 → 46,6
architecture sim of tb_tst_serloop1_n2 is
signal CLK50 : slbit := '0';
signal CLK_STOP : slbit := '0';
 
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
67,9 → 67,9
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
 
78,8 → 78,7
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_STOP => CLK_STOP
CLK => CLK50
);
 
UUT : entity work.sys_tst_serloop1_n2
113,7 → 112,6
port map (
CLKS => CLK50,
CLKH => CLK50,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
/trunk/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom
1,4 → 1,4
# conf
# configure
sys_conf = sys_conf2_sim.vhd
# libs
../../../../vlib/slvtypes.vhd
/trunk/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vhd
1,6 → 1,6
-- $Id: tb_tst_serloop2_n2.vhd 444 2011-12-25 10:04:58Z mueller $
-- $Id: tb_tst_serloop2_n2.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
26,6 → 26,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2 remove CLK_STOP logic (simstop via report)
-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack
-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
-- 2011-11-17 426 1.0.1 use dcm_sfs now
48,7 → 49,6
architecture sim of tb_tst_serloop2_n2 is
signal CLK50 : slbit := '0';
signal CLK_STOP : slbit := '0';
 
signal CLKS : slbit := '0';
signal CLKH : slbit := '0';
73,9 → 73,9
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
 
84,8 → 84,7
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_STOP => CLK_STOP
CLK => CLK50
);
 
DCM_S : dcm_sfs
141,7 → 140,6
port map (
CLKS => CLKS,
CLKH => CLKH,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
/trunk/rtl/sys_gen/tst_serloop/nexys2/tb/tbrun.yml
0,0 → 1,17
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-00-10 806 1.1 use nossim because no _ssim support available
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${ise_modes_nossim}
#
- tag: [default, ise, sys_tst_serloop1, n2]
test: |
tbrun_tbw tb_tst_serloop1_n2${ms}
 
- tag: [default, ise, sys_tst_serloop2, n2]
test: |
tbrun_tbw tb_tst_serloop2_n2${ms}
/trunk/rtl/sys_gen/tst_serloop/nexys3/sys_conf2.vhd
0,0 → 1,39
-- $Id: sys_conf2.vhd 641 2015-02-01 22:12:15Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-11 438 1.0.1 use with ser=usr=100 MHz
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package sys_conf is
 
constant sys_conf_clkudiv_usecdiv : integer := 100; -- default usec (was 150)
constant sys_conf_clksdiv_usecdiv : integer := 100; -- default usec (was 60)
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_uart_cdinit : integer := 868-1; -- 100000000/115200
end package sys_conf;
/trunk/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop2_n3.ucf_cpp
0,0 → 1,30
## $Id: sys_tst_serloop2_n3.ucf_cpp 441 2011-12-20 17:01:16Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-12-11 438 1.0.1 temporarily use with ser=usr=100 MHz
## 2011-11-27 433 1.0 Initial version
##
 
NET "I_CLK100" TNM_NET = "I_CLK100";
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns AFTER "I_CLK100";
 
## rules to prevent default 'cross clock' constraints for the dcm generated
## clocks CLK(150 MHz) and CLKS(60 MHz). All essential domain crossing done
## via fifo's or dedicated capture/synch flops.
 
##NET "CLK" TNM_NET = "CLK";
##NET "CLKS" TNM_NET = "CLKS";
##TIMESPEC "TS_CDC_CLK_CLKS" = FROM "I_CLK100" TO "CLKS" 10 ns;
##TIMESPEC "TS_CDC_CLK_CLKS" = FROM "CLK" TO "CLKS" 10 ns;
##TIMESPEC "TS_CDC_CLKS_CLK" = FROM "CLKS" TO "I_CLK100" 10 ns;
 
## std board
##
#include "bplib/nexys3/nexys3_pins.ucf"
##
## Pmod B0 - RS232
##
#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf"
/trunk/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop2_n3.vbom
0,0 → 1,22
# libs
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../tst_serlooplib.vbom
../../../vlib/serport/serportlib.vbom
../../../bplib/nxcramlib/nxcramlib.vhd
${sys_conf := sys_conf2.vhd}
# components
[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio.vbom
../tst_serloop_hiomap.vbom
../../../vlib/serport/serport_2clock.vbom
../tst_serloop.vbom
../../../bplib/nxcramlib/nx_cram_dummy.vbom
# design
sys_tst_serloop2_n3.vhd
@ucf_cpp: sys_tst_serloop2_n3.ucf
/trunk/rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop2_n3.vhd
0,0 → 1,312
-- $Id: sys_tst_serloop2_n3.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop2_n3 - syn
-- Description: Tester serial link for nexys3
--
-- Dependencies: vlib/xlib/dcm_sfs
-- genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_2clock
-- tst_serloop
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-27 433 13.1 O40d xc6slx16-2 486 652 59 237 t 6.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-11 438 1.0.2 add dcm monitor hack; use with ser=usr=100 MHz
-- 2011-12-09 437 1.0.1 rename serport stat->moni port
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
 
-- ----------------------------------------------------------------------------
 
entity sys_tst_serloop2_n3 is -- top level
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop2_n3;
 
architecture syn of sys_tst_serloop2_n3 is
 
signal CLK : slbit := '0';
signal RESET : slbit := '0';
 
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
 
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
 
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal LED_OUT : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
 
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
 
-- some signals for dcm monitor hack
signal LOCKED_DCMU : slbit := '0';
signal LOCKED_DCMS : slbit := '0';
signal R_MSECU_CNT : slv10 := (others=>'0');
signal R_MSECS_CNT : slv10 := (others=>'0');
 
begin
 
DCM_U : dcm_sfs
generic map (
CLKFX_DIVIDE => 1, -- was 2
CLKFX_MULTIPLY => 1, -- was 3
CLKIN_PERIOD => 10.0)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => LOCKED_DCMU
);
 
CLKDIV_U : clkdivce
generic map (
CDUWIDTH => 8,
USECDIV => sys_conf_clkudiv_usecdiv, -- syn: 150 sim: 30
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
 
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 1, -- was 5
CLKFX_MULTIPLY => 1, -- was 3
CLKIN_PERIOD => 10.0)
port map (
CLKIN => I_CLK100,
CLKFX => CLKS,
LOCKED => LOCKED_DCMS
);
 
CLKDIV_S : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksdiv_usecdiv, -- syn: 60 sim: 12
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLKS,
CE_USEC => open,
CE_MSEC => CES_MSEC
);
 
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED_OUT,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
 
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
 
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLKS,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_2clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLKU => CLK,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
 
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
 
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
 
-- this is a hack to monitor the two dcm's
 
proc_msecu: process (CLK)
begin
if rising_edge(CLK) then
if CE_MSEC = '1' then
R_MSECU_CNT <= slv(unsigned(R_MSECU_CNT) + 1);
end if;
end if;
end process proc_msecu;
 
proc_msecs: process (CLKS)
begin
if rising_edge(CLKS) then
if CES_MSEC = '1' then
R_MSECS_CNT <= slv(unsigned(R_MSECS_CNT) + 1);
end if;
end if;
end process proc_msecs;
LED_OUT(7) <= R_MSECU_CNT(9) or (not LOCKED_DCMU);
LED_OUT(6) <= R_MSECS_CNT(9) or (not LOCKED_DCMS);
LED_OUT(5 downto 0) <= LED(5 downto 0);
end syn;
/trunk/rtl/sys_gen/tst_serloop/nexys3/tb/Makefile
6,6 → 6,7
# 2011-11-27 433 1.0 Initial version
#
EXE_all = tb_tst_serloop1_n3
EXE_all += tb_tst_serloop2_n3
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk
#
/trunk/rtl/sys_gen/tst_serloop/nexys3/tb/sys_conf2_sim.vhd
0,0 → 1,44
-- $Id: sys_conf2_sim.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n3 (for test bench)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package sys_conf is
 
-- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec
-- to 60 cycles (1 usec). This affects the pulse generators (usec) and
-- mainly the autobauder. A break will be detected after 128 msec periods,
-- this in simulation after 128 usec or 6400 cycles. This is compatible with
-- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
constant sys_conf_clkudiv_usecdiv : integer := 30; -- default usec
constant sys_conf_clksdiv_usecdiv : integer := 12; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
end package sys_conf;
/trunk/rtl/sys_gen/tst_serloop/nexys3/tb/sys_tst_serloop2_n3.ucf_cpp
0,0 → 1,44
link ../sys_tst_serloop2_n3.ucf_cpp
trunk/rtl/sys_gen/tst_serloop/nexys3/tb/sys_tst_serloop2_n3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom =================================================================== --- trunk/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom (revision 36) +++ trunk/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom (revision 37) @@ -1,4 +1,4 @@ -# conf +# configure sys_conf = sys_conf1_sim.vhd # libs ../../../../vlib/slvtypes.vhd Index: trunk/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd =================================================================== --- trunk/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd (revision 36) +++ trunk/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd (revision 37) @@ -1,6 +1,6 @@ --- $Id: tb_tst_serloop1_n3.vhd 444 2011-12-25 10:04:58Z mueller $ +-- $Id: tb_tst_serloop1_n3.vhd 805 2016-09-03 08:09:52Z mueller $ -- --- Copyright 2011- by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -25,6 +25,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-09-03 805 1.2 remove CLK_STOP logic (simstop via report) -- 2011-12-23 444 1.1 use new simclk -- 2011-12-11 438 1.0 Initial version ------------------------------------------------------------------------------ @@ -44,7 +45,6 @@ architecture sim of tb_tst_serloop1_n3 is signal CLK100 : slbit := '0'; - signal CLK_STOP : slbit := '0'; signal I_RXD : slbit := '1'; signal O_TXD : slbit := '1'; @@ -66,9 +66,9 @@ signal FUSP_RXD : slbit := '1'; signal FUSP_TXD : slbit := '1'; - constant clock_period : time := 10 ns; - constant clock_offset : time := 200 ns; - constant delay_time : time := 2 ns; + constant clock_period : Delay_length := 10 ns; + constant clock_offset : Delay_length := 200 ns; + constant delay_time : Delay_length := 2 ns; begin @@ -77,8 +77,7 @@ PERIOD => clock_period, OFFSET => clock_offset) port map ( - CLK => CLK100, - CLK_STOP => CLK_STOP + CLK => CLK100 ); UUT : entity work.sys_tst_serloop1_n3 @@ -113,7 +112,6 @@ port map ( CLKS => CLK100, CLKH => CLK100, - CLK_STOP => CLK_STOP, P0_RXD => RXD, P0_TXD => TXD, P0_RTS_N => '0',
/trunk/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop2_n3.vbom
0,0 → 1,13
# configure
sys_conf = sys_conf2_sim.vhd
# libs
../../../../vlib/slvtypes.vhd
../../../../vlib/xlib/xlib.vhd
../../../../vlib/simlib/simlib.vhd
# components
../../../../vlib/simlib/simclk.vbom
../../../../vlib/xlib/dcm_sfs_gsim.vbom
../sys_tst_serloop2_n3.vbom -UUT
../../tb/tb_tst_serloop.vbom
# design
tb_tst_serloop2_n3.vhd
/trunk/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop2_n3.vhd
0,0 → 1,165
-- $Id: tb_tst_serloop2_n3.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop2_n3 - sim
-- Description: Test bench for sys_tst_serloop2_n3
--
-- Dependencies: simlib/simclk
-- vlib/xlib/dcm_sfs
-- sys_tst_serloop2_n3 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop2_n3
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.1 remove CLK_STOP logic (simstop via report)
-- 2011-12-23 444 1.1 use new simclk
-- 2011-12-11 438 1.0.1 temporarily use with ser=usr=100 MHz
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
 
entity tb_tst_serloop2_n3 is
end tb_tst_serloop2_n3;
 
architecture sim of tb_tst_serloop2_n3 is
signal CLK100 : slbit := '0';
 
signal CLKS : slbit := '0';
signal CLKH : slbit := '0';
 
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
 
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
 
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
 
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
 
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100
);
 
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 1, -- currently 1-to-1
CLKFX_MULTIPLY => 1,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => CLK100,
CLKFX => CLKS,
LOCKED => open
);
DCM_H : dcm_sfs
generic map (
CLKFX_DIVIDE => 1, -- currently 1-to-1
CLKFX_MULTIPLY => 1,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => CLK100,
CLKFX => CLKH,
LOCKED => open
);
UUT : entity work.sys_tst_serloop2_n3
port map (
I_CLK100 => CLK100,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_PPCM_CE_N => open,
O_PPCM_RST_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
 
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLKS,
CLKH => CLKH,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN(3 downto 0)
);
 
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
 
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
 
end sim;
/trunk/rtl/sys_gen/tst_serloop/nexys3/tb/tbrun.yml
0,0 → 1,17
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-00-10 806 1.1 use nossim because no _ssim support available
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${ise_modes_nossim}
#
- tag: [default, ise, sys_tst_serloop1, n3]
test: |
tbrun_tbw tb_tst_serloop1_n3${ms}
 
- tag: [default, ise, sys_tst_serloop2, n3]
test: |
tbrun_tbw tb_tst_serloop2_n3${ms}
/trunk/rtl/sys_gen/tst_serloop/nexys4/sys_conf2.vhd
0,0 → 1,68
-- $Id: sys_conf2.vhd 775 2016-06-18 13:42:00Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n4 (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2015.4-2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-06-18 775 1.0.1 use PLL for clkser_gentype
-- 2016-03-25 752 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package sys_conf is
 
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 5; -- f 20 Mhz
constant sys_conf_clksys_vcomultiply : positive := 36; -- vco 720 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 72 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clksys_msecdiv : integer := 1000; -- default msec
 
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
constant sys_conf_clkser_msecdiv : integer := 1000; -- default msec
 
-- configure hio interfaces -----------------------------------------------
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
 
-- configure serport ------------------------------------------------------
constant sys_conf_uart_defbaud : integer := 115200; -- default 115k baud
 
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
 
constant sys_conf_uart_cdinit : integer :=
(sys_conf_clkser/sys_conf_uart_defbaud)-1;
end package sys_conf;
/trunk/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vbom
0,0 → 1,21
# libs
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../tst_serlooplib.vbom
../../../vlib/serport/serportlib.vbom
${sys_conf := sys_conf2.vhd}
# components
[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_4line_iob.vbom
../../../bplib/bpgen/sn_humanio.vbom
../tst_serloop_hiomap.vbom
../../../vlib/serport/serport_2clock2.vbom
../tst_serloop.vbom
# design
sys_tst_serloop2_n4.vhd
@xdc:../../../bplib/nexys4/nexys4_pclk.xdc
@xdc:../../../bplib/nexys4/nexys4_pins.xdc
/trunk/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vhd
0,0 → 1,267
-- $Id: sys_tst_serloop2_n4.vhd 772 2016-06-05 12:55:11Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop1_n4 - syn
-- Description: Tester serial link for nexys4 (serport_1clock case)
--
-- Dependencies: vlib/xlib/s7_cmt_sfs
-- vlib/genlib/clkdivce
-- bpgen/bp_rs232_4line_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_2clock2
-- tst_serloop
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2016-03-25 751 2015.4 xc7a100t-1 415 402x 32 0 185
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-06-05 722 1.0.1 use CDUWIDTH=7 for CLKS, 120 MHz is natural choice
-- 2015-02-01 641 1.0 Initial version (derived from sys_tst_serloop1_n4)
------------------------------------------------------------------------------
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.sys_conf.all;
 
-- ----------------------------------------------------------------------------
 
entity sys_tst_serloop2_n4 is -- top level
-- implements nexys4_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_tst_serloop2_n4;
 
architecture syn of sys_tst_serloop2_n4 is
 
signal CLK : slbit := '0';
signal RESET : slbit := '0';
 
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
 
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
 
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
 
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
 
begin
 
GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
 
CLKDIV_CLK : clkdivce
generic map (
CDUWIDTH => 8,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => sys_conf_clksys_msecdiv)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
 
GEN_CLKSER : s7_cmt_sfs -- clock generator serport -----------
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clkser_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLKS,
LOCKED => open
);
 
CLKDIV_CLKS : clkdivce
generic map (
CDUWIDTH => 7, -- good up to 127 MHz
USECDIV => sys_conf_clkser_mhz,
MSECDIV => sys_conf_clkser_msecdiv)
port map (
CLK => CLKS,
CE_USEC => open,
CE_MSEC => CES_MSEC
);
 
HIO : sn_humanio
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
 
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0),
LED => LED(7 downto 0),
DSP_DAT => DSP_DAT(15 downto 0),
DSP_DP => DSP_DP(3 downto 0)
);
 
IOB_RS232 : bp_rs232_4line_iob
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
SERPORT : serport_2clock2
generic map (
CDWIDTH => 12,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLKU => CLK,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
 
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
 
-- show autobauder clock divisor on msb of display
DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0);
DSP_DAT(19) <= '0';
DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f;
DSP_DP(7 downto 4) <= "0010";
 
-- setup unused outputs in nexys4
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
 
end syn;
/trunk/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vmfset
0,0 → 1,40
# $Id: sys_tst_serloop2_n4.vmfset 773 2016-06-05 20:03:15Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# false_path -hold ignored by synth ----------------------------
I [Designutils 20-1567] # generic
 
# port driven by constant --------------------------------------
# --> RGBLED0 unused # OK 2016-06-05
i [Synth 8-3917] O_RGBLED0[\d]
# --> upper 8 LEDs unused
i [Synth 8-3917] O_LED[(8|9)]
i [Synth 8-3917] O_LED[1\d]
 
# tying undriven pin to constant -------------------------------
# upper 8 LEDs unused # OK 2016-06-05
i [Synth 8-3295] HIO:LED[\d*]
 
# unconnected ports --------------------------------------------
# --> unused SWI and BTN # OK 2016-06-05
i [Synth 8-3331] tst_serloop_hiomap.*SWI[\d]
i [Synth 8-3331] tst_serloop_hiomap.*BTN[\d]
# --> clkdiv isn't displayed # OK 2016-06-05
i [Synth 8-3331] SER_MONI[abclkdiv.*][\d*]
# --> other unused fields which aren't visualized # OK 2016-06-05
i [Synth 8-3331] SER_MONI[(rxact|txact|abdone|rxerr|rxovr)]
i [Synth 8-3331] HIO_CNTL[enaftdi]
 
# unused sequential element ------------------------------------
I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic
# --> currently CDUWIDTH=8, but clock below 127 MHz # OK 2016-06-05
i [Synth 8-3332] CLKDIV_CLK/R_REGS_reg[ucnt][7]
# --> many HIO pins not used # OK 2016-06-05
i [Synth 8-3332] HIO/IOB_(SWI|BTN)/R_DI_reg[\d*]
i [Synth 8-3332] HIO/DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange)][\d*]
 
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]
I [Vivado 12-2489] # multiple of 1 ps
I [Physopt 32-742] # BRAM Flop Optimization
/trunk/rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf2_sim.vhd
0,0 → 1,71
-- $Id: sys_conf2_sim.vhd 775 2016-06-18 13:42:00Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n4 (for test bench)
--
-- Dependencies: -
-- Tool versions: viv 2015.4-2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-06-18 775 1.0.1 use PLL for clkser_gentype
-- 2016-04-09 760 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package sys_conf is
 
-- in simulation a usec stays to 120 cycles (1.0 usec) and a msec to
-- 240 cycles (2 usec). This affects mainly the autobauder. A break will be
-- detected after 128 msec periods, this in simulation after 256 usec or
-- 30720 cycles. This is compatible with bitrates of 115200 baud or higher
-- (115200 <-> 8.68 usec <-> 1040 cycles)
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 5; -- f 20 Mhz
constant sys_conf_clksys_vcomultiply : positive := 36; -- vco 720 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 72 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
 
constant sys_conf_clksys_msecdiv : integer := 2; -- shortened !!
 
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
 
constant sys_conf_clkser_msecdiv : integer := 2; -- shortened !!
 
-- configure hio interfaces -----------------------------------------------
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
 
-- configure serport ------------------------------------------------------
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
 
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
 
end package sys_conf;
/trunk/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vhd
1,6 → 1,6
-- $Id: tb_tst_serloop1_n4.vhd 760 2016-04-09 16:17:13Z mueller $
-- $Id: tb_tst_serloop1_n4.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
26,6 → 26,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2 remove CLK_STOP logic (simstop via report)
-- 2016-04-09 760 1.1 clock now from cmt and configurable
-- 2015-02-21 438 1.0 Initial version (cloned from tb_tst_serloop1_n3)
------------------------------------------------------------------------------
46,7 → 47,6
architecture sim of tb_tst_serloop1_n4 is
signal CLK100 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK : slbit := '0';
 
64,9 → 64,9
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
 
75,8 → 75,7
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100,
CLK_STOP => CLK_STOP
CLK => CLK100
);
 
GEN_CLKSYS : entity work.s7_cmt_sfs_tb
115,7 → 114,6
port map (
CLKS => CLK,
CLKH => CLK,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => RTS_N,
/trunk/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop2_n4.vbom
0,0 → 1,11
# libs
../../../../vlib/slvtypes.vhd
../../../../vlib/simlib/simlib.vhd
${sys_conf := sys_conf2_sim.vhd}
# components
../../../../vlib/simlib/simclk.vbom
../../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom
../sys_tst_serloop2_n4.vbom -UUT
../../tb/tb_tst_serloop.vbom
# design
tb_tst_serloop2_n4.vhd
/trunk/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop2_n4.vhd
0,0 → 1,152
-- $Id: tb_tst_serloop2_n4.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop2_n4 - sim
-- Description: Test bench for sys_tst_serloop2_n4
--
-- Dependencies: simlib/simclk
-- vlib/xlib/tb/s7_cmt_sfs_tb
-- sys_tst_serloop2_n4 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop2_n4
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.1 remove CLK_STOP logic (simstop via report)
-- 2016-04-09 760 1.0 Initial version (cloned from tb_tst_serloop1_n4)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.simlib.all;
use work.sys_conf.all;
 
entity tb_tst_serloop2_n4 is
end tb_tst_serloop2_n4;
 
architecture sim of tb_tst_serloop2_n4 is
signal CLK100 : slbit := '0';
signal CLKS : slbit := '0';
signal CLKH : slbit := '0';
 
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
 
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
 
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100
);
 
GEN_CLKSYS : entity work.s7_cmt_sfs_tb
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => CLK100,
CLKFX => CLKH,
LOCKED => open
);
GEN_CLKSER : entity work.s7_cmt_sfs_tb
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clkser_gentype)
port map (
CLKIN => CLK100,
CLKFX => CLKS,
LOCKED => open
);
UUT : entity work.sys_tst_serloop2_n4
port map (
I_CLK100 => CLK100,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => '1',
O_LED => open,
O_RGBLED0 => open,
O_RGBLED1 => open,
O_ANO_N => open,
O_SEG_N => open
);
 
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLKS,
CLKH => CLKH,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => RTS_N,
P0_CTS_N => CTS_N,
P1_RXD => open, -- port 1 unused for n4 !
P1_TXD => '0',
P1_RTS_N => '0',
P1_CTS_N => open,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0)
);
 
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
RTS_N <= O_RTS_N after delay_time;
I_CTS_N <= CTS_N after delay_time;
 
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
 
end sim;
/trunk/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop2_n4_ssim.vbom
0,0 → 1,12
# libs
../../../../vlib/slvtypes.vhd
../../../../vlib/simlib/simlib.vhd
${sys_conf := sys_conf2_sim.vhd}
# components
../../../../vlib/simlib/simclk.vbom
../../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom
sys_tst_serloop2_n4_ssim.vhd -UUT
../../tb/tb_tst_serloop.vbom
# design
tb_tst_serloop2_n4.vhd
@top:tb_tst_serloop2_n4
/trunk/rtl/sys_gen/tst_serloop/nexys4/tb/tbrun.yml
0,0 → 1,16
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [default, viv, sys_tst_serloop1, n4]
test: |
tbrun_tbw tb_tst_serloop1_n4${ms}
 
- tag: [default, viv, sys_tst_serloop2, n4]
test: |
tbrun_tbw tb_tst_serloop2_n4${ms}
/trunk/rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom
1,4 → 1,4
# conf
# configure
sys_conf = sys_conf_sim.vhd
# libs
../../../../vlib/slvtypes.vhd
/trunk/rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vhd
1,6 → 1,6
-- $Id: tb_tst_serloop_s3.vhd 444 2011-12-25 10:04:58Z mueller $
-- $Id: tb_tst_serloop_s3.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
26,6 → 26,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2 remove CLK_STOP logic (simstop via report)
-- 2011-12-23 444 1.1 use new simclk
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-06 420 1.0 Initial version
47,7 → 48,6
architecture sim of tb_tst_serloop_s3 is
signal CLK50 : slbit := '0';
signal CLK_STOP : slbit := '0';
 
signal CLKS : slbit := '0';
71,9 → 71,9
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
 
82,8 → 82,7
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_STOP => CLK_STOP
CLK => CLK50
);
 
DCM_S : dcm_sfs
123,7 → 122,6
port map (
CLKS => CLKS,
CLKH => CLKS,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
/trunk/rtl/sys_gen/tst_serloop/s3board/tb/tbrun.yml
0,0 → 1,13
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-00-10 806 1.1 use nossim because no _ssim support available
# 2016-08-12 797 1.0 Initial version
#
- default:
mode: ${ise_modes_nossim}
#
- tag: [default, ise, sys_tst_serloop, s3]
test: |
tbrun_tbw tb_tst_serloop_s3${ms}
/trunk/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vbom
1,6 → 1,7
# libs
../../../vlib/slvtypes.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
../../../vlib/serport/tb/serportlib_tb.vhd
# components
../../../vlib/simlib/simclkcnt.vbom
/trunk/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd
1,4 → 1,4
-- $Id: tb_tst_serloop.vhd 764 2016-04-23 18:21:44Z mueller $
-- $Id: tb_tst_serloop.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
25,6 → 25,8
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2.2 remove CLK_STOP logic (simstop via report)
-- 2016-08-18 799 1.2.1 remove 'assert false' from report statements
-- 2016-04-23 764 1.2 use serport/tb/serport_(uart_rxtx|xontx)_tb
-- use assert to halt simulation
-- 2011-12-23 444 1.1 use new simclkcnt
40,6 → 42,7
 
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.serportlib_tb.all;
 
entity tb_tst_serloop is
46,7 → 49,6
port (
CLKS : in slbit; -- clock for serport
CLKH : in slbit; -- clock for humanio
CLK_STOP : out slbit; -- clock stop
P0_RXD : out slbit; -- port 0 receive data (board view)
P0_TXD : in slbit; -- port 0 transmit data (board view)
P0_RTS_N : in slbit; -- port 0 rts_n
62,7 → 64,6
 
architecture sim of tb_tst_serloop is
signal CLK_STOP_L : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal UART_RESET : slbit := '0';
441,26 → 442,19
testempty_ea(iline);
end loop; -- file_loop
 
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
 
-- extra wait for at least two character times (20 bit times)
-- to allow tx and rx of the last character
waitclk(20*(to_integer(unsigned(CLKDIV))+1));
 
CLK_STOP_L <= '1';
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
 
wait for 500 ns; -- allows dcm's to stop
SB_SIMSTOP <= '1'; -- signal simulation stop
wait for 100 ns; -- monitor grace time
report "Simulation Finished" severity failure; -- end simulation
 
assert false report "Simulation Finished" severity failure;
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
 
end process proc_stim;
 
CLK_STOP <= CLK_STOP_L;
proc_moni: process
variable oline : line;
variable dclk : integer := 0;
/trunk/rtl/sys_gen/tst_serloop/tbrun.yml
0,0 → 1,10
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-22 800 1.0 Initial version
#
- include: s3board/tb/tbrun.yml
- include: nexys2/tb/tbrun.yml
- include: nexys3/tb/tbrun.yml
- include: nexys4/tb/tbrun.yml
/trunk/rtl/sys_gen/tst_snhumanio/Makefile
0,0 → 1,37
# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-20 749 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#
/trunk/rtl/sys_gen/tst_sram/nexys2/.cvsignore
0,0 → 1,2
sys_tst_sram_n2.ucf
_impact*
/trunk/rtl/sys_gen/tst_sram/nexys2/Makefile
0,0 → 1,31
# $Id: Makefile 801 2016-08-27 16:47:01Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-26 801 1.2 use explicit VBOM_all, no wildcard
# 2011-08-13 405 1.1 use includes from rtl/make; use imp_s3_speed_maptd
# 2010-05-23 294 1.0 Initial version
#
VBOM_all = sys_tst_sram_n2.vbom
BIT_all = $(VBOM_all:.vbom=.bit)
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk
XFLOWOPT_IMP = imp_s3_speed_maptd.opt
#
.PHONY : all clean
#
all : sys_tst_sram_n2.bit
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#-----
#
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
endif
#
/trunk/rtl/sys_gen/tst_sram/nexys2/sys_conf.vbom
0,0 → 1,5
# libs
../../../vlib/slvtypes.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
# design
sys_conf.vhd
/trunk/rtl/sys_gen/tst_sram/nexys2/sys_conf.vhd
0,0 → 1,60
-- $Id: sys_conf.vhd 788 2016-07-16 22:23:23Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.2 use cram_*delay functions to determine delays
-- 2012-12-20 614 1.1.4 use 85 MHz (max after rlv4 update)
-- 2010-11-27 341 1.1.3 add sys_conf_clksys_mhz (clksys in MHz)
-- 2010-11-26 340 1.1.2 default now clksys=60 MHz
-- 2010-11-22 339 1.1.1 add memctl related constants
-- 2010-11-13 338 1.1 add dcm related constants
-- 2010-05-23 294 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.nxcramlib.all;
 
package sys_conf is
 
constant sys_conf_clkfx_divide : positive := 10;
constant sys_conf_clkfx_multiply : positive := 17;
 
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
 
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
 
end package sys_conf;
/trunk/rtl/sys_gen/tst_sram/nexys2/sys_tst_sram_n2.ucf_cpp
0,0 → 1,14
## $Id: sys_tst_sram_n2.ucf_cpp 336 2010-11-06 18:28:27Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
## 2010-05-23 294 1.0 Initial version
##
 
NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
 
#include "bplib/nexys2/nexys2_pins.ucf"
/trunk/rtl/sys_gen/tst_sram/nexys2/sys_tst_sram_n2.vbom
0,0 → 1,23
# libs
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/rbus/rblib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/s3board/s3boardlib.vbom
../../../bplib/nxcramlib/nxcramlib.vhd
${sys_conf := sys_conf.vbom}
# components
[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2line_iob.vbom
../../../bplib/bpgen/sn_humanio.vbom
../../../vlib/rlink/rlink_sp1c.vbom
../tst_sram.vbom
../../../bplib/nxcramlib/nx_cram_memctl_as.vbom
# design
sys_tst_sram_n2.vhd
@ucf_cpp: sys_tst_sram_n2.ucf
/trunk/rtl/sys_gen/tst_sram/nexys2/sys_tst_sram_n2.vhd
0,0 → 1,311
-- $Id: sys_tst_sram_n2.vhd 791 2016-07-21 22:01:10Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_sram_n2 - syn
-- Description: test of nexys2 sram and its controller
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2line_iob
-- bplib/bpgen/sn_humanio
-- vlib/rlink/rlink_sp1c
-- tst_sram
-- bplib/nxcramlib/nx_cram_memctl_as
--
-- Test bench: tb/tb_tst_sram_n2
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.29-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2014-12-20 614 14.7 131013 xc3s1200e-4 878 1881 96 1428 t 11.7 ns (85M)
-- 2014-08-13 581 14.7 131013 xc3s1200e-4 721 1515 64 1119 t 10.5 ns (95M)
-- 2011-12-21 442 13.1 O40d xc3s1200e-4 721 1510 64 1112 p 10.5 ns (95M)
-- 2010-12-31 352 12.1 M53d xc3s1200e-4 701 1426 36 901 p 10.5 ns (95M)
-- 2010-11-27 341 12.1 M53d xc3s1200e-4 674 1387 36 867 p 10.5 ns (95M)
-- 2010-11-06 336 12.1 M53d xc3s1200e-4 665 1388 36 864 p 18.9 ns
-- 2010-06-03 300 11.4 L68 xc3s1200e-4 667 1378 36 860 p 15.8 ns
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 659 1371 18 848 p 15.8 ns
-- 2010-05-24 294 11.4 L68 xc3s1200e-4 663 1358 18 841 p 15.8 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-10 785 1.5.1 SWI(1) now XON
-- 2016-07-09 784 1.5 tst_sram with AWIDTH and 22bit support
-- 2016-03-19 748 1.4.2 define rlink SYSID
-- 2015-04-11 666 1.4.1 rearrange XON handling
-- 2014-08-28 588 1.4 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit
-- 2011-12-23 444 1.2 remove clksys output hack
-- 2011-12-21 442 1.1.6 use rlink_sp1c
-- 2011-11-26 433 1.1.5 use nx_cram_memctl_as now
-- 2011-11-23 432 1.1.4 now numeric_std clean; update O_FLA_CE_N usage
-- 2011-11-17 426 1.1.3 use dcm_sfs now
-- 2011-07-08 390 1.1.2 use now sn_humanio
-- 2011-07-02 387 1.1.1 use bp_rs232_2line_iob now
-- 2010-12-31 352 1.1 port to rbv3
-- 2010-11-27 341 1.0.6 now proper clkdivce handling
-- 2010-11-22 339 1.0.5 use memctl delays from sys_conf constants
-- 2010-11-13 338 1.0.4 add DCM and O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.0.3 rename input pin CLK -> I_CLK50
-- 2010-10-23 335 1.0.2 rename RRI_LAM->RB_LAM;
-- 2010-06-03 300 1.0.1 use default FAWIDTH for rri_core_serport
-- 2010-05-23 294 1.0 Initial version (derived from sys_tst_sram_s3)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.s3boardlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
 
-- ----------------------------------------------------------------------------
 
entity sys_tst_sram_n2 is -- top level
-- implements nexys2_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit -- flash ce.. (act.low)
);
end sys_tst_sram_n2;
 
architecture syn of sys_tst_sram_n2 is
signal CLK : slbit := '0';
 
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
 
signal GBL_RESET : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
 
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
 
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
 
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
 
signal MEM_RESET : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACK_W : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv22 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
 
constant sysid_proj : slv16 := x"0104"; -- tst_sram
constant sysid_board : slv8 := x"02"; -- nexys2
constant sysid_vers : slv8 := x"00";
 
begin
 
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
 
IOB_RS232 : bp_rs232_2line_iob
port map (
CLK => CLK,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
 
HIO : sn_humanio
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
 
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6, -- 64 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => x"ffe8")
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => GBL_RESET,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
 
TST : entity work.tst_sram
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
AWIDTH => 22)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
MEM_RESET => MEM_RESET,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ACK_W => MEM_ACK_W,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
 
CRAMCTL : nx_cram_memctl_as
generic map (
READ0DELAY => sys_conf_memctl_read0delay, -- was 2 for 50 MHz
READ1DELAY => sys_conf_memctl_read1delay, -- was 2 "
WRITEDELAY => sys_conf_memctl_writedelay) -- was 3 "
port map (
CLK => CLK,
RESET => MEM_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => MEM_ACK_W,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
 
RB_SRES <= RB_SRES_TST; -- can be sres_or later...
RB_LAM(0) <= RB_LAM_TST;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
end syn;
 
/trunk/rtl/sys_gen/tst_sram/nexys2/tb/.cvsignore
0,0 → 1,2
tb_tst_sram_n2
sys_tst_sram_n2.ucf
/trunk/rtl/sys_gen/tst_sram/nexys2/tb/Makefile
0,0 → 1,33
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-23 294 1.0 Initial version
#
EXE_all = tb_tst_sram_n2
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean
rm -f sys_tst_sram_n2.ucf
#
#-----
#
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(wildcard *.o.dep_ghdl)
endif
#
/trunk/rtl/sys_gen/tst_sram/nexys2/tb/sys_conf_sim.vbom
0,0 → 1,5
# libs
../../../../vlib/slvtypes.vhd
../../../../bplib/nxcramlib/nxcramlib.vhd
# design
sys_conf_sim.vhd
/trunk/rtl/sys_gen/tst_sram/nexys2/tb/sys_conf_sim.vhd
0,0 → 1,55
-- $Id: sys_conf_sim.vhd 788 2016-07-16 22:23:23Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_* (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.2 use cram_*delay functions to determine delays
-- 2011-11-27 433 1.1.2 use /1*1 to skip dcm, _ssim fails with dcm
-- 2010-11-22 339 1.1.1 add memctl related constants; now clksys=60 MHz
-- 2010-11-13 338 1.1 add dcm related constants
-- 2010-05-25 294 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.nxcramlib.all;
 
package sys_conf is
 
constant sys_conf_clkfx_divide : positive := 1; -- skip dcm for sim !!
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
 
end package sys_conf;
/trunk/rtl/sys_gen/tst_sram/nexys2/tb/sys_tst_sram_n2.ucf_cpp
0,0 → 1,55
link ../sys_tst_sram_n2.ucf_cpp
trunk/rtl/sys_gen/tst_sram/nexys2/tb/sys_tst_sram_n2.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2.vbom (revision 37) @@ -0,0 +1,9 @@ +# configure tb_nexsy2 with sys_tst_sram_n2 target; +# use vhdl configure file (tb_tst_sram_n2.vhd) to allow +# that all configurations will co-exist in work library +# configure +nexys2_aif = ../sys_tst_sram_n2.vbom +sys_conf = sys_conf_sim.vbom +# design +../../../../bplib/nexys2/tb/tb_nexys2.vbom +tb_tst_sram_n2.vhd Index: trunk/rtl/sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2.vhd =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2.vhd (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2.vhd (revision 37) @@ -0,0 +1,39 @@ +-- $Id: tb_tst_sram_n2.vhd 437 2011-12-09 19:38:07Z mueller $ +-- +-- Copyright 2010- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_sram_n2 +-- Description: Configuration for tb_tst_sram_s2 for tb_nexys2 +-- +-- Dependencies: sys_tst_sram_n2 +-- +-- To test: sys_tst_sram_n2 +-- +-- Verified: +-- Date Rev Code ghdl ise Target Comment +-- 2010-05-24 294 - 0.26 11.4 L68 xc3s1200e u:ok +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-05-24 294 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_sram_n2 of tb_nexys2 is + + for sim + for all : nexys2_aif + use entity work.sys_tst_sram_n2; + end for; + end for; + +end tb_tst_sram_n2; Index: trunk/rtl/sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2_ssim.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2_ssim.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2_ssim.vbom (revision 37) @@ -0,0 +1,8 @@ +# configure for _*sim case +# Note: this tb uses sys_tst_sram_n2.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +# configure +nexys2_aif = sys_tst_sram_n2_ssim.vhd +# design +tb_tst_sram_n2.vbom +@top:tb_tst_sram_n2 Index: trunk/rtl/sys_gen/tst_sram/nexys2/tb/tbrun.yml =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys2/tb/tbrun.yml (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys2/tb/tbrun.yml (revision 37) @@ -0,0 +1,19 @@ +# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-08-28 803 1.1 use ${ise_modes_noisim} when ISim can't be used +# 2016-08-21 799 1.0 Initial version +# +- default: + mode: ${ise_modes_noisim} +# +- tag: [default, ise, sys_tst_sram, n2, base] + test: | + tbrun_tbwrri --lsuf base --pack tst_sram tb_tst_sram_n2${ms} \ + tst_sram::setup tst_sram::test_all + +- tag: [default, ise, sys_tst_sram, n2, stress] + test: | + tbrun_tbwrri --lsuf stress --pack tst_sram tb_tst_sram_n2${ms} \ + tst_sram::setup tst_sram::test_sim Index: trunk/rtl/sys_gen/tst_sram/nexys2/tb/tbw.dat =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys2/tb/tbw.dat (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys2/tb/tbw.dat (revision 37) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 352 2011-01-02 13:01:37Z mueller $ +# +[tb_tst_sram_n2] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: trunk/rtl/sys_gen/tst_sram/nexys2/tb =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys2/tb (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys2/tb (revision 37)
trunk/rtl/sys_gen/tst_sram/nexys2/tb Property changes : Added: svn:ignore ## -0,0 +1,44 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb +tb_tst_sram_n2 +sys_tst_sram_n2.ucf Index: trunk/rtl/sys_gen/tst_sram/nexys2 =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys2 (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys2 (revision 37)
trunk/rtl/sys_gen/tst_sram/nexys2 Property changes : Added: svn:ignore ## -0,0 +1,44 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb +sys_tst_sram_n2.ucf +_impact* Index: trunk/rtl/sys_gen/tst_sram/nexys3/.cvsignore =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/.cvsignore (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/.cvsignore (revision 37) @@ -0,0 +1 @@ +sys_tst_sram_n3.ucf Index: trunk/rtl/sys_gen/tst_sram/nexys3/Makefile =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/Makefile (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/Makefile (revision 37) @@ -0,0 +1,29 @@ +# $Id: Makefile 801 2016-08-27 16:47:01Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-08-26 801 1.1 use explicit VBOM_all, no wildcard +# 2011-11-27 433 1.0 Initial version +# +VBOM_all = sys_tst_sram_n3.vbom +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk +# +.PHONY : all clean +# +all : sys_tst_sram_n3.bit +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#----- +# +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: trunk/rtl/sys_gen/tst_sram/nexys3/sys_conf.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/sys_conf.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/sys_conf.vbom (revision 37) @@ -0,0 +1,5 @@ +# libs +../../../vlib/slvtypes.vhd +../../../bplib/nxcramlib/nxcramlib.vhd +# design +sys_conf.vhd Index: trunk/rtl/sys_gen/tst_sram/nexys3/sys_conf.vhd =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/sys_conf.vhd (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/sys_conf.vhd (revision 37) @@ -0,0 +1,59 @@ +-- $Id: sys_conf.vhd 788 2016-07-16 22:23:23Z mueller $ +-- +-- Copyright 2011-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_sram_n3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-07-10 786 1.2 memctl with page mode, new read1delay +-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect +-- 2011-11-27 433 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.nxcramlib.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "DCM"; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + + constant sys_conf_memctl_read0delay : positive := + cram_read0delay(sys_conf_clksys_mhz); + constant sys_conf_memctl_read1delay : positive := + cram_read1delay(sys_conf_clksys_mhz); + constant sys_conf_memctl_writedelay : positive := + cram_writedelay(sys_conf_clksys_mhz); + +end package sys_conf; Index: trunk/rtl/sys_gen/tst_sram/nexys3/sys_tst_sram_n3.ucf_cpp =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/sys_tst_sram_n3.ucf_cpp (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/sys_tst_sram_n3.ucf_cpp (revision 37) @@ -0,0 +1,20 @@ +## $Id: sys_tst_sram_n3.ucf_cpp 435 2011-12-04 20:15:25Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-12-03 435 1.1 use also pmb0_rs232 +## 2011-11-27 433 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## std board +## +#include "bplib/nexys3/nexys3_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf" Index: trunk/rtl/sys_gen/tst_sram/nexys3/sys_tst_sram_n3.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/sys_tst_sram_n3.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/sys_tst_sram_n3.vbom (revision 37) @@ -0,0 +1,23 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/s3board/s3boardlib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +${sys_conf := sys_conf.vbom} +# components +[xst,vsyn]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../tst_sram.vbom +../../../bplib/nxcramlib/nx_cram_memctl_as.vbom +# design +sys_tst_sram_n3.vhd +@ucf_cpp: sys_tst_sram_n3.ucf Index: trunk/rtl/sys_gen/tst_sram/nexys3/sys_tst_sram_n3.vhd =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/sys_tst_sram_n3.vhd (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/sys_tst_sram_n3.vhd (revision 37) @@ -0,0 +1,315 @@ +-- $Id: sys_tst_sram_n3.vhd 791 2016-07-21 22:01:10Z mueller $ +-- +-- Copyright 2011-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_sram_n3 - syn +-- Description: test of nexys3 sram and its controller +-- +-- Dependencies: vlib/xlib/s6_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2l4l_iob +-- bplib/bpgen/sn_humanio +-- vlib/rlink/rlink_sp1c +-- tst_sram +-- bplib/nxcramlib/nx_cram_memctl_as +-- +-- Test bench: tb/tb_tst_sram_n3 +-- +-- Target Devices: generic +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2014-12-20 614 14.7 131013 xc6slx16-2 922 1574 48 574 t 9.6 ns +-- 2014-08-13 581 14.7 131013 xc6slx16-2 765 1261 32 441 t 9.6 ns +-- 2011-12-21 442 13.4 O40d xc6slx16-2 722 1367 32 506 t 9.6 ns +-- 2011-11-27 433 13.4 O40d xc6slx16-2 699 1194 20 406 t 8.9 ns +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-07-10 785 1.5.1 SWI(1) now XON; SWI(0) now portsel +-- 2016-07-09 784 1.5 tst_sram with AWIDTH and 22bit support +-- 2016-03-19 748 1.4.2 define rlink SYSID +-- 2015-04-11 666 1.4.1 rearrange XON handling +-- 2014-08-28 588 1.4 use new rlink v4 iface and 4 bit STAT +-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit +-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect +-- 2011-12-21 442 1.1.1 use rlink_sp1c +-- 2011-12-03 435 1.1 use int&ext serport and bp_rs232_2l4l_iob +-- 2011-11-27 433 1.0 Initial version (derived from sys_tst_sram_n2) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.s3boardlib.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_sram_n3 is -- top level + -- implements nexys3_fusp_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit; -- ppcm: ... + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_sram_n3; + +architecture syn of sys_tst_sram_n3 is + + signal CLK : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal GBL_RESET : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + signal RB_LAM_TST : slbit := '0'; + + signal MEM_RESET : slbit := '0'; + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACK_W : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv22 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + constant sysid_proj : slv16 := x"0104"; -- tst_sram + constant sysid_board : slv8 := x"03"; -- nexys3 + constant sysid_vers : slv8 := x"00"; + +begin + + GEN_CLKSYS : s6_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, -- good for up to 127 MHz ! + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + HIO : sn_humanio + generic map ( + BWIDTH => 5) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp1c + generic map ( + BTOWIDTH => 6, -- 64 cycles access timeout + RTAWIDTH => 12, + SYSID => sysid_proj & sysid_board & sysid_vers, + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => 0, + RBMON_RBADDR => x"ffe8") + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => GBL_RESET, + ENAXON => SWI(1), + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + TST : entity work.tst_sram + generic map ( + RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)), + AWIDTH => 22) + port map ( + CLK => CLK, + RESET => GBL_RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_STAT => RB_STAT, + RB_LAM => RB_LAM_TST, + SWI => SWI, + BTN => BTN(3 downto 0), + LED => LED, + DSP_DAT => DSP_DAT, + MEM_RESET => MEM_RESET, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ACK_W => MEM_ACK_W, + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO + ); + + CRAMCTL : nx_cram_memctl_as + generic map ( + READ0DELAY => sys_conf_memctl_read0delay, -- was 2 for 50 MHz + READ1DELAY => sys_conf_memctl_read1delay, -- was 2 " + WRITEDELAY => sys_conf_memctl_writedelay) -- was 3 " + port map ( + CLK => CLK, + RESET => MEM_RESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => MEM_ACK_W, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled + O_PPCM_RST_N <= '1'; -- + + RB_SRES <= RB_SRES_TST; -- can be sres_or later... + RB_LAM(0) <= RB_LAM_TST; + + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + +end syn; + Index: trunk/rtl/sys_gen/tst_sram/nexys3/tb/.cvsignore =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/tb/.cvsignore (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/tb/.cvsignore (revision 37) @@ -0,0 +1,2 @@ +tb_tst_sram_n3 +sys_tst_sram_n3.ucf Index: trunk/rtl/sys_gen/tst_sram/nexys3/tb/Makefile =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/tb/Makefile (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/tb/Makefile (revision 37) @@ -0,0 +1,32 @@ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-27 433 1.0 Initial version +# +EXE_all = tb_tst_sram_n3 +# +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean + rm -f sys_tst_sram_n3.ucf +# +#----- +# +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: trunk/rtl/sys_gen/tst_sram/nexys3/tb/sys_conf_sim.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/tb/sys_conf_sim.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/tb/sys_conf_sim.vbom (revision 37) @@ -0,0 +1,5 @@ +# libs +../../../../vlib/slvtypes.vhd +../../../../bplib/nxcramlib/nxcramlib.vhd +# design +sys_conf_sim.vhd Index: trunk/rtl/sys_gen/tst_sram/nexys3/tb/sys_conf_sim.vhd =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/tb/sys_conf_sim.vhd (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/tb/sys_conf_sim.vhd (revision 37) @@ -0,0 +1,56 @@ +-- $Id: sys_conf_sim.vhd 788 2016-07-16 22:23:23Z mueller $ +-- +-- Copyright 2011-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_sram_n3 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-07-16 788 1.2 use cram_*delay functions to determine delays +-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect +-- 2011-11-27 433 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.nxcramlib.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "DCM"; + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_memctl_read0delay : positive := + cram_read0delay(sys_conf_clksys_mhz); + constant sys_conf_memctl_read1delay : positive := + cram_read1delay(sys_conf_clksys_mhz); + constant sys_conf_memctl_writedelay : positive := + cram_writedelay(sys_conf_clksys_mhz); + +end package sys_conf; Index: trunk/rtl/sys_gen/tst_sram/nexys3/tb/sys_tst_sram_n3.ucf_cpp =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/tb/sys_tst_sram_n3.ucf_cpp (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/tb/sys_tst_sram_n3.ucf_cpp (revision 37) @@ -0,0 +1 @@ +link ../sys_tst_sram_n3.ucf_cpp \ No newline at end of file
trunk/rtl/sys_gen/tst_sram/nexys3/tb/sys_tst_sram_n3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/sys_gen/tst_sram/nexys3/tb/tb_tst_sram_n3.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/tb/tb_tst_sram_n3.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/tb/tb_tst_sram_n3.vbom (revision 37) @@ -0,0 +1,9 @@ +# configure tb_nexsy3_fusp with sys_tst_sram_n3 target; +# use vhdl configure file (tb_tst_sram_n3.vhd) to allow +# that all configurations will co-exist in work library +# configure +nexys3_fusp_aif = ../sys_tst_sram_n3.vbom +sys_conf = sys_conf_sim.vbom +# design +../../../../bplib/nexys3/tb/tb_nexys3_fusp.vbom +tb_tst_sram_n3.vhd Index: trunk/rtl/sys_gen/tst_sram/nexys3/tb/tb_tst_sram_n3.vhd =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/tb/tb_tst_sram_n3.vhd (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/tb/tb_tst_sram_n3.vhd (revision 37) @@ -0,0 +1,40 @@ +-- $Id: tb_tst_sram_n3.vhd 435 2011-12-04 20:15:25Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_sram_n3 +-- Description: Configuration for tb_tst_sram_n3 for tb_nexys3_fusp +-- +-- Dependencies: sys_tst_sram_n3 +-- +-- To test: sys_tst_sram_n3 +-- +-- Verified: +-- Date Rev Code ghdl ise Target Comment +-- 2011-11-27 433 - 0.29 13.1 O40d xc6slx16 ??? +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-03 435 1.1 use tb_nexys3_fusp +-- 2011-11-27 433 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_sram_n3 of tb_nexys3_fusp is + + for sim + for all : nexys3_fusp_aif + use entity work.sys_tst_sram_n3; + end for; + end for; + +end tb_tst_sram_n3; Index: trunk/rtl/sys_gen/tst_sram/nexys3/tb/tb_tst_sram_n3_ssim.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/tb/tb_tst_sram_n3_ssim.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/tb/tb_tst_sram_n3_ssim.vbom (revision 37) @@ -0,0 +1,8 @@ +# configure for _*sim case +# Note: this tb uses sys_tst_sram_n3.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +# configure +nexys3_fusp_aif = sys_tst_sram_n3_ssim.vhd +# design +tb_tst_sram_n3.vbom +@top:tb_tst_sram_n3 Index: trunk/rtl/sys_gen/tst_sram/nexys3/tb/tbrun.yml =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/tb/tbrun.yml (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/tb/tbrun.yml (revision 37) @@ -0,0 +1,19 @@ +# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-08-28 803 1.1 use ${ise_modes_noisim} when ISim can't be used +# 2016-08-21 799 1.0 Initial version +# +- default: + mode: ${ise_modes_noisim} +# +- tag: [default, ise, sys_tst_sram, n3, base] + test: | + tbrun_tbwrri --lsuf base --pack tst_sram tb_tst_sram_n3${ms} \ + tst_sram::setup tst_sram::test_all + +- tag: [default, ise, sys_tst_sram, n3, stress] + test: | + tbrun_tbwrri --lsuf stress --pack tst_sram tb_tst_sram_n3${ms} \ + tst_sram::setup tst_sram::test_sim Index: trunk/rtl/sys_gen/tst_sram/nexys3/tb/tbw.dat =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/tb/tbw.dat (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/tb/tbw.dat (revision 37) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 433 2011-11-27 22:04:39Z mueller $ +# +[tb_tst_sram_n3] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: trunk/rtl/sys_gen/tst_sram/nexys3/tb =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3/tb (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3/tb (revision 37)
trunk/rtl/sys_gen/tst_sram/nexys3/tb Property changes : Added: svn:ignore ## -0,0 +1,44 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb +tb_tst_sram_n3 +sys_tst_sram_n3.ucf Index: trunk/rtl/sys_gen/tst_sram/nexys3 =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys3 (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys3 (revision 37)
trunk/rtl/sys_gen/tst_sram/nexys3 Property changes : Added: svn:ignore ## -0,0 +1,43 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb +sys_tst_sram_n3.ucf Index: trunk/rtl/sys_gen/tst_sram/nexys4/.cvsignore =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/.cvsignore (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/.cvsignore (revision 37) @@ -0,0 +1 @@ +sys_tst_sram_n4.ucf Index: trunk/rtl/sys_gen/tst_sram/nexys4/Makefile =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/Makefile (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/Makefile (revision 37) @@ -0,0 +1,26 @@ +# $Id: Makefile 801 2016-08-27 16:47:01Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-08-26 801 1.1 use explicit VBOM_all, no wildcard +# 2015-01-25 639 1.0 Initial version +# +VBOM_all = sys_tst_sram_n4.vbom +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# Index: trunk/rtl/sys_gen/tst_sram/nexys4/Makefile.ise =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/Makefile.ise (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/Makefile.ise (revision 37) @@ -0,0 +1,29 @@ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-09-21 534 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys4.mk +# +.PHONY : all clean +# +all : sys_tst_sram_n4.bit +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#----- +# +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: trunk/rtl/sys_gen/tst_sram/nexys4/sys_conf.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/sys_conf.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/sys_conf.vbom (revision 37) @@ -0,0 +1,5 @@ +# libs +../../../vlib/slvtypes.vhd +../../../bplib/nxcramlib/nxcramlib.vhd +# design +sys_conf.vhd Index: trunk/rtl/sys_gen/tst_sram/nexys4/sys_conf.vhd =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/sys_conf.vhd (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/sys_conf.vhd (revision 37) @@ -0,0 +1,70 @@ +-- $Id: sys_conf.vhd 788 2016-07-16 22:23:23Z mueller $ +-- +-- Copyright 2013-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_sram_n4 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-07-16 788 1.2 use cram_*delay functions to determine delays +-- 2016-06-18 775 1.1.1 use PLL for clkser_gentype +-- 2016-03-29 756 1.1 use serport_2clock2 -> define clkser +-- 2013-09-21 534 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.nxcramlib.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; + + constant sys_conf_memctl_read0delay : positive := + cram_read0delay(sys_conf_clksys_mhz); + constant sys_conf_memctl_read1delay : positive := + cram_read1delay(sys_conf_clksys_mhz); + constant sys_conf_memctl_writedelay : positive := + cram_writedelay(sys_conf_clksys_mhz); + +end package sys_conf; Index: trunk/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.ucf_cpp =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.ucf_cpp (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.ucf_cpp (revision 37) @@ -0,0 +1,16 @@ +## $Id: sys_tst_sram_n4.ucf_cpp 643 2015-02-07 17:41:53Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-09-21 534 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## std board +## +#include "bplib/nexys4/nexys4_pins.ucf" +#include "bplib/nexys4/nexys4_pins_cram.ucf" Index: trunk/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vbom (revision 37) @@ -0,0 +1,29 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/s3board/s3boardlib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +${sys_conf := sys_conf.vbom} +# components +[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_4line_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../../../vlib/rlink/rlink_sp2c.vbom +../tst_sram.vbom +../../../bplib/nxcramlib/nx_cram_memctl_as.vbom +../../../vlib/rbus/rbd_usracc.vbom +../../../vlib/rbus/rb_sres_or_4.vbom +# design +sys_tst_sram_n4.vhd +@ucf_cpp: sys_tst_sram_n4.ucf +@xdc:../../../bplib/nexys4/nexys4_pclk.xdc +@xdc:../../../bplib/nexys4/nexys4_pins.xdc +@xdc:../../../bplib/nexys4/nexys4_pins_cram.xdc Index: trunk/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vhd =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vhd (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vhd (revision 37) @@ -0,0 +1,366 @@ +-- $Id: sys_tst_sram_n4.vhd 791 2016-07-21 22:01:10Z mueller $ +-- +-- Copyright 2013-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_sram_n4 - syn +-- Description: test of nexys4 sram and its controller +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_4line_iob +-- bplib/bpgen/sn_humanio +-- vlib/rlink/rlink_sp2c +-- tst_sram +-- bplib/nxcramlib/nx_cram_memctl_as +-- vlib/rbus/rbd_usracc +-- vlib/rbus/rb_sres_or_2 +-- +-- Test bench: tb/tb_tst_sram_n4 +-- +-- Target Devices: generic +-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2016-03-29 756 2015.4 xc7a100t-1 918 1207 24 5 428 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-07-10 785 1.5.1 SWI(1) now XON +-- 2016-07-09 784 1.5 tst_sram with AWIDTH and 22bit support +-- 2016-04-02 758 1.4.1 add rbd_usracc (bitfile+jtag timestamp access) +-- 2016-03-28 755 1.4 use serport_2clock2 +-- 2016-03-19 748 1.3.3 define rlink SYSID +-- 2015-04-11 666 1.3.2 rearrange XON handling +-- 2015-02-01 641 1.3.1 separate I_BTNRST_N +-- 2015-01-31 640 1.3 drop fusp iface; use new sn_hio +-- 2014-08-28 588 1.2 use new rlink v4 ifaceand 4 bit STAT +-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit +-- 2013-09-28 535 1.0.1 use proper clock manager +-- 2013-09-21 534 1.0 Initial version (derived from sys_tst_sram_n3) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rbdlib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.s3boardlib.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_sram_n4 is -- top level + -- implements nexys4_cram_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4 switches + I_BTN : in slv5; -- n4 buttons + I_BTNRST_N : in slbit; -- n4 reset button + O_LED : out slv16; -- n4 leds + O_RGBLED0 : out slv3; -- n4 rgb-led 0 + O_RGBLED1 : out slv3; -- n4 rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end sys_tst_sram_n4; + +architecture syn of sys_tst_sram_n4 is + + signal CLK : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CES_MSEC : slbit := '0'; + + signal GBL_RESET : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv32 := (others=>'0'); + signal DSP_DP : slv8 := (others=>'0'); + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; + + signal RB_LAM_TST : slbit := '0'; + + signal MEM_RESET : slbit := '0'; + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACK_W : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv22 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + constant sysid_proj : slv16 := x"0104"; -- tst_sram + constant sysid_board : slv8 := x"05"; -- nexys4 + constant sysid_vers : slv8 := x"00"; + +begin + + GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- + generic map ( + CDUWIDTH => 7, -- good for up to 127 MHz ! + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clkser_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLKS, + LOCKED => open + ); + + CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clkser_mhz, + MSECDIV => 1000) + port map ( + CLK => CLKS, + CE_USEC => open, + CE_MSEC => CES_MSEC + ); + + IOB_RS232 : bp_rs232_4line_iob + port map ( + CLK => CLKS, + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_CTS_N => I_CTS_N, + O_RTS_N => O_RTS_N + ); + + HIO : sn_humanio + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 3) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp2c + generic map ( + BTOWIDTH => 6, -- 64 cycles access timeout + RTAWIDTH => 12, + SYSID => sysid_proj & sysid_board & sysid_vers, + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 12, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => 0, + RBMON_RBADDR => x"ffe8") + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => GBL_RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, + ENAXON => SWI(1), + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + TST : entity work.tst_sram + generic map ( + RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)), + AWIDTH => 22) + port map ( + CLK => CLK, + RESET => GBL_RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_STAT => RB_STAT, + RB_LAM => RB_LAM_TST, + SWI => SWI(7 downto 0), + BTN => BTN(3 downto 0), + LED => LED(7 downto 0), + DSP_DAT => DSP_DAT(15 downto 0), + MEM_RESET => MEM_RESET, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ACK_W => MEM_ACK_W, + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO + ); + + CRAMCTL : nx_cram_memctl_as + generic map ( + READ0DELAY => sys_conf_memctl_read0delay, + READ1DELAY => sys_conf_memctl_read1delay, + WRITEDELAY => sys_conf_memctl_writedelay) + port map ( + CLK => CLK, + RESET => MEM_RESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => MEM_ACK_W, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + + RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_TST, + RB_SRES_2 => RB_SRES_USRACC, + RB_SRES_OR => RB_SRES + ); + + RB_LAM(0) <= RB_LAM_TST; + + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + + DSP_DP(7 downto 4) <= "0010"; + DSP_DAT(31 downto 16) <= SER_MONI.abclkdiv(11 downto 0) & + '0' & SER_MONI.abclkdiv_f; + + -- setup unused outputs in nexys4 + O_RGBLED0 <= (others=>'0'); + O_RGBLED1 <= (others=>not I_BTNRST_N); + +end syn; + Index: trunk/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vmfset =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vmfset (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vmfset (revision 37) @@ -0,0 +1,45 @@ +# $Id: sys_tst_sram_n4.vmfset 785 2016-07-10 12:22:41Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# false_path -hold ignored by synth ---------------------------- +I [Designutils 20-1567] # generic + +# port driven by constant -------------------------------------- +i [Synth 8-3917] O_RGBLED0[\d] # OK 2016-06-05 + +# tying undriven pin to constant ------------------------------- +# upper 8 LEDs unused # OK 2016-06-05 +i [Synth 8-3295] HIO:LED[\d*] +# only few LAMs used # OK 2016-06-05 +i [Synth 8-3295] RLINK:RB_LAM[\d*] + +# unconnected ports -------------------------------------------- +I [Synth 8-3331] RB_MREQ # generic +# --> I_MEM_WAIT not used by current nx_cram_memctl_as # OK 2016-06-05 +i [Synth 8-3331] nx_cram_memctl_as.*I_MEM_WAIT +# --> MEM_ACK_W not used by current tst_sram # OK 2016-06-05 +i [Synth 8-3331] tst_sram.*MEM_ACK_W +# --> rlink_sp2c doesn't use CE_USEC and CE_MSEC # OK 2016-06-05 +i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC) + +# unused sequential element ------------------------------------ +I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic +# --> many HIO pins not used # OK 2016-06-05 +i [Synth 8-3332] HIO/IOB_LED/R_DO_reg[\d*] +i [Synth 8-3332] HIO/IOB_(SWI|BTN)/R_DI_reg[\d*] +i [Synth 8-3332] HIO/DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange)][\d*] +# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05 +i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop] +i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn] +# --> only RB_STAT 0,1 used by tst_sram # OK 2016-06-05 +i [Synth 8-3332] RLINK/CORE/RL/R_BREGS_reg[stat][(2|3)] +# --> CE_USEC isn't used (also not in rlink_sp2c) # OK 2016-06-05 +i [Synth 8-3332] CLKDIV_CLK/R_REGS_reg[usec] +# --> CES_USEC isn't used # OK 2016-06-05 +i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec] + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization Index: trunk/rtl/sys_gen/tst_sram/nexys4/tb/.cvsignore =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/tb/.cvsignore (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/tb/.cvsignore (revision 37) @@ -0,0 +1,2 @@ +tb_tst_sram_n4 +sys_tst_sram_n4.ucf Index: trunk/rtl/sys_gen/tst_sram/nexys4/tb/Makefile =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/tb/Makefile (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/tb/Makefile (revision 37) @@ -0,0 +1,42 @@ +# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-06-18 776 1.1.1 add xsim_clean +# 2016-04-22 763 1.1 add include dep_vsim +# 2016-02-07 729 1.0.1 add generic_xsim.mk +# 2015-02-21 649 1.0 Initial version +# +EXE_all = tb_tst_sram_n4 +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +include $(wildcard *.o.dep_ghdl) +endif +# Index: trunk/rtl/sys_gen/tst_sram/nexys4/tb/Makefile.ise =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/tb/Makefile.ise (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/tb/Makefile.ise (revision 37) @@ -0,0 +1,33 @@ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-09-21 534 1.0 Initial version +# +EXE_all = tb_tst_sram_n4 +# +include ${RETROBASE}/rtl/make_ise/xflow_default_nexys4.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean + rm -f sys_tst_sram_n4.ucf +# +#----- +# +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: trunk/rtl/sys_gen/tst_sram/nexys4/tb/sys_conf_sim.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/tb/sys_conf_sim.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/tb/sys_conf_sim.vbom (revision 37) @@ -0,0 +1,5 @@ +# libs +../../../../vlib/slvtypes.vhd +../../../../bplib/nxcramlib/nxcramlib.vhd +# design +sys_conf_sim.vhd Index: trunk/rtl/sys_gen/tst_sram/nexys4/tb/sys_conf_sim.vhd =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/tb/sys_conf_sim.vhd (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/tb/sys_conf_sim.vhd (revision 37) @@ -0,0 +1,68 @@ +-- $Id: sys_conf_sim.vhd 788 2016-07-16 22:23:23Z mueller $ +-- +-- Copyright 2013-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_sram_n4 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-07-16 788 1.3 use cram_*delay functions to determine delays +-- 2016-07-10 786 1.2 memctl with page mode, new read1delay +-- 2016-06-18 775 1.1.1 use PLL for clkser_gentype +-- 2016-03-29 756 1.1 use serport_2clock2 -> define clkser +-- 2013-09-21 534 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.nxcramlib.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_memctl_read0delay : positive := + cram_read0delay(sys_conf_clksys_mhz); + constant sys_conf_memctl_read1delay : positive := + cram_read1delay(sys_conf_clksys_mhz); + constant sys_conf_memctl_writedelay : positive := + cram_writedelay(sys_conf_clksys_mhz); + +end package sys_conf; Index: trunk/rtl/sys_gen/tst_sram/nexys4/tb/sys_tst_sram_n4.ucf_cpp =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/tb/sys_tst_sram_n4.ucf_cpp (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/tb/sys_tst_sram_n4.ucf_cpp (revision 37) @@ -0,0 +1 @@ +link ../sys_tst_sram_n4.ucf_cpp \ No newline at end of file
trunk/rtl/sys_gen/tst_sram/nexys4/tb/sys_tst_sram_n4.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/sys_gen/tst_sram/nexys4/tb/tb_tst_sram_n4.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/tb/tb_tst_sram_n4.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/tb/tb_tst_sram_n4.vbom (revision 37) @@ -0,0 +1,9 @@ +# configure tb_nexsy4_cram with sys_tst_sram_n4 target; +# use vhdl configure file (tb_tst_sram_n4.vhd) to allow +# that all configurations will co-exist in work library +# configure +nexys4_cram_aif = ../sys_tst_sram_n4.vbom +sys_conf = sys_conf_sim.vbom +# design +../../../../bplib/nexys4/tb/tb_nexys4_cram.vbom +tb_tst_sram_n4.vhd Index: trunk/rtl/sys_gen/tst_sram/nexys4/tb/tb_tst_sram_n4.vhd =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/tb/tb_tst_sram_n4.vhd (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/tb/tb_tst_sram_n4.vhd (revision 37) @@ -0,0 +1,40 @@ +-- $Id: tb_tst_sram_n4.vhd 643 2015-02-07 17:41:53Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_sram_n4 +-- Description: Configuration for tb_tst_sram_n4 for tb_nexys4_fusp +-- +-- Dependencies: sys_tst_sram_n4 +-- +-- To test: sys_tst_sram_n4 +-- +-- Verified: +-- Date Rev Code ghdl ise Target Comment +-- 2013-??-?? 534 - 0.29 13.1 O40d xc6slx16 ??? +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-06 643 1.1 use tb_nexys4_cram now +-- 2013-09-21 534 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_sram_n4 of tb_nexys4_cram is + + for sim + for all : nexys4_cram_aif + use entity work.sys_tst_sram_n4; + end for; + end for; + +end tb_tst_sram_n4; Index: trunk/rtl/sys_gen/tst_sram/nexys4/tb/tb_tst_sram_n4_ssim.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/tb/tb_tst_sram_n4_ssim.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/tb/tb_tst_sram_n4_ssim.vbom (revision 37) @@ -0,0 +1,8 @@ +# configure for _*sim case +# Note: this tb uses sys_tst_sram_n4.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +# configure +nexys4_cram_aif = sys_tst_sram_n4_ssim.vhd +# design +tb_tst_sram_n4.vbom +@top:tb_tst_sram_n4 Index: trunk/rtl/sys_gen/tst_sram/nexys4/tb/tbrun.yml =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/tb/tbrun.yml (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/tb/tbrun.yml (revision 37) @@ -0,0 +1,18 @@ +# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-08-21 799 1.0 Initial version +# +- default: + mode: ${viv_modes} +# +- tag: [default, viv, sys_tst_sram, n4, base] + test: | + tbrun_tbwrri --lsuf base --pack tst_sram tb_tst_sram_n4${ms} \ + tst_sram::setup tst_sram::test_all + +- tag: [default, viv, sys_tst_sram, n4, stress] + test: | + tbrun_tbwrri --lsuf stress --pack tst_sram tb_tst_sram_n4${ms} \ + tst_sram::setup tst_sram::test_sim Index: trunk/rtl/sys_gen/tst_sram/nexys4/tb/tbw.dat =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/tb/tbw.dat (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/tb/tbw.dat (revision 37) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 534 2013-09-22 21:37:24Z mueller $ +# +[tb_tst_sram_n4] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: trunk/rtl/sys_gen/tst_sram/nexys4/tb =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4/tb (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4/tb (revision 37)
trunk/rtl/sys_gen/tst_sram/nexys4/tb Property changes : Added: svn:ignore ## -0,0 +1,44 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb +tb_tst_sram_n4 +sys_tst_sram_n4.ucf Index: trunk/rtl/sys_gen/tst_sram/nexys4 =================================================================== --- trunk/rtl/sys_gen/tst_sram/nexys4 (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/nexys4 (revision 37)
trunk/rtl/sys_gen/tst_sram/nexys4 Property changes : Added: svn:ignore ## -0,0 +1,43 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb +sys_tst_sram_n4.ucf Index: trunk/rtl/sys_gen/tst_sram/s3board/.cvsignore =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/.cvsignore (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/.cvsignore (revision 37) @@ -0,0 +1,3 @@ +sys_tst_sram_s3.ucf +sys_tst_sram_simple.ucf +sys_tst_sram_basics.ucf Index: trunk/rtl/sys_gen/tst_sram/s3board/Makefile =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/Makefile (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/Makefile (revision 37) @@ -0,0 +1,35 @@ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.4 use includes from rtl/make +# 2010-05-23 294 1.3.1 rename sys_tst_sram -> sys_tst_sram_s3 +# 2010-04-24 282 1.3 use %.impact rule, all=BIT_all now +# 2010-04-17 281 1.2 targeted to sys_tst_sram +# 2007-12-20 103 1.1.2 clean rm's generated ucf files +# 2007-12-09 100 1.1.1 set ISE_PATH +# 2007-11-19 98 1.1 use auto dep +# 2007-11-19 96 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk +# +.PHONY : all clean +# +all : sys_tst_sram_s3.bit +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#----- +# +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: trunk/rtl/sys_gen/tst_sram/s3board/sys_conf.vhd =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/sys_conf.vhd (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/sys_conf.vhd (revision 37) @@ -0,0 +1,34 @@ +-- $Id: sys_conf.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_* (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Revision History: +-- Date Rev Version Comment +-- 2007-11-18 96 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_ser2rri_cdinit : integer := 434-1; -- 50000000/115200 + +end package sys_conf; Index: trunk/rtl/sys_gen/tst_sram/s3board/sys_tst_sram_s3.ucf_cpp =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/sys_tst_sram_s3.ucf_cpp (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/sys_tst_sram_s3.ucf_cpp (revision 37) @@ -0,0 +1,14 @@ +## $Id: sys_tst_sram_s3.ucf_cpp 336 2010-11-06 18:28:27Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50 +## 2007-12-20 103 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +#include "bplib/s3board/s3board_pins.ucf" Index: trunk/rtl/sys_gen/tst_sram/s3board/sys_tst_sram_s3.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/sys_tst_sram_s3.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/sys_tst_sram_s3.vbom (revision 37) @@ -0,0 +1,19 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/s3board/s3boardlib.vbom +${sys_conf := sys_conf.vhd} +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2line_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../tst_sram.vbom +../../../bplib/s3board/s3_sram_memctl.vbom +# design +sys_tst_sram_s3.vhd +@ucf_cpp: sys_tst_sram_s3.ucf Index: trunk/rtl/sys_gen/tst_sram/s3board/sys_tst_sram_s3.vhd =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/sys_tst_sram_s3.vhd (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/sys_tst_sram_s3.vhd (revision 37) @@ -0,0 +1,297 @@ +-- $Id: sys_tst_sram_s3.vhd 791 2016-07-21 22:01:10Z mueller $ +-- +-- Copyright 2007-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_sram_s3 - syn +-- Description: test of s3board sram and its controller +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2line_iob +-- bplib/bpgen/sn_humanio +-- vlib/rlink/rlink_sp1c +-- tst_sram +-- bplib/s3board/s3_sram_memctl +-- +-- Test bench: tb/tb_tst_sram_s3 +-- +-- Target Devices: generic +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.33 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2014-12-20 614 14.7 131013 xc3s1000-4 816 1801 96 1135 t 18.3 ns +-- 2014-08-13 581 14.7 131013 xc3s1000-4 664 1433 64 899 t 16.3 ns +-- 2011-12-21 352 12.1 M53d xc3s1000-4 664 1433 64 898 p 17.1 ns +-- 2010-12-31 352 12.1 M53d xc3s200-4 644 1366 36 856 p 14.6 ns +-- 2010-11-06 336 12.1 M53d xc3s200-4 605 1334 36 824 p 14.6 ns +-- 2010-05-21 291 11.4 L68 xc3s200-4 600 1301 18 795 p 16.6 ns +-- 2010-05-16 291 11.4 L68 xc3s200-4 594 1273 18 764 p 15.3 ns +-- 2010-04-04 274 11.4 L68 xc3s200-4 607 1303 18 807 p 14.2 ns +-- 2009-11-14 249 11.2 L46 xc3s1000-4 603 1340 18 795 p 18.8 ns +-- 2009-11-08 248 11.2 L46 xc3s1000-4 594 1329 18 771 p 15.4 ns +-- 2009-11-08 248 8.2.3 I34 xc3s1000-4 616 1320 18 805 p 16.3 ns +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-07-10 785 2.3.4 SWI(1) now XON +-- 2016-07-09 784 2.3.3 tst_sram with AWIDTH and 22bit support +-- 2016-03-19 748 2.3.2 define rlink SYSID +-- 2015-04-11 666 2.3.1 rearrange XON handling +-- 2014-08-28 588 2.3 use new rlink v4 iface and 4 bit STAT +-- 2014-08-15 583 2.2 rb_mreq addr now 16 bit +-- 2011-12-21 442 2.1.4 use rlink_sp1c +-- 2011-11-21 432 2.1.3 now numeric_std clean +-- 2011-07-08 390 2.1.2 use now sn_humanio +-- 2011-07-02 387 2.1.1 use bp_rs232_2line_iob now +-- 2010-12-31 352 2.1 port to rbv3 +-- 2010-11-06 336 2.0.5 rename input pin CLK -> I_CLK50 +-- 2010-10-23 335 2.0.4 rename RRI_LAM->RB_LAM; +-- 2010-06-03 300 2.0.3 use default FAWIDTH for rri_core_serport +-- 2010-05-32 294 2.0.2 rename sys_tst_sram -> sys_tst_sram_s3 +-- 2010-05-21 292 2.0.1 move memory controler to top level entity +-- 2010-05-16 291 2.0 move tester code to tst_sram; use s3_rs232_iob_int +-- 2010-05-02 287 1.1.6 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM +-- drop RP_IINT from interfaces; drop RTSFLUSH generic +-- 2010-05-01 286 1.1.5 set RTSFLUSH=>false till tested; rri_a_ -> rbaddr_ +-- 2010-04-24 281 1.1.4 mv from vlib/s3board/sys/sys_s3board_memtest.vhd +-- 2010-04-18 279 1.1.3 drop RTSFBUF generic for rri_serport +-- 2010-04-10 275 1.1.2 use s3_humanio, rri_core_serport; +-- 2010-04-04 274 1.1.1 add CE_USEC, CP_FLUSH, CTS_N, RTS_N signals +-- 2009-11-14 249 1.1 ported to rri V2 rb_mreq/rb_sres interface; cleaner +-- rbus logic, should work with 2nd rbus device +-- 2008-02-17 117 1.0.5 use req,we rather req_r,req_w interface +-- 2008-01-20 113 1.0.4 rename memdrv->memctl_s3sram +-- 2008-01-20 112 1.0.3 rename clkgen->clkdivce +-- 2007-12-24 105 1.0.2 now fully implemented +-- 2007-12-22 104 1.0.1 finish mblk, add smem and sblk. +-- 2007-12-20 103 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.s3boardlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_sram_s3 is -- top level + -- implements s3board_aif + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end sys_tst_sram_s3; + +architecture syn of sys_tst_sram_s3 is + + signal CLK : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal GBL_RESET : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + signal RB_LAM_TST : slbit := '0'; + + signal MEM_RESET : slbit := '0'; + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACK_W : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv18 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + constant sysid_proj : slv16 := x"0104"; -- tst_sram + constant sysid_board : slv8 := x"01"; -- s3board + constant sysid_vers : slv8 := x"00"; + +begin + + CLK <= I_CLK50; -- use 50MHz as system clock + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 6, + USECDIV => 50, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2line_iob + port map ( + CLK => CLK, + RXD => RXD, + TXD => TXD, + I_RXD => I_RXD, + O_TXD => O_TXD + ); + + HIO : sn_humanio + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp1c + generic map ( + BTOWIDTH => 6, -- 64 cycles access timeout + RTAWIDTH => 12, + SYSID => (others=>'0'), + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => 0, + RBMON_RBADDR => x"ffe8") + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => GBL_RESET, + ENAXON => SWI(1), + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + TST : entity work.tst_sram + generic map ( + RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)), + AWIDTH => 18) + port map ( + CLK => CLK, + RESET => GBL_RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_STAT => RB_STAT, + RB_LAM => RB_LAM_TST, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + MEM_RESET => MEM_RESET, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ACK_W => MEM_ACK_W, + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO + ); + + SRAMCTL : s3_sram_memctl + port map ( + CLK => CLK, + RESET => MEM_RESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => MEM_ACK_W, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + RB_SRES <= RB_SRES_TST; -- can be sres_or later... + RB_LAM(0) <= RB_LAM_TST; + + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + +end syn; + Index: trunk/rtl/sys_gen/tst_sram/s3board/tb/.cvsignore =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/tb/.cvsignore (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/tb/.cvsignore (revision 37) @@ -0,0 +1,4 @@ +tb_tst_sram_s3 +tb_tst_sram_simple +sys_tst_sram_s3.ucf +sys_tst_sram_simple.ucf Index: trunk/rtl/sys_gen/tst_sram/s3board/tb/Makefile =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/tb/Makefile (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/tb/Makefile (revision 37) @@ -0,0 +1,36 @@ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.3 use includes from rtl/make +# 2010-05-23 294 1.2.1 rename tb_tst_sram -> tb_tst_sram_s3 +# 2007-12-09 100 1.1 use vbom autodep +# 2007-11-19 96 1.0 Initial version +# +EXE_all = tb_tst_sram_s3 +# +include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean + rm -f sys_tst_sram_s3.ucf + rm -f sys_tst_sram_simple.ucf +# +#----- +# +include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: trunk/rtl/sys_gen/tst_sram/s3board/tb/sys_conf_sim.vhd =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/tb/sys_conf_sim.vhd (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/tb/sys_conf_sim.vhd (revision 37) @@ -0,0 +1,34 @@ +-- $Id: sys_conf_sim.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_* (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Revision History: +-- Date Rev Version Comment +-- 2007-11-18 96 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + +end package sys_conf; Index: trunk/rtl/sys_gen/tst_sram/s3board/tb/sys_tst_sram_s3.ucf_cpp =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/tb/sys_tst_sram_s3.ucf_cpp (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/tb/sys_tst_sram_s3.ucf_cpp (revision 37) @@ -0,0 +1 @@ +link ../sys_tst_sram_s3.ucf_cpp \ No newline at end of file
trunk/rtl/sys_gen/tst_sram/s3board/tb/sys_tst_sram_s3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/sys_gen/tst_sram/s3board/tb/tb_tst_sram_s3.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/tb/tb_tst_sram_s3.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/tb/tb_tst_sram_s3.vbom (revision 37) @@ -0,0 +1,9 @@ +# configure tb_s3board with sys_tst_sram_s3 target; +# use vhdl configure file (tb_tst_sram_s3.vhd) to allow +# that all configurations will co-exist in work library +# configure +s3board_aif = ../sys_tst_sram_s3.vbom +sys_conf = sys_conf_sim.vhd +# design +../../../../bplib/s3board/tb/tb_s3board.vbom +tb_tst_sram_s3.vhd Index: trunk/rtl/sys_gen/tst_sram/s3board/tb/tb_tst_sram_s3.vhd =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/tb/tb_tst_sram_s3.vhd (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/tb/tb_tst_sram_s3.vhd (revision 37) @@ -0,0 +1,43 @@ +-- $Id: tb_tst_sram_s3.vhd 437 2011-12-09 19:38:07Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_sram_s3 +-- Description: Configuration for tb_tst_sram_s3 for tb_s3board +-- +-- Dependencies: sys_tst_sram_s3 +-- +-- To test: sys_tst_sram_s3 +-- +-- Verified: +-- Date Rev Code ghdl ise Target Comment +-- 2007-12-23 105 _ssim 0.26 8.2.03 I34 xc3s1000 u:ok +-- 2007-12-23 105 - 0.26 8.2.03 I34 - u:ok +-- 2007-12-21 103 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok +-- 2007-12-21 103 - 0.26 8.1.03 I27 - c:ok +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-05-23 294 1.0.1 renamed to tb_tst_sram_s3 +-- 2007-12-21 103 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_sram_s3 of tb_s3board is + + for sim + for all : s3board_aif + use entity work.sys_tst_sram_s3; + end for; + end for; + +end tb_tst_sram_s3; Index: trunk/rtl/sys_gen/tst_sram/s3board/tb/tb_tst_sram_s3_ssim.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/tb/tb_tst_sram_s3_ssim.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/tb/tb_tst_sram_s3_ssim.vbom (revision 37) @@ -0,0 +1,8 @@ +# configure for _*sim case +# Note: this tb uses sys_tst_sram_s3.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +# configure +s3board_aif = sys_tst_sram_s3_ssim.vhd +# design +tb_tst_sram_s3.vbom +@top:tb_tst_sram_s3 Index: trunk/rtl/sys_gen/tst_sram/s3board/tb/tbrun.yml =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/tb/tbrun.yml (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/tb/tbrun.yml (revision 37) @@ -0,0 +1,19 @@ +# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-08-28 803 1.1 use ${ise_modes_noisim} when ISim can't be used +# 2016-08-21 799 1.0 Initial version +# +- default: + mode: ${ise_modes_noisim} +# +- tag: [default, ise, sys_tst_sram, s3, base] + test: | + tbrun_tbwrri --lsuf base --pack tst_sram tb_tst_sram_s3${ms} \ + tst_sram::setup tst_sram::test_all + +- tag: [default, ise, sys_tst_sram, s3, stress] + test: | + tbrun_tbwrri --lsuf stress --pack tst_sram tb_tst_sram_s3${ms} \ + tst_sram::setup tst_sram::test_sim Index: trunk/rtl/sys_gen/tst_sram/s3board/tb/tbw.dat =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/tb/tbw.dat (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/tb/tbw.dat (revision 37) @@ -0,0 +1,11 @@ +# $Id: tbw.dat 352 2011-01-02 13:01:37Z mueller $ +# +[tb_tst_sram_s3] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = +# +[tb_tst_sram_simple] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: trunk/rtl/sys_gen/tst_sram/s3board/tb =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board/tb (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board/tb (revision 37)
trunk/rtl/sys_gen/tst_sram/s3board/tb Property changes : Added: svn:ignore ## -0,0 +1,46 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb +tb_tst_sram_s3 +tb_tst_sram_simple +sys_tst_sram_s3.ucf +sys_tst_sram_simple.ucf Index: trunk/rtl/sys_gen/tst_sram/s3board =================================================================== --- trunk/rtl/sys_gen/tst_sram/s3board (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/s3board (revision 37)
trunk/rtl/sys_gen/tst_sram/s3board Property changes : Added: svn:ignore ## -0,0 +1,45 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb +sys_tst_sram_s3.ucf +sys_tst_sram_simple.ucf +sys_tst_sram_basics.ucf Index: trunk/rtl/sys_gen/tst_sram/tbrun.yml =================================================================== --- trunk/rtl/sys_gen/tst_sram/tbrun.yml (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/tbrun.yml (revision 37) @@ -0,0 +1,10 @@ +# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-08-13 798 1.0 Initial version +# +- include: s3board/tb/tbrun.yml +- include: nexys2/tb/tbrun.yml +- include: nexys3/tb/tbrun.yml +- include: nexys4/tb/tbrun.yml Index: trunk/rtl/sys_gen/tst_sram/tst_sram.vbom =================================================================== --- trunk/rtl/sys_gen/tst_sram/tst_sram.vbom (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/tst_sram.vbom (revision 37) @@ -0,0 +1,14 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/memlib/memlib.vhd +../../vlib/rbus/rblib.vhd +${sys_conf} +# components +[sim]../../vlib/memlib/ram_1swsr_wfirst_gen.vbom +[sim]../../vlib/memlib/ram_2swsr_wfirst_gen.vbom +[xst]../../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vbom +[vsyn]../../vlib/memlib/ram_1swsr_wfirst_gen.vbom +[xst]../../vlib/memlib/ram_2swsr_wfirst_gen_unisim.vbom +[vsyn]../../vlib/memlib/ram_2swsr_wfirst_gen.vbom +# design +tst_sram.vhd Index: trunk/rtl/sys_gen/tst_sram/tst_sram.vhd =================================================================== --- trunk/rtl/sys_gen/tst_sram/tst_sram.vhd (nonexistent) +++ trunk/rtl/sys_gen/tst_sram/tst_sram.vhd (revision 37) @@ -0,0 +1,1097 @@ +-- $Id: tst_sram.vhd 785 2016-07-10 12:22:41Z mueller $ +-- +-- Copyright 2007-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tst_sram - syn +-- Description: test of s3board sram and its controller +-- +-- Dependencies: vlib/memlib/ram_1swsr_wfirst_gen +-- vlib/memlib/ram_2swsr_wfirst_gen +-- vlib/rlink/rlink_base_serport +-- +-- Test bench: nexys4/tb/tb_tst_sram_n4 (with cram) +-- nexys3/tb/tb_tst_sram_n3 (with cram) +-- nexys2/tb/tb_tst_sram_n2 (with cram) +-- s3board/tb/tb_tst_sram_s3 (with sram) +-- +-- Target Devices: generic +-- Tool versions: xst 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-07-10 785 1.5.1 std SWI layout: now (7:4) disp select, SWI(1)->XON +-- 2016-07-09 784 1.5 AWIDTH generic, add 22bit support for cram +-- 2016-05-22 767 1.4.1 don't init N_REGS (vivado fix for fsm inference) +-- 2014-09-05 591 1.4 use new rlink v4 iface and 4 bit STAT +-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit +-- 2011-11-21 432 1.2.0 now numeric_std clean +-- 2010-12-31 352 1.2 port to rbv3 +-- 2010-10-23 335 1.1.3 rename RRI_LAM->RB_LAM; +-- 2010-06-18 306 1.1.2 rename rbus data fields to _rbf_ +-- 2010-06-03 299 1.1.1 correct rbus init logic (use we, RB_ADDR) +-- 2010-05-24 294 1.1 Correct _al->_dl logic, remove BUSY=0 condition +-- 2010-05-21 292 1.0.1 move memory controler to top level entity +-- 2010-05-16 291 1.0 Initial version (extracted from sys_tst_sram) +-- now RB_SRES only driven when selected +------------------------------------------------------------------------------ +-- +-- rbus registers: +-- +-- Address Bits Name r/w/f Function +-- bbb00000 15:00 mdih r/w/- Memory data input register, high word +-- bbb00001 15:00 mdil r/w/- Memory data input register, low word +-- bbb00010 15:00 mdoh r/-/- Memory data output register, high word +-- bbb00011 15:00 mdol r/-/- Memory data output register, low word +-- bbb00100 01:00 maddrh r/w/- Memory address register, high word +-- bbb00101 15:00 maddrl r/w/- Memory address register, low word +-- +-- bbb00110 mcmd -/-/f Immediate memory command register +-- 14 ld -/-/f if 1 load addrh field to maddr high word +-- 13 inc -/-/f if 1 post-increment maddr +-- 12 we -/-/f if 1 do write cycle, otherwise read +-- 11:08 be -/-/f byte enables (used for writes) +-- *:00 addrh -/-/f maddr high word (loaded of ld=1) +-- +-- bbb00111 15:00 mblk r/w/- Memory block read/write +-- pairs of r/w to access memory directly +-- read access logic: +-- than mdo is read from mem(maddr) +-- 1st read gives mdoh, 2nd loads mdol +-- maddr is post-incrememted +-- write access logic: +-- 1st write loads mdih, 2nd loads mdil +-- than mdi is written to mem(maddr) +-- maddr is post-incrememted +-- +-- bbb01000 10:00 slim r/w/- Sequencer range register +-- bbb01001 10:00 saddr r/w/- Sequencer address register +-- bbb01010 15:00 sblk r/w/- Sequencer memory block read/write +-- groups of 4 r/w to access sequencer mem +-- access order: 11,10,01,00 +-- bbb01011 15:00 sblkc r/w/- Like sblk, access to command part +-- groups of 2 r/w to access sequencer mem +-- access order: 11,10 +-- bbb01100 15:00 sblkd r/w/- Like sblk, access to data part +-- groups of 2 r/w to access sequencer mem +-- access order: 01,00 +-- bbb01101 sstat r/w/- Sequencer status register +-- 15 wide r/-/- 1 if AWIDTH=22 +-- 09 wswap r/w/- enable swap of upper 4 addr bits +-- 08 wloop r/w/- enable wide (22bit) loop (default 18bit) +-- 07 loop r/w/- loop till maddr= +-- 06 xord r/w/- xor memory address with maddr +-- 05 xora r/w/- xor memory data with mdi +-- 04 veri r/w/- verify memory reads +-- 01 fail r/-/- 1 if sequencer stopped after failure +-- 00 run r/-/- 1 if sequencer running +-- bbb01110 sstart -/-/f Start sequencer (sstat.run=1, .fail=0) +-- bbb01111 sstop -/-/f Stop sequencer (sstat.run=0) +-- bbb10000 10:00 seaddr r/-/- Current sequencer address +-- bbb10001 15:00 sedath r/-/- Current sequencer data (high word) +-- bbb10010 15:00 sedatl r/-/- Current sequencer data ( low word) +-- +-- Sequencer memory format +-- 64 bit wide, upper 32 bits sequencer command, lower 32 bits data +-- Item Bits Name Function +-- scmd 31:28 wait number of wait cycles +-- 24 we write enable +-- 23:20 be byte enables +-- 17:00 addr address +-- +------------------------------------------------------------------------------ +-- +-- Usage of S3BOARD Switches, Buttons, LEDs: +-- +-- BTN(3:0): unused +-- +-- SWI(7:4): determine data displayed +-- SWI 3210 +-- 0000 mdil +-- 0001 mdih +-- 0010 mem_do.l +-- 0011 mem_do.h +-- 0100 maddr.l +-- 0101 maddr.h +-- 0110 slim +-- 0111 saddr +-- 1000 sstat +-- 1001 seaddr +-- 1010 sedatl +-- 1011 sedath +-- 1100 smem_b0 data.l +-- 1101 smem_b1 data.h +-- 1110 smem_b2 cmd.l +-- 1111 smem_b3 cmd.h +-- SWI(3:2): unused +-- SWI(1): 1 enable XON +-- SWI(0): RS232 port select (on some boards) +-- +-- LED(7): or of all unused BTNs and SWI +-- LED(6): R_REGS.sloop +-- LED(5): R_REGS.sveri +-- LED(4): R_REGS.sfail +-- LED(3): R_REGS.srun +-- LED(2): MEM_ACT_W +-- LED(1): MEM_ACT_R +-- LED(0): MEM_BUSY +-- +-- DSP: data as selected by SWI(7..4) +-- +-- DP(3): not SER_MONI.txok (shows tx back preasure) +-- DP(2): SER_MONI.txact (shows tx activity) +-- DP(1): not SER_MONI.rxok (shows rx back preasure) +-- DP(0): SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.memlib.all; +use work.rblib.all; + +-- ---------------------------------------------------------------------------- + +entity tst_sram is -- tester for sram memctl + generic ( + RB_ADDR : slv16 := slv(to_unsigned(2#0000000000000000#,16)); + AWIDTH : natural := 18); + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + RB_STAT : out slv4; -- rbus: status flags + RB_LAM : out slbit; -- remote attention + SWI : in slv8; -- hio switches + BTN : in slv4; -- hio buttons + LED : out slv8; -- hio leds + DSP_DAT : out slv16; -- hio display data + MEM_RESET : out slbit; -- mem: reset + MEM_REQ : out slbit; -- mem: request + MEM_WE : out slbit; -- mem: write enable + MEM_BUSY : in slbit; -- mem: controller busy + MEM_ACK_R : in slbit; -- mem: acknowledge read + MEM_ACK_W : in slbit; -- mem: acknowledge write + MEM_ACT_R : in slbit; -- mem: signal active read + MEM_ACT_W : in slbit; -- mem: signal active write + MEM_ADDR : out slv(AWIDTH-1 downto 0); -- mem: address + MEM_BE : out slv4; -- mem: byte enable + MEM_DI : out slv32; -- mem: data in (memory view) + MEM_DO : in slv32 -- mem: data out (memory view) + ); +end tst_sram; + +architecture syn of tst_sram is + + signal SEQ_RESET : slbit := '0'; + + signal SMEM_CEA : slbit := '0'; + signal SMEM_B3_WE : slbit := '0'; + signal SMEM_B2_WE : slbit := '0'; + signal SMEM_B1_WE : slbit := '0'; + signal SMEM_B0_WE : slbit := '0'; + signal SMEM_WEB : slbit := '0'; + signal SMEM_CMD : slv32 := (others=>'0'); + signal SMEM_DATA : slv32 := (others=>'0'); + + type state_type is ( + s_idle, -- s_idle: wait for input + s_mcmd, -- s_mcmd: immediate memory r/w + s_mcmd_read, -- s_mcmd_read: wait for read completion + s_mblk_wr1, -- s_mblk_wr1: mem blk write, get datal + s_mblk_wr2, -- s_mblk_wr2: mem blk write, do write + s_mblk_rd1, -- s_mblk_rd1: mem blk read, wait, datah + s_mblk_rd2, -- s_mblk_rd2: mem blk read, datal + s_sblk_rd, -- s_sblk_rd: read smem for sblk + s_sblk, -- s_sblk: process sblk transfers + s_sstart, -- s_sstart: sequencer startup + s_sload, -- s_sload: sequencer load data + s_srun, -- s_srun: run sequencer commands + s_sloop -- s_sloop: stop or loop + ); + + type regs_type is record + state : state_type; -- state + rbsel : slbit; -- rbus select + maddr : slv(AWIDTH-1 downto 0); -- memory address + mdi : slv32; -- memory data input + saddr : slv11; -- sequencer address + slim : slv11; -- sequencer range + sbank : slv2; -- current sblk bank + srun : slbit; -- seq: run flag + slast : slbit; -- seq: last cmd flag + sfail : slbit; -- seq: fail flag + swcnt : slv4; -- seq: wait counter + scaddr : slv11; -- seq: current address + sveri : slbit; -- seq: verify mode (check data) + sxora : slbit; -- seq: xor maddr into address + sxord : slbit; -- seq: xor mdi into data + sloop : slbit; -- seq: loop over maddr + swloop : slbit; -- seq: enable wide loop (22bit) + swswap : slbit; -- seq: enable top 4 bit addr swap + mrp_val_al : slbit; -- mrp: valid flag, addr latch stage + mrp_adr_al : slv11; -- mrp: seq address, addr latch stage + mrp_dat_al : slv32; -- mrp: exp mem data, addr latch stage + mrp_val_dl : slbit; -- mrp: valid flag, data latch stage + mrp_adr_dl : slv11; -- mrp: seq address, data latch stage + mrp_dat_dl : slv32; -- mrp: exp mem data, data latch stage + se_addr : slv11; -- seq err: seq address + se_data : slv32; -- seq err: memory data + dispval : slv16; -- data for display + end record regs_type; + + constant maddrzero : slv(AWIDTH-1 downto 0) := (others=>'0'); + + constant regs_init : regs_type := ( + s_idle, -- state + '0', -- rbsel + maddrzero, -- maddr + (others=>'0'), -- mdi + (others=>'0'), -- saddr + (others=>'0'), -- slim + (others=>'0'), -- sbank + '0','0','0', -- srun, slast, sfail + (others=>'0'), -- swcnt + (others=>'0'), -- scaddr + '0','0','0', -- sveri,sxora,sxord + '0','0','0', -- sloop,swloop,swswap + '0', -- mrp_val_al + (others=>'0'), -- mrp_adr_al + (others=>'0'), -- mrp_dat_al + '0', -- mrp_val_dl + (others=>'0'), -- mrp_adr_dl + (others=>'0'), -- mrp_dat_dl + (others=>'0'), -- se_addr + (others=>'0'), -- se_data + (others=>'0') -- dispval + ); + + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) + + subtype maddr_f_wh is integer range AWIDTH-1 downto 16; + subtype maddr_f_wl is integer range 15 downto 0; + + subtype maddr_f_scmd is integer range 17 downto 0; + subtype maddr_f_top4 is integer range AWIDTH-1 downto AWIDTH-1-3; + subtype maddr_f_mid4 is integer range AWIDTH-1-4 downto AWIDTH-1-7; + subtype maddr_f_bot is integer range AWIDTH-1-8 downto 0; + + subtype df_word0 is integer range 15 downto 0; + subtype df_word1 is integer range 31 downto 16; + + subtype maddrh_rbf_h is integer range AWIDTH-1-16 downto 0; + + constant mcmd_rbf_ld: integer := 14; + constant mcmd_rbf_inc: integer := 13; + constant mcmd_rbf_we: integer := 12; + subtype mcmd_rbf_be is integer range 11 downto 8; + subtype mcmd_rbf_addrh is integer range AWIDTH-1-16 downto 0; + + constant sstat_rbf_wide: integer := 15; + constant sstat_rbf_wswap: integer := 9; + constant sstat_rbf_wloop: integer := 8; + constant sstat_rbf_loop: integer := 7; + constant sstat_rbf_xord: integer := 6; + constant sstat_rbf_xora: integer := 5; + constant sstat_rbf_veri: integer := 4; + constant sstat_rbf_fail: integer := 1; + constant sstat_rbf_run: integer := 0; + + subtype scmd_rbf_wait is integer range 31 downto 28; + constant scmd_rbf_we: integer := 24; + subtype scmd_rbf_be is integer range 23 downto 20; + subtype scmd_rbf_addr is integer range 17 downto 0; + + constant rbaddr_mdih: slv5 := "00000"; -- 0 -/r/w + constant rbaddr_mdil: slv5 := "00001"; -- 1 -/r/w + constant rbaddr_mdoh: slv5 := "00010"; -- 2 -/r/- + constant rbaddr_mdol: slv5 := "00011"; -- 3 -/r/- + constant rbaddr_maddrh: slv5 := "00100"; -- 4 -/r/w + constant rbaddr_maddrl: slv5 := "00101"; -- 5 -/r/w + constant rbaddr_mcmd: slv5 := "00110"; -- 6 -/-/w + constant rbaddr_mblk: slv5 := "00111"; -- 7 -/r/w + constant rbaddr_slim: slv5 := "01000"; -- 8 -/r/w + constant rbaddr_saddr: slv5 := "01001"; -- 9 -/r/w + constant rbaddr_sblk: slv5 := "01010"; -- 10 -/r/w + constant rbaddr_sblkc: slv5 := "01011"; -- 11 -/r/w + constant rbaddr_sblkd: slv5 := "01100"; -- 12 -/r/w + constant rbaddr_sstat: slv5 := "01101"; -- 13 -/r/w + constant rbaddr_sstart: slv5 := "01110"; -- 14 f/-/- + constant rbaddr_sstop: slv5 := "01111"; -- 15 f/-/- + constant rbaddr_seaddr: slv5 := "10000"; -- 16 -/r/- + constant rbaddr_sedath: slv5 := "10001"; -- 17 -/r/- + constant rbaddr_sedatl: slv5 := "10010"; -- 18 -/r/- + + constant omux_mdil: slv4 := "0000"; + constant omux_mdih: slv4 := "0001"; + constant omux_memdol: slv4 := "0010"; + constant omux_memdoh: slv4 := "0011"; + constant omux_maddrl: slv4 := "0100"; + constant omux_maddrh: slv4 := "0101"; + constant omux_slim: slv4 := "0110"; + constant omux_saddr: slv4 := "0111"; + constant omux_sstat: slv4 := "1000"; + constant omux_seaddr: slv4 := "1001"; + constant omux_sedatl: slv4 := "1010"; + constant omux_sedath: slv4 := "1011"; + constant omux_smemb0: slv4 := "1100"; + constant omux_smemb1: slv4 := "1101"; + constant omux_smemb2: slv4 := "1110"; + constant omux_smemb3: slv4 := "1111"; + +begin + + assert AWIDTH=18 or AWIDTH=22 + report "assert(AWIDTH=18 or AWIDTH=22): unsupported AWIDTH" + severity failure; + + SMEM_B3 : ram_1swsr_wfirst_gen + generic map ( + AWIDTH => 11, + DWIDTH => 16) + port map ( + CLK => CLK, + EN => SMEM_CEA, + WE => SMEM_B3_WE, + ADDR => R_REGS.saddr, + DI => RB_MREQ.din, + DO => SMEM_CMD(df_word1) + ); + + SMEM_B2 : ram_1swsr_wfirst_gen + generic map ( + AWIDTH => 11, + DWIDTH => 16) + port map ( + CLK => CLK, + EN => SMEM_CEA, + WE => SMEM_B2_WE, + ADDR => R_REGS.saddr, + DI => RB_MREQ.din, + DO => SMEM_CMD(df_word0) + ); + + SMEM_B1 : ram_2swsr_wfirst_gen + generic map ( + AWIDTH => 11, + DWIDTH => 16) + port map ( + CLKA => CLK, + CLKB => CLK, + ENA => SMEM_CEA, + ENB => SMEM_WEB, + WEA => SMEM_B1_WE, + WEB => SMEM_WEB, + ADDRA => R_REGS.saddr, + ADDRB => R_REGS.mrp_adr_dl, + DIA => RB_MREQ.din, + DIB => MEM_DO(df_word1), + DOA => SMEM_DATA(df_word1), + DOB => open + ); + + SMEM_B0 : ram_2swsr_wfirst_gen + generic map ( + AWIDTH => 11, + DWIDTH => 16) + port map ( + CLKA => CLK, + CLKB => CLK, + ENA => SMEM_CEA, + ENB => SMEM_WEB, + WEA => SMEM_B0_WE, + WEB => SMEM_WEB, + ADDRA => R_REGS.saddr, + ADDRB => R_REGS.mrp_adr_dl, + DIA => RB_MREQ.din, + DIB => MEM_DO(df_word0), + DOA => SMEM_DATA(df_word0), + DOB => open + ); + + -- look for init's against the rbus base address + -- generate subsystem resets depending in data bits + proc_reset: process (RESET, RB_MREQ) + begin + + SEQ_RESET <= RESET; + MEM_RESET <= RESET; + + if RB_MREQ.init='1' and RB_MREQ.addr=RB_ADDR then + SEQ_RESET <= RB_MREQ.din(0); + MEM_RESET <= RB_MREQ.din(1); + end if; + + end process proc_reset; + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if SEQ_RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, RB_MREQ, + MEM_BUSY, MEM_ACT_R, MEM_ACK_R, MEM_DO, + SMEM_CMD, SMEM_DATA, + SWI) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable irb_ack : slbit := '0'; + variable irb_busy : slbit := '0'; + variable irb_err : slbit := '0'; + variable irb_dout : slv16 := (others=>'0'); + variable irbena : slbit := '0'; -- re or we -> rbus request + variable irbact : slbit := '0'; -- sel and (re or we) -> device active + + variable imem_reqr : slbit := '0'; + variable imem_reqw : slbit := '0'; + variable imem_be : slv4 := (others=>'0'); + variable imem_addr : slv(AWIDTH-1 downto 0) := (others=>'0'); + variable imem_di : slv32 := (others=>'0'); + + variable ixor_addr : slv(AWIDTH-1 downto 0) := (others=>'0'); + variable ixor_data : slv32 := (others=>'0'); + variable imaddr_chk: slv(AWIDTH-1 downto 0) := (others=>'0'); + + variable isblk_ok : slbit := '0'; + variable isbank : slv2 := "11"; + + variable maddr_inc : slbit := '0'; + variable saddr_inc : slbit := '0'; + variable saddr_next : slbit := '0'; + variable saddr_last : slbit := '0'; + variable swcnt_inc : slbit := '0'; + + variable ilam : slbit := '0'; + + variable omux_sel : slv4 := "0000"; + variable omux_dat : slv16 := (others=>'0'); + + constant c_maddr_ones : slv(AWIDTH-1 downto 0) := (others=>'1'); + + begin + + r := R_REGS; + n := R_REGS; + + irb_ack := '0'; + irb_busy := '0'; + irb_err := '0'; + irb_dout := (others=>'0'); + + irbena := RB_MREQ.re or RB_MREQ.we; + irbact := '0'; + + imem_reqr := '0'; + imem_reqw := '0'; + imem_be := (others=>'1'); + imem_addr := r.maddr; + imem_di := r.mdi; + + ixor_addr := (others=>'0'); + ixor_data := (others=>'0'); + + isblk_ok := '0'; + isbank := "11"; + + maddr_inc := '0'; + saddr_inc := '0'; + saddr_next := '0'; + saddr_last := '0'; + swcnt_inc := '0'; + + ilam := '0'; + + omux_sel := omux_mdil; + omux_dat := (others=>'0'); + + SMEM_CEA <= '0'; + SMEM_B3_WE <= '0'; + SMEM_B2_WE <= '0'; + SMEM_B1_WE <= '0'; + SMEM_B0_WE <= '0'; + SMEM_WEB <= '0'; + + if r.saddr = r.slim then + saddr_last := '1'; + end if; + + if r.mrp_val_dl='1' and MEM_ACK_R='1' then + n.mrp_val_dl := '0'; + if r.sveri = '1' then + if r.mrp_dat_dl /= MEM_DO and -- mismatch + r.sfail='0' then -- and no fail set yet + ilam := '1'; + n.sfail := '1'; + n.srun := '0'; + n.se_addr := r.mrp_adr_dl; + n.se_data := MEM_DO; + end if; + else + SMEM_WEB <= '1'; + end if; + end if; + if r.mrp_val_al='1' and MEM_ACT_R='1' then + n.mrp_val_al := '0'; + n.mrp_val_dl := r.mrp_val_al; + n.mrp_adr_dl := r.mrp_adr_al; + n.mrp_dat_dl := r.mrp_dat_al; + end if; + + -- rbus address decoder + n.rbsel := '0'; + if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 5)=RB_ADDR(15 downto 5) then + n.rbsel := '1'; + end if; + + if r.rbsel='1' and irbena='1' then + irb_ack := '1'; -- ack all (maybe rejected later) + irbact := '1'; -- signal device active + end if; + + case r.state is + + when s_idle => -- s_idle: wait for rbus requests ---- + + if r.rbsel = '1' then -- rbus select + + case RB_MREQ.addr(4 downto 0) is -- rbus address decoder + + when rbaddr_mdih => + omux_sel := omux_mdih; + if RB_MREQ.we = '1' then + n.mdi(df_word1) := RB_MREQ.din; + end if; + + when rbaddr_mdil => + omux_sel := omux_mdil; + if RB_MREQ.we = '1' then + n.mdi(df_word0) := RB_MREQ.din; + end if; + + when rbaddr_mdoh => + omux_sel := omux_memdoh; + if RB_MREQ.we = '1' then + irb_err := '1'; -- read-only reg + end if; + + when rbaddr_mdol => + omux_sel := omux_memdol; + if RB_MREQ.we = '1' then + irb_err := '1'; -- read-only reg + end if; + + when rbaddr_maddrh => + omux_sel := omux_maddrh; + if RB_MREQ.we = '1' then + n.maddr(maddr_f_wh) := RB_MREQ.din(maddrh_rbf_h); + end if; + + when rbaddr_maddrl => + omux_sel := omux_maddrl; + if RB_MREQ.we = '1' then + n.maddr(maddr_f_wl) := RB_MREQ.din; + end if; + + when rbaddr_mcmd => + if RB_MREQ.we = '1' then + if RB_MREQ.din(mcmd_rbf_ld) = '1' then + n.maddr(maddr_f_wh) := RB_MREQ.din(mcmd_rbf_addrh); + end if; + irb_busy := '1'; + n.state := s_mcmd; + end if; + if RB_MREQ.re = '1' then + irb_err := '1'; -- write-only reg + end if; + + when rbaddr_mblk => + imem_addr := r.maddr; + + if RB_MREQ.we = '1' then + n.mdi(df_word1) := RB_MREQ.din; + n.state := s_mblk_wr1; + end if; + if RB_MREQ.re = '1' then + irb_busy := '1'; + imem_reqr := '1'; + if MEM_BUSY = '0' then + maddr_inc := '1'; + n.state := s_mblk_rd1; + end if; + end if; + + when rbaddr_slim => + omux_sel := omux_slim; + if RB_MREQ.we = '1' then + n.slim := RB_MREQ.din(r.slim'range); + end if; + + when rbaddr_saddr => + omux_sel := omux_saddr; + if RB_MREQ.we = '1' then + n.saddr := RB_MREQ.din(r.saddr'range); + end if; + + when rbaddr_sblk|rbaddr_sblkc|rbaddr_sblkd => + if RB_MREQ.we = '1' then + n.sbank := "11"; + irb_busy := '1'; + n.state := s_sblk; + end if; + if RB_MREQ.re = '1' then + n.sbank := "11"; + irb_busy := '1'; + n.state := s_sblk_rd; + end if; + + when rbaddr_sstat => + omux_sel := omux_sstat; + if RB_MREQ.we = '1' then + n.swswap := RB_MREQ.din(sstat_rbf_wswap); + n.swloop := RB_MREQ.din(sstat_rbf_wloop); + n.sloop := RB_MREQ.din(sstat_rbf_loop); + n.sxord := RB_MREQ.din(sstat_rbf_xord); + n.sxora := RB_MREQ.din(sstat_rbf_xora); + n.sveri := RB_MREQ.din(sstat_rbf_veri); + end if; + + when rbaddr_sstart => + if RB_MREQ.we = '1' then + n.sfail := '0'; + n.state := s_sstart; + end if; + if RB_MREQ.re = '1' then + irb_err := '1'; -- write-only reg + end if; + + when rbaddr_sstop => + if RB_MREQ.we = '1' then + n.srun := '0'; + end if; + if RB_MREQ.re = '1' then + irb_err := '1'; -- write-only reg + end if; + + when rbaddr_seaddr => + omux_sel := omux_seaddr; + if RB_MREQ.we = '1' then + irb_err := '1'; -- read-only reg + end if; + + when rbaddr_sedath => + omux_sel := omux_sedath; + if RB_MREQ.we = '1' then + irb_err := '1'; -- read-only reg + end if; + + when rbaddr_sedatl => + omux_sel := omux_sedatl; + if RB_MREQ.we = '1' then + irb_err := '1'; -- read-only reg + end if; + + when others => + irb_ack := '0'; -- refuse ack in case of bad addr + end case; + + else -- no rbus request (rb_mreq.ack='0') + + if r.srun = '1' then + n.state := s_srun; + end if; + + end if; + + when s_mcmd=> -- s_mcmd: immediate memory r/w ------ + if RB_MREQ.din(mcmd_rbf_we) = '1' then -- write command + imem_reqw := '1'; + else -- read command + imem_reqr := '1'; + end if; + imem_be := RB_MREQ.din(mcmd_rbf_be); + imem_addr := r.maddr; + imem_di := r.mdi; + + if irbact = '0' then -- rbus cycle abort + n.state := s_idle; -- quit + else + if MEM_BUSY = '0' then -- command accepted ? + if RB_MREQ.din(mcmd_rbf_inc) = '1' then -- maddr inc requested + maddr_inc := '1'; + end if; + if RB_MREQ.din(mcmd_rbf_we) = '1' then -- write command + n.state := s_idle; + else -- read command + irb_busy := '1'; + n.state := s_mcmd_read; + end if; + else -- otherwise + irb_busy := '1'; -- hold and wait + end if; + end if; + + when s_mcmd_read => -- s_mcmd_read: wait for read completion + + if irbact = '0' then -- rbus cycle abort + n.state := s_idle; -- quit + else + if MEM_ACK_R = '1' then -- read acknowledge seen + n.state := s_idle; + else -- otherwise + irb_busy := '1'; -- hold and wait + end if; + end if; + + when s_mblk_wr1 => -- s_mblk_wr1: mem blk write, get datal + if irbact = '1' then -- wait for rbus request + if RB_MREQ.we = '1' and -- write access and cmd ok ? + RB_MREQ.addr(4 downto 0)=rbaddr_mblk then + n.mdi(df_word0) := RB_MREQ.din; -- latch datal + irb_busy := '1'; + n.state := s_mblk_wr2; -- next: issue mem write + else + irb_err := '1'; -- signal error + n.state := s_idle; -- return to dispatch + end if; + end if; + + when s_mblk_wr2 => -- s_mblk_wr2: mem blk write, do write + n.state := s_mblk_wr2; -- needed to prevent vivado iSTATE + imem_reqw := '1'; + imem_be := (others=>'1'); + imem_addr := r.maddr; + imem_di := r.mdi; + + if irbact = '0' then -- rbus cycle abort + n.state := s_idle; -- quit + else + if MEM_BUSY = '0' then -- command accepted ? + maddr_inc := '1'; + n.state := s_idle; + else -- otherwise + irb_busy := '1'; -- hold and wait + end if; + end if; + + when s_mblk_rd1 => -- s_mblk_rd1: mem blk read, wait, datah + omux_sel := omux_memdoh; -- return mem datah + if irbact = '0' then -- rbus cycle abort + n.state := s_idle; -- quit + else + if MEM_ACK_R = '1' then -- read acknowledge seen + n.state := s_mblk_rd2; + else -- otherwise + irb_busy := '1'; -- hold and wait + end if; + end if; + + when s_mblk_rd2 => -- s_mblk_rd2: mem blk read, datal --- + omux_sel := omux_memdol; -- return mem datal + if irbact = '1' then -- wait for rbus request + if RB_MREQ.re = '1' and -- read access and cmd ok ? + RB_MREQ.addr(4 downto 0)=rbaddr_mblk then + n.state := s_idle; + else -- write if unexpected cmd addr + irb_err := '1'; -- signal error + n.state := s_idle; -- return to dispatch + end if; + end if; + + when s_sblk_rd => -- s_sblk_rd: read smem for sblk ----- + if irbact = '0' then -- rbus cycle abort + n.state := s_idle; -- quit + else + irb_busy := '1'; + SMEM_CEA <= '1'; + n.state := s_sblk; + end if; + + when s_sblk => -- s_sblk: process sblk transfers ---- + + isblk_ok := irbact; + + case RB_MREQ.addr(4 downto 0) is + when rbaddr_sblk => + isbank := r.sbank; + if r.sbank = "00" then + saddr_next := irbact; + end if; + when rbaddr_sblkc => + isbank := '1' & r.sbank(0); + if r.sbank(0) = '0' then + saddr_next := irbact; + end if; + when rbaddr_sblkd => + isbank := '0' & r.sbank(0); + if r.sbank(0) = '0' then + saddr_next := irbact; + end if; + when others => + isblk_ok := '0'; + end case; + + if isblk_ok='1' and RB_MREQ.we='1' then + SMEM_CEA <= '1'; + case isbank is + when "11" => SMEM_B3_WE <= '1'; + when "10" => SMEM_B2_WE <= '1'; + when "01" => SMEM_B1_WE <= '1'; + when "00" => SMEM_B0_WE <= '1'; + when others => null; + end case; + end if; + + case isbank is + when "11" => omux_sel := omux_smemb3; + when "10" => omux_sel := omux_smemb2; + when "01" => omux_sel := omux_smemb1; + when "00" => omux_sel := omux_smemb0; + when others => null; + end case; + + if isblk_ok = '1' then -- in active sblk cycle ? + n.sbank := slv(unsigned(r.sbank) - 1); + if saddr_next = '1' then + saddr_inc := '1'; + if RB_MREQ.re = '1' then + n.state := s_sblk_rd; + end if; + end if; + else -- not in active sblk cycle + if irbact = '1' then -- if request than other address + irb_busy := '1'; -- hold interface and + n.state := s_idle; -- back to dispatcher to handle + end if; + end if; + + when s_sstart => -- s_sstart: sequencer startup ------- + irb_busy := irbact; + n.slast := '0'; + n.srun := '1'; + n.saddr := (others=>'0'); + n.se_addr := (others=>'0'); + n.se_data := (others=>'0'); + n.state := s_sload; + + when s_sload => -- s_sload: sequencer load data ------ + irb_busy := irbact; + SMEM_CEA <= '1'; + n.scaddr := r.saddr; + saddr_inc := '1'; + if saddr_last = '1' then + n.slast := '1'; + end if; + n.state := s_srun; + + when s_srun => -- s_srun: run sequencer commands ---- + irb_busy := irbact; + ixor_addr := r.maddr; + if r.sxora = '0' then + ixor_addr(maddr_f_scmd) := SMEM_CMD(scmd_rbf_addr); + else + ixor_addr(maddr_f_scmd) := SMEM_CMD(scmd_rbf_addr) xor + r.maddr(maddr_f_scmd); + end if; + + if r.swswap = '1' then + ixor_addr := ixor_addr(maddr_f_mid4) & ixor_addr(maddr_f_top4) & + ixor_addr(maddr_f_bot); + end if; + + if r.sxord = '0' then + ixor_data := SMEM_DATA; + else + ixor_data := SMEM_DATA xor r.mdi; + end if; + imem_addr := ixor_addr; + imem_be := SMEM_CMD(scmd_rbf_be); + imem_di := ixor_data; + + if SMEM_CMD(scmd_rbf_wait) /= r.swcnt then + swcnt_inc := '1'; + else + if SMEM_CMD(scmd_rbf_we) = '1' then + imem_reqw := '1'; + else + imem_reqr := '1'; + end if; + if MEM_BUSY = '0' then + if imem_reqr = '1' then + n.mrp_val_al := '1'; + n.mrp_adr_al := r.scaddr; + n.mrp_dat_al := ixor_data; + end if; + if r.srun = '0' then + n.state := s_idle; + elsif r.slast = '1' then + n.state := s_sloop; + else + SMEM_CEA <= '1'; + n.scaddr := r.saddr; + saddr_inc := '1'; + if saddr_last = '1' then + n.slast := '1'; + end if; + if irbact = '1' then -- pending rbus request ? + n.state := s_idle; -- than goto dispatcher + end if; + end if; + end if; + end if; + + when s_sloop => -- s_sloop: stop or loop ------------- + irb_busy := irbact; + imaddr_chk := r.maddr; + if AWIDTH = 22 and r.swloop = '0' then + imaddr_chk(maddr_f_top4) := (others=>'1'); + end if; + if MEM_ACT_R='0' and MEM_ACK_R='0' then -- wait here till mem read done + if r.sfail='0' and r.sloop='1' and -- no fail and loop requested ? + imaddr_chk/=c_maddr_ones then -- and not wrapping + maddr_inc := '1'; -- increment maddr + n.state := s_sstart; -- and restart + else -- otherwise + ilam := not r.sfail; -- signal attention unless fail set + n.srun := '0'; -- stop sequencer + n.state := s_idle; -- goto dispatcher + end if; + end if; + + when others => null; + end case; + + if maddr_inc = '1' then + n.maddr := slv(unsigned(r.maddr) + 1); + end if; + + if saddr_inc = '1' then + n.saddr := slv(unsigned(r.saddr) + 1); + end if; + + if swcnt_inc = '1' then + n.swcnt := slv(unsigned(r.swcnt) + 1); + else + n.swcnt := (others=>'0'); + end if; + + if irbact = '0' then -- if no rbus request, use SWI for mux + omux_sel := SWI(7 downto 4); + end if; + + case omux_sel is + when omux_mdil => + omux_dat := r.mdi(df_word0); + when omux_mdih => + omux_dat := r.mdi(df_word1); + when omux_memdoh => + omux_dat := MEM_DO(df_word1); + when omux_memdol => + omux_dat := MEM_DO(df_word0); + when omux_maddrh => + omux_dat := (others=>'0'); + omux_dat(maddrh_rbf_h) := r.maddr(maddr_f_wh); + when omux_maddrl => + omux_dat := r.maddr(maddr_f_wl); + when omux_slim => + omux_dat := (others=>'0'); + omux_dat(r.slim'range) := r.slim; + when omux_saddr => + omux_dat := (others=>'0'); + omux_dat(r.saddr'range) := r.saddr; + when omux_sstat => + omux_dat := (others=>'0'); + if AWIDTH = 22 then + omux_dat(sstat_rbf_wide) := '1'; + end if; + omux_dat(sstat_rbf_wswap) := r.swswap; + omux_dat(sstat_rbf_wloop) := r.swloop; + omux_dat(sstat_rbf_loop) := r.sloop; + omux_dat(sstat_rbf_xord) := r.sxord; + omux_dat(sstat_rbf_xora) := r.sxora; + omux_dat(sstat_rbf_veri) := r.sveri; + omux_dat(sstat_rbf_fail) := r.sfail; + omux_dat(sstat_rbf_run) := r.srun; + when omux_seaddr => + omux_dat := (others=>'0'); + omux_dat(r.se_addr'range) := r.se_addr; + when omux_sedath => + omux_dat := r.se_data(df_word1); + when omux_sedatl => + omux_dat := r.se_data(df_word0); + when omux_smemb0 => + omux_dat := SMEM_DATA(df_word0); + when omux_smemb1 => + omux_dat := SMEM_DATA(df_word1); + when omux_smemb2 => + omux_dat := SMEM_CMD(df_word0); + when omux_smemb3 => + omux_dat := SMEM_CMD(df_word1); + + when others => null; + end case; + + if irbact = '1' then + irb_dout := omux_dat; -- if rbus request, drive dout + else + n.dispval := omux_dat; -- if no rbus request, display mux value + end if; + + N_REGS <= n; + + RB_SRES <= rb_sres_init; + RB_SRES.ack <= irb_ack; + RB_SRES.busy <= irb_busy; + RB_SRES.err <= irb_err; + RB_SRES.dout <= irb_dout; + + MEM_REQ <= imem_reqr or imem_reqw; + MEM_WE <= imem_reqw; + MEM_BE <= imem_be; + MEM_ADDR <= imem_addr; + MEM_DI <= imem_di; + + RB_LAM <= ilam; + + end process proc_next; + + RB_STAT(3) <= '0'; + RB_STAT(2) <= '0'; + RB_STAT(1) <= R_REGS.sfail; + RB_STAT(0) <= R_REGS.srun; + + DSP_DAT <= R_REGS.dispval; + + LED(0) <= MEM_BUSY; + LED(1) <= MEM_ACT_R; + LED(2) <= MEM_ACT_W; + LED(3) <= R_REGS.srun; + LED(4) <= R_REGS.sfail; + LED(5) <= R_REGS.sveri; + LED(6) <= R_REGS.sloop; + LED(7) <= SWI(3) or SWI(2) or SWI(1) or SWI(0) or + BTN(0) or BTN(1) or BTN(2) or BTN(3); + +end syn; Index: trunk/rtl/sys_gen/tst_sram =================================================================== --- trunk/rtl/sys_gen/tst_sram (nonexistent) +++ trunk/rtl/sys_gen/tst_sram (revision 37)
trunk/rtl/sys_gen/tst_sram Property changes : Added: svn:ignore ## -0,0 +1,42 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb Index: trunk/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom =================================================================== --- trunk/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom (revision 36) +++ trunk/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom (revision 37) @@ -11,7 +11,7 @@ ../../../ibus/iblib.vhd ../../../ibus/ibdlib.vhd ../../../w11a/pdp11.vhd -sys_conf = sys_conf.vhd +${sys_conf := sys_conf.vhd} # components [xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom [ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom Index: trunk/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty.vbom =================================================================== --- trunk/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty.vbom (revision 36) +++ trunk/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty.vbom (revision 37) @@ -1,7 +1,9 @@ # configure tb_arty with sys_w11a_br_arty target; # use vhdl configure file (tb_w11a_br_arty.vhd) to allow # that all configurations will co-exist in work library -${basys3_aif := ../sys_w11a_br_arty.vbom} +# configure +arty_aif = ../sys_w11a_br_arty.vbom sys_conf = sys_conf_sim.vhd +# design ../../../../bplib/arty/tb/tb_arty.vbom tb_w11a_br_arty.vhd Index: trunk/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty_ssim.vbom =================================================================== --- trunk/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty_ssim.vbom (revision 36) +++ trunk/rtl/sys_gen/w11a/arty_bram/tb/tb_w11a_br_arty_ssim.vbom (revision 37) @@ -1,6 +1,8 @@ # configure for _*sim case # Note: this tb uses sys_w11a_br_arty.vbom in local directory # (not in .. as usual) to allow a tb specific configure !!! +# configure basys3_aif = sys_w11a_br_arty_ssim.vhd +# design tb_w11a_br_arty.vbom @top:tb_w11a_br_arty Index: trunk/rtl/sys_gen/w11a/arty_bram/tb/tbrun.yml =================================================================== --- trunk/rtl/sys_gen/w11a/arty_bram/tb/tbrun.yml (nonexistent) +++ trunk/rtl/sys_gen/w11a/arty_bram/tb/tbrun.yml (revision 37) @@ -0,0 +1,35 @@ +# $Id: tbrun.yml 809 2016-09-18 19:49:14Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-09-18 809 1.0.1 use 60 sec tout for run_pdpcp tb_pdp11core_stim +# 2016-08-21 799 1.0 Initial version +# +- default: + mode: ${viv_modes} +# +- tag: [default, viv, sys_w11a, br_arty, stim1] + test: | + tbrun_tbwrri --hxon --lsuf stim1 tb_w11a_br_arty${ms} \ + "rlink::run_rri ../../../../w11a/tb/tb_rlink_tba_pdp11core_stim.dat" + +- tag: [default, viv, sys_w11a, br_arty, mem70] + test: | + tbrun_tbwrri --hxon --lsuf mem70 --pack rw11 tb_w11a_br_arty${ms} \ + "rw11::setup_cpu" "rw11::run_pdpcp ../../tb/tb_w11a_mem70.dat" + +- tag: [default, viv, sys_w11a, br_arty, stim2] + test: | + tbrun_tbwrri --hxon --lsuf stim2 --pack rw11 tb_w11a_br_arty${ms} \ + "rw11::setup_cpu" \ + "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat 60." + +- tag: [default, viv, sys_w11a, br_arty, tbcpu] + test: | + tbrun_tbwrri --hxon --lsuf tbcpu --pack rw11 tb_w11a_br_arty${ms} \ + "rw11::setup_cpu" "rw11::tbench @cpu_all.dat" + +- tag: [default, viv, sys_w11a, br_arty, tbdev] + test: | + tbrun_tbwrri --hxon --lsuf tbdev --pack rw11 tb_w11a_br_arty${ms} \ + "rw11::setup_cpu" "rw11::tbench @dev_all.dat" Index: trunk/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom =================================================================== --- trunk/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom (revision 36) +++ trunk/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom (revision 37) @@ -12,7 +12,7 @@ ../../../ibus/iblib.vhd ../../../ibus/ibdlib.vhd ../../../w11a/pdp11.vhd -sys_conf = sys_conf.vhd +${sys_conf := sys_conf.vhd} # components [xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom [ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom Index: trunk/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3.vbom =================================================================== --- trunk/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3.vbom (revision 36) +++ trunk/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3.vbom (revision 37) @@ -1,7 +1,9 @@ # configure tb_basys3 with sys_w11a_b3 target; # use vhdl configure file (tb_w11a_b3.vhd) to allow # that all configurations will co-exist in work library -${basys3_aif := ../sys_w11a_b3.vbom} +# configure +basys3_aif = ../sys_w11a_b3.vbom sys_conf = sys_conf_sim.vhd +# design ../../../../bplib/basys3/tb/tb_basys3.vbom tb_w11a_b3.vhd Index: trunk/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3_ssim.vbom =================================================================== --- trunk/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3_ssim.vbom (revision 36) +++ trunk/rtl/sys_gen/w11a/basys3/tb/tb_w11a_b3_ssim.vbom (revision 37) @@ -1,6 +1,8 @@ # configure for _*sim case # Note: this tb uses sys_w11a_b3.vbom in local directory # (not in .. as usual) to allow a tb specific configure !!! +# configure basys3_aif = sys_w11a_b3_ssim.vhd +# design tb_w11a_b3.vbom @top:tb_w11a_b3 Index: trunk/rtl/sys_gen/w11a/basys3/tb/tbrun.yml =================================================================== --- trunk/rtl/sys_gen/w11a/basys3/tb/tbrun.yml (nonexistent) +++ trunk/rtl/sys_gen/w11a/basys3/tb/tbrun.yml (revision 37) @@ -0,0 +1,35 @@ +# $Id: tbrun.yml 809 2016-09-18 19:49:14Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-09-18 809 1.0.1 use 60 sec tout for run_pdpcp tb_pdp11core_stim +# 2016-08-13 798 1.0 Initial version +# +- default: + mode: ${viv_modes} +# +- tag: [default, viv, sys_w11a, b3, stim1] + test: | + tbrun_tbwrri --hxon --lsuf stim1 tb_w11a_b3${ms} \ + "rlink::run_rri ../../../../w11a/tb/tb_rlink_tba_pdp11core_stim.dat" + +- tag: [default, viv, sys_w11a, b3, mem70] + test: | + tbrun_tbwrri --hxon --lsuf mem70 --pack rw11 tb_w11a_b3${ms} \ + "rw11::setup_cpu" "rw11::run_pdpcp ../../tb/tb_w11a_mem70.dat" + +- tag: [default, viv, sys_w11a, b3, stim2] + test: | + tbrun_tbwrri --hxon --lsuf stim2 --pack rw11 tb_w11a_b3${ms} \ + "rw11::setup_cpu" \ + "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat 60." + +- tag: [default, viv, sys_w11a, b3, tbcpu] + test: | + tbrun_tbwrri --hxon --lsuf tbcpu --pack rw11 tb_w11a_b3${ms} \ + "rw11::setup_cpu" "rw11::tbench @cpu_all.dat" + +- tag: [default, viv, sys_w11a, b3, tbdev] + test: | + tbrun_tbwrri --hxon --lsuf tbdev --pack rw11 tb_w11a_b3${ms} \ + "rw11::setup_cpu" "rw11::tbench @dev_all.dat" Index: trunk/rtl/sys_gen/w11a/nexys2/Makefile =================================================================== --- trunk/rtl/sys_gen/w11a/nexys2/Makefile (revision 36) +++ trunk/rtl/sys_gen/w11a/nexys2/Makefile (revision 37) @@ -1,12 +1,13 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# $Id: Makefile 801 2016-08-27 16:47:01Z mueller $ # # Revision History: # Date Rev Version Comment +# 2016-08-26 801 1.3 use explicit VBOM_all, no wildcard # 2013-04-20 509 1.2 add fx2 support # 2011-08-13 405 1.1 use includes from rtl/make # 2010-05-28 295 1.0 Initial version (derived from _s3 version) # -VBOM_all = $(wildcard *.vbom) +VBOM_all = sys_w11a_n2.vbom BIT_all = $(VBOM_all:.vbom=.bit) # include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk Index: trunk/rtl/sys_gen/w11a/nexys2/sys_conf.vbom =================================================================== --- trunk/rtl/sys_gen/w11a/nexys2/sys_conf.vbom (nonexistent) +++ trunk/rtl/sys_gen/w11a/nexys2/sys_conf.vbom (revision 37) @@ -0,0 +1,5 @@ +# libs +../../../vlib/slvtypes.vhd +../../../bplib/nxcramlib/nxcramlib.vhd +# design +sys_conf.vhd Index: trunk/rtl/sys_gen/w11a/nexys2/sys_conf.vhd =================================================================== --- trunk/rtl/sys_gen/w11a/nexys2/sys_conf.vhd (revision 36) +++ trunk/rtl/sys_gen/w11a/nexys2/sys_conf.vhd (revision 37) @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 770 2016-05-28 14:15:00Z mueller $ +-- $Id: sys_conf.vhd 788 2016-07-16 22:23:23Z mueller $ -- -- Copyright 2010-2016 by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-07-16 788 1.6 use cram_*delay functions to determine delays -- 2016-05-28 770 1.5.1 sys_conf_mem_losize now type natural -- 2016-03-22 750 1.5 add sys_conf_cache_twidth -- 2015-06-26 695 1.4.2 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) @@ -37,13 +38,8 @@ use ieee.std_logic_1164.all; use work.slvtypes.all; +use work.nxcramlib.all; --- valid system clock / delay combinations: --- div mul clksys read0 read1 write --- 1 1 50.0 2 2 3 --- 25 27 54.0 3 3 3 --- 25 29 58.0 3 3 4 - package sys_conf is -- configure clocks -------------------------------------------------------- @@ -66,9 +62,7 @@ constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable -- configure memory controller --------------------------------------------- - constant sys_conf_memctl_read0delay : positive := 3; - constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; - constant sys_conf_memctl_writedelay : positive := 4; + -- now under derived constants -- configure w11 cpu core -------------------------------------------------- constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte @@ -99,4 +93,11 @@ constant sys_conf_ser2rri_cdinit : integer := (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + constant sys_conf_memctl_read0delay : positive := + cram_read0delay(sys_conf_clksys_mhz); + constant sys_conf_memctl_read1delay : positive := + cram_read1delay(sys_conf_clksys_mhz); + constant sys_conf_memctl_writedelay : positive := + cram_writedelay(sys_conf_clksys_mhz); + end package sys_conf;
/trunk/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom
13,7 → 13,7
../../../ibus/iblib.vhd
../../../ibus/ibdlib.vhd
../../../w11a/pdp11.vhd
sys_conf = sys_conf.vhd
${sys_conf := sys_conf.vbom}
# components
[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom
/trunk/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
1,4 → 1,4
-- $Id: sys_w11a_n2.vhd 748 2016-03-20 15:18:50Z mueller $
-- $Id: sys_w11a_n2.vhd 791 2016-07-21 22:01:10Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
423,7 → 423,7
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
 
SRAM_CTL: nx_cram_memctl_as -- memory controller -----------------
CRAMCTL: nx_cram_memctl_as -- memory controller -----------------
generic map (
READ0DELAY => sys_conf_memctl_read0delay,
READ1DELAY => sys_conf_memctl_read1delay,
/trunk/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vbom
0,0 → 1,5
# libs
../../../../vlib/slvtypes.vhd
../../../../bplib/nxcramlib/nxcramlib.vhd
# design
sys_conf_sim.vhd
/trunk/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 770 2016-05-28 14:15:00Z mueller $
-- $Id: sys_conf_sim.vhd 788 2016-07-16 22:23:23Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,6 → 19,7
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.6 use cram_*delay functions to determine delays
-- 2016-05-28 770 1.5.1 sys_conf_mem_losize now type natural
-- 2016-03-22 750 1.5 add sys_conf_cache_twidth
-- 2015-06-26 695 1.4.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
35,6 → 36,7
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.nxcramlib.all;
 
package sys_conf is
 
53,9 → 55,7
constant sys_conf_fx2_ccwidth : positive := 5;
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_read0delay : positive := 3;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 4;
-- now under derived constants
 
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
90,4 → 90,11
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
 
end package sys_conf;
/trunk/rtl/sys_gen/w11a/nexys2/tb/tb_w11a_n2.vbom
1,7 → 1,9
# configure tb_nexys2_fusp_cuff with sys_w11a_n2 target;
# use vhdl configure file (tb_w11a_n2.vhd) to allow
# that all configurations will co-exist in work library
# configure
nexys2_fusp_cuff_aif = ../sys_w11a_n2.vbom
sys_conf = sys_conf_sim.vhd
sys_conf = sys_conf_sim.vbom
# design
../../../../bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom
tb_w11a_n2.vhd
/trunk/rtl/sys_gen/w11a/nexys2/tb/tb_w11a_n2_ssim.vbom
1,6 → 1,8
# configure for _*sim case
# Note: this tb uses sys_w11a_n2.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
# configure
nexys2_fusp_cuff_aif = sys_w11a_n2_ssim.vhd
# design
tb_w11a_n2.vbom
@top:tb_w11a_n2
/trunk/rtl/sys_gen/w11a/nexys2/tb/tbrun.yml
0,0 → 1,41
# $Id: tbrun.yml 809 2016-09-18 19:49:14Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-09-18 809 1.1.1 use 60 sec tout for run_pdpcp tb_pdp11core_stim
# 2016-08-28 803 1.1 use ${ise_modes_noisim} when ISim can't be used
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${ise_modes_noisim}
#
- tag: [default, ise, sys_w11a, n2, stim1]
test: |
tbrun_tbwrri --cuff --lsuf stim1 tb_w11a_n2${ms} \
"rlink::run_rri ../../../../w11a/tb/tb_rlink_tba_pdp11core_stim.dat"
 
- tag: [default, ise, sys_w11a, n2, mem70]
test: |
tbrun_tbwrri --cuff --lsuf mem70 --pack rw11 tb_w11a_n2${ms} \
"rw11::setup_cpu" "rw11::run_pdpcp ../../tb/tb_w11a_mem70.dat"
 
- tag: [default, ise, sys_w11a, n2, mem70_n2]
test: |
tbrun_tbwrri --cuff --lsuf mem70_n2 --pack rw11 tb_w11a_n2${ms} \
"rw11::setup_cpu" "rw11::run_pdpcp ../../tb/tb_w11a_mem70_n2.dat"
 
- tag: [default, ise, sys_w11a, n2, stim2]
test: |
tbrun_tbwrri --cuff --lsuf stim2 --pack rw11 tb_w11a_n2${ms} \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat 60."
 
- tag: [default, ise, sys_w11a, n2, tbcpu]
test: |
tbrun_tbwrri --cuff --lsuf tbcpu --pack rw11 tb_w11a_n2${ms} \
"rw11::setup_cpu" "rw11::tbench @cpu_all.dat"
 
- tag: [default, ise, sys_w11a, n2, tbdev]
test: |
tbrun_tbwrri --cuff --lsuf tbdev --pack rw11 tb_w11a_n2${ms} \
"rw11::setup_cpu" "rw11::tbench @dev_all.dat"
/trunk/rtl/sys_gen/w11a/nexys3/Makefile
1,11 → 1,12
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
# $Id: Makefile 801 2016-08-27 16:47:01Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-26 801 1.3 use explicit VBOM_all, no wildcard
# 2013-04-20 509 1.2 add fx2 support
# 2011-11-20 430 1.0 Initial version (derived from _n2 version)
#
VBOM_all = $(wildcard *.vbom)
VBOM_all = sys_w11a_n3.vbom
BIT_all = $(VBOM_all:.vbom=.bit)
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk
/trunk/rtl/sys_gen/w11a/nexys3/sys_conf.vbom
0,0 → 1,5
# libs
../../../vlib/slvtypes.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
# design
sys_conf.vhd
/trunk/rtl/sys_gen/w11a/nexys3/sys_conf.vhd
1,4 → 1,4
-- $Id: sys_conf.vhd 770 2016-05-28 14:15:00Z mueller $
-- $Id: sys_conf.vhd 788 2016-07-16 22:23:23Z mueller $
--
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,6 → 19,8
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.7 use cram_*delay functions to determine delays
-- 2016-07-10 786 1.6 memctl with page mode, new read1delay
-- 2016-05-28 770 1.5.1 sys_conf_mem_losize now type natural
-- 2016-03-22 750 1.5 add sys_conf_cache_twidth
-- 2015-06-26 695 1.4.2 add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
38,16 → 40,8
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.nxcramlib.all;
 
-- valid system clock / delay combinations (see n2_cram_memctl_as.vhd):
-- div mul clksys read0 read1 write
-- 2 1 50.0 2 2 3
-- 4 3 75.0 4 4 5 (also 70 MHz)
-- 5 4 80.0 5 5 5
-- 20 17 85.0 5 5 6
-- 10 9 90.0 6 6 6 (also 95 MHz)
-- 1 1 100.0 6 6 7
 
package sys_conf is
 
-- configure clocks --------------------------------------------------------
65,9 → 59,7
constant sys_conf_fx2_ccwidth : positive := 5;
 
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_read0delay : positive := 4;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 5;
-- now under derived constants
 
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
106,5 → 98,12
 
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
 
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
 
end package sys_conf;
/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom
13,7 → 13,7
../../../ibus/iblib.vhd
../../../ibus/ibdlib.vhd
../../../w11a/pdp11.vhd
sys_conf = sys_conf.vhd
${sys_conf := sys_conf.vbom}
# components
[xst,vsyn]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd
1,4 → 1,4
-- $Id: sys_w11a_n3.vhd 748 2016-03-20 15:18:50Z mueller $
-- $Id: sys_w11a_n3.vhd 791 2016-07-21 22:01:10Z mueller $
--
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
395,7 → 395,7
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
 
SRAM_CTL: nx_cram_memctl_as -- memory controller -----------------
CRAMCTL: nx_cram_memctl_as -- memory controller -----------------
generic map (
READ0DELAY => sys_conf_memctl_read0delay,
READ1DELAY => sys_conf_memctl_read1delay,
/trunk/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vbom
0,0 → 1,5
# libs
../../../../vlib/slvtypes.vhd
../../../../bplib/nxcramlib/nxcramlib.vhd
# design
sys_conf_sim.vhd
/trunk/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 770 2016-05-28 14:15:00Z mueller $
-- $Id: sys_conf_sim.vhd 788 2016-07-16 22:23:23Z mueller $
--
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,6 → 19,7
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.7 use cram_*delay functions to determine delays
-- 2016-05-28 770 1.6.1 sys_conf_mem_losize now type natural
-- 2016-03-22 750 1.6 add sys_conf_cache_twidth
-- 2015-12-26 718 1.5.2 use clksys=64 (as since r692 in sys_conf.vhd)
35,6 → 36,7
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.nxcramlib.all;
 
package sys_conf is
 
53,9 → 55,7
constant sys_conf_fx2_ccwidth : positive := 5;
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_read0delay : positive := 4; -- for <75 MHz (???)
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 5;
-- now under derived constants
 
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
92,4 → 92,11
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
 
end package sys_conf;
/trunk/rtl/sys_gen/w11a/nexys3/tb/tb_w11a_n3.vbom
1,7 → 1,9
# configure tb_nexys3_fusp with sys_w11a_n3 target;
# use vhdl configure file (tb_w11a_n3.vhd) to allow
# that all configurations will co-exist in work library
# configure
nexys3_fusp_cuff_aif = ../sys_w11a_n3.vbom
sys_conf = sys_conf_sim.vhd
sys_conf = sys_conf_sim.vbom
# design
../../../../bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom
tb_w11a_n3.vhd
/trunk/rtl/sys_gen/w11a/nexys3/tb/tb_w11a_n3_ssim.vbom
1,6 → 1,8
# configure for _*sim case
# Note: this tb uses sys_w11a_n3.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
# configure
nexys3_fusp_cuff_aif = sys_w11a_n3_ssim.vhd
# design
tb_w11a_n3.vbom
@top:tb_w11a_n3
/trunk/rtl/sys_gen/w11a/nexys3/tb/tbrun.yml
0,0 → 1,41
# $Id: tbrun.yml 809 2016-09-18 19:49:14Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-09-18 809 1.1.1 use 60 sec tout for run_pdpcp tb_pdp11core_stim
# 2016-08-28 803 1.1 use ${ise_modes_noisim} when ISim can't be used
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${ise_modes_noisim}
#
- tag: [default, ise, sys_w11a, n3, stim1]
test: |
tbrun_tbwrri --cuff --lsuf stim1 tb_w11a_n3${ms} \
"rlink::run_rri ../../../../w11a/tb/tb_rlink_tba_pdp11core_stim.dat"
 
- tag: [default, ise, sys_w11a, n3, mem70]
test: |
tbrun_tbwrri --cuff --lsuf mem70 --pack rw11 tb_w11a_n3${ms} \
"rw11::setup_cpu" "rw11::run_pdpcp ../../tb/tb_w11a_mem70.dat"
 
- tag: [default, ise, sys_w11a, n3, mem70_n2]
test: |
tbrun_tbwrri --cuff --lsuf mem70_n2 --pack rw11 tb_w11a_n3${ms} \
"rw11::setup_cpu" "rw11::run_pdpcp ../../tb/tb_w11a_mem70_n2.dat"
 
- tag: [default, ise, sys_w11a, n3, stim2]
test: |
tbrun_tbwrri --cuff --lsuf stim2 --pack rw11 tb_w11a_n3${ms} \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat 60."
 
- tag: [default, ise, sys_w11a, n3, tbcpu]
test: |
tbrun_tbwrri --cuff --lsuf tbcpu --pack rw11 tb_w11a_n3${ms} \
"rw11::setup_cpu" "rw11::tbench @cpu_all.dat"
 
- tag: [default, ise, sys_w11a, n3, tbdev]
test: |
tbrun_tbwrri --cuff --lsuf tbdev --pack rw11 tb_w11a_n3${ms} \
"rw11::setup_cpu" "rw11::tbench @dev_all.dat"
/trunk/rtl/sys_gen/w11a/nexys4/Makefile
1,10 → 1,11
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
# $Id: Makefile 801 2016-08-27 16:47:01Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-26 801 1.1 use explicit VBOM_all, no wildcard
# 2015-01-25 637 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
VBOM_all = sys_w11a_n4.vbom
BIT_all = $(VBOM_all:.vbom=.bit)
#
include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk
/trunk/rtl/sys_gen/w11a/nexys4/sys_conf.vbom
0,0 → 1,5
# libs
../../../vlib/slvtypes.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
# design
sys_conf.vhd
/trunk/rtl/sys_gen/w11a/nexys4/sys_conf.vhd
1,4 → 1,4
-- $Id: sys_conf.vhd 775 2016-06-18 13:42:00Z mueller $
-- $Id: sys_conf.vhd 788 2016-07-16 22:23:23Z mueller $
--
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,6 → 19,7
-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.5 use cram_*delay functions to determine delays
-- 2016-06-18 775 1.4.5 use PLL for clkser_gentype
-- 2016-06-04 772 1.4.4 go for 80 MHz and 64 kB cache, best compromise
-- 2016-05-28 771 1.4.3 set dmcmon_awidth=0, useless without dmscnt
37,16 → 38,8
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.nxcramlib.all;
 
-- valid system clock / delay combinations (see n2_cram_memctl_as.vhd):
-- div mul clksys read0 read1 write
-- 2 1 50.0 2 2 3
-- 4 3 75.0 4 4 5 (also 70 MHz)
-- 5 4 80.0 5 5 5
-- 20 17 85.0 5 5 6
-- 10 9 90.0 6 6 6 (also 95 MHz)
-- 1 1 100.0 6 6 7
 
package sys_conf is
 
-- configure clocks --------------------------------------------------------
65,9 → 58,7
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
 
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_read0delay : positive := 5;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 5;
-- now under derived constants
 
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
112,4 → 103,12
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
 
end package sys_conf;
/trunk/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom
13,7 → 13,7
../../../ibus/iblib.vhd
../../../ibus/ibdlib.vhd
../../../w11a/pdp11.vhd
sys_conf = sys_conf.vhd
${sys_conf := sys_conf.vbom}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
/trunk/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd
1,4 → 1,4
-- $Id: sys_w11a_n4.vhd 768 2016-05-26 16:47:00Z mueller $
-- $Id: sys_w11a_n4.vhd 791 2016-07-21 22:01:10Z mueller $
--
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
393,7 → 393,7
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
 
CRAM_CTL: nx_cram_memctl_as -- memory controller -----------------
CRAMCTL: nx_cram_memctl_as -- memory controller -----------------
generic map (
READ0DELAY => sys_conf_memctl_read0delay,
READ1DELAY => sys_conf_memctl_read1delay,
/trunk/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vbom
0,0 → 1,5
# libs
../../../../vlib/slvtypes.vhd
../../../../bplib/nxcramlib/nxcramlib.vhd
# design
sys_conf_sim.vhd
/trunk/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 775 2016-06-18 13:42:00Z mueller $
-- $Id: sys_conf_sim.vhd 788 2016-07-16 22:23:23Z mueller $
--
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,6 → 19,7
-- Tool versions: xst 14.5-14.7; viv 2016.1-2016.2; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.5 use cram_*delay functions to determine delays
-- 2016-06-18 775 1.4.5 use PLL for clkser_gentype
-- 2016-06-04 772 1.4.4 go for 80 MHz and 64 kB cache, best compromise
-- 2016-05-28 771 1.4.3 set dmcmon_awidth=0, useless without dmscnt
37,6 → 38,7
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.nxcramlib.all;
 
package sys_conf is
 
56,9 → 58,7
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_read0delay : positive := 6; -- for 100 MHz
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 7;
-- now under derived constants
 
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
100,4 → 100,12
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
 
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
 
end package sys_conf;
/trunk/rtl/sys_gen/w11a/nexys4/tb/tb_w11a_n4.vbom
1,7 → 1,9
# configure tb_nexys4_cram with sys_w11a_n4 target;
# use vhdl configure file (tb_w11a_n4.vhd) to allow
# that all configurations will co-exist in work library
# configure
nexys4_cram_aif = ../sys_w11a_n4.vbom
sys_conf = sys_conf_sim.vhd
sys_conf = sys_conf_sim.vbom
# design
../../../../bplib/nexys4/tb/tb_nexys4_cram.vbom
tb_w11a_n4.vhd
/trunk/rtl/sys_gen/w11a/nexys4/tb/tb_w11a_n4_ssim.vbom
1,6 → 1,8
# configure for _*sim case
# Note: this tb uses sys_w11a_n4.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
# configure
nexys4_cram_aif = sys_w11a_n4_ssim.vhd
# design
tb_w11a_n4.vbom
@top:tb_w11a_n4
/trunk/rtl/sys_gen/w11a/nexys4/tb/tbrun.yml
0,0 → 1,40
# $Id: tbrun.yml 809 2016-09-18 19:49:14Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-09-18 809 1.0.1 use 60 sec tout for run_pdpcp tb_pdp11core_stim
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [default, viv, sys_w11a, n4, stim1]
test: |
tbrun_tbwrri --lsuf stim1 tb_w11a_n4${ms} \
"rlink::run_rri ../../../../w11a/tb/tb_rlink_tba_pdp11core_stim.dat"
 
- tag: [default, viv, sys_w11a, n4, mem70]
test: |
tbrun_tbwrri --lsuf mem70 --pack rw11 tb_w11a_n4${ms} \
"rw11::setup_cpu" "rw11::run_pdpcp ../../tb/tb_w11a_mem70.dat"
 
- tag: [default, viv, sys_w11a, n4, mem70_n2]
test: |
tbrun_tbwrri --lsuf mem70_n2 --pack rw11 tb_w11a_n4${ms} \
"rw11::setup_cpu" "rw11::run_pdpcp ../../tb/tb_w11a_mem70_n2.dat"
 
- tag: [default, viv, sys_w11a, n4, stim2]
test: |
tbrun_tbwrri --lsuf stim2 --pack rw11 tb_w11a_n4${ms} \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat 60."
 
- tag: [default, viv, sys_w11a, n4, tbcpu]
test: |
tbrun_tbwrri --lsuf tbcpu --pack rw11 tb_w11a_n4${ms} \
"rw11::setup_cpu" "rw11::tbench @cpu_all.dat"
 
- tag: [default, viv, sys_w11a, n4, tbdev]
test: |
tbrun_tbwrri --lsuf tbdev --pack rw11 tb_w11a_n4${ms} \
"rw11::setup_cpu" "rw11::tbench @dev_all.dat"
/trunk/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom
10,7 → 10,7
../../../ibus/iblib.vhd
../../../ibus/ibdlib.vhd
../../../w11a/pdp11.vhd
sys_conf = sys_conf.vhd
${sys_conf := sys_conf.vhd}
# components
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
/trunk/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
1,4 → 1,4
-- $Id: sys_w11a_s3.vhd 748 2016-03-20 15:18:50Z mueller $
-- $Id: sys_w11a_s3.vhd 791 2016-07-21 22:01:10Z mueller $
--
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
393,7 → 393,7
EI_VECT => EI_VECT,
DISPREG => DISPREG);
 
SRAM_CTL: s3_sram_memctl -- memory controller -----------------
SRAMCTL: s3_sram_memctl -- memory controller -----------------
port map (
CLK => CLK,
RESET => GRESET,
/trunk/rtl/sys_gen/w11a/s3board/tb/tb_w11a_s3.vbom
1,7 → 1,9
# configure tb_s3board_fusp with sys_w11a_s3 target;
# use vhdl configure file (tb_w11a_s3.vhd) to allow
# that all configurations will co-exist in work library
# configure
s3board_fusp_aif = ../sys_w11a_s3.vbom
sys_conf = sys_conf_sim.vhd
# design
../../../../bplib/s3board/tb/tb_s3board_fusp.vbom
tb_w11a_s3.vhd
/trunk/rtl/sys_gen/w11a/s3board/tb/tb_w11a_s3_ssim.vbom
1,6 → 1,8
# configure for _*sim case
# Note: this tb uses sys_w11a_s3.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
# configure
s3board_fusp_aif = sys_w11a_s3_ssim.vhd
# design
tb_w11a_s3.vbom
@top:tb_w11a_s3
/trunk/rtl/sys_gen/w11a/s3board/tb/tbrun.yml
0,0 → 1,41
# $Id: tbrun.yml 809 2016-09-18 19:49:14Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-09-18 809 1.1.1 use 60 sec tout for run_pdpcp tb_pdp11core_stim
# 2016-08-28 803 1.1 use ${ise_modes_noisim} when ISim can't be used
# 2016-08-13 798 1.0 Initial version
#
- default:
mode: ${ise_modes_noisim}
#
- tag: [default, ise, sys_w11a, s3, stim1]
test: |
tbrun_tbwrri --lsuf stim1 tb_w11a_s3${ms} \
"rlink::run_rri ../../../../w11a/tb/tb_rlink_tba_pdp11core_stim.dat"
 
- tag: [default, ise, sys_w11a, s3, mem70]
test: |
tbrun_tbwrri --lsuf mem70 --pack rw11 tb_w11a_s3${ms} \
"rw11::setup_cpu" "rw11::run_pdpcp ../../tb/tb_w11a_mem70.dat"
 
- tag: [default, ise, sys_w11a, s3, mem70_s3]
test: |
tbrun_tbwrri --lsuf mem70_s3 --pack rw11 tb_w11a_s3${ms} \
"rw11::setup_cpu" "rw11::run_pdpcp ../../tb/tb_w11a_mem70_s3.dat"
 
- tag: [default, ise, sys_w11a, s3, stim2]
test: |
tbrun_tbwrri --lsuf stim2 --pack rw11 tb_w11a_s3${ms} \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat 60."
 
- tag: [default, ise, sys_w11a, s3, tbcpu]
test: |
tbrun_tbwrri --lsuf tbcpu --pack rw11 tb_w11a_s3${ms} \
"rw11::setup_cpu" "rw11::tbench @cpu_all.dat"
 
- tag: [default, ise, sys_w11a, s3, tbdev]
test: |
tbrun_tbwrri --lsuf tbdev --pack rw11 tb_w11a_s3${ms} \
"rw11::setup_cpu" "rw11::tbench @dev_all.dat"
/trunk/rtl/sys_gen/w11a/tb/tb_w11a_mem70.dat
0,0 → 1,186
# $Id: tb_w11a_mem70.dat 802 2016-08-27 19:00:23Z mueller $
#
# Tests generic parts of 11/70 memory system
#
# Revision History:
# Date Rev Version Comment
# 2016-08-27 802 1.4 changed to accommodate up to 128 kByte cache size
# 2010-06-13 305 1.3 rename lal,lah -> wal,wah; replace 'sta' -> 'stapc'
# 2010-06-05 301 1.2.1 move size register check to new _s3 and _n2.dat
# 2008-03-02 121 1.2 moved ubmap+rdma tests to tb/tb_pdp11_core_ubmap.dat
# 2008-02-24 119 1.1 add ubmap and rdma transfers
# 2008-02-23 118 1.0 initial version
#
.mode pdpcp
.tocmd 50
.tostp 100
.togo 5000
.rlmon 0
.rbmon 0
#
.reset
.wait 10
.anena 1
#
#-----------------------------------------------------------------------------
C Test access to 11/70 memory system registers
wal 177740
rmi d=000000 -- 177740: Low Error Address Register
rmi d=000000 -- 177742: High Error Address Register
rmi d=000000 -- 177744: Memory System Error Register
rmi d=000000 -- 177746: Control Register
rmi d=000000 -- 177750: Maintenance Register
rmi d=- -- 177752: Hit/Miss Register
wal 177760
rmi d=- -- 177760: Lower size Register (check access but not value)
rmi d=000000 -- 177762: Upper size Register
#
#-----------------------------------------------------------------------------
# Note on cache:
# - original cache size was 8 kByte
# --> 000000,020000,040000,060000,.. share one cache line
# - the new configurable cache can be as big as 128 kByte
# - the hit/miss tests below will work for up maximal cache size and use
# 22bit mode access and two areas 120 kByte appart
# wah/wal 00/0000xx
# wah/wal 02/0000xx
#
C Test 1: cache basic rmiss test (do we get data from mem on rmiss ?)
#
wal 000000 -- write 00,000000
wah 000100
bwm 8
000000
000002
000004
000006
000010
000012
000014
000016
wal 000000 -- write 02,000000
wah 000102
bwm 8
020000
020002
020004
020006
020010
020012
020014
020016
wal 000000 -- read 00,000000
wah 000100
brm 8
d=000000
d=000002
d=000004
d=000006
d=000010
d=000012
d=000014
d=000016
wal 000000 -- read 02,000000 (will miss)
wah 000102
brm 8
d=020000
d=020002
d=020004
d=020006
d=020010
d=020012
d=020014
d=020016
#-----------------------------------------------------------------------------
C Test 2: Hit/Miss register
#
wal 000004 -- 7 read on same location -> 6 hits
wah 000102
rm d=020004
rm d=020004
rm d=020004
rm d=020004
rm d=020004
rm d=020004
rm d=020004
wal 177752 -- hit/miss reg
rm d=000077 -- 111 111
#
wal 000004 -- 1 read on conflicting address -> 1 miss
wah 000100
rm d=000004
wal 177752 -- hit/miss reg
rm d=000076 -- 111 110
#
wal 000006 -- 1 read on next word in line -> 1 hit
wah 000100
rm d=000006
wal 177752 -- hit/miss reg
rm d=000075 -- 111 101
#
wal 000010 -- read next 4 words -> alternating miss/hit
wah 000100
brm 4
d=000010
d=000012
d=000014
d=000016
wal 177752 -- hit/miss reg
rm d=000025 -- 010 101
#
wal 000020 -- write next 4 words -> 4 miss
wah 000100
bwm 4
000020
000022
000024
000026
wal 177752 -- hit/miss reg
rm d=000020 -- 010 000
#
wal 000020 -- re-read these 4 words -> 4 hit
wah 000100
brm 4
d=000020
d=000022
d=000024
d=000026
wal 177752 -- hit/miss reg
rm d=000017 -- 001 111
#
wal 000010 -- 02,000010 in cache, owerwrite cache line, 1st word
wah 000102
wm 120010 -- write -> miss
rmi d=120010 -- re-read -> hit
rmi d=020012 -- read 2nd -> miss
wal 177752 -- hit/miss reg
rm d=000072 -- 111 010
#-----------------------------------------------------------------------------
C Test 3: Control Register: test force miss bits
#
wal 177746 -- control reg
wm 000014 -- set fmiss bits
rm d=000014
#
wal 000020 -- re-read last 4 words -> 4 forced misses
brm 4
d=000020
d=000022
d=000024
d=000026
wal 177752 -- hit/miss reg
rm d=000040 -- 100 000
#
wal 177746 -- control reg
wm 000000 -- clear fmiss bits again
rm d=000000
#
wal 000020 -- re-read last 4 words -> 4 hits
brm 4
d=000020
d=000022
d=000024
d=000026
wal 177752 -- hit/miss reg
rm d=000017 -- 001 111
#
/trunk/rtl/sys_gen/w11a/tb/tb_w11a_mem70_n2.dat
0,0 → 1,157
# $Id: tb_w11a_mem70_n2.dat 351 2010-12-30 21:50:54Z mueller $
#
# Tests 11/70 memory system, Nexys 2 specific size test and probing
#
# Revision History:
# Date Rev Version Comment
# 2010-06-13 305 1.1 rename lal,lah -> wal,wah; replace 'sta' -> 'stapc'
# 2010-06-06 301 1.0 initial version
#
.mode pdpcp
.tocmd 50
.tostp 100
.togo 5000
.rlmon 0
.rbmon 0
#
.reset
.wait 10
.anena 1
#
#-----------------------------------------------------------------------------
C Test 1: memory system size
wal 177760
rmi d=167777 -- 177760: Lower size Register (for 4MB-256kB system)
rmi d=000000 -- 177762: Upper size Register
#
#-----------------------------------------------------------------------------
C Test 2: probe memory
#
# cache size is 8 kByte --> 000000,020000,040000,060000,.. share one cache line
# Probe 8 areas in memory, 512 kB apart.
# 00,000000 00,000100
# 10,000000 10,000110
# 20,000000 20,000120
# 30,000000 30,000130
# 40,000000 40,000140
# 50,000000 50,000150
# 60,000000 60,000160
# 70,000000 70,000170
#
# write data
#
wal 000000 -- write to 00,000000
wah 000100 -- use 22 bit mode
wm 100000
wal 000100 -- write to 00,000100
wah 000100 -- use 22 bit mode
wm 100100
#
wal 000000 -- write to 10,000000
wah 000110 -- use 22 bit mode
wm 110000
wal 000110 -- write to 10,000110
wah 000110 -- use 22 bit mode
wm 110110
#
wal 000000 -- write to 20,000000
wah 000120 -- use 22 bit mode
wm 120000
wal 000120 -- write to 20,000120
wah 000120 -- use 22 bit mode
wm 120120
#
wal 000000 -- write to 30,000000
wah 000130 -- use 22 bit mode
wm 130000
wal 000130 -- write to 30,000130
wah 000130 -- use 22 bit mode
wm 130130
#
wal 000000 -- write to 40,000000
wah 000140 -- use 22 bit mode
wm 140000
wal 000140 -- write to 40,000140
wah 000140 -- use 22 bit mode
wm 140140
#
wal 000000 -- write to 50,000000
wah 000150 -- use 22 bit mode
wm 150000
wal 000150 -- write to 50,000150
wah 000150 -- use 22 bit mode
wm 150150
#
wal 000000 -- write to 60,000000
wah 000160 -- use 22 bit mode
wm 160000
wal 000160 -- write to 60,000160
wah 000160 -- use 22 bit mode
wm 160160
#
wal 000000 -- write to 70,000000
wah 000170 -- use 22 bit mode
wm 170000
wal 000170 -- write to 70,000170
wah 000170 -- use 22 bit mode
wm 170170
#
#
# read data
#
wal 000000 -- read from 00,000000
wah 000100 -- use 22 bit mode
rm d=100000
wal 000100 -- read from 00,000100
wah 000100 -- use 22 bit mode
rm d=100100
#
wal 000000 -- read from 10,000000
wah 000110 -- use 22 bit mode
rm d=110000
wal 000110 -- read from 10,000110
wah 000110 -- use 22 bit mode
rm d=110110
#
wal 000000 -- read from 20,000000
wah 000120 -- use 22 bit mode
rm d=120000
wal 000120 -- read from 20,000120
wah 000120 -- use 22 bit mode
rm d=120120
#
wal 000000 -- read from 30,000000
wah 000130 -- use 22 bit mode
rm d=130000
wal 000130 -- read from 30,000130
wah 000130 -- use 22 bit mode
rm d=130130
#
wal 000000 -- read from 40,000000
wah 000140 -- use 22 bit mode
rm d=140000
wal 000140 -- read from 40,000140
wah 000140 -- use 22 bit mode
rm d=140140
#
wal 000000 -- read from 50,000000
wah 000150 -- use 22 bit mode
rm d=150000
wal 000150 -- read from 50,000150
wah 000150 -- use 22 bit mode
rm d=150150
#
wal 000000 -- read from 60,000000
wah 000160 -- use 22 bit mode
rm d=160000
wal 000160 -- read from 60,000160
wah 000160 -- use 22 bit mode
rm d=160160
#
wal 000000 -- read from 70,000000
wah 000170 -- use 22 bit mode
rm d=170000
wal 000170 -- read from 70,000170
wah 000170 -- use 22 bit mode
rm d=170170
#
/trunk/rtl/sys_gen/w11a/tb/tb_w11a_mem70_s3.dat
0,0 → 1,157
# $Id: tb_w11a_mem70_s3.dat 351 2010-12-30 21:50:54Z mueller $
#
# Tests 11/70 memory system, S3board specific size test and probing
#
# Revision History:
# Date Rev Version Comment
# 2010-06-13 305 1.1 rename lal,lah -> wal,wah; replace 'sta' -> 'stapc'
# 2010-06-06 301 1.0 initial version
#
.mode pdpcp
.tocmd 50
.tostp 100
.togo 5000
.rlmon 0
.rbmon 0
#
.reset
.wait 10
.anena 1
#
#-----------------------------------------------------------------------------
C Test 1: memory system size
wal 177760
rmi d=037777 -- 177760: Lower size Register (for 1MB system)
rmi d=000000 -- 177762: Upper size Register
#
#-----------------------------------------------------------------------------
C Test 2: probe memory
#
# cache size is 8 kByte --> 000000,020000,040000,060000,.. share one cache line
# Probe 8 areas in memory, 128 kB apart.
# 00,000000 00,000100
# 02,000000 02,000102
# 04,000000 04,000104
# 06,000000 06,000106
# 00,000000 10,000110
# 12,000000 12,000112
# 14,000000 14,000114
# 16,000000 16,000116
#
# write data
#
wal 000000 -- write to 00,000000
wah 000100 -- use 22 bit mode
wm 100000
wal 000100 -- write to 00,000100
wah 000100 -- use 22 bit mode
wm 100100
#
wal 000000 -- write to 02,000000
wah 000102 -- use 22 bit mode
wm 102000
wal 000102 -- write to 02,000102
wah 000102 -- use 22 bit mode
wm 102102
#
wal 000000 -- write to 04,000000
wah 000104 -- use 22 bit mode
wm 104000
wal 000104 -- write to 04,000104
wah 000104 -- use 22 bit mode
wm 104104
#
wal 000000 -- write to 06,000000
wah 000106 -- use 22 bit mode
wm 106000
wal 000106 -- write to 06,000106
wah 000106 -- use 22 bit mode
wm 106106
#
wal 000000 -- write to 10,000000
wah 000110 -- use 22 bit mode
wm 110000
wal 000110 -- write to 10,000110
wah 000110 -- use 22 bit mode
wm 110110
#
wal 000000 -- write to 12,000000
wah 000112 -- use 22 bit mode
wm 112000
wal 000112 -- write to 12,000112
wah 000112 -- use 22 bit mode
wm 112112
#
wal 000000 -- write to 14,000000
wah 000114 -- use 22 bit mode
wm 114000
wal 000114 -- write to 14,000114
wah 000114 -- use 22 bit mode
wm 114114
#
wal 000000 -- write to 16,000000
wah 000116 -- use 22 bit mode
wm 116000
wal 000116 -- write to 16,000116
wah 000116 -- use 22 bit mode
wm 116116
#
#
# read data
#
wal 000000 -- read from 00,000000
wah 000100 -- use 22 bit mode
rm d=100000
wal 000100 -- read from 00,000100
wah 000100 -- use 22 bit mode
rm d=100100
#
wal 000000 -- read from 02,000000
wah 000102 -- use 22 bit mode
rm d=102000
wal 000102 -- read from 02,000102
wah 000102 -- use 22 bit mode
rm d=102102
#
wal 000000 -- read from 04,000000
wah 000104 -- use 22 bit mode
rm d=104000
wal 000104 -- read from 04,000104
wah 000104 -- use 22 bit mode
rm d=104104
#
wal 000000 -- read from 06,000000
wah 000106 -- use 22 bit mode
rm d=106000
wal 000106 -- read from 06,000106
wah 000106 -- use 22 bit mode
rm d=106106
#
wal 000000 -- read from 10,000000
wah 000110 -- use 22 bit mode
rm d=110000
wal 000110 -- read from 10,000110
wah 000110 -- use 22 bit mode
rm d=110110
#
wal 000000 -- read from 12,000000
wah 000112 -- use 22 bit mode
rm d=112000
wal 000112 -- read from 12,000112
wah 000112 -- use 22 bit mode
rm d=112112
#
wal 000000 -- read from 14,000000
wah 000114 -- use 22 bit mode
rm d=114000
wal 000114 -- read from 14,000114
wah 000114 -- use 22 bit mode
rm d=114114
#
wal 000000 -- read from 16,000000
wah 000116 -- use 22 bit mode
rm d=116000
wal 000116 -- read from 16,000116
wah 000116 -- use 22 bit mode
rm d=116116
#
/trunk/rtl/sys_gen/w11a/tbrun.yml
0,0 → 1,12
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-22 800 1.0 Initial version
#
- include: s3board/tb/tbrun.yml
- include: nexys2/tb/tbrun.yml
- include: nexys3/tb/tbrun.yml
- include: nexys4/tb/tbrun.yml
- include: basys3/tb/tbrun.yml
- include: arty_bram/tb/tbrun.yml
/trunk/rtl/vlib/comlib/Makefile
0,0 → 1,37
# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-20 749 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#
/trunk/rtl/vlib/comlib/tb/tb_cdata2byte.vhd
1,4 → 1,4
-- $Id: tb_cdata2byte.vhd 599 2014-10-25 13:43:56Z mueller $
-- $Id: tb_cdata2byte.vhd 790 2016-07-20 18:52:44Z mueller $
--
-- Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
52,7 → 52,7
architecture sim of tb_cdata2byte is
constant clk_dsc : clock_dsc := (20 ns, 1 ns, 1 ns);
constant clk_offset : time := 200 ns;
constant clk_offset : Delay_length := 200 ns;
signal CLK : slbit := '0';
signal RESET : slbit := '0';
/trunk/rtl/vlib/comlib/tb/tb_cdata2byte_ssim.vbom
1,4 → 1,6
# configure for _*sim case
# configure
uut = tbd_cdata2byte_ssim.vhd
# design
tb_cdata2byte.vbom
@top:tb_cdata2byte
/trunk/rtl/vlib/comlib/tb/tbrun.yml
0,0 → 1,12
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-12 797 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [default, viv, comlib, cdata2byte]
test: |
tbrun_tbw tb_cdata2byte${ms}
/trunk/rtl/vlib/genlib/Makefile
0,0 → 1,37
# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-20 749 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#
/trunk/rtl/vlib/genlib/clkdivce.vhd
1,4 → 1,4
-- $Id: clkdivce.vhd 751 2016-03-25 19:46:11Z mueller $
-- $Id: clkdivce.vhd 807 2016-09-17 07:49:26Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
20,12 → 20,15
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- Date Rev Version Comment
-- 2011-10-22 418 1.0.3 now numeric_std clean
-- 2008-01-20 112 1.0.2 rename clkgen->clkdivce; remove SYS_CLK port
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
-- Note: for test bench usage a copy of the clkdivce entity, with _tb
-- appended to the name, has been created in the /tb sub folder.
-- Ensure to update the copy when this file is changed !!
 
library ieee;
use ieee.std_logic_1164.all;
/trunk/rtl/vlib/genlib/tb/.cvsignore
0,0 → 1,7
tb_cnt_array_dram
tb_cnt_array_dram_stim
tb_debounce_gen
tb_debounce_gen_stim
tb_gray_cnt_n
tb_timer
tb_timer_stim
/trunk/rtl/vlib/genlib/tb/Makefile
0,0 → 1,46
# $Id: Makefile 744 2016-03-13 20:28:25Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-13 744 1.0 Initial version
#
EXE_all = tb_cnt_array_dram
EXE_all += tb_debounce_gen
EXE_all += tb_gray_cnt_n
EXE_all += tb_timer
 
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_osim clean
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_osim : $(EXE_all:=_osim)
#
all_XSim : $(EXE_all:=_XSim)
all_XSim_ssim : $(EXE_all:=_XSim_ssim)
all_XSim_osim : $(EXE_all:=_XSim_osim)
all_XSim_tsim : $(EXE_all:=_XSim_tsim)
#
clean : viv_clean ghdl_clean xsim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsim)
endif
#
/trunk/rtl/vlib/genlib/tb/Makefile.ise
0,0 → 1,45
# -*- makefile-gmake -*-
# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2014-07-27 545 1.4.1 make reference board configurable via XTW_BOARD
# 2011-08-13 405 1.4 use includes from rtl/make
# 2010-04-17 277 1.3 add ISim support; add tb_timer
# 2007-12-28 106 1.2.1 add tb_gray_cnt_n
# 2007-11-26 98 1.2 use make includes
# 2007-07-15 66 1.1 use vbomconv
# 2007-06-16 57 1.0 Initial version
#
EXE_all = tb_cnt_array_dram
EXE_all += tb_debounce_gen
EXE_all += tb_gray_cnt_n
EXE_all += tb_timer
#
# reference board for test synthesis is Spartan-6 based Nexys3
ifndef XTW_BOARD
XTW_BOARD=nexys3
endif
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_isim.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
endif
#
/trunk/rtl/vlib/genlib/tb/clkdivce_tb.vbom
0,0 → 1,4
# libs
../../slvtypes.vhd
# design
clkdivce_tb.vhd
/trunk/rtl/vlib/genlib/tb/clkdivce_tb.vhd
0,0 → 1,112
-- $Id: clkdivce_tb.vhd 806 2016-09-10 20:59:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: clkdivce_tb - sim
-- Description: Generate usec and msec enable signals (SIM only!)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-10 806 1.0 Initial version (copied from clkdivce)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
 
entity clkdivce_tb is -- generate usec/msec ce pulses
generic (
CDUWIDTH : positive := 6; -- usec clock divider width
USECDIV : positive := 50; -- divider ratio for usec pulse
MSECDIV : positive := 1000); -- divider ratio for msec pulse
port (
CLK : in slbit; -- input clock
CE_USEC : out slbit; -- usec pulse
CE_MSEC : out slbit -- msec pulse
);
end clkdivce_tb;
 
 
architecture sim of clkdivce_tb is
 
type regs_type is record
ucnt : slv(CDUWIDTH-1 downto 0); -- usec clock divider counter
mcnt : slv10; -- msec clock divider counter
usec : slbit; -- usec pulse
msec : slbit; -- msec pulse
end record regs_type;
 
constant regs_init : regs_type := (
slv(to_unsigned(USECDIV-1,CDUWIDTH)),
slv(to_unsigned(MSECDIV-1,10)),
'0','0'
);
 
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
begin
 
assert USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024
report "assert(USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024): " &
"USECDIV too large for given CDUWIDTH or MSECDIV>1024"
severity failure;
 
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
 
end process proc_regs;
 
proc_next: process (R_REGS)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
begin
 
r := R_REGS;
n := R_REGS;
 
n.usec := '0';
n.msec := '0';
 
n.ucnt := slv(unsigned(r.ucnt) - 1);
if unsigned(r.ucnt) = 0 then
n.usec := '1';
n.ucnt := slv(to_unsigned(USECDIV-1,CDUWIDTH));
n.mcnt := slv(unsigned(r.mcnt) - 1);
if unsigned(r.mcnt) = 0 then
n.msec := '1';
n.mcnt := slv(to_unsigned(MSECDIV-1,10));
end if;
end if;
N_REGS <= n;
 
CE_USEC <= r.usec;
CE_MSEC <= r.msec;
end process proc_next;
 
 
end sim;
/trunk/rtl/vlib/genlib/tb/tbrun.yml
0,0 → 1,12
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-12 797 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [default, viv, genlib]
test: |
tbrun_tbw tb_cnt_array_dram${ms}
/trunk/rtl/vlib/genlib/tb
trunk/rtl/vlib/genlib/tb Property changes : Added: svn:ignore ## -0,0 +1,49 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb +tb_cnt_array_dram +tb_cnt_array_dram_stim +tb_debounce_gen +tb_debounce_gen_stim +tb_gray_cnt_n +tb_timer +tb_timer_stim Index: trunk/rtl/vlib/memlib/Makefile =================================================================== --- trunk/rtl/vlib/memlib/Makefile (nonexistent) +++ trunk/rtl/vlib/memlib/Makefile (revision 37) @@ -0,0 +1,37 @@ +# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-03-20 749 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +DCP_all = $(VBOM_all:.vbom=_syn.dcp) +# +# reference board for test synthesis is Artix-7 based Nexys4 +ifndef XTW_BOARD + XTW_BOARD=nexys4 +endif +include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk +# +.PHONY : catch all +# +catch : + @echo "no default target defined, use" + @echo " make all" + @echo " make _syn.dcp" + @exit 1 +# +all : $(DCP_all) +# +clean : viv_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# Index: trunk/rtl/vlib/memlib/fifo_2c_dram.ucf =================================================================== --- trunk/rtl/vlib/memlib/fifo_2c_dram.ucf (nonexistent) +++ trunk/rtl/vlib/memlib/fifo_2c_dram.ucf (revision 37) @@ -0,0 +1,13 @@ +## $Id: fifo_2c_dram.ucf 109 2008-01-01 22:02:27Z mueller $ +## +## ucf for test synthesis only +## +NET "CLKW" TNM_NET = "CLKW"; +TIMESPEC "TS_CLKW" = PERIOD "CLKW" 20 ns HIGH 50 %; +NET "CLKR" TNM_NET = "CLKR"; +TIMESPEC "TS_CLKR" = PERIOD "CLKR" 20 ns HIGH 50 %; +## +OFFSET = IN 10 ns BEFORE "CLKW"; +OFFSET = IN 10 ns BEFORE "CLKR"; +OFFSET = OUT 20 ns AFTER "CLKW"; +OFFSET = OUT 20 ns AFTER "CLKR"; Index: trunk/rtl/vlib/rbus/Makefile =================================================================== --- trunk/rtl/vlib/rbus/Makefile (nonexistent) +++ trunk/rtl/vlib/rbus/Makefile (revision 37) @@ -0,0 +1,37 @@ +# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-03-20 749 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +DCP_all = $(VBOM_all:.vbom=_syn.dcp) +# +# reference board for test synthesis is Artix-7 based Nexys4 +ifndef XTW_BOARD + XTW_BOARD=nexys4 +endif +include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk +# +.PHONY : catch all +# +catch : + @echo "no default target defined, use" + @echo " make all" + @echo " make _syn.dcp" + @exit 1 +# +all : $(DCP_all) +# +clean : viv_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# Index: trunk/rtl/vlib/rbus/rbd_eyemon.vhd =================================================================== --- trunk/rtl/vlib/rbus/rbd_eyemon.vhd (revision 36) +++ trunk/rtl/vlib/rbus/rbd_eyemon.vhd (revision 37) @@ -1,4 +1,4 @@ --- $Id: rbd_eyemon.vhd 767 2016-05-26 07:47:51Z mueller $ +-- $Id: rbd_eyemon.vhd 784 2016-07-09 22:17:01Z mueller $ -- -- Copyright 2010-2016 by Walter F.J. Mueller -- @@ -29,7 +29,7 @@ -- -- Revision History: -- Date Rev Version Comment --- 2016-05-22 787 4.1.1 don't init N_REGS (vivado fix for fsm inference) +-- 2016-05-22 767 4.1.1 don't init N_REGS (vivado fix for fsm inference) -- 2014-09-13 593 4.1 no default rbus addess anymore, def=0 -- 2014-08-15 583 4.0 rb_mreq addr now 16 bit -- 2011-11-19 427 1.0.3 now numeric_std clean Index: trunk/rtl/vlib/rlink/Makefile =================================================================== --- trunk/rtl/vlib/rlink/Makefile (nonexistent) +++ trunk/rtl/vlib/rlink/Makefile (revision 37) @@ -0,0 +1,37 @@ +# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-03-20 749 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +DCP_all = $(VBOM_all:.vbom=_syn.dcp) +# +# reference board for test synthesis is Artix-7 based Nexys4 +ifndef XTW_BOARD + XTW_BOARD=nexys4 +endif +include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk +# +.PHONY : catch all +# +catch : + @echo "no default target defined, use" + @echo " make all" + @echo " make _syn.dcp" + @exit 1 +# +all : $(DCP_all) +# +clean : viv_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# Index: trunk/rtl/vlib/rlink/rlink_core.vhd =================================================================== --- trunk/rtl/vlib/rlink/rlink_core.vhd (revision 36) +++ trunk/rtl/vlib/rlink/rlink_core.vhd (revision 37) @@ -1,4 +1,4 @@ --- $Id: rlink_core.vhd 767 2016-05-26 07:47:51Z mueller $ +-- $Id: rlink_core.vhd 799 2016-08-21 09:20:19Z mueller $ -- -- Copyright 2007-2016 by Walter F.J. Mueller -- @@ -28,7 +28,7 @@ -- tb/tb_rlink_tba_ttcombo -- -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -39,7 +39,8 @@ -- -- Revision History: -- Date Rev Version Comment --- 2016-05-22 787 4.1.2 don't init N_REGS (vivado fix for fsm inference) +-- 2016-08-18 799 4.1.3 remove 'assert false' from report statements +-- 2016-05-22 767 4.1.2 don't init N_REGS (vivado fix for fsm inference) -- 2015-12-26 718 4.1.1 add proc_sres: strip 'x' from RB_SRES.dout -- 2014-12-21 617 4.1 use stat(_rbf_rbtout) to signal rbus timeout -- 2014-12-20 614 4.0 largely rewritten; 2 FSMs; v3 protocol; 4 bit STAT @@ -520,8 +521,7 @@ sres.dout := to_x01(RB_SRES.dout); if sres.ack = '1' and sres.busy = '0' and is_x(sres.dout) then - assert false - report "rlink_core: seen 'x' in rb_sres.data" + report "rlink_core: seen 'x' in rb_sres.data" severity warning; sres.dout := (others=>'1'); end if;
/trunk/rtl/vlib/rlink/tb/rlink_tba.vbom
0,0 → 1,8
# libs
../../slvtypes.vhd
../../comlib/comlib.vhd
../rlinklib.vbom
rlinktblib.vhd
# components
# design
rlink_tba.vhd
/trunk/rtl/vlib/rlink/tb/rlink_tba.vhd
0,0 → 1,629
-- $Id: rlink_tba.vhd 595 2014-09-28 08:47:45Z mueller $
--
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_tba - syn
-- Description: rlink test bench adapter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic [synthesizable, but only used in tb's]
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-09-27 595 4.0 now full rlink v4 iface
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit; add state r_txal;
-- 2011-11-22 432 3.0.2 now numeric_std clean
-- 2011-11-19 427 3.0.1 fix crc8_update usage;
-- 2010-12-24 347 3.0 rename rritba->rlink_tba, CP_*->RL_*; rbus v3 port;
-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-05-05 289 1.0.3 drop dead snooper code and unneeded unsigned casts
-- 2008-03-02 121 1.0.2 remove snoopers
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.comlib.all;
use work.rlinklib.all;
use work.rlinktblib.all;
 
entity rlink_tba is -- rlink test bench adapter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CNTL : in rlink_tba_cntl_type; -- control port
DI : in slv16; -- input data
STAT : out rlink_tba_stat_type; -- status port
DO : out slv16; -- output data
RL_DI : out slv9; -- rlink: data in
RL_ENA : out slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv9; -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : out slbit -- rlink: data hold
);
end entity rlink_tba;
 
 
architecture syn of rlink_tba is
 
constant d_f_cflag : integer := 8; -- d9: comma flag
subtype d_f_data is integer range 7 downto 0; -- d9: data field
 
subtype f_byte1 is integer range 15 downto 8;
subtype f_byte0 is integer range 7 downto 0;
 
type txstate_type is (
s_txidle, -- s_txidle: wait for ENA
s_txsop, -- s_txsop: send sop
s_txeop, -- s_txeop: send eop
s_txcmd, -- s_txcmd: send cmd
s_txal, -- s_txal: send addr lsb
s_txah, -- s_txah: send addr msb
s_txcl, -- s_txcl: send blk count lsb
s_txch, -- s_txcl: send blk count msb
s_txdl, -- s_txdl: send data lsb
s_txdh, -- s_txdh: send data msb
s_txcrcl1, -- s_txcrcl1: send cmd crc lsb in wblk
s_txcrch1, -- s_txcrch1: send cmd crc msb in wblk
s_txwbld, -- s_txwbld: wblk data load
s_txwbdl, -- s_txwbdl: wblk send data lsb
s_txwbdh, -- s_txwbdh: wblk send data msb
s_txcrcl2, -- s_txcrcl2: send final crc lsb
s_txcrch2 -- s_txcrch2: send final crc msb
);
type txregs_type is record
state : txstate_type; -- state
ccmd : slv3; -- current command
snum : slv5; -- command sequence number
crc : slv16; -- crc (cmd and data)
braddr : slv16; -- block read address
bdata : slv16; -- block data
bloop : slbit; -- block loop flag
tcnt : slv16; -- tcnt (down count for wblk)
sopdone : slbit; -- sop send
eoppend : slbit; -- eop pending
end record txregs_type;
 
constant txregs_init : txregs_type := (
s_txidle, -- state
"000", -- ccmd
"00000", -- snum
(others=>'0'), -- crc
(others=>'0'), -- braddr
(others=>'0'), -- bdata
'0', -- bloop
(others=>'0'), -- tcnt
'0','0' -- sopdone, eoppend
);
 
type rxstate_type is (
s_rxidle, -- s_rxidle: wait for ENA
s_rxcmd, -- s_rxcmd: wait cmd
s_rxcl, -- s_rxcl: wait cnt lsb
s_rxch, -- s_rxcl: wait cnt msb
s_rxbabo, -- s_rxbabo: wait babo
s_rxdcl, -- s_rxdcl: wait dcnt lsb
s_rxdch, -- s_rxdch: wait dcnt msb
s_rxdl, -- s_rxdl: wait data lsb
s_rxdh, -- s_rxdh: wait data msb
s_rxstat, -- s_rxstat: wait status
s_rxcrcl, -- s_rxcrcl: wait crc lsb
s_rxcrch, -- s_rxcrch: wait crc msb
s_rxapl, -- s_rxapl: wait attn pat lsb
s_rxaph, -- s_rxaph: wait attn pat msb
s_rxacl, -- s_rxapl: wait attn crc lsb
s_rxach -- s_rxaph: wait attn crc msb
);
type rxregs_type is record
state : rxstate_type; -- state
ccmd : slv3; -- current command
crc : slv16; -- crc
bwaddr : slv16; -- block write address
data : slv16; -- received data
dcnt : slv16; -- done count
tcnt : slv16; -- tcnt (down count for rblk)
ack : slbit; -- ack flag
err : slbit; -- crc error flag
stat : slv8; -- stat
apend : slbit; -- attn pending
ano : slbit; -- attn notify seen
apat : slv16; -- attn pat
end record rxregs_type;
 
constant rxregs_init : rxregs_type := (
s_rxidle, -- state
"000", -- ccmd
(others=>'0'), -- crc
(others=>'0'), -- bwaddr
(others=>'0'), -- data
(others=>'0'), -- dcnt
(others=>'0'), -- tcnt
'0','0', -- ack, err
(others=>'0'), -- stat
'0','0', -- apend, ano
(others=>'0') -- attn pat
);
signal R_TXREGS : txregs_type := txregs_init; -- TX state registers
signal N_TXREGS : txregs_type := txregs_init; -- TX next value state regs
 
signal R_RXREGS : rxregs_type := rxregs_init; -- RX state registers
signal N_RXREGS : rxregs_type := rxregs_init; -- RX next value state regs
 
signal TXBUSY : slbit := '0';
signal RXBUSY : slbit := '0';
 
signal STAT_L : rlink_tba_stat_type := rlink_tba_stat_init; -- local, readable
 
begin
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_TXREGS <= txregs_init;
R_RXREGS <= rxregs_init;
else
R_TXREGS <= N_TXREGS;
R_RXREGS <= N_RXREGS;
end if;
end if;
 
end process proc_regs;
 
-- tx FSM ==================================================================
proc_txnext: process (R_TXREGS, CNTL, DI, RL_BUSY)
variable r : txregs_type := txregs_init;
variable n : txregs_type := txregs_init;
 
variable itxbusy : slbit := '0';
variable icpdi : slv9 := (others=>'0');
variable iena : slbit := '0';
variable ibre : slbit := '0';
variable do_crc : slbit := '0';
 
begin
 
r := R_TXREGS;
n := R_TXREGS;
 
itxbusy := '1';
icpdi := (others=>'0');
iena := '0';
ibre := '0';
do_crc := '0';
 
if CNTL.eop='1' and r.state/= s_txidle then -- if eop requested and busy
n.eoppend := '1'; -- queue it
end if;
case r.state is
when s_txidle => -- s_txidle: wait for ENA ------------
itxbusy := '0';
if CNTL.ena = '1' then -- cmd requested
n.ccmd := CNTL.cmd;
if CNTL.eop = '1' then -- if eop requested with ENA
n.eoppend := '1'; -- queue it, eop after this cmd
end if;
if r.sopdone = '0' then -- if not in active packet
n.snum := (others=>'0'); -- set snum=0
n.state := s_txsop; -- send sop
else
n.state := s_txcmd;
end if;
else -- no cmd requested
if CNTL.eop='1' and r.sopdone='1' then -- if eop req and in packet
n.state := s_txeop; -- send eop
end if;
end if;
when s_txsop => -- s_txsop: send sop -----------------
n.sopdone := '1';
icpdi := c_rlink_dat_sop;
iena := '1';
if RL_BUSY = '0' then
n.crc := (others=>'0');
n.state := s_txcmd;
end if;
 
when s_txeop => -- s_txeop: send eop -----------------
n.sopdone := '0';
n.eoppend := '0';
icpdi := c_rlink_dat_eop;
iena := '1';
if RL_BUSY = '0' then
n.crc := (others=>'0');
n.state := s_txidle;
end if;
 
when s_txcmd => -- s_txcmd: send cmd -----------------
n.tcnt := CNTL.cnt;
n.braddr := (others=>'0');
icpdi(c_rlink_cmd_rbf_seq) := r.snum;
icpdi(c_rlink_cmd_rbf_code) := r.ccmd;
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.snum := slv(unsigned(r.snum) + 1);-- otherwise just increment snum
case r.ccmd is
when c_rlink_cmd_labo => n.state := s_txcrcl2;
when c_rlink_cmd_attn => n.state := s_txcrcl2;
when others => n.state := s_txal;
end case;
end if;
 
when s_txal => -- s_txal: send addr lsb -------------
icpdi := '0' & CNTL.addr(f_byte0);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txah;
end if;
when s_txah => -- s_txah: send addr msb -------------
icpdi := '0' & CNTL.addr(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
case r.ccmd is
when c_rlink_cmd_rreg => n.state := s_txcrcl2;
when c_rlink_cmd_rblk => n.state := s_txcl;
when c_rlink_cmd_wblk => n.state := s_txcl;
when others => n.state := s_txdl;
end case;
end if;
when s_txcl => -- s_txcl: send blk count lsb -------
icpdi := '0' & CNTL.cnt(f_byte0);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txch;
end if;
when s_txch => -- s_txch: send blk count msb -------
icpdi := '0' & CNTL.cnt(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
if r.ccmd = c_rlink_cmd_wblk then
n.state := s_txcrcl1;
else
n.state := s_txcrcl2;
end if;
end if;
when s_txdl => -- s_txdl: send data lsb -------------
icpdi := '0' & DI(d_f_data);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txdh;
end if;
when s_txdh => -- s_txdh: send data msb -------------
icpdi := '0' & DI(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txcrcl2;
end if;
 
when s_txcrcl1 => -- s_txcrcl1: send cmd crc lsb in wblk
icpdi := '0' & r.crc(f_byte0);
iena := '1';
if RL_BUSY = '0' then
n.state := s_txcrch1;
end if;
 
when s_txcrch1 => -- s_txcrch1: send cmd crc msb in wblk
icpdi := '0' & r.crc(f_byte1);
iena := '1';
if RL_BUSY = '0' then
n.state := s_txwbld;
end if;
 
when s_txwbld => -- s_txwbld: wblk data load ----------
-- this state runs when s_wreg is
-- executed in rlink, thus doesn't cost
-- an extra cycle in 2nd+ iteration.
ibre := '1';
n.bdata := DI;
n.tcnt := slv(unsigned(r.tcnt) - 1);
n.braddr := slv(unsigned(r.braddr) + 1);
if unsigned(r.tcnt) = 1 then
n.bloop := '0';
else
n.bloop := '1';
end if;
n.state := s_txwbdl;
 
when s_txwbdl => -- s_txwbdl: wblk send data lsb ------
icpdi := '0' & r.bdata(f_byte0);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txwbdh;
end if;
 
when s_txwbdh => -- s_txwbdh: wblk send data msb ------
icpdi := '0' & r.bdata(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
if r.bloop = '1' then
n.state := s_txwbld;
else
n.state := s_txcrcl2;
end if;
end if;
when s_txcrcl2 => -- s_txcrcl2: send final crc lsb -----
icpdi := '0' & r.crc(f_byte0);
iena := '1';
if RL_BUSY = '0' then
n.state := s_txcrch2;
end if;
when s_txcrch2 => -- s_txcrch2: send final crc msb -----
icpdi := '0' & r.crc(f_byte1);
iena := '1';
if RL_BUSY = '0' then
if r.eoppend = '1' or unsigned(r.snum)=31 then
n.state := s_txeop;
else
n.state := s_txidle;
end if;
end if;
when others => null; -- <> --------------------------------
end case;
 
if do_crc = '1' then
n.crc := crc16_update(r.crc, icpdi(d_f_data));
end if;
N_TXREGS <= n;
 
TXBUSY <= itxbusy;
 
STAT_L.braddr <= r.braddr;
STAT_L.bre <= ibre;
 
RL_DI <= icpdi;
RL_ENA <= iena;
end process proc_txnext;
 
-- rx FSM ==================================================================
 
proc_rxnext: process (R_RXREGS, CNTL, RL_DO, RL_VAL)
variable r : rxregs_type := rxregs_init;
variable n : rxregs_type := rxregs_init;
 
variable irxbusy : slbit := '0';
variable ibwe : slbit := '0';
variable do_crc : slbit := '0';
variable ido : slv16 := (others=>'0');
 
begin
 
r := R_RXREGS;
n := R_RXREGS;
 
n.ack := '0';
n.ano := '0';
 
irxbusy := '1';
ibwe := '0';
do_crc := '0';
ido := r.data;
 
case r.state is
when s_rxidle => -- s_rxidle: wait --------------------
n.crc := (others=>'0');
n.err := '0';
 
if RL_VAL = '1' then
if RL_DO = c_rlink_dat_attn then -- attn seen ?
n.state := s_rxapl;
elsif RL_DO = c_rlink_dat_sop then
n.state := s_rxcmd;
end if;
else
irxbusy := '0'; -- signal rx not busy
end if;
 
when s_rxcmd => -- s_rxcmd: wait cmd ----------------
if RL_VAL = '1' then
if RL_DO = c_rlink_dat_eop then
n.state := s_rxidle;
else
n.bwaddr := (others=>'0');
do_crc := '1';
n.ccmd := RL_DO(n.ccmd'range);
case RL_DO(n.ccmd'range) is
when c_rlink_cmd_rreg => n.state := s_rxdl;
when c_rlink_cmd_rblk => n.state := s_rxcl;
when c_rlink_cmd_wreg => n.state := s_rxstat;
when c_rlink_cmd_wblk => n.state := s_rxdcl;
when c_rlink_cmd_labo => n.state := s_rxbabo;
when c_rlink_cmd_attn => n.state := s_rxdl;
when c_rlink_cmd_init => n.state := s_rxstat;
when others => null;
end case;
end if;
else
irxbusy := '0'; -- signal rx not busy
end if;
 
when s_rxcl => -- s_rxcl: wait cnt lsb --------------
if RL_VAL = '1' then
do_crc := '1';
n.tcnt(f_byte0) := RL_DO(d_f_data);
n.state := s_rxch;
end if;
 
when s_rxch => -- s_rxch: wait cnt msb --------------
if RL_VAL = '1' then
do_crc := '1';
n.tcnt(f_byte1) := RL_DO(d_f_data);
n.state := s_rxdl;
end if;
 
when s_rxbabo => -- s_rxbabo: wait babo ---------------
if RL_VAL = '1' then
do_crc := '1';
n.data(15 downto 0) := (others=>'0');
n.data(f_byte0) := RL_DO(d_f_data);
n.state := s_rxstat;
end if;
 
when s_rxdl => -- s_rxdl: wait data lsb -------------
if RL_VAL = '1' then
do_crc := '1';
n.data(f_byte0) := RL_DO(d_f_data);
n.state := s_rxdh;
end if;
when s_rxdh => -- s_rxdh: wait data msb -------------
if RL_VAL = '1' then
do_crc := '1';
n.data(f_byte1) := RL_DO(d_f_data);
n.tcnt := slv(unsigned(r.tcnt) - 1);
n.bwaddr := slv(unsigned(r.bwaddr) + 1);
if r.ccmd = c_rlink_cmd_rblk then
ido(f_byte1) := RL_DO(d_f_data);
ibwe := '1';
end if;
if r.ccmd /= c_rlink_cmd_rblk then
n.state := s_rxstat;
elsif unsigned(r.tcnt) = 1 then
n.state := s_rxdcl;
else
n.state := s_rxdl;
end if;
end if;
 
when s_rxdcl => -- s_rxdcl: wait dcnt lsb ------------
if RL_VAL = '1' then
do_crc := '1';
n.dcnt(f_byte0) := RL_DO(d_f_data);
n.state := s_rxdch;
end if;
when s_rxdch => -- s_rxdch: wait dcnt msb ------------
if RL_VAL = '1' then
do_crc := '1';
n.dcnt(f_byte1) := RL_DO(d_f_data);
n.state := s_rxstat;
end if;
when s_rxstat => -- s_rxstat: wait status -------------
if RL_VAL = '1' then
do_crc := '1';
n.stat := RL_DO(d_f_data);
n.apend := RL_DO(c_rlink_stat_rbf_attn); -- update attn status
n.state := s_rxcrcl;
end if;
when s_rxcrcl => -- s_rxcrcl: wait crc lsb ------------
if RL_VAL = '1' then
if r.crc(f_byte0) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.state := s_rxcrch;
end if;
when s_rxcrch => -- s_rxcrch: wait crc msb ------------
if RL_VAL = '1' then
if r.crc(f_byte1) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.ack := '1';
n.state := s_rxcmd;
end if;
 
when s_rxapl => -- s_rxapl: wait attn pat lsb --------
if RL_VAL = '1' then
do_crc := '1';
n.apat(f_byte0) := RL_DO(d_f_data);
n.state := s_rxaph;
end if;
when s_rxaph => -- s_rxaph: wait attn pat msb --------
if RL_VAL = '1' then
do_crc := '1';
n.apat(f_byte1) := RL_DO(d_f_data);
n.state := s_rxacl;
end if;
 
when s_rxacl => -- s_rxacl: wait attn crc lsb --------
if RL_VAL = '1' then
if r.crc(f_byte0) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.state := s_rxach;
end if;
when s_rxach => -- s_rxach: wait attn crc msb --------
if RL_VAL = '1' then
if r.crc(f_byte1) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.ano := '1';
n.state := s_rxidle;
end if;
when others => null; -- <> --------------------------------
end case;
 
if do_crc = '1' then
n.crc := crc16_update(r.crc, RL_DO(d_f_data));
end if;
N_RXREGS <= n;
 
RXBUSY <= irxbusy;
 
DO <= ido;
STAT_L.stat <= r.stat;
STAT_L.ack <= r.ack;
STAT_L.err <= r.err;
STAT_L.bwaddr <= r.bwaddr;
STAT_L.bwe <= ibwe;
STAT_L.dcnt <= r.dcnt;
STAT_L.apend <= r.apend;
STAT_L.ano <= r.ano;
STAT_L.apat <= r.apat;
RL_HOLD <= '0';
end process proc_rxnext;
 
STAT_L.busy <= RXBUSY or TXBUSY;
STAT <= STAT_L;
 
end syn;
/trunk/rtl/vlib/rlink/tb/rlinktblib.vhd
1,6 → 1,6
-- $Id: rlinktblib.vhd 595 2014-09-28 08:47:45Z mueller $
-- $Id: rlinktblib.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
16,9 → 16,10
-- Description: rlink test environment components
--
-- Dependencies: -
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Tool versions: xst 8.2-14.7; viv 2015.4-2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-13 730 4.1 drop tbcore_rlink component definition
-- 2014-08-28 588 4.0 now full rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2011-12-23 444 3.1 new clock iface for tbcore_rlink; drop .._dcm
132,18 → 133,6
);
end component;
 
component tbcore_rlink is -- core of vhpi_cext based test bench
port (
CLK : in slbit; -- control interface clock
CLK_STOP : out slbit; -- clock stop trigger
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end component;
 
-- FIXME after this point !!
 
component rricp_rp is -- rri comm->reg port aif forwarder
/trunk/rtl/vlib/rlink/tb/tb_rlink.vbom
14,7 → 14,7
# components
../../simlib/simclk.vbom
../../simlib/simclkcnt.vbom
../../genlib/clkdivce.vbom
../../genlib/tb/clkdivce_tb.vbom
../../rbus/rbd_tester.vbom
${uut := tbd_rlink_direct.vbom} -UUT
# design
/trunk/rtl/vlib/rlink/tb/tb_rlink.vhd
1,6 → 1,6
-- $Id: tb_rlink.vhd 596 2014-10-17 19:50:07Z mueller $
-- $Id: tb_rlink.vhd 807 2016-09-17 07:49:26Z mueller $
--
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
17,8 → 17,8
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- genlib/clkdivce
-- rbus/tbd_tester
-- genlib/tb/clkdivce_tb
-- rbus/rbd_tester
-- tbd_rlink_gen [UUT]
--
-- To test: rlink_core (via tbd_rlink_direct)
26,10 → 26,11
-- rlink_serport (via tbd_rlink_serport)
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-10 806 4.1.1 use clkdivce_tb
-- 2014-10-12 596 4.1 use readgen_ea; add get_cmd_ea; labo instead of stat
-- add txblk,rxblk,rxrbeg,rxrend,rxcbs,anmsg commands
-- 2014-08-28 588 4.0 now rlink v4 iface -> txcac has 16 bit; 4 bit STAT
194,10 → 195,10
shared variable sv_nrxlist : natural := 0;
shared variable sv_rxind : natural := 0;
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
 
component tbd_rlink_gen is -- rlink, generic tb design interface
port (
240,7 → 241,7
 
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
CLKDIV : clkdivce
CLKDIV : entity work.clkdivce_tb
generic map (
CDUWIDTH => 6,
USECDIV => 4,
/trunk/rtl/vlib/rlink/tb/tb_rlink_direct.vbom
1,6 → 1,8
# configure tb_rlink with tbd_rlink_direct wrapper
# use vhdl configure file (tb_rlink_direct.vhd) at allow
# that all configurations will co-exist in work library
# configure
uut = tbd_rlink_direct.vbom
# design
tb_rlink.vbom
tb_rlink_direct.vhd
/trunk/rtl/vlib/rlink/tb/tb_rlink_direct_ssim.vbom
1,4 → 1,6
# configure tb_rlink with tbd_rlink_direct wrapper; _*sim case
# configure
uut = tbd_rlink_direct_ssim.vhd
# design
tb_rlink_direct.vbom
@top : tb_rlink_direct
/trunk/rtl/vlib/rlink/tb/tb_rlink_sp1c.vbom
1,6 → 1,8
# configure tb_rlink with tbd_rlink_sp1c wrapper;
# use vhdl configure file (tb_rlink_sp1c.vhd) to allow
# that all configurations will co-exist in work library
# configure
uut = tbd_rlink_sp1c.vbom
# design
tb_rlink.vbom
tb_rlink_sp1c.vhd
/trunk/rtl/vlib/rlink/tb/tb_rlink_sp1c_ssim.vbom
1,5 → 1,7
# configure tb_rlink with tbd_rlink_sp1c wrapper; _*sim case
# configure
tbd_rlink_gen = tbd_rlink_sp1c.vbom
tbu_rlink_sp1c = tbu_rlink_sp1c_ssim.vhd
# design
tb_rlink_sp1c.vbom
@top:tb_rlink_sp1c
/trunk/rtl/vlib/rlink/tb/tb_rlink_tba.vbom
0,0 → 1,24
# Not meant for direct top level usage. Used with
# tb_rlink_tba_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../slvtypes.vhd
../../genlib/genlib.vhd
../../comlib/comlib.vhd
../../rbus/rblib.vhd
../rlinklib.vbom
rlinktblib.vhd
../../simlib/simlib.vhd
# components
../../simlib/simclk.vbom
../../simlib/simclkcnt.vbom
../../genlib/tb/clkdivce_tb.vbom
rlink_tba.vbom
../rlink_core.vbom
${rbtba_aif := tbd_tba_ttcombo.vbom} -UUT
../rlink_mon.vbom
../../rbus/rb_mon.vbom
# design
tb_rlink_tba.vhd
@top:tb_rlink_tba
/trunk/rtl/vlib/rlink/tb/tb_rlink_tba.vhd
0,0 → 1,810
-- $Id: tb_rlink_tba.vhd 806 2016-09-10 20:59:29Z mueller $
--
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_rlink_tba - sim
-- Description: Test bench for rbus devices via rlink_tba
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- genlib/tb/clkdivce_tb
-- rlink_tba
-- rlink_core
-- rbtba_aif [UUT]
-- rlink_mon
-- rb_mon
--
-- To test: generic, any rbtba_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-10 806 4.0.1 use clkdivce_tb
-- 2014-12-20 616 4.0.1 add dcnt check (with -n=) and .ndef
-- 2014-09-21 595 4.0 now full rlink v4 iface, 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2011-12-23 444 3.2 use new simclk/simclkcnt
-- 2011-11-22 432 3.1.1 now numeric_std clean
-- 2010-12-29 351 3.1 use rbtba_aif now, support _ssim level again
-- 2010-12-28 350 3.0.3 list cmd address, list send data for wreg/init
-- 2010-12-27 349 3.0.2 suppress D CHECK message for all masked rreg/rblk
-- 2010-12-25 348 3.0.1 drop RL_FLUSH support, add RL_MONI for rlink_core
-- 2010-12-24 347 3.0 rm tb_rritba->tb_rlink_tba, CP_*->RL_*;rbus v3 port
-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-05 301 2.1.3 rename _rpmon -> _rbmon, .rpmon -> .rbmon
-- 2010-06-03 299 2.1.2 use sv_ prefix for shared variables
-- 2010-05-02 287 2.1.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-03 274 2.1 add CP_FLUSH for rri_core
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.1.4 CLK_CYCLE now 31 bits
-- 2008-03-02 121 1.1.3 default .sdef now checks for errors, ignore
-- status bits and the attn flag.
-- 2008-01-20 112 1.1.2 rename clkgen->clkdivce
-- 2007-12-23 105 1.1.1 add .dbas[io] (allows to set base for data values)
-- 2007-11-24 98 1.1 add RP_IINT support
-- 2007-10-26 92 1.0.2 use DONE timestamp at end of execution
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.genlib.all;
use work.comlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.simlib.all;
 
entity tb_rlink_tba is
end tb_rlink_tba;
 
architecture sim of tb_rlink_tba is
signal CLK : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RESET : slbit := '0';
signal TBA_CNTL : rlink_tba_cntl_type := rlink_tba_cntl_init;
signal TBA_DI : slv16 := (others=>'0');
signal TBA_STAT : rlink_tba_stat_type := rlink_tba_stat_init;
signal TBA_DO : slv16 := (others=>'0');
signal RL_DI : slv9 := (others=>'0');
signal RL_ENA : slbit := '0';
signal RL_BUSY : slbit := '0';
signal RL_DO : slv9 := (others=>'0');
signal RL_VAL : slbit := '0';
signal RL_HOLD : slbit := '0';
signal RL_MONI : rl_moni_type := rl_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
 
signal RB_MREQ_aval : slbit := '0';
signal RB_MREQ_re : slbit := '0';
signal RB_MREQ_we : slbit := '0';
signal RB_MREQ_initt: slbit := '0';
signal RB_MREQ_addr : slv16 := (others=>'0');
signal RB_MREQ_din : slv16 := (others=>'0');
signal RB_SRES_ack : slbit := '0';
signal RB_SRES_busy : slbit := '0';
signal RB_SRES_err : slbit := '0';
signal RB_SRES_dout : slv16 := (others=>'0');
 
signal RLMON_EN : slbit := '0';
signal RBMON_EN : slbit := '0';
 
signal N_CMD_CODE : string(1 to 4) := (others=>' ');
signal N_CMD_ADDR : slv16 := (others=>'0');
signal N_CMD_DATA : slv16 := (others=>'0');
signal N_CHK_DATA : boolean := false;
signal N_REF_DATA : slv16 := (others=>'0');
signal N_MSK_DATA : slv16 := (others=>'0');
signal N_CHK_DONE : boolean := false;
signal N_REF_DONE : slv16 := (others=>'0');
signal N_CHK_STAT : boolean := false;
signal N_REF_STAT : slv8 := (others=>'0');
signal N_MSK_STAT : slv8 := (others=>'0');
 
signal R_CMD_CODE : string(1 to 4) := (others=>' ');
signal R_CMD_ADDR : slv16 := (others=>'0');
signal R_CMD_DATA : slv16 := (others=>'0');
signal R_CHK_DATA : boolean := false;
signal R_REF_DATA : slv16 := (others=>'0');
signal R_MSK_DATA : slv16 := (others=>'0');
signal R_CHK_DONE : boolean := false;
signal R_REF_DONE : slv16 := (others=>'0');
signal R_CHK_STAT : boolean := false;
signal R_REF_STAT : slv8 := (others=>'0');
signal R_MSK_STAT : slv8 := (others=>'0');
 
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
 
shared variable sv_dbasi : integer := 2;
shared variable sv_dbaso : integer := 2;
 
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
 
begin
 
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
 
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
CLKDIV : entity work.clkdivce_tb
generic map (
CDUWIDTH => 6,
USECDIV => 4,
MSECDIV => 5)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
 
TBA : rlink_tba
port map (
CLK => CLK,
RESET => RESET,
CNTL => TBA_CNTL,
DI => TBA_DI,
STAT => TBA_STAT,
DO => TBA_DO,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
 
RLINK : rlink_core
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => (others=>'0'))
port map (
CLK => CLK,
CE_INT => CE_MSEC,
RESET => RESET,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
 
RB_MREQ_aval <= RB_MREQ.aval;
RB_MREQ_re <= RB_MREQ.re;
RB_MREQ_we <= RB_MREQ.we;
RB_MREQ_initt<= RB_MREQ.init;
RB_MREQ_addr <= RB_MREQ.addr;
RB_MREQ_din <= RB_MREQ.din;
 
RB_SRES.ack <= RB_SRES_ack;
RB_SRES.busy <= RB_SRES_busy;
RB_SRES.err <= RB_SRES_err;
RB_SRES.dout <= RB_SRES_dout;
UUT : rbtba_aif
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ_aval => RB_MREQ_aval,
RB_MREQ_re => RB_MREQ_re,
RB_MREQ_we => RB_MREQ_we,
RB_MREQ_initt=> RB_MREQ_initt,
RB_MREQ_addr => RB_MREQ_addr,
RB_MREQ_din => RB_MREQ_din,
RB_SRES_ack => RB_SRES_ack,
RB_SRES_busy => RB_SRES_busy,
RB_SRES_err => RB_SRES_err,
RB_SRES_dout => RB_SRES_dout,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
RLMON : rlink_mon
generic map (
DWIDTH => RL_DI'length)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
ENA => RLMON_EN,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
 
RBMON : rb_mon
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
ENA => RBMON_EN,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
 
proc_stim: process
file fstim : text open read_mode is "tb_rlink_tba_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable ien : slbit := '0';
variable iaddr : slv16 := (others=>'0');
variable idata : slv16 := (others=>'0');
variable bcnt : integer := 0;
variable ccnt : integer := 0;
variable cmax : integer := 32;
variable nwait : integer := 0;
variable amnemo : string(1 to 6) := (others=>' ');
variable newline : boolean := true;
variable chk_data : boolean := false;
variable ref_data : slv16 := (others=>'0');
variable msk_data : slv16 := (others=>'0');
variable chk_stat : boolean := false;
variable ref_stat : slv8 := (others=>'0');
variable msk_stat : slv8 := (others=>'0');
variable chk_sdef : boolean := true;
variable ref_sdef : slv8 := (others=>'0');
variable msk_sdef : slv8 := "11111000"; -- ignore status bits and attn
variable chk_ndef : boolean := true;
 
type amrec_type is record
name : string(1 to 6);
addr : slv16;
end record;
constant amrec_init : amrec_type := ((others=>' '),
(others=>'0'));
constant amtbl_size : integer := 256;
type amtbl_type is array (1 to amtbl_size) of amrec_type;
 
variable amtbl_defs : integer := 0;
variable amtbl : amtbl_type := (others=>amrec_init);
procedure get_addr(L: inout line;
addr: out slv16) is
variable ichar : character := ' ';
variable name : string(1 to 6) := (others=>' ');
variable ok : boolean := false;
variable iaddr : slv16 := (others=>'0');
variable iaddr_or : slv16 := (others=>'0');
begin
 
readwhite(L);
 
readoptchar(L, '.', ok);
if ok then
readword_ea(L, name);
for i in 1 to amtbl_defs loop
if amtbl(i).name = name then
iaddr := amtbl(i).addr;
readoptchar(L, '|', ok);
if ok then
readgen_ea(L, iaddr_or);
for i in iaddr_or'range loop
if iaddr_or(i) = '1' then
iaddr(i) := '1';
end if;
end loop;
end if;
addr := iaddr;
return;
end if;
end loop;
report "address mnemonic not defined: " & name
severity failure;
end if;
readgen_ea(L, addr);
end procedure get_addr;
 
procedure cmd_waitdone is
variable nwait : integer := 0;
begin
nwait := 0;
while TBA_STAT.busy='1' loop
nwait := nwait + 1;
assert nwait<2000 report "assert(nwait<2000)" severity failure;
wait for clock_period;
end loop;
end procedure cmd_waitdone;
 
procedure setup_check_n (
bcnt : in integer)
is
variable chk_done : boolean := false;
variable ref_done : slv16 := (others=>'0');
begin
readtagval_ea(iline, "n", chk_done, ref_done, 10);
if chk_done then
N_CHK_DONE <= chk_done;
N_REF_DONE <= ref_done;
else
N_CHK_DONE <= chk_ndef;
N_REF_DONE <= slv(to_unsigned(bcnt,16));
end if;
end procedure setup_check_n;
 
procedure setup_check_d is
variable chk_data : boolean := false;
variable ref_data : slv16 := (others=>'0');
variable msk_data : slv16 := (others=>'0');
begin
readtagval2_ea(iline, "d", chk_data, ref_data, msk_data, sv_dbasi);
N_CHK_DATA <= chk_data;
N_REF_DATA <= ref_data;
N_MSK_DATA <= msk_data;
end procedure setup_check_d;
 
procedure setup_check_s is
variable chk_stat : boolean := false;
variable ref_stat : slv8 := (others=>'0');
variable msk_stat : slv8 := (others=>'0');
begin
readtagval2_ea(iline, "s", chk_stat, ref_stat, msk_stat);
if chk_stat then
N_CHK_STAT <= chk_stat;
N_REF_STAT <= ref_stat;
N_MSK_STAT <= msk_stat;
else
N_CHK_STAT <= chk_sdef;
N_REF_STAT <= ref_sdef;
N_MSK_STAT <= msk_sdef;
end if;
end procedure setup_check_s;
 
procedure cmd_start (
cmd : in slv3;
addr : in slv16 := (others=>'0');
data : in slv16 := (others=>'0');
bcnt : in integer := 1) is
begin
TBA_CNTL <= rlink_tba_cntl_init;
TBA_CNTL.cmd <= cmd;
TBA_CNTl.addr <= addr;
TBA_CNTL.cnt <= slv(to_unsigned(bcnt,16));
TBA_DI <= data;
 
ccnt := ccnt + 1;
if ccnt >= cmax then
ccnt := 0;
TBA_CNTL.eop <= '1';
end if;
 
TBA_CNTL.ena <= '1';
wait for clock_period;
TBA_CNTL.ena <= '0';
TBA_CNTL.eop <= '0';
end procedure cmd_start;
begin
wait for clock_offset - setup_time;
 
file_loop: while not endfile(fstim) loop
 
readline (fstim, iline);
if TBA_STAT.ack = '1' and -- if ack cycle
iline'length>0 then -- and non empty line
if iline(1) = 'C' then -- and leading 'C'
wait for clock_period; -- wait cycle to ensure that comment
-- comes after moni response
end if;
end if;
readcomment(iline, ok);
next file_loop when ok;
 
readword(iline, dname, ok);
if ok then
N_CMD_CODE <= " ";
N_CHK_DATA <= false;
N_CHK_DONE <= false;
N_CHK_STAT <= false;
 
case dname is
when ".mode " => -- .mode
readword_ea(iline, dname);
assert dname="rri "
report "assert .mode == rri" severity failure;
 
when ".rlmon" => -- .rlmon
read_ea(iline, ien);
RLMON_EN <= ien;
wait for 2*clock_period; -- wait for monitor to start
 
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
RBMON_EN <= ien;
wait for 2*clock_period; -- wait for monitor to start
 
when ".sdef " => -- .sdef , set default for status chk
readtagval2_ea(iline, "s", chk_sdef, ref_sdef, msk_sdef);
 
when ".ndef " => -- .ndef , enable/disable done chk
read_ea(iline, idata(0));
chk_ndef := idata(0) = '1';
 
when ".amclr" => -- .amclr , clear addr mnemo table
amtbl_defs := 0;
amtbl := (others=>amrec_init);
when ".amdef" => -- .amdef , define addr mnemo table
assert amtbl_defs<amtbl_size
report "assert(amtbl_defs<amtbl_size): too many .amdef's"
severity failure;
readword_ea(iline, amnemo);
readgen_ea(iline, iaddr);
amtbl_defs := amtbl_defs + 1;
amtbl(amtbl_defs).name := amnemo;
amtbl(amtbl_defs).addr := iaddr;
when ".dbasi" => -- .dbasi
read_ea(iline, idelta);
assert idelta=2 or idelta=8 or idelta=16
report "assert(dbasi = 2,8, or 16)"
severity failure;
sv_dbasi := idelta;
when ".dbaso" => -- .dbaso
read_ea(iline, idelta);
assert idelta=2 or idelta=8 or idelta=16
report "assert(dbaso = 2,8, or 16)"
severity failure;
sv_dbaso := idelta;
 
when ".cmax " => -- .cmax
readint_ea(iline, cmax, 1, 32);
 
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".wtlam" => -- .wtlam
read_ea(iline, idelta);
nwait := 0;
loop
if TBA_STAT.ano='1' or nwait>=idelta then
writetimestamp(oline, CLK_CYCLE, ": .wtlam" & " nwait=");
write(oline, nwait, left);
if TBA_STAT.ano = '0' then
write(oline, string'(" FAIL TIMEOUT"));
end if;
writeline(output, oline);
exit;
end if;
nwait := nwait + 1;
wait for clock_period;
end loop;
 
when ".eop " => -- .eop
TBA_CNTL <= rlink_tba_cntl_init;
TBA_CNTL.eop <= '1';
wait for clock_period;
TBA_CNTL.eop <= '0';
wait for clock_period; -- wait (or rlink_tba will hang...)
ccnt := 0;
when "rreg " => -- rreg
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
N_CMD_DATA <= (others=>'Z');
setup_check_d;
setup_check_s;
cmd_start(cmd=>c_rlink_cmd_rreg, addr=>iaddr);
cmd_waitdone;
when "rblk " => -- rblk
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
N_CMD_DATA <= (others=>'Z');
read_ea(iline, bcnt);
assert bcnt>0 report "assert(bcnt>0)" severity failure;
setup_check_n(bcnt);
setup_check_s;
cmd_start(cmd=>c_rlink_cmd_rblk, addr=>iaddr, bcnt=>bcnt);
 
testempty_ea(iline);
newline := true;
for i in 1 to bcnt loop
while TBA_STAT.bwe='0' loop
wait for clock_period;
end loop;
if newline then
rblk_line: loop
readline (fstim, iline);
readcomment(iline, ok);
exit rblk_line when not ok;
end loop;
end if;
readtagval2_ea(iline, "d", chk_data, ref_data, msk_data,sv_dbasi);
N_CHK_DATA <= chk_data;
N_REF_DATA <= ref_data;
N_MSK_DATA <= msk_data;
testempty(iline, newline);
wait for clock_period;
end loop;
N_CHK_DATA <= false;
cmd_waitdone;
when "wreg " => -- wreg
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
readgen_ea(iline, idata, sv_dbasi);
N_CMD_DATA <= idata;
setup_check_s;
cmd_start(cmd=>c_rlink_cmd_wreg, addr=>iaddr, data=>idata);
cmd_waitdone;
when "wblk " => -- wblk
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
N_CMD_DATA <= (others=>'Z');
read_ea(iline, bcnt);
assert bcnt>0 report "assert(bcnt>0)" severity failure;
setup_check_n(bcnt);
setup_check_s;
cmd_start(cmd=>c_rlink_cmd_wblk, addr=>iaddr, bcnt=>bcnt);
 
testempty_ea(iline);
newline := true;
for i in 1 to bcnt loop
while TBA_STAT.bre='0' loop
wait for clock_period;
end loop;
if newline then
wblk_line: loop
readline (fstim, iline);
readcomment(iline, ok);
exit wblk_line when not ok;
end loop;
end if;
readgen_ea(iline, idata, sv_dbasi);
TBA_DI <= idata;
testempty(iline, newline);
wait for clock_period;
end loop;
cmd_waitdone;
when "labo " => -- labo
N_CMD_CODE <= dname(N_CMD_CODE'range);
N_CMD_ADDR <= (others=>'0');
N_CMD_DATA <= (others=>'Z');
setup_check_d;
setup_check_s;
cmd_start(cmd=>c_rlink_cmd_labo);
cmd_waitdone;
when "attn " => -- attn
N_CMD_CODE <= dname(N_CMD_CODE'range);
N_CMD_ADDR <= (others=>'0');
N_CMD_DATA <= (others=>'Z');
setup_check_d;
setup_check_s;
cmd_start(cmd=>c_rlink_cmd_attn);
cmd_waitdone;
when "init " => -- init
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
readgen_ea(iline, idata, sv_dbasi);
N_CMD_DATA <= idata;
setup_check_s;
cmd_start(cmd=>c_rlink_cmd_init, addr=>iaddr, data=>idata);
cmd_waitdone;
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
 
else
report "failed to find command" severity failure;
 
end if;
 
testempty_ea(iline);
end loop; -- file_loop:
 
wait for 4*clock_period;
CLK_STOP <= '1';
 
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
 
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
 
end process proc_stim;
 
proc_moni: process
variable oline : line;
variable chk_ok : boolean := true;
begin
 
loop
wait until rising_edge(CLK);
R_CMD_CODE <= N_CMD_CODE;
R_CMD_ADDR <= N_CMD_ADDR;
R_CMD_DATA <= N_CMD_DATA;
R_CHK_DATA <= N_CHK_DATA;
R_REF_DATA <= N_REF_DATA;
R_MSK_DATA <= N_MSK_DATA;
R_CHK_DONE <= N_CHK_DONE;
R_REF_DONE <= N_REF_DONE;
R_CHK_STAT <= N_CHK_STAT;
R_REF_STAT <= N_REF_STAT;
R_MSK_STAT <= N_MSK_STAT;
 
if TBA_STAT.bwe = '1' then
writetimestamp(oline, CLK_CYCLE, ": rblk ");
writehex(oline, R_CMD_ADDR, right, 4);
write(oline, string'(" bwe=1 "));
writegen(oline, TBA_DO, right, base=>sv_dbaso);
if N_CHK_DATA then
if N_MSK_DATA /= "1111111111111111" then -- not all masked off
write(oline, string'(" .D.-CHECK"));
else
write(oline, string'(" ...-CHECK"));
end if;
if unsigned((TBA_DO xor N_REF_DATA) and (not N_MSK_DATA)) /= 0 then
write(oline, string'(" FAIL d="));
writegen(oline, N_REF_DATA, base=>sv_dbaso);
if unsigned(N_MSK_DATA) /= 0 then
write(oline, string'(","));
writegen(oline, N_MSK_DATA, base=>sv_dbaso);
end if;
else
write(oline, string'(" OK"));
end if;
end if;
writeline(output, oline);
end if;
if TBA_STAT.ack = '1' then
writetimestamp(oline, CLK_CYCLE, ": ");
write(oline, R_CMD_CODE);
writehex(oline, R_CMD_ADDR, right, 5);
write(oline, string'(" "));
write(oline, TBA_STAT.err, right, 1);
write(oline, TBA_STAT.stat, right, 9);
write(oline, string'(" "));
if R_CMD_CODE="wreg" or R_CMD_CODE="init" then
writegen(oline, R_CMD_DATA, right, base=>sv_dbaso);
else
writegen(oline, TBA_DO, right, base=>sv_dbaso);
end if;
if R_CHK_DATA or R_CHK_DONE or R_CHK_STAT then
chk_ok := true;
write(oline, string'(" "));
if R_CHK_DONE then
write(oline, string'("N"));
else
write(oline, string'("."));
end if;
if R_CHK_DATA and R_MSK_DATA/="1111111111111111" then
write(oline, string'("D"));
else
write(oline, string'("."));
end if;
if R_CHK_STAT and R_MSK_STAT/="11111111" then
write(oline, string'("S"));
else
write(oline, string'("."));
end if;
write(oline, string'("-CHECK"));
if R_CHK_DONE then
if TBA_STAT.dcnt /= R_REF_DONE then
chk_ok := false;
write(oline, string'(" FAIL n="));
write(oline, to_integer(unsigned(R_REF_DONE)));
end if;
end if;
if R_CHK_DATA then
if unsigned((TBA_DO xor R_REF_DATA) and (not R_MSK_DATA)) /= 0 then
chk_ok := false;
write(oline, string'(" FAIL d="));
writegen(oline, R_REF_DATA, base=>sv_dbaso);
if unsigned(R_MSK_DATA) /= 0 then
write(oline, string'(","));
writegen(oline, R_MSK_DATA, base=>sv_dbaso);
end if;
end if;
end if;
if R_CHK_STAT then
if unsigned((TBA_STAT.stat xor R_REF_STAT) and
(not R_MSK_STAT)) /= 0 then
chk_ok := false;
write(oline, string'(" FAIL s="));
write(oline, R_REF_STAT);
if unsigned(R_MSK_STAT) /= 0 then
write(oline, string'(","));
write(oline, R_MSK_STAT);
end if;
end if;
end if;
if chk_ok then
write(oline, string'(" OK"));
end if;
end if;
writeline(output, oline);
end if;
if TBA_STAT.ano = '1' then
writetimestamp(oline, CLK_CYCLE, ": ---- attn notify ---- ");
write(oline, TBA_STAT.apat, right, 16);
writeline(output, oline);
end if;
end loop;
end process proc_moni;
 
end sim;
/trunk/rtl/vlib/rlink/tb/tbd_tba_ttcombo.vbom
0,0 → 1,12
# libs
../../slvtypes.vhd
../../rbus/rblib.vhd
../../rbus/rbdlib.vhd
# components
../../rbus/rbd_tester.vbom
../../rbus/rbd_bram.vbom
../../rbus/rbd_rbmon.vbom
../../rbus/rb_sres_or_4.vbom
# design
tbd_tba_ttcombo.vhd
@xdc:../../generic_clk_100mhz.xdc
/trunk/rtl/vlib/rlink/tb/tbd_tba_ttcombo.vhd
0,0 → 1,149
-- $Id: tbd_tba_ttcombo.vhd 593 2014-09-14 22:21:33Z mueller $
--
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_tba_ttcombo - syn
-- Description: rbtba_aif wrapper for test target
--
-- Dependencies: rbd_tester
-- rbd_bram
-- rbd_rbmon
-- rb_sres_or_4
--
-- Test bench: tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
--
-- Synthesised (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-29 351 12.1 M53d xc3s1000-4 192 538 32 342 s 10.1
-- 2010-12-23 347 12.1 M53d xc3s1000-4 78 204 32 133 s 8.1
--
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-09-13 593 4.0 use new rlink v4 iface and 4 bit STAT; new addr
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2011-11-22 432 3.1.2 now numeric_std clean
-- 2010-12-29 351 3.1.1 moved in from rbus/rbd_ttcombo; port to rbtba_aif
-- 2010-12-26 349 3.1 add rbd_bram and rbd_rbmon
-- 2010-12-23 347 3.0 rename rrirp_ttcombo->rbd_ttcombo; essentially a
-- rewrite, use rbd_tester;
-- ---------- old V2 and V1 history removed
-- 2007-08-16 74 1.0 Initial version
------------------------------------------------------------------------------
--
-- address layout:
--
-- rbd_rbmon ffe8/8
-- rbd_tester ffe0/8
-- rbd_bram fe00/2
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
 
entity rbd_tba_ttcombo is -- rbtba_aif wrapper for test target
-- implements rbtba_aif
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ_aval : in slbit; -- rbus: request - aval
RB_MREQ_re : in slbit; -- rbus: request - re
RB_MREQ_we : in slbit; -- rbus: request - we
RB_MREQ_initt : in slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : in slv16; -- rbus: request - addr
RB_MREQ_din : in slv16; -- rbus: request - din
RB_SRES_ack : out slbit; -- rbus: response - ack
RB_SRES_busy : out slbit; -- rbus: response - busy
RB_SRES_err : out slbit; -- rbus: response - err
RB_SRES_dout : out slv16; -- rbus: response - dout
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv4 -- rbus: status flags
);
end entity rbd_tba_ttcombo;
 
 
architecture syn of rbd_tba_ttcombo is
signal RB_SRES_TEST : rb_sres_type := rb_sres_init;
signal RB_SRES_BRAM : rb_sres_type := rb_sres_init;
signal RB_SRES_MON : rb_sres_type := rb_sres_init;
 
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
begin
RB_MREQ.aval <= RB_MREQ_aval;
RB_MREQ.re <= RB_MREQ_re;
RB_MREQ.we <= RB_MREQ_we;
RB_MREQ.init <= RB_MREQ_initt;
RB_MREQ.addr <= RB_MREQ_addr;
RB_MREQ.din <= RB_MREQ_din;
 
RB_SRES_ack <= RB_SRES.ack;
RB_SRES_busy <= RB_SRES.busy;
RB_SRES_err <= RB_SRES.err;
RB_SRES_dout <= RB_SRES.dout;
 
TEST: rbd_tester
generic map (
RB_ADDR => slv(to_unsigned(16#ffe0#,16)))
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TEST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
MON: rbd_rbmon
generic map (
RB_ADDR => slv(to_unsigned(16#ffe8#,16)),
AWIDTH => 9)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_MON,
RB_SRES_SUM => RB_SRES
);
BRAM: rbd_bram
generic map (
RB_ADDR => slv(to_unsigned(16#fe00#,16)))
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_BRAM
);
RB_SRES_OR : rb_sres_or_4
port map (
RB_SRES_1 => RB_SRES_TEST,
RB_SRES_2 => RB_SRES_BRAM,
RB_SRES_3 => RB_SRES_MON,
RB_SRES_4 => rb_sres_init,
RB_SRES_OR => RB_SRES
);
end syn;
/trunk/rtl/vlib/rlink/tb/tbrun.yml
0,0 → 1,23
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-09-17 807 1.1 use nossim because _ssim support broken; add sp1c
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${viv_modes_nossim}
#
- tag: [default, viv, rlink, direct]
test: |
tbrun_tbw tb_rlink_direct${ms}
- tag: [default, viv, rlink, sp1c]
test: |
tbrun_tbw tb_rlink_sp1c${ms}
- tag: [default, viv, rlink, ttcombo]
test: |
- tag: [default, viv, rlink, eyemon]
test: |
/trunk/rtl/vlib/rlink/tbcore/tbcore_rlink.vhd
1,4 → 1,4
-- $Id: tbcore_rlink.vhd 731 2016-02-14 21:07:14Z mueller $
-- $Id: tbcore_rlink.vhd 808 2016-09-17 13:02:46Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
21,9 → 21,11
-- To test: generic, any rlink_cext based target
--
-- Target Devices: generic
-- Tool versions: ghdl 0.26-0.31
-- Tool versions: ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-17 807 3.2.2 conf: .sinit -> .sdata; finite length SB_VAL pulse
-- 2016-09-02 805 3.2.1 conf: add .wait and CONF_DONE; drop CLK_STOP
-- 2016-02-07 729 3.2 use rlink_cext_iface (allow VHPI and DPI backend)
-- 2015-11-01 712 3.1.3 proc_stim: drive SB_CNTL from start to avoid 'U'
-- 2013-01-04 469 3.1.2 use 1ns wait for .sinit to allow simbus debugging
53,7 → 55,6
entity tbcore_rlink is -- core of rlink_cext based test bench
port (
CLK : in slbit; -- control interface clock
CLK_STOP : out slbit; -- clock stop trigger
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
69,6 → 70,7
signal CEXT_RXDATA : slv32 := (others=>'0');
signal CEXT_RXVAL : slbit := '0';
signal CEXT_RXHOLD : slbit := '1';
signal CONF_DONE : slbit := '0';
 
begin
95,9 → 97,13
variable dname : string(1 to 6) := (others=>' ');
variable ien : slbit := '0';
variable ibit : integer := 0;
variable twait : Delay_length := 0 ns;
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
 
CONF_DONE <= '0';
SB_SIMSTOP <= 'L';
SB_CNTL <= (others=>'L');
SB_VAL <= 'L';
120,6 → 126,7
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
report "assert bit number in range of SB_CNTL"
severity failure;
wait for 1 ns;
if ien = '1' then
SB_CNTL(ibit) <= 'H';
else
128,6 → 135,7
 
when ".rlmon" => -- .rlmon
read_ea(iline, ien);
wait for 1 ns;
if ien = '1' then
SB_CNTL(sbcntl_sbf_rlmon) <= 'H';
else
136,6 → 144,7
 
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
wait for 1 ns;
if ien = '1' then
SB_CNTL(sbcntl_sbf_rbmon) <= 'H';
else
142,9 → 151,10
SB_CNTL(sbcntl_sbf_rbmon) <= 'L';
end if;
 
when ".sinit" => -- .sinit
readgen_ea(iline, iaddr, 8);
readgen_ea(iline, idata, 8);
when ".sdata" => -- .sdata
readgen_ea(iline, iaddr, 16);
readgen_ea(iline, idata, 16);
wait for 1 ns;
SB_ADDR <= iaddr;
SB_DATA <= idata;
SB_VAL <= 'H';
152,8 → 162,11
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
wait for 1 ns;
 
when ".wait " => -- .wait
read_ea(iline, twait);
wait for twait;
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
172,6 → 185,8
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
 
CONF_DONE <= '1';
 
wait; -- halt process here
end process proc_conf;
187,7 → 202,6
begin
 
-- setup init values for all output ports
CLK_STOP <= '0';
RX_DATA <= (others=>'0');
RX_VAL <= '0';
 
198,11 → 212,14
 
CEXT_RXHOLD <= '1';
-- wait for 10 clock cycles (design run up)
-- wait for CONF_DONE, but at least 10 clock cycles (conf+design run up)
for i in 0 to 9 loop
wait until rising_edge(CLK);
end loop; -- i
 
while CONF_DONE = '0' loop
wait until rising_edge(CLK);
end loop;
writetimestamp(oline, CLK_CYCLE, ": START");
writeline(output, oline);
 
241,10 → 258,13
else
SB_ADDR <= iaddr;
SB_DATA <= idata;
-- In principle a delta cycle long pulse is enough to make the
-- simbus transfer. A 500 ps long pulse is generated to ensure
-- that SB_VAL is visible in a viewer. That works up to 1 GHz
SB_VAL <= '1';
wait for 0 ns;
wait for 500 ps;
SB_VAL <= 'Z';
wait for 0 ns;
wait for 0 ps;
end if;
end if;
elsif irxint = -1 then -- end-of-file seen
264,14 → 284,13
for i in 0 to 49 loop
wait until rising_edge(CLK);
end loop; -- i
CLK_STOP <= '1';
 
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
 
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
SB_SIMSTOP <= '1'; -- signal simulation stop
wait for 100 ns; -- monitor grace time
report "Simulation Finished" severity failure; -- end simulation
 
end process proc_stim;
 
/trunk/rtl/vlib/serport/Makefile
0,0 → 1,37
# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-20 749 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#
/trunk/rtl/vlib/serport/serport_uart_autobaud.vhd
1,4 → 1,4
-- $Id: serport_uart_autobaud.vhd 774 2016-06-12 17:08:47Z mueller $
-- $Id: serport_uart_autobaud.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
21,7 → 21,7
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2015-02-01 641 1.1 add CLKDIV_F
-- 2011-10-22 417 1.0.4 now numeric_std clean
-- 2010-04-18 279 1.0.3 change ccnt start value to -3, better rounding
/trunk/rtl/vlib/serport/serport_uart_rx.vhd
1,4 → 1,4
-- $Id: serport_uart_rx.vhd 774 2016-06-12 17:08:47Z mueller $
-- $Id: serport_uart_rx.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
27,7 → 27,7
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 2.0.4 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 2.0.4 don't init N_REGS (vivado fix for fsm inference)
-- 2011-10-22 417 2.0.3 now numeric_std clean
-- 2009-07-12 233 2.0.2 remove snoopers
-- 2008-03-02 121 2.0.1 comment out snoopers
/trunk/rtl/vlib/serport/tb/serport_uart_rx_tb.vhd
1,4 → 1,4
-- $Id: serport_uart_rx_tb.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: serport_uart_rx_tb.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
26,7 → 26,7
-- Tool versions: ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.0.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 1.0.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-01-03 724 1.0 Initial version (copied from serport_uart_rx)
------------------------------------------------------------------------------
 
/trunk/rtl/vlib/serport/tb/tb_serport_autobaud.vhd
1,4 → 1,4
-- $Id: tb_serport_autobaud.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: tb_serport_autobaud.vhd 790 2016-07-20 18:52:44Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
88,10 → 88,10
signal R_MON_VAL_2 : slbit := '0';
signal R_MON_DAT_2 : slv8 := (others=>'0');
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
 
begin
 
/trunk/rtl/vlib/serport/tb/tb_serport_autobaud_ssim.vbom
1,4 → 1,6
# configure for _*sim case
# configure
uut = tbd_serport_autobaud_ssim.vhd
# design
tb_serport_autobaud.vbom
@top:tb_serport_autobaud
/trunk/rtl/vlib/serport/tb/tb_serport_uart_rx.vhd
1,4 → 1,4
-- $Id: tb_serport_uart_rx.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: tb_serport_uart_rx.vhd 790 2016-07-20 18:52:44Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
75,10 → 75,10
signal R_MON_ERR_2 : slbit := '0';
signal R_MON_DAT_2 : slv8 := (others=>'0');
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
 
begin
 
/trunk/rtl/vlib/serport/tb/tb_serport_uart_rx_ssim.vbom
1,4 → 1,6
# configure for _*sim case
# configure
uut = tbd_serport_uart_rx_ssim.vhd
# design
tb_serport_uart_rx.vbom
@top:tb_serport_uart_rx
/trunk/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vhd
1,4 → 1,4
-- $Id: tb_serport_uart_rxtx.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: tb_serport_uart_rxtx.vhd 790 2016-07-20 18:52:44Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
79,10 → 79,10
signal R_MON_VAL_2 : slbit := '0';
signal R_MON_DAT_2 : slv8 := (others=>'0');
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
 
begin
 
/trunk/rtl/vlib/serport/tb/tb_serport_uart_rxtx_ssim.vbom
1,4 → 1,6
# configure for _*sim case
# configure
uut = tbd_serport_uart_rxtx_ssim.vhd
# design
tb_serport_uart_rxtx.vbom
@top:tb_serport_uart_rxtx
/trunk/rtl/vlib/serport/tb/tbrun.yml
0,0 → 1,20
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-12 797 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [default, viv, serport, rx]
test: |
tbrun_tbw tb_serport_uart_rx${ms}
 
- tag: [default, viv, serport, rxtx]
test: |
tbrun_tbw tb_serport_uart_rxtx${ms}
- tag: [default, viv, serport, autobaud]
test: |
tbrun_tbw tb_serport_autobaud${ms}
/trunk/rtl/vlib/simlib/simbididly.vbom
0,0 → 1,5
# libs
../slvtypes.vhd
# components
# design
simbididly.vhd
/trunk/rtl/vlib/simlib/simbididly.vhd
0,0 → 1,124
-- $Id: simbididly.vhd 793 2016-07-23 19:38:55Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: simbididly - sim
-- Description: Bi-directional bus delay for test benches
--
-- Dependencies: -
-- Test bench: tb_simbididly
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-23 793 1.0.1 ensure non-zero DELAY
-- 2016-07-17 789 1.0 Initial version (use separate driver regs now)
-- 2016-07-16 787 0.1 First draft
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
 
entity simbididly is -- test bench bi-directional bus delay
generic (
DELAY : Delay_length; -- transport delay between A and B (>0ns!)
DWIDTH : positive := 16); -- data port width
port (
A : inout slv(DWIDTH-1 downto 0); -- port A
B : inout slv(DWIDTH-1 downto 0) -- port B
);
end entity simbididly;
 
 
architecture sim of simbididly is
 
type state_type is (
s_idle, -- s_idle: both ports high-z
s_a2b, -- s_a2b: A drives, B listens
s_b2a -- s_b2a: B drives, A listens
);
 
constant all_z : slv(DWIDTH-1 downto 0) := (others=>'Z');
 
signal R_STATE : state_type := s_idle;
signal R_A : slv(DWIDTH-1 downto 0) := (others=>'Z');
signal R_B : slv(DWIDTH-1 downto 0) := (others=>'Z');
 
begin
 
process
 
variable istate : state_type := s_idle;
begin
 
-- the delay model can enter into a delta cycle oszillation mode
-- when DELAY is 0 ns. So ensure the delay is non-zero
assert DELAY > 0 ns report "DELAY > 0 ns" severity failure;
while true loop
-- if idle check whether A or B port starts to drive bus
-- Note: both signal R_STATE and variable istate is updated
-- istate is needed to control the driver section below in the
-- same delta cycle based on the most recent state state
istate := R_STATE;
 
if now > 0 ns then -- to avoid startup problems
if R_STATE = s_idle then
if A /= all_z then
R_STATE <= s_a2b;
istate := s_a2b;
elsif B /= all_z then
R_STATE <= s_b2a;
istate := s_b2a;
end if;
end if;
end if;
case istate is
when s_a2b =>
R_B <= transport A after DELAY;
if A = all_z then R_STATE <= s_idle after DELAY; end if;
when s_b2a =>
R_A <= transport B after DELAY;
if B = all_z then R_STATE <= s_idle after DELAY; end if;
when others => null;
end case;
 
-- Note: the driver clash check is done by comparing an internal signal
-- with the external signal. If they differ this indicates a clash.
-- Just checking for 'x' gives false alarms when the bus is driven
-- with 'x', which can for example come from a memory model before
-- valid data is available.
if now > 0 ns then -- to avoid startup problems
case istate is
when s_a2b =>
assert B = R_B report "driver clash B port" severity error;
when s_b2a =>
assert A = R_A report "driver clash A port" severity error;
when others => null;
end case;
end if;
wait on A,B;
end loop;
 
end process;
 
A <= R_A;
B <= R_B;
end sim;
/trunk/rtl/vlib/simlib/simbus.vhd
1,6 → 1,6
-- $Id: simbus.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: simbus.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
16,10 → 16,11
-- Description: Global signals for support control in test benches
--
-- Dependencies: -
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 2.0 remove global clock cycle signal
-- 2016-09-02 805 2.1 rename SB_CLKSTOP > SB_SIMSTOP; init with 'L'
-- 2011-12-23 444 2.0 remove global clock cycle signal SB_CLKCYCLE
-- 2010-04-24 282 1.1 add SB_(VAL|ADDR|DATA)
-- 2008-03-24 129 1.0.1 use 31 bits for SB_CLKCYCLE
-- 2007-08-27 76 1.0 Initial version
32,15 → 33,15
 
package simbus is
signal SB_CLKSTOP : slbit := '0'; -- global clock stop
signal SB_CNTL : slv16 := (others=>'0'); -- global signals tb -> uut
signal SB_SIMSTOP : slbit := 'L'; -- global simulation stop
signal SB_CNTL : slv16 := (others=>'L'); -- global signals tb -> uut
signal SB_STAT : slv16 := (others=>'0'); -- global signals uut -> tb
signal SB_VAL : slbit := '0'; -- init bcast valid
signal SB_ADDR : slv8 := (others=>'0'); -- init bcast address
signal SB_DATA : slv16 := (others=>'0'); -- init bcast data
signal SB_VAL : slbit := 'L'; -- init bcast valid
signal SB_ADDR : slv8 := (others=>'L'); -- init bcast address
signal SB_DATA : slv16 := (others=>'L'); -- init bcast data
 
-- Note: SB_CNTL, SB_VAL, SB_ADDR, SB_DATA can have weak ('L','H') and
-- strong ('0','1') drivers. Therefore always remove strenght before
-- using, e.g. with to_x01()
-- Note: SB_SIMSTOP, SB_CNTL, SB_VAL, SB_ADDR, SB_DATA can have weak
-- ('L','H') and strong ('0','1') drivers. Therefore always remove
-- strenght before using, e.g. with to_x01()
end package simbus;
/trunk/rtl/vlib/simlib/simclk.vhd
1,6 → 1,6
-- $Id: simclk.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: simclk.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
18,10 → 18,11
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 2.0.1 CLK_STOP now optional port
-- 2011-12-23 444 2.0 remove CLK_CYCLE output port
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-03-24 129 1.0.2 CLK_CYCLE now 31 bits
35,11 → 36,11
 
entity simclk is -- test bench clock generator
generic (
PERIOD : time := 20 ns; -- clock period
OFFSET : time := 200 ns); -- clock offset (first up transition)
PERIOD : Delay_length := 20 ns; -- clock period
OFFSET : Delay_length := 200 ns); -- clock offset (first up transition)
port (
CLK : out slbit; -- clock
CLK_STOP : in slbit -- clock stop trigger
CLK_STOP : in slbit := '0' -- clock stop trigger
);
end entity simclk;
 
47,7 → 48,7
begin
 
proc_clk: process
constant clock_halfperiod : time := PERIOD/2;
constant clock_halfperiod : Delay_length := PERIOD/2;
begin
 
CLK <= '0';
/trunk/rtl/vlib/simlib/simclkcnt.vhd
1,4 → 1,4
-- $Id: simclkcnt.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: simclkcnt.vhd 787 2016-07-16 14:40:41Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
18,7 → 18,7
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31
-- Tool versions: xst 12.1-14.7; viv 2016.2; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
/trunk/rtl/vlib/simlib/simlib.vhd
1,4 → 1,4
-- $Id: simlib.vhd 774 2016-06-12 17:08:47Z mueller $
-- $Id: simlib.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2006-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
22,6 → 22,8
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 2.1.4 simclk(v): CLK_STOP,CLK_HOLD now optional ports
-- 2016-07-16 787 2.1.3 add simbididly component
-- 2016-06-12 774 2.1.2 add writetimens()
-- 2014-10-25 599 2.1.1 add wait_* procedures; writeoptint: no dat clear
-- 2014-10-18 597 2.1 add simfifo_*, writetrace procedures
240,9 → 242,9
dat : in slv); -- value
type clock_dsc is record -- clock descriptor
period : time; -- clock period
hold : time; -- hold time = clock yo stim time
setup : time; -- setup time = moni to clock time
period : Delay_length; -- clock period
hold : Delay_length; -- hold time = clock yo stim time
setup : Delay_length; -- setup time = moni to clock time
end record;
 
procedure wait_nextstim( -- wait for next stim time
294,11 → 296,11
 
component simclk is -- test bench clock generator
generic (
PERIOD : time := 20 ns; -- clock period
OFFSET : time := 200 ns); -- clock offset (first up transition)
PERIOD : Delay_length := 20 ns; -- clock period
OFFSET : Delay_length := 200 ns); -- clock offset (first up transition)
port (
CLK : out slbit; -- clock
CLK_STOP : in slbit -- clock stop trigger
CLK_STOP : in slbit := '0' -- clock stop trigger
);
end component;
 
306,9 → 308,9
-- with variable periods
port (
CLK : out slbit; -- clock
CLK_PERIOD : in time; -- clock period
CLK_HOLD : in slbit; -- if 1, hold clocks in 0 state
CLK_STOP : in slbit -- clock stop trigger
CLK_PERIOD : in Delay_length; -- clock period
CLK_HOLD : in slbit := '0'; -- if 1, hold clocks in 0 state
CLK_STOP : in slbit := '0' -- clock stop trigger
);
end component;
 
319,6 → 321,16
);
end component;
 
component simbididly is -- test bench bi-directional bus delay
generic (
DELAY : Delay_length; -- transport delay between A and B
DWIDTH : positive := 16); -- data port width
port (
A : inout slv(DWIDTH-1 downto 0); -- port A
B : inout slv(DWIDTH-1 downto 0) -- port B
);
end component;
 
end package simlib;
 
-- ----------------------------------------------------------------------------
/trunk/rtl/vlib/xlib/Makefile
0,0 → 1,37
# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-20 749 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#
/trunk/rtl/vlib/xlib/dcm_sfs_gsim.vhd
1,4 → 1,4
-- $Id: dcm_sfs_gsim.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: dcm_sfs_gsim.vhd 790 2016-07-20 18:52:44Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
48,7 → 48,7
architecture sim of dcm_sfs is
 
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : time := 0 ns;
signal CLKOUT_PERIOD : Delay_length := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
56,8 → 56,8
 
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
92,8 → 92,8
 
proc_clkout : process
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
 
/trunk/rtl/vlib/xlib/gsr_pulse.vbom
0,0 → 1,4
# libs
@lib:unisim
# design
gsr_pulse.vhd
/trunk/rtl/vlib/xlib/gsr_pulse.vhd
0,0 → 1,54
-- $Id: gsr_pulse.vhd 809 2016-09-18 19:49:14Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gsr_pulse - sim
-- Description: pulse GSR at startup
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- 2016-09-17 808 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.ALL;
 
entity gsr_pulse is -- pulse GSR at startup
generic (
GSR_WIDTH : Delay_length:= 100 ns); -- GSR pulse length
end gsr_pulse;
 
 
architecture sim of gsr_pulse is
 
begin
 
process
begin
 
-- Uses weak driver to prevent a driver clash when glbl.v is loaded too
-- In case glbl.v is present it will overwrite (to be tested...)
UNISIM.VCOMPONENTS.GSR <= 'H';
wait for GSR_WIDTH;
UNISIM.VCOMPONENTS.GSR <= 'L';
wait;
end process;
 
end sim;
/trunk/rtl/vlib/xlib/gsr_pulse_dummy.vbom
0,0 → 1,4
# libs
# components
# design
gsr_pulse_dummy.vhd
/trunk/rtl/vlib/xlib/gsr_pulse_dummy.vhd
0,0 → 1,41
-- $Id: gsr_pulse_dummy.vhd 809 2016-09-18 19:49:14Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gsr_pulse - sim
-- Description: pulse GSR at startup (no action dummy for behavioral sims)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- 2016-09-17 808 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity gsr_pulse is -- pulse GSR at startup
generic (
GSR_WIDTH : Delay_length:= 100 ns); -- GSR pulse length
end gsr_pulse;
 
 
architecture sim of gsr_pulse is
 
begin
 
-- dummy, for behavioral simulations without VCOMPONENTS
 
end sim;
/trunk/rtl/vlib/xlib/s6_cmt_sfs_gsim.vhd
1,4 → 1,4
-- $Id: s6_cmt_sfs_gsim.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: s6_cmt_sfs_gsim.vhd 799 2016-08-21 09:20:19Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,10 → 19,11
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-6
-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.31
-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-08-18 799 1.0.1 remove 'assert false' from report statements
-- 2013-10-06 538 1.0 Initial version (derived from s7_cmt_sfs_gsim)
------------------------------------------------------------------------------
 
51,7 → 52,7
architecture sim of s6_cmt_sfs is
 
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : time := 0 ns;
signal CLKOUT_PERIOD : Delay_length := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
65,12 → 66,12
constant f_pdmin_pll : integer := 19;
constant f_pdmax_pll : integer := 375;
 
variable t_vco : time := 0 ns;
variable t_vcomin : time := 0 ns;
variable t_vcomax : time := 0 ns;
variable t_pd : time := 0 ns;
variable t_pdmin : time := 0 ns;
variable t_pdmax : time := 0 ns;
variable t_vco : Delay_length := 0 ns;
variable t_vcomin : Delay_length := 0 ns;
variable t_vcomax : Delay_length := 0 ns;
variable t_pd : Delay_length := 0 ns;
variable t_pdmin : Delay_length := 0 ns;
variable t_pdmax : Delay_length := 0 ns;
 
begin
-- validate generics
77,8 → 78,7
 
if not (GEN_TYPE = "PLL" or GEN_TYPE = "DCM") then
assert false
report "assert(GEN_TYPE='PLL' or GEN_TYPE='DCM')"
report "assert(GEN_TYPE='PLL' or GEN_TYPE='DCM')"
severity failure;
end if;
 
90,8 → 90,7
VCO_MULTIPLY<1 or VCO_MULTIPLY>64 or
OUT_DIVIDE<1 or OUT_DIVIDE>128
then
assert false
report
report
"assert(VCO_DIVIDE in 1:52 VCO_MULTIPLY in 1:64 OUT_DIVIDE in 1:128)"
severity failure;
end if;
106,14 → 105,12
t_vco := t_pd / VCO_MULTIPLY;
 
if t_vco<t_vcomin or t_vco>t_vcomax then
assert false
report "assert(VCO frequency out of range)"
report "assert(VCO frequency out of range)"
severity failure;
end if;
if t_pd<t_pdmin or t_pd>t_pdmax then
assert FALSE
report "assert(PD frequency out of range)"
report "assert(PD frequency out of range)"
severity failure;
end if;
 
125,8 → 122,7
VCO_MULTIPLY<2 or VCO_MULTIPLY>32 or
OUT_DIVIDE/=1
then
assert false
report
report
"assert(VCO_DIVIDE in 1:32 VCO_MULTIPLY in 2:32 OUT_DIVIDE=1)"
severity failure;
end if;
139,8 → 135,8
 
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
175,8 → 171,8
 
proc_clkout : process
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
 
/trunk/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd
1,4 → 1,4
-- $Id: s7_cmt_sfs_gsim.vhd 760 2016-04-09 16:17:13Z mueller $
-- $Id: s7_cmt_sfs_gsim.vhd 799 2016-08-21 09:20:19Z mueller $
--
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,10 → 19,11
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Series-7
-- Tool versions: xst 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.31
-- Tool versions: xst 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-08-18 799 1.1.1 remove 'assert false' from report statements
-- 2016-04-09 760 1.1 BUGFIX: correct mmcm range check boundaries
-- 2013-09-28 535 1.0 Initial version (derived from dcm_sfs_gsim)
------------------------------------------------------------------------------
55,7 → 56,7
architecture sim of s7_cmt_sfs is
 
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : time := 0 ns;
signal CLKOUT_PERIOD : Delay_length := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
74,12 → 75,12
constant f_pdmin_mmcm : integer := 10;
constant f_pdmax_mmcm : integer := 450;
 
variable t_vco : time := 0 ns;
variable t_vcomin : time := 0 ns;
variable t_vcomax : time := 0 ns;
variable t_pd : time := 0 ns;
variable t_pdmin : time := 0 ns;
variable t_pdmax : time := 0 ns;
variable t_vco : Delay_length := 0 ns;
variable t_vcomin : Delay_length := 0 ns;
variable t_vcomax : Delay_length := 0 ns;
variable t_pd : Delay_length := 0 ns;
variable t_pdmin : Delay_length := 0 ns;
variable t_pdmax : Delay_length := 0 ns;
 
begin
-- validate generics
86,8 → 87,7
 
if not (GEN_TYPE = "PLL" or GEN_TYPE = "MMCM") then
assert false
report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
severity failure;
end if;
 
99,8 → 99,7
VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
OUT_DIVIDE<1 or OUT_DIVIDE>128
then
assert false
report
report
"assert(VCO_DIVIDE in 1:56 VCO_MULTIPLY in 2:64 OUT_DIVIDE in 1:128)"
severity failure;
end if;
118,8 → 117,7
VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
OUT_DIVIDE<1 or OUT_DIVIDE>128
then
assert false
report
report
"assert(VCO_DIVIDE in 1:106 VCO_MULTIPLY in 2:64 OUT_DIVIDE in 1:128)"
severity failure;
end if;
136,14 → 134,12
t_vco := t_pd / VCO_MULTIPLY;
 
if t_vco<t_vcomin or t_vco>t_vcomax then
assert false
report "assert(VCO frequency out of range)"
report "assert(VCO frequency out of range)"
severity failure;
end if;
if t_pd<t_pdmin or t_pd>t_pdmax then
assert FALSE
report "assert(PD frequency out of range)"
report "assert(PD frequency out of range)"
severity failure;
end if;
 
154,8 → 150,8
 
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
190,8 → 186,8
 
proc_clkout : process
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
 
/trunk/rtl/vlib/xlib/tb/s7_cmt_sfs_tb.vhd
1,4 → 1,4
-- $Id: s7_cmt_sfs_tb.vhd 760 2016-04-09 16:17:13Z mueller $
-- $Id: s7_cmt_sfs_tb.vhd 799 2016-08-21 09:20:19Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,10 → 19,11
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Series-7
-- Tool versions: xst 14.7; viv 2015.4; ghdl 0.31
-- Tool versions: xst 14.7; viv 2015.4-2016.2; ghdl 0.31-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-08-18 799 1.1.1 remove 'assert false' from report statements
-- 2016-04-09 760 1.1 BUGFIX: correct mmcm range check boundaries
-- 2016-02-20 734 1.0 Initial version (copied from s7_cmt_sfs_gsim)
------------------------------------------------------------------------------
52,7 → 53,7
architecture sim of s7_cmt_sfs_tb is
 
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : time := 0 ns;
signal CLKOUT_PERIOD : Delay_length := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
71,12 → 72,12
constant f_pdmin_mmcm : integer := 10;
constant f_pdmax_mmcm : integer := 450;
 
variable t_vco : time := 0 ns;
variable t_vcomin : time := 0 ns;
variable t_vcomax : time := 0 ns;
variable t_pd : time := 0 ns;
variable t_pdmin : time := 0 ns;
variable t_pdmax : time := 0 ns;
variable t_vco : Delay_length := 0 ns;
variable t_vcomin : Delay_length := 0 ns;
variable t_vcomax : Delay_length := 0 ns;
variable t_pd : Delay_length := 0 ns;
variable t_pdmin : Delay_length := 0 ns;
variable t_pdmax : Delay_length := 0 ns;
 
begin
-- validate generics
83,8 → 84,7
 
if not (GEN_TYPE = "PLL" or GEN_TYPE = "MMCM") then
assert false
report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
severity failure;
end if;
 
96,8 → 96,7
VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
OUT_DIVIDE<1 or OUT_DIVIDE>128
then
assert false
report
report
"assert(VCO_DIVIDE in 1:56 VCO_MULTIPLY in 2:64 OUT_DIVIDE in 1:128)"
severity failure;
end if;
115,8 → 114,7
VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
OUT_DIVIDE<1 or OUT_DIVIDE>128
then
assert false
report
report
"assert(VCO_DIVIDE in 1:106 VCO_MULTIPLY in 2:64 OUT_DIVIDE in 1:128)"
severity failure;
end if;
133,15 → 131,13
t_vco := t_pd / VCO_MULTIPLY;
 
if t_vco<t_vcomin or t_vco>t_vcomax then
assert false
report "assert(VCO frequency out of range); t_cvo: "
report "assert(VCO frequency out of range); t_cvo: "
& time'image(t_vco)
severity failure;
end if;
if t_pd<t_pdmin or t_pd>t_pdmax then
assert FALSE
report "assert(PD frequency out of range)"
report "assert(PD frequency out of range)"
severity failure;
end if;
 
152,8 → 148,8
 
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
188,8 → 184,8
 
proc_clkout : process
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
 
/trunk/rtl/w11a/Makefile
0,0 → 1,37
# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-20 749 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#
/trunk/rtl/w11a/pdp11_bram_memctl.vhd
1,4 → 1,4
-- $Id: pdp11_bram_memctl.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: pdp11_bram_memctl.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
22,7 → 22,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-03-20 749 1.1 use ram_1swsr_wfirst_gen rather BRAM_SINGLE_MACRO
-- 2015-02-08 644 1.0 Initial version
------------------------------------------------------------------------------
/trunk/rtl/w11a/pdp11_cache.vhd
1,4 → 1,4
-- $Id: pdp11_cache.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: pdp11_cache.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2008-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
33,7 → 33,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-03-22 751 1.1 now configurable size (8,16,32,64,128 kB)
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-02-23 118 1.0.2 ce cache in s_idle to avoid U's in sim
/trunk/rtl/w11a/pdp11_core.vhd
1,6 → 1,6
-- $Id: pdp11_core.vhd 702 2015-07-19 17:36:09Z mueller $
-- $Id: pdp11_core.vhd 812 2016-10-03 18:39:50Z mueller $
--
-- Copyright 2006-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
27,9 → 27,10
-- tb/tb_rlink_tba_pdp11core
--
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-10-03 812 1.4.3 drop SNUM signal, not used anymore
-- 2015-07-19 702 1.4.2 add DM_STAT_SE port; re-arrange DM_STAT_CO usage
-- 2015-07-05 697 1.4.1 wire istart,istop,cpustep to DM_STAT_CO
-- 2015-06-26 695 1.4.1 connect SNUM (current state number)
115,7 → 116,6
signal INT_VECT : slv9_2 := (others=>'0');
signal CP_STAT_L : cp_stat_type := cp_stat_init;
signal INT_ACK : slbit := '0';
signal SNUM : slv8 := (others=>'0');
 
signal IB_SRES_DP : ib_sres_type := ib_sres_init;
signal IB_SRES_SEQ : ib_sres_type := ib_sres_init;
/trunk/rtl/w11a/pdp11_core_rbus.vhd
1,4 → 1,4
-- $Id: pdp11_core_rbus.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: pdp11_core_rbus.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
27,7 → 27,7
--
-- Revision History: -
-- Date Rev Version Comment
-- 2016-05-22 787 1.5.2 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 1.5.2 don't init N_REGS (vivado fix for fsm inference)
-- 2015-07-10 700 1.5.1 add cpuact logic, redefine lam as cpuact 1->0
-- 2015-05-09 677 1.5 start/stop/suspend overhaul; reset overhaul
-- 2014-12-26 621 1.4 use full size 4k word ibus window
/trunk/rtl/w11a/pdp11_dmscnt.vhd
1,4 → 1,4
-- $Id: pdp11_dmscnt.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: pdp11_dmscnt.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
27,7 → 27,7
--
-- Revision History: -
-- Date Rev Version Comment
-- 2016-05-22 787 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2015-12-28 721 1.1 use laddr/waddr; use ena instead of cnt;
-- 2015-07-19 702 1.0 Initial version
-- 2015-06-26 695 1.0 First draft
/trunk/rtl/w11a/pdp11_sequencer.vhd
1,4 → 1,4
-- $Id: pdp11_sequencer.vhd 768 2016-05-26 16:47:00Z mueller $
-- $Id: pdp11_sequencer.vhd 812 2016-10-03 18:39:50Z mueller $
--
-- Copyright 2006-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
22,6 → 22,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-10-03 812 1.6.7 always define DM_STAT_SE.snum
-- 2016-05-26 768 1.6.6 don't init N_REGS (vivado fix for fsm inference)
-- proc_snum conditional (vivado fsm workaround)
-- 2015-08-02 708 1.6.5 BUGFIX: proper trap_mmu and trap_ysv handling
2403,7 → 2404,7
 
-- state number creation logic is conditional, only done when monitor
-- enabled. Due to sythnesis impact in vivado
SNUM : if sys_conf_dmscnt generate
SNUM1 : if sys_conf_dmscnt generate
begin
proc_snum : process (R_STATE)
variable isnum : slv8 := (others=>'0');
2542,7 → 2543,12
end case;
DM_STAT_SE.snum <= isnum;
end process proc_snum;
end generate SNUM;
end generate SNUM1;
 
SNUM0 : if not sys_conf_dmscnt generate
begin
DM_STAT_SE.snum <= (others=>'0');
end generate SNUM0;
end syn;
/trunk/rtl/w11a/pdp11_sim.vhd
1,4 → 1,4
-- $Id: pdp11_sim.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: pdp11_sim.vhd 790 2016-07-20 18:52:44Z mueller $
--
-- Copyright 2006-2007 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
31,10 → 31,10
 
package pdp11_sim is
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 5 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 5 ns;
 
end package pdp11_sim;
 
/trunk/rtl/w11a/pdp11_vmbox.vhd
1,4 → 1,4
-- $Id: pdp11_vmbox.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: pdp11_vmbox.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2006-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
27,7 → 27,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.6.6 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 1.6.6 don't init N_REGS (vivado fix for fsm inference)
-- 2015-07-03 697 1.6.5 much wider DM_STAT_VM
-- 2015-04-04 662 1.6.4 atowidth now 6 (was 5) to support ibdr_rprm reset
-- 2011-11-18 427 1.6.3 now numeric_std clean
/trunk/rtl/w11a/tb/Makefile
5,6 → 5,7
# 2016-03-13 744 1.0 Initial version
#
EXE_all = tb_pdp11core
EXE_all += tb_rlink_tba_pdp11core
 
#
# reference board for test synthesis is Artix-7 based Nexys4
/trunk/rtl/w11a/tb/tb_pdp11core_ssim.vbom
1,4 → 1,6
# configure for _*sim case
# configure
uut = tbd_pdp11core_ssim.vhd
# design
tb_pdp11core.vbom
@top:tb_pdp11core
/trunk/rtl/w11a/tb/tb_pdp11core_ubmap.dat
0,0 → 1,305
# $Id: tb_pdp11core_ubmap.dat 674 2015-05-04 16:17:40Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2015-05-03 674 1.5 start/stop/suspend overhaul
# 2008-03-02 121 1.0 extracted from sys/tb/tb_s3board_pdp11core_mem70
#
.mode pdpcp
.tocmd 50
.tostp 100
.togo 5000
.rlmon 0
.rbmon 0
#
.reset
.wait 10
.anena 1
#
#-----------------------------------------------------------------------------
C Test 1: Write/Read ubmap registers
wal 170200
bwm 64
177777 -- write all bits
177777 -- write all bits
000100 -- map 1
000001
000200 -- map 2
000002
000300 -- map 3
000003
000400 -- map 4
000004
000500 -- map 5
000005
000600 -- map 6
000006
000700 -- map 7
000007
001000 -- map 10
000010
001100 -- map 11
000011
001200 -- map 12
000012
001300 -- map 13
000013
001400 -- map 14
000014
001500 -- map 15
000015
001600 -- map 16
000016
001700 -- map 17
000017
002000 -- map 20
000020
002100 -- map 21
000021
002200 -- map 22
000022
002300 -- map 23
000023
002400 -- map 24
000024
002500 -- map 25
000025
002600 -- map 26
000026
002700 -- map 27
000027
003000 -- map 30
000030
003100 -- map 31
000031
003200 -- map 32
000032
003300 -- map 33
000033
003400 -- map 34
000034
003500 -- map 35
000035
003600 -- map 36
000036
003700 -- map 37
000037
wal 170200
brm 64
d=177776 -- only 15:01 are writable, bit 0 is 0
d=000077 -- only 5:00 are writable, upper 10 bits are 0
d=000100 -- map 1
d=000001
d=000200 -- map 2
d=000002
d=000300 -- map 3
d=000003
d=000400 -- map 4
d=000004
d=000500 -- map 5
d=000005
d=000600 -- map 6
d=000006
d=000700 -- map 7
d=000007
d=001000 -- map 10
d=000010
d=001100 -- map 11
d=000011
d=001200 -- map 12
d=000012
d=001300 -- map 13
d=000013
d=001400 -- map 14
d=000014
d=001500 -- map 15
d=000015
d=001600 -- map 16
d=000016
d=001700 -- map 17
d=000017
d=002000 -- map 20
d=000020
d=002100 -- map 21
d=000021
d=002200 -- map 22
d=000022
d=002300 -- map 23
d=000023
d=002400 -- map 24
d=000024
d=002500 -- map 25
d=000025
d=002600 -- map 26
d=000026
d=002700 -- map 27
d=000027
d=003000 -- map 30
d=000030
d=003100 -- map 31
d=000031
d=003200 -- map 32
d=000032
d=003300 -- map 33
d=000033
d=003400 -- map 34
d=000034
d=003500 -- map 35
d=000035
d=003600 -- map 36
d=000036
d=003700 -- map 37
d=000037
#
#-----------------------------------------------------------------------------
C Test 2: Write/Read memory via bwm/brm and Unibus map
#
wal 170200 -- setup test map
bwm 4
000000 -- map 0: 000000 -> 000000
000000 --
004000 -- map 1: 020000 -> 004000
000000
wal 170200 -- verify test map
brm 4
d=000000 -- map 0
d=000000 --
d=004000 -- map 1
d=000000
#
C Test 2.1 write/read with ubmap off in MMU
#
wal 020000 -- Page 1
wah 000200 -- ubmap=1
bwm 4
000100
000101
000102
000103
wal 020000
brm 4
d=000100
d=000101
d=000102
d=000103
#
C Test 2.2 write/read with ubmap on in MMU
#
wal 172516 -- SSR3
wm 000040 -- set ubmap=1
wal 020000 -- Page 1
wah 000200 -- ubmap=1
bwm 4
000200
000201
000202
000203
wal 020000 -- check that old transfer data unchanged
brm 4
d=000100
d=000101
d=000102
d=000103
wal 004000 -- 020000 was mapped to 004000, check data
brm 4
d=000200
d=000201
d=000202
d=000203
#-----------------------------------------------------------------------------
C Test 3: Write/Read memory via bwm/brm and Unibus map while CPU running
C Setup trap catchers
#
# FU DATA C
wal 000004 -- vectors: 4...34 (trap catcher)
bwm 14
000006 -- PC:06 ; vector 4
000000 -- PS:0
000012 -- PC:12 ; vector 10
000000 -- PS:0
000016 -- PC:16 ; vector 14 (T bit; BPT)
000000 -- PS:0
000022 -- PC:22 ; vector 20 (IOT)
000000 -- PS:0
000026 -- PC:26 ; vector 24 (Power fail, not used)
000000 -- PS:0
000032 -- PC:32 ; vector 30 (EMT)
000000 -- PS:0
000036 -- PC:36 ; vector 34 (TRAP)
000000 -- PS:0
wal 000240 -- vectors: 240,244,250 (trap catcher)
bwm 6
000242 -- PC:242 ; vector 240 (PIRQ)
000000 -- PS:0
000246 -- PC:246 ; vector 244 (FPU)
000000 -- PS:0
000252 -- PC:252 ; vector 250 (MMU)
000000 -- PS:0
#
C Setup Code
#
wal 002000
bwm 7
005211 -- inc (r1) ; increment a mem location
005312 -- dec (r2) ; decrement a ubus location
005700 -- tst r0 ; test for loop
001774 -- beq .-4 ; loop while r0=0
011103 -- mov (r1),r3 ; sum mem and ubus location
061203 -- add (r2),r3 ; r3 should be 0
000000 -- halt
#
C Start Code
wr0 000000 -- 0 for looping
wr1 002100 -- a mem addr
wr2 172256 -- a ubus addr: MMU SM mode AR page 7 (is a 16bit r/w reg)
wpc 002000
sta -- 'start' does no reset (keeps SSR3.ubmap=1)
#
wal 020200 -- Page 1
wah 000200 -- ubmap=1
bwm 16
000300
000301
000302
000303
000304
000305
000306
000307
000310
000311
000312
000313
000314
000315
000316
000317
#
wr0 000001 -- 1 for stop looping
wtgo -- wait for cpu halt
#
rpc d=002016 -- ! pc
wal 002100 -- check mem loc (for visual inspection)
rm d=-
wal 172256 -- check ubus loc (for visual inspection)
rm d=-
rr3 d=000000 -- ! r3 (is sum of mem and ubus location)
#
wal 004200 -- 020200 was mapped to 004200, check data
brm 16
d=000300
d=000301
d=000302
d=000303
d=000304
d=000305
d=000306
d=000307
d=000310
d=000311
d=000312
d=000313
d=000314
d=000315
d=000316
d=000317
/trunk/rtl/w11a/tb/tb_rlink_tba_pdp11core.vbom
0,0 → 1,8
# configure tb_rlink_tba with rbd_tba_pdp11core target;
# use vhdl configure file (tb_rlink_tba_pdp11core.vhd) to allow
# that all configurations will co-exist in work library
# configure
rbtba_aif = tbd_tba_pdp11core.vbom
# design
../../vlib/rlink/tb/tb_rlink_tba.vbom
tb_rlink_tba_pdp11core.vhd
/trunk/rtl/w11a/tb/tb_rlink_tba_pdp11core.vhd
0,0 → 1,44
-- $Id: tb_rlink_tba_pdp11core.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_rlink_tba_pdp11core
-- Description: Configuration for tb_rlink_tba_pdp11core for tb_rlink_tba.
--
-- Dependencies: tbd_tba_pdp11core
--
-- To test: pdp11_core_rbus
-- pdp11_core
--
-- Verified (with tb_rlink_tba_pdp11core_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2010-12-30 351 _ssim 0.29 12.1 xc3s1000 c:ok
-- 2010-12-30 351 - 0.29 - c:ok
-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-12 88 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-30 351 1.1 renamed from tb_rritba_pdp11core
-- 2007-08-10 72 1.0 Initial version
------------------------------------------------------------------------------
 
configuration tb_rlink_tba_pdp11core of tb_rlink_tba is
 
for sim
for all : rbtba_aif
use entity work.tbd_tba_pdp11core;
end for;
end for;
 
end tb_rlink_tba_pdp11core;
/trunk/rtl/w11a/tb/tb_rlink_tba_pdp11core_ibdr.dat
0,0 → 1,154
# $Id: tb_rlink_tba_pdp11core_ibdr.dat 675 2015-05-08 21:05:08Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2015-05-03 674 1.5 start/stop/suspend overhaul
# 2014-12-26 621 1.4 adopt wmembe,ribr,wibr testing to new 4k window
# 2014-09-27 595 1.3 now for rlink v4 iface
# 2014-08-15 583 1.2 rb_mreq addr now 16 bit
# 2010-06-18 306 1.1 adapt to new rri<->cp implementation
# 2008-03-02 121 1.0.2 test byte access via RRI
# 2008-02-24 119 1.0.1 added lah,rps,wps command definition
# 2008-01-20 113 1.0 Initial version
#
.mode rri
.wait 5
.rlmon 0
.rbmon 0
.cmax 32
#
# setup address mnemonics
.amclr
#
# cpu addresses
#
.amdef conf 0000000000000000
.amdef cntl 0000000000000001
.amdef stat 0000000000000010
.amdef psw 0000000000000011
.amdef al 0000000000000100
.amdef ah 0000000000000101
.amdef mem 0000000000000110
.amdef memi 0000000000000111
#
.amdef r0 0000000000001000
.amdef r1 0000000000001001
.amdef r2 0000000000001010
.amdef r3 0000000000001011
.amdef r4 0000000000001100
.amdef r5 0000000000001101
.amdef sp 0000000000001110
.amdef pc 0000000000001111
.amdef membe 0000000000010000
#
# ibus -> ibr mapping: (addr-160000)/2 + 40000
# RKWC: 177406 -> ibr 047603
# RKBA: 177410 -> ibr 047604
# XCSR: 177564 -> ibr 047672
# XBUF: 177566 -> ibr 047673
#
.amdef RKWC o"047603"
.amdef RKBA o"047604"
.amdef XCSR o"047672"
.amdef XBUF o"047673"
#
# setup stat check default
.sdef s=00000000
#
C cmderr
C |cmdmerr
C ||cpususp
C |||cpugo
C ||||attention flags set
C |||||rbtout
C ||||||rbnak
C |||||||rberr
C ||||||||
C 00000000
C
C cmd addr ----stat ------------data ---check---
C
C -----------------------------------------------------------------------------
C Reset CPU to get defined state
#
wreg .cntl o"000004" -- init (cpfunc_creset=00100)
#
C -----------------------------------------------------------------------------
C write/read membe register (is 2:0)
#
wreg .membe o"000001" -- set membe (be=01 stick=0)
rreg .membe d=o"000001" -- ! membe
wreg .membe o"000006" -- set membe (be=10 stick=1)
rreg .membe d=o"000006" -- ! membe
wreg .membe o"000003" -- set membe (be=11 stick=0)
rreg .membe d=o"000003" -- ! membe
#
C -----------------------------------------------------------------------------
C read/write a ibd register via CPU and RRI (use RK11 RKWC/RKBA [177406/177410])
#
wreg .al o"177406" --#RKWC
wreg .memi o"123456" -- write RKWC via CPU
wreg .memi o"170707" -- write RKBA via CPU
wreg .al o"177406" --
rreg .memi d=o"123456" -- read RKWC via CPU
rreg .memi d=o"170707" -- read RKBA via CPU
#
rreg .RKWC d=o"123456" -- read RKWC via RRI
rreg .RKBA d=o"170707" -- read RKBA via RRI
wreg .RKWC o"107070" -- write RKWC via RRI
wreg .RKBA o"106060" -- write RKBA via RRI
#
wreg .al o"177406" -- #RKWC
rreg .memi d=o"107070" -- read RKWC via CPU
rreg .memi d=o"106060" -- read RKBA via CPU
#
C -----------------------------------------------------------------------------
C byte read/write a ibd register via RRI (use RK11 RKWC [177406])
#
wreg .al o"177406" --#RKWC
wreg .membe o"000003" -- set membe
rreg .membe d=o"000003" -- ! membe
wreg .RKWC o"070070" -- write RKWC via RRI
rreg .mem d=o"070070" -- read RKWC via CPU
#
wreg .membe o"000001" -- set membe (address lower byte)
rreg .membe d=o"000001" -- ! membe
wreg .RKWC o"000060" -- write RKWC via RRI
rreg .mem d=o"070060" -- read RKWC via CPU
#
wreg .membe o"000002" -- set membe (address upper byte)
rreg .membe d=o"000002" -- ! membe
wreg .RKWC o"060000" -- write RKWC via RRI
rreg .mem d=o"060060" -- read RKWC via CPU
#
rreg .membe d=o"000003" -- ! membe (wasn't sticky, so 11)
wreg .RKWC o"050050" -- write RKWC via RRI
rreg .mem d=o"050050" -- read RKWC via CPU
#
wreg .membe o"000005" -- set membe (address lower byte, sticky
rreg .membe d=o"000005" -- ! membe
wreg .RKWC o"000040" -- write RKWC via RRI
rreg .mem d=o"050040" -- read RKWC via CPU
rreg .membe d=o"000005" -- ! membe (now sticky, stays!)
wreg .RKWC o"000030" -- write RKWC via RRI
rreg .mem d=o"050030" -- read RKWC via CPU
#
wreg .membe o"000003" -- set membe
rreg .membe d=o"000003" -- ! membe
#
C -----------------------------------------------------------------------------
C test device attention (use DL11 XCSR/XBUF [177564/177566])
#
rreg .XCSR d=o"000200" -- read XCSR via RRI: XRDY=1
rreg .XBUF d=o"001000" -- read XBUF via RRI: RRDY=1,XDONE=0
wreg .al o"177566" -- #XBUF
wreg .mem o"000123" s=00001000 -- write XBUF via CPU
rreg .XCSR d=o"000000" s=00001000 -- read XCSR via RRI: XRDY=0
rreg .XBUF d=o"001523" s=00001000 -- read XBUF via RRI: RRDY=1,XDONE=1
rreg .XBUF d=o"001123" s=00001000 -- read2 XBUF via RRI: RRDY=1,XDONE=0
rreg .XCSR d=o"000200" s=00001000 -- read XCSR via RRI: XRDY=1
attn d=o"000002" s=00000000 -- read/clean LAM's: lam(1) used by DL11
#
C -----------------------------------------------------------------------------
C finally reset CPU
wreg .cntl o"000004" -- init (cpfunc_creset=00100)
/trunk/rtl/w11a/tb/tb_rlink_tba_pdp11core_ssim.vbom
0,0 → 1,9
# configure tb_rlink_tba with tbd_tba_pdp11core target;
# use vhdl configure file (tb_rlink_tba_pdp11core.vhd) to allow
# that all configurations will co-exist in work library
# configure
rbtba_aif = tbd_tba_pdp11core_ssim.vhd
# design
../../vlib/rlink/tb/tb_rlink_tba.vbom
tb_rlink_tba_pdp11core.vhd
@top : tb_rlink_tba_pdp11core
/trunk/rtl/w11a/tb/tb_rlink_tba_pdp11core_stim.dat
0,0 → 1,359
# $Id: tb_rlink_tba_pdp11core_stim.dat 805 2016-09-03 08:09:52Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2015-05-08 675 1.5 start/stop/suspend overhaul
# 2014-12-26 621 1.4 adopt wmembe,ribr,wibr testing to new 4k window
# 2014-12-20 614 1.6 now for rlink v4 iface
# 2014-08-15 583 1.5 rb_mreq addr now 16 bit
# 2014-07-31 576 1.4.1 only one data item per line after rblk/wblk
# 2010-06-13 305 1.4 adapt to new rri<->cp implementation
# 2008-05-03 143 1.3.4 adapt to new cpurust code for reset
# 2008-04-27 140 1.3.3 adapt to new stat interface (with cpursta)
# 2008-02-24 119 1.3.2 added lah,rps,wps command definition; use them
# 2008-01-20 113 1.3.1 CPU attn now on bit 0
# 2007-11-24 98 1.3 adapt to new internal init handling
# 2007-09-16 83 1.2.2 add 'rst' at end to get back into ground state
# 2007-09-02 79 1.2.1 add '.mode' command
# 2007-08-12 74 1.2 test LAM and attn handling
# 2007-08-10 72 1.1.1 renamed to tb_rritba_pdp11core_stim.dat
# 2007-07-29 70 1.1 use .amdef now
# 2007-07-28 69 1.0 Initial version
#
.mode rri
.wait 5
.rlmon 0
.rbmon 0
.cmax 32
#
# setup address mnemonics
.amclr
#
.amdef conf 0000000000000000
.amdef cntl 0000000000000001
.amdef stat 0000000000000010
.amdef psw 0000000000000011
.amdef al 0000000000000100
.amdef ah 0000000000000101
.amdef mem 0000000000000110
.amdef memi 0000000000000111
#
.amdef r0 0000000000001000
.amdef r1 0000000000001001
.amdef r2 0000000000001010
.amdef r3 0000000000001011
.amdef r4 0000000000001100
.amdef r5 0000000000001101
.amdef sp 0000000000001110
.amdef pc 0000000000001111
#
# setup stat check default
.sdef s=00000000
#
C cmderr
C |cmdmerr
C ||cpususp
C |||cpugo
C ||||attention flags set
C |||||rbtout
C ||||||rbnak
C |||||||rberr
C ||||||||
C 00000000
C
C cmd addr ----stat ------------data ---check---
C
C ----------------------------------------------------------------------------
C write registers
#
wreg .r0 o"000001" -- set r0
wreg .r1 o"000101" -- set r1
wreg .r2 o"000201" -- set r2
wreg .r3 o"000301" -- set r3
wreg .r4 o"000401" -- set r4
wreg .r5 o"000501" -- set r5
wreg .sp o"000601" -- set sp
wreg .pc o"000701" -- set pc
C ---------------------------------------------------------------------------
C read registers
#
rreg .r0 d=o"000001" -- ! r0
rreg .r1 d=o"000101" -- ! r1
rreg .r2 d=o"000201" -- ! r2
rreg .r3 d=o"000301" -- ! r3
rreg .r4 d=o"000401" -- ! r4
rreg .r5 d=o"000501" -- ! r5
rreg .sp d=o"000601" -- ! sp
rreg .pc d=o"000701" -- ! pc
C ---------------------------------------------------------------------------
C write memory (via wreg, use wreg/memi)
#
wreg .al o"002000" -- write mem(2000,...,2006)
wreg .memi o"007700"
wreg .memi o"007710"
wreg .memi o"007720"
wreg .memi o"007730"
C ----------------------------------------------------------------------------
C read memory (via rreg, use rreg/memi)
#
wreg .al o"002000"
rreg .memi d=o"007700"
rreg .memi d=o"007710"
rreg .memi d=o"007720"
rreg .memi d=o"007730"
C ----------------------------------------------------------------------------
C write memory (via wblk)
#
wreg .al o"002010" -- write mem(2010,...,2016)
wblk .memi 4
o"007740"
o"007750"
o"007760"
o"007770"
C ----------------------------------------------------------------------------
C read memory (via rblk)
#
wreg .al o"002000"
rblk .memi 8
d=o"007700"
d=o"007710"
d=o"007720"
d=o"007730"
d=o"007740"
d=o"007750"
d=o"007760"
d=o"007770"
C ----------------------------------------------------------------------------
C read/write PSW via various mechanisms
C via wps/rps
wreg .psw o"000017"
rreg .psw d=o"000017"
wreg .psw o"000000"
rreg .psw d=o"000000"
#
C via 16bit cp addressing (al 177776)
wreg .al o"177776" -- addr=psw
wreg .mem o"000017" -- set all cc flags in psw
rreg .mem d=o"000017" -- ! psw
rreg .psw d=o"000017"
wreg .mem o"000000" -- clear all cc flags in psw
rreg .mem d=o"000000" -- ! psw
rreg .psw d=o"000000"
#
C via 22bit cp addressing (al 177776; ah 177)
wreg .al o"177776" -- addr=psw
wreg .ah o"000177"
wreg .mem o"000017" -- set all cc flags in psw
rreg .mem d=o"000017" -- ! psw
rreg .psw d=o"000017"
wreg .mem o"000000" -- clear all cc flags in psw
rreg .mem d=o"000000" -- ! psw
rreg .psw d=o"000000"
C ----------------------------------------------------------------------------
C write register set 1, sm,um stack
#
wreg .psw o"004000" -- psw: cm=kernel, set=1
wreg .r0 o"010001" -- set r0 = 010001
wreg .r1 o"010101" -- set r1 = 010101
wreg .r2 o"010201" -- set r2 = 010201
wreg .r3 o"010301" -- set r3 = 010301
wreg .r4 o"010401" -- set r4 = 010401
wreg .r5 o"010501" -- set r5 = 010501
wreg .psw o"044000" -- psw: cm=super(01),set=1
wreg .sp o"010601" -- set ssp = 010601
wreg .psw o"144000" -- psw: cm=user(11),set=1
wreg .sp o"110601" -- set isp = 110601
C ----------------------------------------------------------------------------
C read all registers set 0/1, km,sm,um stack
#
wreg .psw o"000000" -- psw: cm=kernel(00),set=0
rreg .r0 d=o"000001" -- ! r0
rreg .r1 d=o"000101" -- ! r1
rreg .r2 d=o"000201" -- ! r2
rreg .r3 d=o"000301" -- ! r3
rreg .r4 d=o"000401" -- ! r4
rreg .r5 d=o"000501" -- ! r5
rreg .sp d=o"000601" -- ! ksp
rreg .pc d=o"000701" -- ! pc
#
wreg .psw o"040000" -- psw: cm=super(01),set=0
rreg .sp d=o"010601" -- ! ssp
wreg .psw o"140000" -- psw: cm=user(11),set=0
rreg .sp d=o"110601" -- ! usp
#
wreg .psw o"144000" -- psw: cm=user(11),set=1
rreg .r0 d=o"010001" -- ! r0
rreg .r1 d=o"010101" -- ! r1
rreg .r2 d=o"010201" -- ! r2
rreg .r3 d=o"010301" -- ! r3
rreg .r4 d=o"010401" -- ! r4
rreg .r5 d=o"010501" -- ! r5
#
wreg .psw o"000000" -- psw=000000;
C ----------------------------------------------------------------------------
C write,read IB space: : MMU SAR supervisor mode (16 bit regs)
#
wreg .al o"172240" -- addr=172240; SM I addr reg
wreg .memi o"012340" -- set 012340
wreg .memi o"012342" -- set 012342
wreg .memi o"012344" -- set 012344
#
wreg .al o"172240" -- addr=172240; SM I addr reg
rreg .memi d=o"012340" -- ! 012340
rreg .memi d=o"012342" -- ! 012342
rreg .memi d=o"012344" -- ! 012344
C ----------------------------------------------------------------------------
C load simple test code 1: "1$:inc r1; sob r0,1$; halt"
#
wreg .al o"002100" -- addr=002100
wreg .memi o"005201" -- inc r1
wreg .memi o"077002" -- sob r0,-2
wreg .memi o"000000" -- halt
C exec test code 1 w/ r0=2; wait 50 cycle; test regs
#
wreg .r0 o"000002" -- set r0 = 2
wreg .r1 o"000000" -- set r1 = 0
wreg .pc o"002100" -- set pc = 2100
wreg .cntl o"000001" s=00010000 -- start (cpfunc_start=00001)
.wait 50
rreg .r0 d=o"000000" s=00001000 -- ! r0=0
rreg .r1 d=o"000002" s=00001000 -- ! r1=2
rreg .pc d=o"002106" s=00001000 -- ! pc=002106
attn d=o"000001" s=00000000 -- read/clean LAM's
wreg .cntl o"000004" -- reset (cpfunc_creset=00100)
C ----------------------------------------------------------------------------
C single step through test code 1
#
wreg .r0 o"000003" -- set r0 = 3
wreg .r1 o"000000" -- set r1 = 0
wreg .pc o"002100" -- set pc = 2100
#
wreg .cntl o"000003" -- step over inc (cpfunc_step=00011)
rreg .r0 d=o"000003" -- ! r0=3
rreg .r1 d=o"000001" -- ! r1=1
rreg .pc d=o"002102" -- ! pc=002102
#
wreg .cntl o"000003" -- step over sob (cpfunc_step=00011)
rreg .r0 d=o"000002" -- ! r0=2
rreg .r1 d=o"000001" -- ! r1=1
rreg .pc d=o"002100" -- ! pc=002100
#
wreg .cntl o"000003" -- step over inc
wreg .cntl o"000003" -- step over sob
rreg .r0 d=o"000001" -- ! r0=1
rreg .r1 d=o"000002" -- ! r1=2
rreg .pc d=o"002100" -- ! pc=002100
C ----------------------------------------------------------------------------
C execute code 1, test stat command while it runs
#
wreg .r0 o"000005" -- set r0 = 5
wreg .r1 o"000000" -- set r1 = 0
wreg .pc o"002100" -- set pc = 2100
wreg .cntl o"000001" s=00010000 -- start (cpfunc_start=00001)
#rreg .stat d=0000000000000100 s=00000000 -- possible w/ tb, not FPGA !!
rreg .stat d=- s=- --
rreg .stat d=- s=- --
rreg .stat d=- s=- -- somewhere the code will stop
rreg .stat d=- s=- --
rreg .stat d=- s=- --
rreg .stat d=0000000000010000 s=00001000 -- ! cpurust=0001
rreg .r0 d=o"000000" s=00001000 -- ! r0=0
rreg .r1 d=o"000005" s=00001000 -- ! r1=5
rreg .pc d=o"002106" s=00001000 -- ! pc=002106
attn d=o"000001" s=00000000 -- read/clean LAM's
wreg .cntl o"000004" -- init (cpfunc_creset=00100)
rreg .stat d=0000000000000000 -- ! cpurust=0000
C ----------------------------------------------------------------------------
C execute code 1, look for attn comma to happen
#
wreg x"ffff" x"8000" -- set rlink anena=1
wreg .r0 o"000005" -- set r0 = 5
wreg .r1 o"000000" -- set r1 = 0
wreg .pc o"002100" -- set pc = 2100
wreg .cntl o"000001" s=00010000 -- start (cpfunc_start=00001)
.eop
.wtlam 100
rreg .stat d=0000000000010000 s=00001000 -- ! cpurust=0001
rreg .r0 d=o"000000" s=00001000 -- ! r0=0
rreg .r1 d=o"000005" s=00001000 -- ! r1=5
rreg .pc d=o"002106" s=00001000 -- ! pc=002106
attn d=o"000001" s=00000000 -- read/clean LAM's
wreg .cntl o"000004" -- init (cpfunc_creset=00100)
rreg .stat d=0000000000000000 -- ! cpurust=0000
C ----------------------------------------------------------------------------
C load test code 2 for single step testing of 'slow' instructions
#
wreg .al o"002200" -- addr=002200
wblk .memi 13
o"067070" -- add @0(r0),@6(r0)
o"000000"
o"000006"
o"067070" -- add @2(r0),@6(r0)
#2210
o"000002"
o"000006"
o"067070" -- add @4(r0),@6(r0)
o"000004"
#2220
o"000006"
o"067070" -- add @0(r0),@6(r0)
o"000000"
o"000006"
#2230
o"000000" -- halt
#
wreg .al o"002240" -- addr=002240
wblk .memi 12
o"002260" -- addresses used by add's
o"002262"
o"002264"
o"002266"
#2250
d"1" -- some data to test d"nnn"
d"-1"
x"dead"
x"beaf"
#2260
o"000010" -- input data used by add's
o"000100"
o"001000"
o"000001" -- result of add's
C ----------------------------------------------------------------------------
C single step through test code 2
#
wreg .pc o"002200" -- set pc = 2200
wreg .r0 o"002240" -- set r0 = 2240
wreg .cntl o"000003" -- step over 1st add (cpfunc_step=00011)
wreg .cntl o"000003" -- step over 2nd add (cpfunc_step=00011)
wreg .cntl o"000003" -- step over 3rd add (cpfunc_step=00011)
#
rreg .r0 d=o"002240" -- ! r0=2240
rreg .pc d=o"002222" -- ! pc=002222
wreg .al o"002240" -- addr=002240
rblk .memi 12
d=- -- skip over pointers, test tag=-
d=-
d=-
d=-
d=b"0000000000000001" -- verify data written with d"nn"
d=b"1111111111111111"
d=x"dead" -- check data written with x"nn"
d=x"beaf"
d=o"000010" -- input data used by add's
d=o"000100"
d=o"001000"
d=o"001111" -- result of add's
#
wreg .cntl o"000003" -- step over 4th add (cpfunc_step=00011)
wreg .cntl o"000003" s=00000000 -- step over halt (cpfunc_step=00011)
rreg .pc d=o"002232" s=00000000 -- ! pc=002232
wreg .al o"002260" s=00000000 -- addr=002260
rblk .memi 4 s=00000000
d=o"000010" -- input data used by add's
d=o"000100"
d=o"001000"
d=o"001121" -- result of add's
C ----------------------------------------------------------------------------
C finally stop and init CPU (clears cpuhalt flag)
wreg .cntl o"000002" -- stop (cpfunc_stop=00010)
wreg .cntl o"000004" -- init (cpfunc_creset=00100)
/trunk/rtl/w11a/tb/tbd_pdp11core.ucf
0,0 → 1,7
# $Id: tbd_pdp11core.ucf 351 2010-12-30 21:50:54Z mueller $
#
#
NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "CLK" ;
OFFSET = OUT 20 ns AFTER "CLK" ;
/trunk/rtl/w11a/tb/tbd_tba_pdp11core.vbom
0,0 → 1,18
# libs
../../vlib/slvtypes.vhd
../../vlib/genlib/genlib.vhd
../../ibus/iblib.vhd
../../ibus/ibdlib.vhd
../pdp11.vbom
${sys_conf := ../sys_conf.vhd}
../../vlib/rbus/rblib.vhd
# components
../../vlib/genlib/clkdivce.vbom
../pdp11_core_rbus.vbom
../pdp11_core.vbom
../pdp11_bram.vbom
../../ibus/ibdr_minisys.vbom
../../vlib/rbus/rb_sres_or_2.vbom
# design
tbd_tba_pdp11core.vhd
@xdc:../../vlib/generic_clk_100mhz.xdc
/trunk/rtl/w11a/tb/tbd_tba_pdp11core.vhd
0,0 → 1,216
-- $Id: tbd_tba_pdp11core.vhd 698 2015-07-05 21:20:18Z mueller $
--
-- Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_tba_pdp11core - syn
-- Description: tbd for testing pdp11_core_rbus plus ibdr_minisys
--
-- Dependencies: genlib/clkdivce
-- pdp11_core_rbus
-- pdp11_core
-- pdp11_bram
-- ibus/ibdr_minisys
-- rbus/rb_sres_or_2
--
-- Test bench: tb_rlink_tba_pdp11core
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
--
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2015-05-09 677 1.6 start/stop/suspend overhaul; reset overhaul
-- 2014-08-28 588 1.5.1 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
-- 2011-11-18 427 1.4.1 now numeric_std clean
-- 2010-12-30 351 1.4 renamed from tbd_pdp11core_rri; rbv3 port;
-- 2010-10-23 335 1.3.2 rename RRI_LAM->RB_LAM;
-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- remove pdp11_ibdr_rri
-- 2010-06-11 303 1.3 use IB_MREQ.racc instead of RRI_REQ
-- 2010-05-02 287 1.2.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- 2010-05-01 285 1.2 port to rri V2 interface
-- 2009-07-12 233 1.1.4 adapt to ibdr_minisys interface changes
-- 2008-08-22 161 1.1.3 use iblib, ibdlib
-- 2008-04-18 136 1.1.2 add RESET for ibdr_minisys
-- 2008-02-23 118 1.1.1 use sys_conf for bram size
-- 2008-02-17 117 1.1 adapt to em_ core interface; use pdp11_bram
-- 2008-01-20 113 1.0 Initial version (factored out from rrirp_pdp11core,
-- add rri access to ibdr now)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.genlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
use work.rblib.all;
 
entity tbd_tba_pdp11core is -- tbd pdp11_core_rbus plus ibdr_minisys
-- implements rbtba_aif
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ_aval : in slbit; -- rbus: request - aval
RB_MREQ_re : in slbit; -- rbus: request - re
RB_MREQ_we : in slbit; -- rbus: request - we
RB_MREQ_initt : in slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : in slv16; -- rbus: request - addr
RB_MREQ_din : in slv16; -- rbus: request - din
RB_SRES_ack : out slbit; -- rbus: response - ack
RB_SRES_busy : out slbit; -- rbus: response - busy
RB_SRES_err : out slbit; -- rbus: response - err
RB_SRES_dout : out slv16; -- rbus: response - dout
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv4 -- rbus: status flags
);
end entity tbd_tba_pdp11core;
 
 
architecture syn of tbd_tba_pdp11core is
 
signal CE_USEC : slbit := '0';
 
signal GRESET : slbit := '0';
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT : cp_stat_type := cp_stat_init;
signal CP_DOUT : slv16 := (others=>'0');
 
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
 
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
 
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
 
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal BRESET : slbit := '0';
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES : ib_sres_type := ib_sres_init;
 
begin
 
RB_MREQ.aval <= RB_MREQ_aval;
RB_MREQ.re <= RB_MREQ_re;
RB_MREQ.we <= RB_MREQ_we;
RB_MREQ.init <= RB_MREQ_initt;
RB_MREQ.addr <= RB_MREQ_addr;
RB_MREQ.din <= RB_MREQ_din;
 
RB_SRES_ack <= RB_SRES.ack;
RB_SRES_busy <= RB_SRES.busy;
RB_SRES_err <= RB_SRES.err;
RB_SRES_dout <= RB_SRES.dout;
 
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => open
);
 
RB2CP : pdp11_core_rbus
generic map (
RB_ADDR_CORE => slv(to_unsigned(16#0000#,16)),
RB_ADDR_IBUS => slv(to_unsigned(16#4000#,16)))
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM(0),
GRESET => GRESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT
);
 
W11A : pdp11_core
port map (
CLK => CLK,
RESET => GRESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
ESUSP_O => open,
ESUSP_I => '0',
ITIMER => open,
HBPT => '0',
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ,
IB_SRES_M => IB_SRES
);
MEM : pdp11_bram
generic map (
AWIDTH => sys_conf_bram_awidth)
port map (
CLK => CLK,
GRESET => GRESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES
);
IBDR_SYS : ibdr_minisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_USEC, -- !! in test benches msec = usec !!
RESET => GRESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => open
);
 
RB_SRES_OR : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_IBD,
RB_SRES_OR => RB_SRES
);
 
end syn;
/trunk/rtl/w11a/tb/tbrun.yml
0,0 → 1,21
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-21 799 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [default, viv, w11a, base]
test: |
tbrun_tbw --lsuf base tb_pdp11core${ms}
#
- tag: [default, viv, w11a, ubmap]
test: |
tbrun_tbw --lsuf ubmap tb_pdp11core${ms} tb_pdp11core_ubmap.dat
#
- tag: [default, viv, w11a, ibdr]
test: |
tbrun_tbw --lsuf ibdr tb_rlink_tba_pdp11core${ms} \
tb_rlink_tba_pdp11core_ibdr.dat
/trunk/tbrun.yml
0,0 → 1,19
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-27 802 1.0 Initial version
#
- include: rtl/vlib/comlib/tb/tbrun.yml
- include: rtl/vlib/serport/tb/tbrun.yml
- include: rtl/vlib/rlink/tb/tbrun.yml
- include: rtl/bplib/issi/tb/tbrun.yml
- include: rtl/bplib/micron/tb/tbrun.yml
- include: rtl/bplib/nxcramlib/tb/tbrun.yml
- include: rtl/bplib/s3board/tb/tbrun.yml
- include: rtl/w11a/tb/tbrun.yml
- include: rtl/sys_gen/tst_serloop/tbrun.yml
- include: rtl/sys_gen/tst_rlink/tbrun.yml
- include: rtl/sys_gen/tst_rlink_cuff/tbrun.yml
- include: rtl/sys_gen/tst_sram/tbrun.yml
- include: rtl/sys_gen/w11a/tbrun.yml
/trunk/tools/bin/ghdl_assert_filter File deleted
trunk/tools/bin/ghdl_assert_filter Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/tools/bin/njobihtm =================================================================== --- trunk/tools/bin/njobihtm (nonexistent) +++ trunk/tools/bin/njobihtm (revision 37) @@ -0,0 +1,119 @@ +#!/usr/bin/perl -w +# $Id: njobihtm 810 2016-10-02 16:51:12Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +# +# Revision History: +# Date Rev Version Comment +# 2016-10-01 810 1.0 Initial version +# + +use 5.14.0; # require Perl 5.14 or higher +use strict; # require strict checking + +use Getopt::Long; + +my %opts = (); + +GetOptions(\%opts, "verbose", "mem=s" + ) + or die "bad options"; + +sub get_cpuinfo; +sub get_meminfo; + +my $ncpu; +my $ntpc; +my $nkb; +my $njob = 1; + +get_cpuinfo(); +get_meminfo(); + +if (defined $ncpu && defined $ntpc && defined $nkb) { +} else { + print STDERR "njobihtm-F: failed to obtain cpu or mem size\n"; + exit 1; +} + + +my $ncore = $ncpu / $ntpc; # number of cores +my $nht = $ncpu - $ncore; + +$njob = $ncore + int($nht/4); + +if ($opts{verbose}) { + printf STDERR "#cpus: %d\n", $ncpu; + printf STDERR "#thread/cpu: %d\n", $ntpc; + printf STDERR "#cores: %d\n", $ncore; + printf STDERR "mem(MB): %d\n", int($nkb/1024); + printf STDERR "#job (cpus): %d\n", $njob; +} + +if (defined $opts{mem}) { + my $mem; + if ($opts{mem} =~ m/^(\d+)([MG])$/) { + $mem = 1024 * $1 if $2 eq 'M'; + $mem = 1024* 1024 * $1 if $2 eq 'G'; + my $njobm = int(($nkb - 1024*1024) / $mem); + $njobm = 1 unless $njobm > 0; + printf STDERR "#job (mem): %d\n", $njobm if $opts{verbose}; + if ($njobm < $njob) { + $njob = $njobm; + } + } else { + print STDERR "njobihtm-F: bad -mem option '$opts{mem}', must be nnn[MG]\n"; + exit 1; + } +} + +print "$njob\n"; + +exit 0; + +#------------------------------------------------------------------------------- +sub get_cpuinfo { + open (LSCPU, "lscpu|") + or die "failed to open 'lscpu|': $!"; + + while () { + chomp; + if (m/^(.*?)\s*:\s*(.*)$/) { + my $tag = $1; + my $val = $2; + # print "+++1 '$tag' : '$val' \n"; + $ncpu = $val if $tag eq 'CPU(s)'; + $ntpc = $val if $tag eq 'Thread(s) per core'; + } + } + close LSCPU; + return; +} + +#------------------------------------------------------------------------------- +sub get_meminfo { + open (MEMINFO, "/proc/meminfo") + or die "failed to open '/proc/meminfo': $!"; + + while () { + chomp; + if (m/^(.*?)\s*:\s*(\d+)\s*kB/) { + my $tag = $1; + my $val = $2; + # print "+++1 '$tag' : '$val' \n"; + $nkb = $val if $tag eq 'MemTotal'; + } + } + close MEMINFO; + return; +} +
trunk/tools/bin/njobihtm Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/tools/bin/tbfilt =================================================================== --- trunk/tools/bin/tbfilt (nonexistent) +++ trunk/tools/bin/tbfilt (revision 37) @@ -0,0 +1,403 @@ +#!/usr/bin/perl -w +# $Id: tbfilt 807 2016-09-17 07:49:26Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +# +# Revision History: +# Date Rev Version Comment +# 2016-09-10 806 1.0 Initial version +# 2016-08-05 795 0.1 First draft +# + +use 5.14.0; # require Perl 5.14 or higher +use strict; # require strict checking + +use Getopt::Long; +use FileHandle; +use POSIX qw(strftime); + +my %opts = (); + +GetOptions(\%opts, "tee=s", "pcom", + "find=s", "all", + "summary", "wide", "compact", "format=s", "nohead" + ) + or die "bad options"; + +sub do_file; +sub conv_fd; +sub conv_ft; +sub conv_fs; +sub conv_fa; +sub conv_tr; +sub conv_tu; +sub conv_ts; +sub conv_tc; +sub conv_tg; +sub conv_st; +sub conv_ss; +sub conv_sc; +sub conv_sg; +sub conv_sp; +sub conv_sm; +sub conv_ec; +sub conv_pf; +sub conv_nf; +sub conv_ns; + +my %fmttbl = (fd => {conv => \&conv_fd, head=>' file-date'}, + ft => {conv => \&conv_ft, head=>' time'}, + fs => {conv => \&conv_fs, head=>' time'}, + fa => {conv => \&conv_fa, head=>'age'}, + tr => {conv => \&conv_tr, head=>' time-real'}, + tu => {conv => \&conv_tu, head=>' time-user'}, + ts => {conv => \&conv_ts, head=>' time-sys'}, + tc => {conv => \&conv_tc, head=>' time-cpu'}, + tg => {conv => \&conv_tg, head=>' time t'}, + st => {conv => \&conv_st, head=>'stime(ns)'}, + ss => {conv => \&conv_ss, head=>'stime'}, + sc => {conv => \&conv_sc, head=>' cycles'}, + sg => {conv => \&conv_sg, head=>' cyc|tim'}, + sp => {conv => \&conv_sp, head=>'sperf'}, + sm => {conv => \&conv_sm, head=>'MHz'}, + ec => {conv => \&conv_ec, head=>'err'}, + pf => {conv => \&conv_pf, head=>'stat'}, + nf => {conv => \&conv_nf, head=>'filename'}, + ns => {conv => \&conv_ns, head=>'filename'}); +my @fmtlst; + +my $format = $ENV{TBFILT_FORMAT}; +$format = '%fd %fs %tr %tc %sc %ec %pf %nf' if $opts{wide}; +$format = '%fa %tg %sg %ec %pf %ns' if $opts{compact}; +$format = $opts{format} if defined $opts{format}; +$format = '%ec %pf %nf' unless defined $format; + +while (length($format)) { + if ($format =~ m/^([^%]*)%([a-z][a-z])/) { + my $pref = $1; + my $code = $2; + if (exists $fmttbl{$code}) { + push @fmtlst, {pref => $pref, + conv => $fmttbl{$code}{conv}, + head => $fmttbl{$code}{head}}; + } else { last; }; + $format = $'; + } else { last; }; +} +if (length($format)) { + print STDERR "tbfilt-f: bad format '$format'\n"; + exit 2; +} + +autoflush STDOUT 1 if (-p STDOUT); + +my $fh_tee; +if (defined $opts{tee} && $opts{tee} ne '') { + $fh_tee = new FileHandle; + $fh_tee->open($opts{tee},'>') or die "failed to open for write '$opts{tee}'"; +} + +my @flist = @ARGV; + +# if find pattern has no '*', expand it +if (defined $opts{find}) { + unless ($opts{find} =~ m/\*/) { + $opts{find} = '.*/tb_.*_' . $opts{find} . '.*\.log'; + } +} + +if (defined $opts{all}) { + if (defined $opts{find}) { + print STDERR "tbfilt-I: -find ignored because -all given\n"; + } + $opts{find} = '.*/tb_.*_[bfsorept]sim(_.*)?\.log'; +} + +if (defined $opts{find}) { + if (scalar (@flist)) { + print STDERR "tbfilt-I: file names ignored because -all or -find given\n"; + @flist = (); + } + open FIND,'-|',"find -regextype egrep -regex '$opts{find}'" + or die "failed to open find pipe"; + + while () { + chomp; + s|^\./||; # drop leading ./ + push @flist, $_; + } + + close FIND; + @flist = sort @flist; + if (scalar (@flist) == 0) { + print STDERR "tbfilt-E: no files found by -find or -all\n"; + exit 2; + } + +} else { + push @flist, '-' if (scalar(@flist) == 0); +} + +my $manyfile = scalar(@flist) > 1; +my $notsumm = not $opts{summary}; +my %vals; +my $exitcode = 0; + +if ($opts{summary} && (not $opts{nohead})) { + foreach my $item (@fmtlst) { + print $item->{pref}; + print $item->{head}; + } + print "\n"; +} + +foreach my $fnam (@flist) { + my $nfail = do_file($fnam); + $exitcode = 1 if $nfail; +} + +exit $exitcode; + +#------------------------------------------------------------------------------- + +sub do_file { + my ($fnam) = @_; + + %vals = (); + $vals{fnam} = $fnam; + $vals{nfail} = 0; + + my $fh; + if ($fnam eq '-') { + $fh = *STDIN; + } else { + $fh = new FileHandle; + $fh->open($fnam,'<') or die "failed to open for read '$fnam'"; + } + + if ($manyfile && $notsumm) { + print "-- $fnam"; + my $npad = 74-length($fnam); + print ' '.('-' x $npad) if $npad > 0; + print "\n"; + } + + while (<$fh>) { + print $fh_tee $_ if defined $fh_tee; + chomp; + my $show; + my $fail; + + $fail = 1 if m/-[EF]:/; + $fail = 1 if m/(ERROR|FAIL)/; + $show = 1 if m/-W:/; + $show = 1 if m/(PASS)/; + $show = 1 if $opts{pcom} && m/^C/; # show lines starting with C + + # ghdl reports or assertions (warning and higher) + if (m/:\((report|assertion) (warning|error|failure)\):/) { + # ignore ieee lib warnings at t=0 + next if /:\@0ms:\(assertion warning\): NUMERIC_STD.*metavalue detected/; + next if /:\@0ms:\(assertion warning\): CONV_INTEGER: There is an 'U'/; + next if /std_logic_arith.*:\@0ms:\(assertion warning\): There is an 'U'/; + # ignore ' Simulation Finished' report failure (used to end ghdl sim) + next if /:\(report failure\): Simulation Finished/; + $fail = 1; + } + + # check for DONE line accept + # 920 ns: DONE -- tb'swithout clock + # 7798080.0 ns 389893: DONE -- single clock tb's + # 56075.0 ns 2094: DONE-w -- multiclock tb's (max taken) + # + if (m/^\s*(\d+\.?\d*)\s+ns\s*(\d*):\s+DONE(-\S+)?\s*$/) { + $show = 1; + $vals{done_ns} = $1; + if ($2 ne '') { + if (defined $vals{done_cyc}) { + $vals{done_cyc} = $2 if $2 > $vals{done_cyc}; + } else { + $vals{done_cyc} = $2; + } + } + } + + # check for time line + # Note: don't root the pattern with /^ --> allow arbitary text before + # the 'time' output. In practice 'time' output (to stderr by bash) + # and ghdl 'report' (also to stderr) get mixed and one might get + # tb_w11a_b3real 0m49.179s user 0m0.993s sys 0m0.293s + # + if (m/real\s+(\d*)m(\d+\.\d*)s\s+ + user\s+(\d*)m(\d+\.\d*)s\s+ + sys\s+(\d*)m(\d+\.\d*)s/x) { + $show = 1; + $vals{treal} = [$1,$2]; + $vals{tuser} = [$3,$4]; + $vals{tsys} = [$5,$6]; + } + + print "$_\n" if ($show || $fail) && $notsumm; + $vals{nfail} += 1 if $fail; + } + + if (not defined $vals{done_ns}) { + print "tbfilt-I: no DONE seen; FAIL\n" if $notsumm; + $vals{nfail} += 1; + } + + $vals{mtime} = ($fnam eq '-') ? time : (stat($fh))[9]; + + if ($opts{summary}) { + foreach my $item (@fmtlst) { + print $item->{pref}; + print &{$item->{conv}}; + } + print "\n"; + } + + return $vals{nfail}; +} + +#------------------------------------------------------------------------------- +sub time_val { + my ($tdsc) = @_; + return undef unless defined $tdsc; + return 60.*$tdsc->[0] + $tdsc->[1]; +} + +sub time_str { + my ($tdsc) = @_; + return ' -' unless defined $tdsc; + return sprintf '%3dm%06.3fs', $tdsc->[0],$tdsc->[1]; +} + +sub time_sum { + my ($tdsc1,$tdsc2) = @_; + return undef unless defined $tdsc1 && defined $tdsc2; + return time_val($tdsc1) + time_val($tdsc2); +} + +sub gconv { + my ($val) = @_; + my $str = sprintf '%4.2f', $val; + return substr($str,0,4); +} + +#------------------------------------------------------------------------------- +sub conv_fd { + return strftime "%F", localtime($vals{mtime}); +} + +sub conv_ft { + return strftime "%T", localtime($vals{mtime}); +} + +sub conv_fs { + return strftime "%H:%M", localtime($vals{mtime}); +} + +sub conv_fa { + my $dt = time - $vals{mtime}; + return sprintf '%2ds', $dt if $dt < 99; + $dt /= 60; return sprintf '%2dm', $dt if $dt < 99; + $dt /= 60; return sprintf '%2dh', $dt if $dt < 60; + $dt /= 24; return sprintf '%2dd', $dt if $dt < 99; + return 'old'; +} + +sub conv_tr { + return time_str($vals{treal}); +} + +sub conv_tu { + return time_str($vals{tuser}); + } + +sub conv_ts { + return time_str($vals{tsys}); +} + +sub conv_tc { + my $tsum = time_sum($vals{tuser}, $vals{tsys}); + return ' -' unless defined $tsum; + my $min = int($tsum/60.); + my $sec = $tsum - 60. * $min; + return sprintf '%3dm%06.3fs', $min, $sec; +} + +sub conv_tg { + my $treal = time_val($vals{treal}); + my $tcpu = time_sum($vals{tuser}, $vals{tsys}); + if (defined $treal && defined $tcpu && $tcpu > 0.4 * $treal) { + return conv_tc() . ' c' ; + } else { + return conv_tr() . ((defined $treal) ? ' r': ' -'); + } +} + +sub conv_st { + return ' -' unless defined $vals{done_ns}; + return sprintf '%9d', $vals{done_ns}; +} + +sub conv_ss { + return ' -' unless defined $vals{done_ns}; + my $stim = 0.001 * $vals{done_ns}; + return gconv($stim) . 'u' if $stim < 999; + $stim *= 0.001; return gconv($stim) . 'm' if $stim < 999; + $stim *= 0.001; return gconv($stim) . 's'; +} + +sub conv_sc { + return ' -' unless defined $vals{done_cyc}; + return sprintf '%8d', $vals{done_cyc}; +} + +sub conv_sg { + return conv_sc() if defined $vals{done_cyc}; + return ' ' . conv_ss(); +} + +sub conv_sp { + my $nc = $vals{done_cyc}; + my $tsum = time_sum($vals{tuser}, $vals{tsys}); + return ' -' unless defined $nc && defined $tsum; + my $sperf = 1000000. * $tsum / $nc; + return gconv($sperf) . 'u' if $sperf < 999; + $sperf *= 0.001; return gconv($sperf) . 'm'; +} + +sub conv_sm { + return ' -' unless defined $vals{done_ns} && $vals{done_ns} > 200 && + defined $vals{done_cyc}; + my $mhz = (1000. * $vals{done_cyc}) / ($vals{done_ns} - 200); + return sprintf '%3d', int($mhz+0.5); +} + +sub conv_ec { + return sprintf '%3d', $vals{nfail}; +} + +sub conv_pf { + return $vals{nfail} ? 'FAIL' : 'PASS'; +} + +sub conv_nf { + return $vals{fnam}; +} + +sub conv_ns { + my $val = $vals{fnam}; + $val =~ s|^.*/||; + return $val; +}
trunk/tools/bin/tbfilt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/tools/bin/tbrun =================================================================== --- trunk/tools/bin/tbrun (nonexistent) +++ trunk/tools/bin/tbrun (revision 37) @@ -0,0 +1,830 @@ +#!/usr/bin/perl -w +# $Id: tbrun 808 2016-09-17 13:02:46Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +# +# Revision History: +# Date Rev Version Comment +# 2016-09-17 808 1.0 Initial version +# 2016-08-09 796 0.1 First draft +# + +use 5.14.0; # require Perl 5.14 or higher +use strict; # require strict checking + +use Getopt::Long; +use FileHandle; +use YAML::XS; +use Cwd; +use IO::Select; +use Time::HiRes qw(gettimeofday); + +my %opts = (); + +GetOptions(\%opts, "tag=s@", "exclude=s@", "mode=s", + "jobs=i", "tee=s", "tmax=i", "dry", "trace", + "nomake", "norun", + "rlmon", "rbmon", "bwait=i", "swait=i" + ) + or die "bad options"; + +sub setup_tagfilter; +sub check_tagfilter; +sub check_modefilter; +sub include_file; +sub read_file; +sub load_yaml; +sub check_keys; +sub expand_vars; +sub merge_lines; +sub merge_expand; +sub key_or_def; +sub handle_include; +sub handle_default; +sub handle_itest; +sub tpr; +sub tpre; +sub print_trace; +sub run_tests_single; +sub run_tests_multi; + +my @tlist; +my @olist; +my @wlist; + + +my %keys_include = ( include => { mode => 'm', ref => ''}, + tag => { mode => 'o', ref => 'ARRAY'} + ); +my %keys_default = ( default => { mode => 'm', ref => 'HASH'} + ); +my %keys_defhash = ( tag => { mode => 'o', ref => 'ARRAY'}, + mode => { mode => 'o', ref => ''} + ); +my %keys_itest = ( test => { mode => 'm', ref => ''}, + tag => { mode => 'o', ref => 'ARRAY'}, + mode => { mode => 'o', ref => ''} + ); + +my $nseen = 0; +my $ntest = 0; +my $ndone = 0; +my $nfail = 0; +my $inicwd = getcwd(); +my %gblvars; + +$gblvars{ise_modes} = '[bsft]sim,ISim_[bsft]sim'; +$gblvars{ise_modes_noisim} = '[bsft]sim'; # when ISim not possible +$gblvars{ise_modes_nossim} = 'bsim,ISim_bsim'; # when ssim not available +# +$gblvars{viv_modes} = '[bsor]sim,XSim_[bsorept]sim'; +$gblvars{viv_modes_nossim} = 'bsim,XSim_bsim'; # when ssim not available + +autoflush STDOUT 1 if -p STDOUT || -t STDOUT; +my $ticker_on = -t STDOUT; + +my $fh_tee; +if (defined $opts{tee} && $opts{tee} ne '') { + $fh_tee = new FileHandle; + $fh_tee->open($opts{tee},'>') or die "failed to open for write '$opts{tee}'"; +} + +$opts{tag} = ['default'] unless defined $opts{tag}; +$opts{mode} = 'bsim' unless defined $opts{mode}; + +my %modecache; +my @modelist; +foreach (split /,/,$opts{mode}) { + $_ .= '_bsim' if m/^[IX]Sim$/; + push @modelist, $_; +} + +push @ARGV, 'tbrun.yml' unless scalar( @ARGV); + +my @tagincl = setup_tagfilter($opts{tag}); +my @tagexcl = setup_tagfilter($opts{exclude}); + +foreach my $fnam (@ARGV) { + include_file($fnam); +} + +$ntest = scalar(@tlist); +unless ($ntest) { + tpre(sprintf "tbrun-E: %d tests found, none selected\n", $nseen); + exit 2; +} + +if (defined $opts{jobs}) { + run_tests_multi(); +} else { + run_tests_single(); +} + +if (defined $opts{dry}) { + tpr(sprintf "#tbrun-I: %d tests found, %d selected\n", $nseen,$ntest); +} + +if ($nfail) { + tpr(sprintf "tbrun-I: %d tests failed of %d tests executed\n",$nfail,$ndone); +} + +exit $nfail ? 1 : 0; + +#------------------------------------------------------------------------------- +sub setup_tagfilter { + my ($targlist) = @_; + return () unless defined $targlist; + my @tagfiltlist; + foreach my $targ (@$targlist) { + my @tagfilt = map { "^($_)\$" } split /,/, $targ; + push @tagfiltlist, \@tagfilt; + } + return @tagfiltlist; +} + +#------------------------------------------------------------------------------- +sub check_tagfilter { + my ($tfiltlist,$tlist) = @_; + foreach my $tfilt (@$tfiltlist) { # loop over filters + my $fok = 1; + foreach my $tfele (@$tfilt) { # loop over filter elements + my $match = 0; + foreach my $tag (@$tlist) { # loop over tags + $match = $tag =~ m/$tfele/; # tag matchs filter element + last if $match; + } + $fok = 0 unless $match; # filter missed if one element missed + } + return 1 if $fok; # return ok of one filter matched + } + return 0; # here if no filter matched +} + +#------------------------------------------------------------------------------- +sub check_modefilter { + my ($mode,$mlist) = @_; + unless (exists $modecache{$mlist}) { + my %mh; + foreach my $mi (split /,/,$mlist) { + if ($mi =~ m/^(.*)\[([a-z]+)\](.*)$/) { + foreach (split //,$2) { + $mh{$1.$_.$3} = 1; + } + } else { + $mh{$mi} = 1; + } + } + $modecache{$mlist} = \%mh; + } + + my $rmh = $modecache{$mlist}; + return exists $$rmh{$mode}; +} + +#------------------------------------------------------------------------------- +sub include_file { + my ($fnam) = @_; + my $fdat = read_file($fnam); + exit 2 unless defined $fdat; + my $ylst = load_yaml($fdat, $fnam); + exit 2 unless defined $ylst; + + my $oldcwd = getcwd(); + + if ($fnam =~ m|^(.*)/(.*)$|) { + chdir $1 or die "chdir to '$1' failed with '$!'"; + } + + my %defhash; + foreach my $yele (@$ylst) { + if (exists $yele->{include}) { + handle_include($yele); + } elsif (exists $yele->{default}) { + handle_default($yele, \%defhash); + } elsif (exists $yele->{test}) { + handle_itest($yele, \%defhash); + } else { + tpr(sprintf "tbrun-E: unknown list element in '%s'\n found keys: %s\n", + $fnam, join(',',sort keys %$yele)); + exit 2; + } + } + + chdir $oldcwd or die "chdir to '$oldcwd' failed with '$!'"; + return; +} + +#------------------------------------------------------------------------------- +sub read_file { + my ($fnam) = @_; + my $fh = new FileHandle; + if (not open $fh, '<', $fnam) { + my $err = $!; + tpre(sprintf "tbrun-E: failed to open '%s'\n cwd: %s\n error: %s\n", + $fnam, getcwd(), $err); + return undef; + } + # nice trick to slurp the whole file into a variable + my $fdat = do { + local $/ = undef; + <$fh>; + }; + close $fh; + return $fdat; +} + +#------------------------------------------------------------------------------- +sub load_yaml { + my ($fdat,$fnam) = @_; + my $ylst; + eval { $ylst = YAML::XS::Load($fdat); }; + if ($@ ne '') { + my $err = $@; + tpre(sprintf "tbrun-E: failed to yaml load '%s'\n cwd: %s\n error: %s\n", + $fnam, getcwd(), $err); + return undef; + } + if (ref $ylst ne 'ARRAY') { + tpre(sprintf "tbrun-E: top level yaml is not a list but '%s'\n", ref $ylst); + return undef; + } + foreach my $yele (@$ylst) { + if (ref $yele ne 'HASH') { + tpre(sprintf "tbrun-E: second level yaml is not a hash '%s'\n", ref $yele); + return undef; + } + } + return $ylst; +} + +#------------------------------------------------------------------------------- +sub check_keys { + my ($yele, $href) = @_; + foreach my $keyele ( keys %$yele ) { + if (not exists $href->{$keyele}) { + tpre(sprintf "tbrun-E: unexpected key '%s'\n", $keyele); + return 0; + } + my $ref = ref $yele->{$keyele}; + if ($ref ne $href->{$keyele}->{ref}) { + tpre(sprintf "tbrun-E: key '%s' is type'%s', expected '%s'\n", + $keyele, $ref, $href->{$keyele}->{ref}); + return 0; + } + } + foreach my $keyref ( keys %$href ) { + next if $href->{$keyref}->{mode} eq 'o'; + if (not exists $yele->{$keyref}) { + tpre(sprintf "tbrun-E: key '%s' missing\n", $keyref); + return 0; + } + } + return 1; +} + +#------------------------------------------------------------------------------- +sub lookup_var { + my ($vnam,$hrefs) = @_; + return $gblvars{$vnam} if exists $gblvars{$vnam}; + if ($vnam =~ m/[A-Z][A-Z0-9_]*/) { + return $ENV{$vnam} if exists $ENV{$vnam}; + } + tpre(sprintf "tbrun-E: can't replace '$vnam'\n"); + exit 2; +} + +#------------------------------------------------------------------------------- +sub expand_vars { + my ($txt,$hrefs) = @_; + my $res = ''; + while ($txt ne '') { + if ($txt =~ m/\$\{([a-zA-Z][a-zA-Z0-9_]*)\}/) { + my $vnam = $1; + my $vrep = lookup_var($vnam, $hrefs); + $res .= $`; + $res .= $vrep; + $txt = $'; + } else { + $res .= $txt; + last; + } + } + return $res; +} + +#------------------------------------------------------------------------------- +sub merge_lines { + my ($txt) = @_; + $txt =~ s|\s*\\\n\s*| |mg; + chomp $txt; + return $txt; +} + +#------------------------------------------------------------------------------- +sub merge_expand { + my ($txt,$hrefs) = @_; + return expand_vars(merge_lines($txt), $hrefs); +} + +#------------------------------------------------------------------------------- +sub key_or_def { + my ($tag,$yele,$defhash) = @_; + return $yele->{$tag} if exists $yele->{$tag}; + return $defhash->{$tag} if exists $defhash->{$tag}; + return undef; +} + +#------------------------------------------------------------------------------- +sub handle_include { + my ($yele) = @_; + check_keys($yele, \%keys_include) or exit 2; + + my $fnam = merge_expand($yele->{include}, undef); + include_file($fnam); + + return; +} + +#------------------------------------------------------------------------------- +sub handle_default { + my ($yele, $defhash) = @_; + check_keys($yele, \%keys_default) or exit 2; + check_keys($yele->{default}, \%keys_defhash) or exit 2; + foreach my $key (keys %{$yele->{default}}) { + $$defhash{$key} = $$yele{default}{$key}; + } + return; +} + +#------------------------------------------------------------------------------- +sub handle_itest { + my ($yele, $defhash) = @_; + check_keys($yele, \%keys_itest) or exit 2; + + $nseen += 1; + + my $tlist = key_or_def('tag', $yele, $defhash); + if (defined $tlist) { + return unless check_tagfilter(\@tagincl, $tlist); + return if check_tagfilter(\@tagexcl, $tlist); + } + + my $mlist = merge_expand(key_or_def('mode', $yele, $defhash), undef); + + foreach my $mode (@modelist) { + next unless check_modefilter($mode, $mlist); + + my $ms = '_' . $mode; + $ms =~ s/_bsim$//; + $gblvars{ms} = $ms; + + my $test = merge_expand($yele->{test}, undef); + + # forward options for tbrun_tbw or tbrun_tbwrri commands + if ($test =~ m/^\s*(tbrun_tbw|tbrun_tbwrri)\s+(.*)$/) { + my $cmd = $1; + my $rest = $2; + $test = $cmd; + $test .= ' --nomake' if $opts{nomake}; + $test .= ' --norun' if $opts{norun}; + if ($cmd eq 'tbrun_tbwrri') { + $test .= ' --rlmon' if $opts{rlmon}; + $test .= ' --rbmon' if $opts{rbmon}; + $test .= ' --bwait '.$opts{bwait} if $opts{bwait}; + $test .= ' --swait '.$opts{swait} if $opts{swait}; + } + $test .= ' ' . $rest; + } + + my $tid = scalar(@tlist); + my $tmsg = sprintf "t%03d - tags: ", $tid; + $tmsg .= join ',',@$tlist if defined $tlist; + + my %titem; + $titem{id} = $tid; + $titem{cd} = getcwd(); + $titem{test} = $test; + $titem{tag} = $tlist; + $titem{tmsg} = $tmsg; + + push @{$titem{locks}}, $titem{cd}; + + push @tlist, \%titem; + + delete $gblvars{ms}; + } + + return; +} + +#------------------------------------------------------------------------------- +sub tpr { + my ($txt) = @_; + print $txt; + print $fh_tee $txt if defined $fh_tee; + return; +} + +#------------------------------------------------------------------------------- +sub tpre { + my ($txt) = @_; + print STDERR $txt; + print $fh_tee $txt if defined $fh_tee; + return; +} + +#------------------------------------------------------------------------------- +sub max { + my ($a,$b) = @_; + return ($a > $b) ? $a : $b; +} + +#------------------------------------------------------------------------------- +sub open_job_fh { + my ($cmd) = @_; + my $fh = new FileHandle; + + # add STDERR->STDOUT redirect (create sub shell of needed) + $cmd = '(' . $cmd . ')' if $cmd =~ m/\n/g; + $cmd .= ' 2>&1'; + + # open returns pid of created process in case an in or out pipe is created + my $pid = open $fh, '-|', $cmd; + # print "+++1 $pid\n"; + + if (not $pid) { + my $err = $!; + my $msg = sprintf "tbrun-E: failed to start '%s'\n cwd: %s\n error: %s\n", + $cmd, getcwd(), $err; + return (undef, undef, $msg); + } + return ($fh, $pid, undef); +} + +#------------------------------------------------------------------------------- +sub run_tests_single { + my $drycd = ''; + foreach my $titem (@tlist) { + my $cdir = $titem->{cd}; + my $test = $titem->{test}; + + chdir $inicwd or die "chdir to '$inicwd' failed with '$!'"; + + if ($opts{dry}) { + if ($cdir ne $drycd) { + tpr("#------------------------------------------------------------\n"); + tpr("cd $cdir\n"); + $drycd = $cdir; + } + tpr("#----------------------------------------\n"); + tpr("# $titem->{tmsg}\n"); + tpr("$test\n"); + + } else { + tpr("#----------------------------------------\n"); + tpr("# $titem->{tmsg}\n"); + $ndone += 1; + my $cmd = ''; + $cmd .= "cd $cdir"; + $cmd .= "\n"; + $cmd .= "$test"; + + my ($fh,$pid,$msg) = open_job_fh($cmd); + if (not defined $fh) { + tpre($msg); + } else { + while (<$fh>) { + print $_; + } + if (not close $fh) { + my $err = $?; + tpr(sprintf "tbrun-I: test FAILed with exit status %d,%d\n", + ($err>>8), ($err&0xff)); + $nfail += 1; + } + } + } + } + + if ($opts{dry}) { + tpr("#------------------------------------------------------------\n"); + tpr(sprintf "cd %s\n", $inicwd); + } + + return; +} + +#------------------------------------------------------------------------------- +sub print_ticker { + return unless $ticker_on; + + my ($rwlist) = @_; + my $msg = ''; + state $lastlength = 0; + + if (defined $rwlist) { + my $time_now = gettimeofday(); + $msg = '#-I: ' . join '; ', map { + sprintf('t%03d: %dl %3.1fs', + $_->{id}, $_->{nlines}, $time_now-$_->{tstart}) + } @$rwlist; + $msg = substr($msg,0,75) . ' ...' if length($msg) >79; + unless (defined $opts{trace}) { + my $suff = sprintf '(%dt,%dw,%do)', + scalar(@tlist), scalar(@wlist), scalar(@olist); + if (length($suff) + length($msg) + 1 <= 79) { + $msg .= ' ' . $suff; + } else { + $msg = substr($msg,0,79-6-length($suff)) . ' ... ' . $suff; + } + } + } + my $newlength = length($msg); + $msg .= ' ' x ($lastlength - $newlength) if $lastlength > $newlength; + print $msg . "\r"; + $lastlength = $newlength; + return; +} + +#------------------------------------------------------------------------------- +sub print_jobs { + while (defined $olist[0]->{exitcode}) { + print_ticker(); + my $titem = shift @olist; + tpr("#----------------------------------------\n"); + tpr("# $titem->{tmsg}\n"); + tpr($titem->{out}); + } + return; +} + +#------------------------------------------------------------------------------- +sub print_trace { + my ($titem) = @_; + my $pref = ''; + my $suff = sprintf '(%dt,%dw,%do)', + scalar(@tlist), scalar(@wlist), scalar(@olist); + if (defined $titem->{exitcode}) { + $pref = ($titem->{exitcode}==0) ? 'pass ' : 'FAIL '; + } else { + $pref = 'start'; + } + my $txt = '#-I: ' . $pref . ' ' . $titem->{tmsg}; + $txt .= ' ' . $suff; + $txt .= "\n"; + print_ticker(); + tpr($txt); + return; +} + +#------------------------------------------------------------------------------- +sub start_jobs { + + # initialize lock hash + my %locks; + foreach my $titem (@wlist) { + foreach my $lock (@{$titem->{locks}}) { + $locks{$lock} = 1; + } + } + + # look for suitable tasks + for (my $i=0; $i < scalar(@tlist) && scalar(@wlist) < $opts{jobs}; ) { + my $titem = $tlist[$i]; + my $nlock = 0; + foreach my $lock (@{$titem->{locks}}) { + if ($locks{$lock}) { + $nlock += 1; + last; + } + } + + # suitable task found + if ($nlock == 0) { + my $cdir = $titem->{cd}; + my $test = $titem->{test}; + $ndone += 1; + + my $cmd = ''; + if ($opts{dry}) { + $cmd .= "cd $cdir"; + $cmd .= "\n"; + $cmd .= "perl -e 'select(undef, undef, undef, 0.2+1.6*rand( 1.))'"; + $cmd .= "\n"; + $cmd .= "echo \"cd $cdir\""; + $cmd .= "\n"; + $cmd .= "echo \"$test\""; + } else { + $cmd .= "cd $cdir"; + $cmd .= "\n"; + $cmd .= "$test"; + } + + # start job + my ($fh,$pid,$msg) = open_job_fh($cmd); + if (not defined $fh) { + $titem->{out} = $msg; + $titem->{exitcode} = 1; + print_trace($titem) if $opts{trace}; + print_jobs(); + } else { + $titem->{fh} = $fh; + $titem->{fd} = fileno($fh); + $titem->{pid} = $pid; + $titem->{out} = ''; + $titem->{tstart} = gettimeofday(); + $titem->{nlines} = 0; + push @wlist, $titem; + foreach my $lock (@{$titem->{locks}}) { + $locks{$lock} = 1; + } + print_trace($titem) if $opts{trace}; + } + splice @tlist, $i, 1; # remove from tlist + next; # and re-test i'th list element + } # if ($nlock == 0) + + $i += 1; # inspect nexyt list element + } # for (my $i=0; ... + return; +} + +#------------------------------------------------------------------------------- +sub kill_job { + my ($titem, $trun) = @_; + my $pid = $titem->{pid}; + my $pgid = getpgrp(0); + my %phash; + + $titem->{killed} = $trun; + + # get process tree data (for whole user, no pgid filtering possible + my $rank = 0; + open PS,"ps -H -o pid,ppid,pgid,comm --user $ENV{USER}|"; + while () { + chomp; + next unless m/^\s*(\d+)\s+(\d+)\s+(\d+)\s(.*)$/; + my $cpid = $1; + my $cppid = $2; + my $cpgid = $3; + my $cargs = $4; + next unless $cpgid == $pgid; # only current process group + next if $cargs =~ m/^\s*ps\s*$/; # skip the 'ps' process itself + $phash{$cpid}->{ppid} = $cppid; + $phash{$cpid}->{pgid} = $cpgid; + $phash{$cpid}->{args} = $cargs; + $phash{$cpid}->{rank} = $rank++; + push @{$phash{$cppid}->{childs}}, $cpid; + } + close PS; + + # sanity check 1: own tbrun process should be included + unless (exists $phash{$$}) { + print_ticker(); + printf "-E: tmax kill logic error: tbrun master pid not in phash\n"; + return; + } + # sanity check 2: job to be killed should be child of master tbrun + unless ($phash{$pid}->{ppid} == $$) { + print_ticker(); + printf "-E: tmax kill logic error: job not child of tbrun\n"; + return; + } + + # determine number of leading blanks in master tbrun line + my $nstrip = 0; + $nstrip = length($1) if ($phash{$$}->{args} =~ m/^(\s*)/); + + # recursively mark all childs of job master + my @pids = ($pid); + while (scalar(@pids)) { + my $cpid = shift @pids; + if (not exists $phash{$cpid}) { + print_ticker(); + printf "-E: tmax kill logic error: child pid not in phash\n"; + return; + } + $phash{$cpid}->{kill} = 1; + if (exists $phash{$cpid}->{childs}) { + push @pids, @{$phash{$cpid}->{childs}}; + } + } + + # build list of pid to be killed, and trace message + my @kpids; + my @ktext; + foreach my $cpid (sort {$phash{$a}->{rank} <=> $phash{$b}->{rank} } + grep {$phash{$_}->{kill}} + keys %phash) { + push @kpids, $cpid; + push @ktext, sprintf "# %6d %6d %6d %s", + $cpid, $phash{$cpid}->{ppid}, + $phash{$cpid}->{pgid}, + substr($phash{$cpid}->{args}, $nstrip); + } + + # print trace message, if selected + if ($opts{trace}) { + print_ticker(); + printf "#-I: kill t%03d after %3.1fs, kill proccesses:\n", + $titem->{id}, $trun, join("\n"); + print "# pid ppid pgid command\n"; + print join("\n",@ktext) . "\n"; + } + + # and finally kill all processes of the job + kill 'TERM', @kpids; + + return; +} + +#------------------------------------------------------------------------------- +sub run_tests_multi { + @olist = @tlist; + + while (scalar(@tlist) || scalar(@wlist)) { # while something to do + # start new jobs, if available and job slots free + start_jobs(); + + my @fhlist = map { $_->{fh} } @wlist; + my %fdhash; + foreach my $titem (@wlist) { + $fdhash{$titem->{fd}} = $titem; + } + + my $sel = IO::Select->new(@fhlist); + my $neof = 0; + my $time_ticker = gettimeofday() + 0.1; + + while ($neof == 0) { + my $wait_ticker = max(0.1, $time_ticker - gettimeofday() + 0.1); + my @fhlist = $sel->can_read($wait_ticker); + my $time_now = gettimeofday(); + if ($time_now >= $time_ticker) { + print_ticker(\@wlist); + $time_ticker = $time_now + 0.9; + } + foreach my $fh (@fhlist) { + my $fd = fileno($fh); + my $titem = $fdhash{$fd}; + my $buf = ''; + my $nb = sysread $fh, $buf, 1024; + + # data read + if ($nb) { + $titem->{out} .= $buf; + $titem->{nlines} += ($buf =~ tr/\n/\n/); # count \n in $buf + + # eof or error + } else { + if (defined $titem->{killed}) { + $titem->{out} .= sprintf + "tbrun-I: test killed after %3.1fs\n", $titem->{killed}; + } + if (not close $fh) { + my $err = $?; + $titem->{out} .= sprintf + "tbrun-I: test FAILed with exit status %d,%d\n", + ($err>>8), ($err&0xff); + $nfail += 1; + $titem->{exitcode} = $err; + } else { + $titem->{exitcode} = 0; + } + + $neof += 1; + for (my $i=0; $i < scalar(@wlist); $i++) { + next unless $wlist[$i]->{fd} == $fd; + splice @wlist, $i, 1; + last; + } + print_trace($titem) if $opts{trace}; + } + } # foreach my $fh ... + + # handle tmax + if (defined $opts{tmax}) { + foreach my $titem (@wlist) { + my $trun = $time_now - $titem->{tstart}; + if ($trun > $opts{tmax}) { + kill_job($titem, $trun) unless defined $titem->{killed}; + } + } + } + + } # while ($neof == 0) + # here if at least one job finished + print_jobs(); + } + + return; +}
trunk/tools/bin/tbrun Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/tools/bin/tbrun_tbw =================================================================== --- trunk/tools/bin/tbrun_tbw (revision 36) +++ trunk/tools/bin/tbrun_tbw (revision 37) @@ -1,5 +1,5 @@ #!/bin/bash -# $Id: tbrun_tbw 779 2016-06-26 15:37:16Z mueller $ +# $Id: tbrun_tbw 807 2016-09-17 07:49:26Z mueller $ # # Copyright 2014-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory @@ -6,6 +6,10 @@ # # Revision History: # Date Rev Version Comment +# 2016-09-03 805 1.2.2 add TIMEFORMAT and time for make commands +# 2016-08-21 800 1.2.1 add -norun, -nomake +# 2016-08-06 795 1.2 use tbfilt; fixup -lsuf logic +# 2016-07-03 782 1.1.4 drop ghdl_assert_filter (use --ieee=... at ghdl lvl) # 2016-06-25 778 1.1.3 drop make ghdl_tmp_clean logic # 2016-06-05 773 1.1.2 use _bsim.log for behavioral sim log # 2016-04-17 762 1.1.1 don't create '-run' for [IX]Sim anymore (now default) @@ -16,13 +20,17 @@ docmd () { - echo "$1" if [[ -z "$optdry" ]] ; then + echo "$2" eval "$1" + else + echo "$1" fi } optdry="" +optnomake="" +optnorun="" optlsuf="" optstack="" optghw="" @@ -32,12 +40,14 @@ # handle options while (( $# > 0 )) ; do case $1 in - -dry|--dry) optdry=$1 ; shift 1 ;; - -lsuf|--lsuf) optlsuf=$2 ; shift 2 ;; - -stack|--stack) optstack=$2 ; shift 2 ;; - -ghw|--ghw) optghw=$2 ; shift 2 ;; - -tbw|--tbw) opttbw=$2 ; shift 2 ;; - -pcom|--pcom) optpcom=$1 ; shift 1 ;; + -dry|--dry) optdry=$1 ; shift 1 ;; + -nomake|--nomake) optnomake=$1 ; shift 1 ;; + -norun|--norun) optnorun=$1 ; shift 1 ;; + -lsuf|--lsuf) optlsuf=$2 ; shift 2 ;; + -stack|--stack) optstack=$2 ; shift 2 ;; + -ghw|--ghw) optghw=$2 ; shift 2 ;; + -tbw|--tbw) opttbw=$2 ; shift 2 ;; + -pcom|--pcom) optpcom=$1 ; shift 1 ;; -*) echo "tbrun_tbw-E: invalid option '$1'"; exit 1 ;; *) break;; esac @@ -51,10 +61,13 @@ echo "Usage: tbrun_tbw [opts] testbench [stimfile]" echo " Options:" echo " --dry dry run, print commands, don't execute" + echo " --nomake don't execute make step" + echo " --norun don't execute run step" echo " --lsuf suff use '_.log' as suffix for log file" echo " --stack nnn use as ghdl stack size" echo " --ghw fname write ghw file with name '.ghw" echo " --tbw opts append to tbw command" + echo " --pcom print test comments" exit 1 fi @@ -80,30 +93,44 @@ fi # issue makes -docmd "make $makeopts $tbench" -exitstat=$? +if [[ -z "$optnomake" ]] ; then + cmd="TIMEFORMAT=$'real %3lR user %3lU sys %3lS'" + cmd+=$'\n' + cmd+="time make $makeopts $tbench" + docmd "$cmd" + exitstat=$? + if (( $exitstat > 0 )) ; then exit $exitstat; fi + echo "" +fi -if (( $exitstat > 0 )) ; then exit $exitstat; fi +# check for test bench +if [[ ! -x $tbench ]] ; then + echo "tbrun_tbw-E: $tbench not existing or not executable" + exit 1 +fi # determine logfile name logsuff="_bsim" if [[ $tbench =~ _[fsorept]sim$ ]] ; then logsuff=""; fi -if [[ -n "$optlsuf" ]] ; then logsuff="_$optlsuf"; fi +if [[ -n "$optlsuf" ]] ; then logsuff+="_$optlsuf"; fi logfile="${tbench}${logsuff}.log" -# now build actual test command (a tbw|filter|tee|egrep pipe) -cmd="time tbw $tbench" -if [[ -n "$stimfile" ]] ; then cmd+=" $stimfile"; fi -if [[ -n "$opttbw" ]] ; then cmd+=" $opttbw"; fi -if [[ -n "$optstack" ]] ; then cmd+=" --stack-max-size=$optstack"; fi -if [[ -n "$optghw" ]] ; then cmd+=" --wave=$optghw.ghw"; fi -cmd+=" 2>&1" -if [[ -n "$isghdl" ]] ; then cmd+=" | ghdl_assert_filter"; fi -cmd+=" | tee $logfile" +# now build actual test command (a tbw | tbfilt pipe) +cmdtb="tbw $tbench" +if [[ -n "$stimfile" ]] ; then cmdtb+=" $stimfile"; fi +if [[ -n "$opttbw" ]] ; then cmdtb+=" $opttbw"; fi +if [[ -n "$optstack" ]] ; then cmdtb+=" --stack-max-size=$optstack"; fi +if [[ -n "$optghw" ]] ; then cmdtb+=" --wave=$optghw.ghw"; fi +cmdtb+=" 2>&1" -pcomtag="" -if [[ -n "$optpcom" ]] ; then pcomtag="^C|"; fi -# FAIL, PASS, DONE come from tbs; ERROR comes from ISim -cmd+=" | egrep \"(${pcomtag}-[EFW]:|ERROR|FAIL|PASS|DONE)\"" -docmd "$cmd" +cmdtf="tbfilt -tee $logfile" +if [[ -n "$optpcom" ]] ; then cmdtf+=" -pcom"; fi + +cmd="(export TIMEFORMAT=$'real %3lR user %3lU sys %3lS'; time $cmdtb) 2>&1" +cmd+=" | $cmdtf" +txt="$cmdtb | $cmdtf" + +if [[ -z "$optnorun" ]] ; then + docmd "$cmd" "$txt" +fi
/trunk/tools/bin/tbrun_tbwrri
1,5 → 1,5
#!/bin/bash
# $Id: tbrun_tbwrri 778 2016-06-25 15:18:01Z mueller $
# $Id: tbrun_tbwrri 808 2016-09-17 13:02:46Z mueller $
#
# Copyright 2014-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
6,9 → 6,14
#
# Revision History:
# Date Rev Version Comment
# 2016-09-17 808 1.3.3 add --r(l|b)mon,(b|s)wait; configure now via _conf=
# 2016-09-03 805 1.3.2 add TIMEFORMAT and time for make commands
# 2016-08-21 800 1.3.1 add -norun, -nomake
# 2016-08-06 795 1.3 use tbfilt; fixup -lsuf logic
# 2016-07-03 783 1.2.5 drop ghdl_assert_filter (use --ieee=... at ghdl lvl)
# 2016-06-25 778 1.2.4 drop make ghdl_tmp_clean logic
# 2016-06-18 776 1.2.3 use ti_rri --tout to set connection timeout
# 2016-06-05 773 1.2.2 use _bsim.log for behavioural sim log
# 2016-06-05 773 1.2.2 use _bsim.log for behavioral sim log
# 2016-03-20 748 1.2.1 BUGFIX: add portsel oob for -hxon
# use 120 sec timeout for simulation
# 2016-03-18 745 1.2 use --sxon and --hxon instead of --xon
26,13 → 31,17
 
docmd ()
{
echo "$1"
if [[ -z "$optdry" ]] ; then
echo "$2"
eval "$1"
else
echo "$1"
fi
}
 
optdry=""
optnomake=""
optnorun=""
optlsuf=""
optstack=""
optghw=""
44,23 → 53,33
optfusp=""
optsxon=""
opthxon=""
optrlmon=""
optrbmon=""
optbwait=0
optswait=0
 
# handle options
while (( $# > 0 )) ; do
case $1 in
-dry|--dry) optdry=$1 ; shift 1 ;;
-lsuf|--lsuf) optlsuf=$2 ; chkval $2 ; shift 2 ;;
-stack|--stack) optstack=$2 ; chkval $2 ; shift 2 ;;
-ghw|--ghw) optghw=$2 ; chkval $2 ; shift 2 ;;
-tbw|--tbw) opttbw=$2 ; chkval $2 ; shift 2 ;;
-pack|--pack) optpack=$2 ; chkval $2 ; shift 2 ;;
-rri|--rri) optrri=$2 ; chkval $2 ; shift 2 ;;
-cuff|--cuff) optcuff=$1 ; shift 1 ;;
-fusp|--fusp) optfusp=$1 ; shift 1 ;;
-sxon|--sxon) optsxon=$1 ; shift 1 ;;
-hxon|--hxon) opthxon=$1 ; shift 1 ;;
-pcom|--pcom) optpcom=$1 ; shift 1 ;;
-\?|-h*|--h*) opthelp=$1 ; shift 1 ;;
-dry|--dry) optdry=$1 ; shift 1 ;;
-nomake|--nomake) optnomake=$1 ; shift 1 ;;
-norun|--norun) optnorun=$1 ; shift 1 ;;
-lsuf|--lsuf) optlsuf=$2 ; chkval $2 ; shift 2 ;;
-stack|--stack) optstack=$2 ; chkval $2 ; shift 2 ;;
-ghw|--ghw) optghw=$2 ; chkval $2 ; shift 2 ;;
-tbw|--tbw) opttbw=$2 ; chkval $2 ; shift 2 ;;
-pack|--pack) optpack=$2 ; chkval $2 ; shift 2 ;;
-rri|--rri) optrri=$2 ; chkval $2 ; shift 2 ;;
-cuff|--cuff) optcuff=$1 ; shift 1 ;;
-fusp|--fusp) optfusp=$1 ; shift 1 ;;
-sxon|--sxon) optsxon=$1 ; shift 1 ;;
-hxon|--hxon) opthxon=$1 ; shift 1 ;;
-pcom|--pcom) optpcom=$1 ; shift 1 ;;
-rlmon|--rlmon) optrlmon=$1 ; shift 1 ;;
-rbmon|--rbmon) optrlmon=$1 ; shift 1 ;;
-bwait|--bwait) optbwait=$2 ; chkval $2 ; shift 2 ;;
-swait|--swait) optswait=$2 ; chkval $2 ; shift 2 ;;
-\?|-h*|--h*) opthelp=$1 ; shift 1 ;;
-*) echo "tbrun_tbwrri-E: invalid option '$1'"; exit 1 ;;
*) break;;
esac
71,6 → 90,8
echo "Usage: tbrun_tbwrri [opts] testbench rricmds..."
echo " Options:"
echo " --dry dry run, print commands, don't execute"
echo " --nomake don't execute make step"
echo " --norun don't execute run step"
echo " --lsuf suff use '_<suff>.log' as suffix for log file"
echo " --stack nnn use <nnn> as ghdl stack size"
echo " --ghw fname write ghw file with name '<fname>.ghw'"
82,6 → 103,10
echo " --sxon use xon with 1st serport (via SWI(1))"
echo " --hxon use xon with 1st serport (hardwired)"
echo " --pcom print test comments"
echo " --rlmon enable rlmon"
echo " --rbmon enable rbmon"
echo " --bwait ns start-up wait in ns for behavioral simulations"
echo " --swait ns start-up wait in ns for post-syn simulations"
exit 1
fi
 
99,32 → 124,80
 
tbench=$1
shift 1
makeopts=""
 
tbenchname=$(basename $tbench)
tbenchpath=$(dirname $tbench)
 
# issue makes
docmd "make -C $tbenchpath $tbenchname"
exitstat=$?
# add -C $tbenchpath only if not '.' to avoid 'Entering/Leaving' messages
makeopts=""
if [[ "$tbenchpath" != "." ]] ; then
makeopts="-C $tbenchpath"
fi
if [[ -z "$optnomake" ]] ; then
cmd="TIMEFORMAT=$'real %3lR user %3lU sys %3lS'"
cmd+=$'\n'
cmd+="time make $makeopts $tbench"
docmd "$cmd"
exitstat=$?
if (( $exitstat > 0 )) ; then exit $exitstat; fi
echo ""
fi
 
if (( $exitstat > 0 )) ; then exit $exitstat; fi
# check for test bench
if [[ ! -x $tbench ]] ; then
echo "tbrun_tbwrri-E: $tbench not existing or not executable"
exit 1
fi
 
# determine logfile name
# determine logfile name and determine startup wait (bwait or swait)
logsuff="_bsim"
if [[ $tbenchname =~ _[sft]sim$ ]] ; then logsuff=""; fi
if [[ -n "$optlsuf" ]] ; then logsuff="_$optlsuf"; fi
waitns=$optbwait
if [[ $tbenchname =~ _[fsorept]sim$ ]] ; then
logsuff=""
waitns=$optswait
fi
if [[ -n "$optlsuf" ]] ; then logsuff+="_$optlsuf"; fi
 
logfile="${tbenchname}${logsuff}.log"
 
# determine simbus configure (done with inline mode _conf={l1;l2;l3})
# Note: .sdata expects hex in full signal size (addr 8 bit, data 16 bit)
conf=""
if [[ -n "$optcuff" ]] ; then
conf+=".sdata 08 0004;" # portsel = 0100 -> fx2
conf+=".sdata 10 0004;" # swi = 0100 -> fx2
fi
 
if [[ -n "$optfusp" ]] ; then
conf+=".sdata 08 0001;" # portsel = 0001 -> 2nd ser
conf+=".sdata 10 0001;" # swi = 0001 -> 2nd ser
fi
 
if [[ -n "$optsxon" ]] ; then
conf+=".sdata 08 0002;" # portsel = 0010 -> 1st ser XON
conf+=".sdata 10 0002;" # swi = 0010 -> 1st ser XON
fi
 
if [[ -n "$opthxon" ]] ; then
conf+=".sdata 08 0002;" # portsel = 0010 -> 1st ser XON
fi
 
if (( $waitns > 0 )) ; then
conf+=".wait $waitns ns;"
fi
 
# now build actual test command
cmd="time ti_rri --run=\"tbw $tbench -fifo"
if [[ -n "$opttbw" ]] ; then cmd+=" $opttbw"; fi
if [[ -n "$optstack" ]] ; then cmd+=" --stack-max-size=$optstack"; fi
cmdtb+="ti_rri --run=\"tbw $tbench -fifo"
if [[ -n "$conf" ]] ; then cmdtb+=" '_conf={$conf}'"; fi
if [[ -n "$opttbw" ]] ; then cmdtb+=" $opttbw"; fi
if [[ -n "$optstack" ]] ; then cmdtb+=" --stack-max-size=$optstack"; fi
if [[ -n "$optghw" ]] ; then
if [[ "$optghw" != *.ghw ]]; then optghw="$optghw.ghw"; fi
cmd+=" --wave=$optghw";
cmdtb+=" --wave=$optghw";
fi
cmd+=" 2>&1 | ghdl_assert_filter\""
cmdtb+=" 2>&1 \""
 
# Note: the following ensurs that we always have 'fifo=,<options>' with an
# empty first field (the default fifo name)
131,54 → 204,36
fifoopts=""
if [[ -n "$opthxon" ]] ; then fifoopts+=",xon"; fi
if [[ -n "$optsxon" ]] ; then fifoopts+=",xon"; fi
if (( $ncfxcount > 0 )) ; then fifoopts+=",noinit"; fi
 
if [[ -n "$fifoopts" ]] ; then
cmd+=" --fifo=$fifoopts"
cmdtb+=" --fifo=$fifoopts"
else
cmd+=" --fifo"
cmdtb+=" --fifo"
fi
 
cmd+=" --logl=3"
cmd+=" --tout=120." # 120 sec timeout for simulation
cmdtb+=" --logl=3"
cmdtb+=" --tout=120." # 120 sec timeout for simulation
 
if [[ -n "$optpack" ]] ; then cmd+=" --pack=$optpack"; fi
if [[ -n "$optrri" ]] ; then cmd+=" $optrri"; fi
if [[ -n "$optpack" ]] ; then cmdtb+=" --pack=$optpack"; fi
if [[ -n "$optrri" ]] ; then cmdtb+=" $optrri"; fi
 
cmd+=" --"
cmdtb+=" --"
 
if [[ -n "$optcuff" ]] ; then
cmd+=" \"rlc oob -sbdata 8 0x4\"" # portsel = 0100 -> fx2
cmd+=" \"rlc oob -sbdata 16 0x4\"" # swi = 0100 -> fx2
fi
while (( $# > 0 )) ; do
cmdtb+=" "
if [[ $1 =~ " " ]] ; then cmdtb+="\""; fi
cmdtb+="$1"
if [[ $1 =~ " " ]] ; then cmdtb+="\""; fi
shift 1
done
 
if [[ -n "$optfusp" ]] ; then
cmd+=" \"rlc oob -sbdata 8 0x1\"" # portsel = 0001 -> 2nd ser
cmd+=" \"rlc oob -sbdata 16 0x1\"" # swi = 0001 -> 2nd ser
fi
cmdtf="tbfilt -tee $logfile"
if [[ -n "$optpcom" ]] ; then cmdtf+=" -pcom"; fi
 
if [[ -n "$optsxon" ]] ; then
cmd+=" \"rlc oob -sbdata 8 0x2\"" # portsel = 0010 -> 1st ser XON
cmd+=" \"rlc oob -sbdata 16 0x2\"" # swi = 0010 -> 1st ser XON
fi
cmd="(export TIMEFORMAT=$'real %3lR user %3lU sys %3lS'; time $cmdtb) 2>&1"
cmd+=" | $cmdtf"
txt="$cmdtb | $cmdtf"
 
if [[ -n "$opthxon" ]] ; then
cmd+=" \"rlc oob -sbdata 8 0x2\"" # portsel = 0010 -> 1st ser XON
if [[ -z "$optnorun" ]] ; then
docmd "$cmd" "$txt"
fi
 
if (( $ncfxcount > 0 )) ; then cmd+=" \"rlc init\""; fi
 
while (( $# > 0 )) ; do
cmd+=" "
if [[ $1 =~ " " ]] ; then cmd+="\""; fi
cmd+="$1"
if [[ $1 =~ " " ]] ; then cmd+="\""; fi
shift 1
done
cmd+=" | tee $logfile"
 
pcomtag=""
if [[ -n "$optpcom" ]] ; then pcomtag="^\#|"; fi
# FAIL, PASS, DONE come from tbs
cmd+=" | egrep \"(${pcomtag}-[EFW]:|FAIL|PASS|DONE)\""
docmd "$cmd"
/trunk/tools/bin/tbw
1,5 → 1,5
#!/usr/bin/perl -w
# $Id: tbw 778 2016-06-25 15:18:01Z mueller $
# $Id: tbw 808 2016-09-17 13:02:46Z mueller $
#
# Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
14,6 → 14,9
#
# Revision History:
# Date Rev Version Comment
# 2016-09-03 805 1.5.4 use {} as delimiter for immediate mode data
# 2016-08-28 804 1.5.3 BUGFIX: xsim: append -R to ARGV (was prepended...)
# 2016-07-02 782 1.5.2 add TBW_GHDL_OPTS
# 2016-06-25 778 1.5.1 support all sim modes
# 2016-04-17 762 1.5 make '-run' default for [IX]Sim, add '-norun'
# 2016-03-20 748 1.4 recode OPTIONS handling and -fifo handling
50,9 → 53,10
use Cwd 'abs_path';
 
my $tb_code;
my $is_isim;
my $is_ghdl; # uses ghdl simulator
my $is_isim; # uses ISE simulator
my $is_isim_run;
my $is_xsim;
my $is_xsim; # uses vivado simulator
my $opt_run;
my $opt_norun;
my $opt_fifo;
62,6 → 66,8
my @args_nam; # list of named args
my @file_dsc; # file descriptors from tbw.dat
 
my $ghdl_opts = $ENV{TBW_GHDL_OPTS}; # ghdl extra options
 
sub print_usage;
 
autoflush STDOUT 1; # autoflush, so nothing lost on exec later
87,7 → 93,7
$tb_code_name = $2;
}
 
# process -run, -fifo and -verbose options (can be in any order now)
# process -norun, -fifo and -verbose options (can be in any order now)
 
while (scalar(@ARGV)) {
my $opt = $ARGV[0];
113,9 → 119,11
if ($tb_code_stem =~ /_XSim$/) { # is it an XSim executable ?
$tb_code_stem =~ s/_XSim$//; # drop _XSim
$is_xsim = 1;
unshift @ARGV,'-R' unless $opt_norun; # run all unless '-norun' given
push @ARGV,'-R' unless $opt_norun; # run all unless '-norun' given
}
 
$is_ghdl = not ($is_isim or $is_xsim);
 
if (not -e $tb_code) {
print "tbw-E: $tb_code not existing or not executable\n";
print_usage;
151,7 → 159,7
}
}
} else {
print "tbw-W: failed to find $tbwdat_file\n";
print "tbw-I: didn't find ${tbwdat_file}, using defaults\n";
}
 
#
228,7 → 236,7
 
} else { # handle link to file cases
 
if ($val =~ /^\[(.*)\]$/) { # immediate data case: "[line1;line2;...]"
if ($val =~ /^\{(.*)\}$/) { # immediate data case: "{line1;line2;...}"
my @lines = split /;/, $1;
my $fname = "$tag\_tmp.tmp";
open TFILE,">$fname" or die "can't create temporary file $fname: $!";
256,7 → 264,7
}
 
if (not -r $val) {
print "tbw-F: file for $tag not existing or not readable: $val\n";
print "tbw-F: file for '$tag' not existing or not readable: $val\n";
exit 1;
}
 
283,6 → 291,13
}
 
#
# additional ghdl options
#
if ($is_ghdl && defined $ghdl_opts) {
push @ARGV, split /\s+/,$ghdl_opts;
}
 
#
# here all ok, finally exec test bench
#
 
296,6 → 311,7
or die "failed to close process pipe to isim: $!";
 
} else { # otherwise just exec
# print ($tb_code . " " . join(" ",@ARGV) . "\n");
exec $tb_code,@ARGV
or die "failed to exec: $!";
}
304,13 → 320,13
sub print_usage {
print "usage: tbw <tb_code> [opts] [filedefs] [ghdl-opts]\n";
print " opts\n";
print " -run for _ISim tb's, runs the tb with a 'run all' command\n";
print " -norun for _ISim tb's, runs the tb without 'run all' command\n";
print " -fifo use rlink_cext fifo, ignore tbw.dat\n";
print " -verbose show the used tag,value settings before execution\n";
print " filedefs define tb input, either filename in tbw.dat order or\n";
print " tag=name or tag=[<content>] pairs with tag matching one in in\n";
print " tbw.dat. The [<content>] form allows to give data inline, e.g.\n";
print " like \"_conf=[.rpmon 1]\"\n";
print " like \"_conf={.rpmon 1}\"\n";
print " ghdl-opts are all other options starting with a '-', they are\n";
print " passed to the testbench. Some useful ghdl options are:\n";
print " --wave=x.ghw\n";
/trunk/tools/bin/ti_rri
1,6 → 1,6
#! /usr/bin/env tclshcpp
# -*- tcl -*-
# $Id: ti_rri 776 2016-06-18 17:22:51Z mueller $
# $Id: ti_rri 799 2016-08-21 09:20:19Z mueller $
#
# Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
230,7 → 230,7
if { $opts(run_) ne "" } {
if { [catch {exec sh -c $opts(run_) &} runpid] } {
puts "-E: failed to execute \"$opts(run_)\" with error message\n $runpid"
puts "aborting..."
puts "-E: aborting..."
return 1
}
}
314,13 → 314,13
if { [catch {source $filename} errmsg] } {
puts "-E: failed to source file \"$filename\" with error message:"
if {[info exists errorInfo]} {puts $errorInfo} else {puts $errmsg}
puts "aborting..."
puts "-E: aborting..."
break
}
# handle @file.dat ect --> not yet supported
} else {
puts "-E: only tcl supported but $filename found"
puts "aborting..."
puts "-E: aborting..."
break
}
 
329,7 → 329,7
if { [catch {eval $cmd} errmsg] } {
puts "-E: eval of \"$cmd\" failed with error message:"
if {[info exists errorInfo]} {puts $errorInfo} else {puts $errmsg}
puts "aborting..."
puts "-E: aborting..."
break
}
}
/trunk/tools/bin/ticonv_pdpcp
1,7 → 1,7
#!/usr/bin/perl -w
# $Id: ticonv_pdpcp 675 2015-05-08 21:05:08Z mueller $
# $Id: ticonv_pdpcp 795 2016-08-09 12:45:58Z mueller $
#
# Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
14,6 → 14,7
#
# Revision History:
# Date Rev Version Comment
# 2016-08-07 795 1.3.2 avoid GetOptions =f (bug in perl v5.22.1)
# 2015-05-08 675 1.3.1 start/stop/suspend overhaul
# 2015-04-03 661 1.3 adopt to new stat checking and mask polarity
# 2014-12-27 622 1.2.1 use wmembe now
34,7 → 35,7
 
my %opts = ();
 
GetOptions(\%opts, "tout=f", "cmax=i"
GetOptions(\%opts, "tout=s", "cmax=i"
)
or die "bad options";
 
/trunk/tools/bin/ticonv_rri
0,0 → 1,546
#!/usr/bin/perl -w
# $Id: ticonv_rri 795 2016-08-09 12:45:58Z mueller $
#
# Copyright 2014-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 2, or at your option any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
# Revision History:
# Date Rev Version Comment
# 2016-08-07 795 1.2.1 avoid GetOptions =f (bug in perl v5.22.1)
# 2015-04-03 661 1.2 adopt to new stat checking and mask polarity
# 2015-01-31 640 1.1.2 use 'rlc get|set' instead of 'rlc config'
# 2014-12-21 616 1.1.1 add .ndef and n= for BlockDone expects
# 2014-12-06 609 1.1 use .cmax and .eop; drop .cclst; (for rlink v4)
# 2014-08-09 580 1.0 Initial version
#
 
#-------------------------------------------------------------------------------
# handles the command:
#
# .mode rri
# .dbaso n
# .rlmon 0|1
# .rbmon 0|1
# .scntl n 0|1
#! .sinit g8 g16 !! NOT YET !!
# .sdef [s=g8]
# .ndef 0|1
# .amclr
# .amdef name g8
# .reset
# .wait n
# .wtlam n
# .cmax n
# .eop
# rreg <addr> [d=g16] [s=g8]
# wreg <addr> g16 [s=g8]
# rblk <addr> n [n=dd] [s=g8]
# followed by n d=g16 data check values
# wblk <addr> n [n=dd] [s=g8]
# followed by n g16 data values
# stat [d=g16] [s=d8]
# attn [d=g16] [s=d8]
# init <addr> g16 [s=g8]
#
 
use 5.005; # require Perl 5.005 or higher
use strict; # require strict checking
 
use Getopt::Long;
use FileHandle;
 
my %opts = ();
 
GetOptions(\%opts, "tout=s", "cmax=i"
)
or die "bad options";
 
sub cmdlist_do;
sub add_addr;
sub add_data;
sub add_edata;
sub add_edata;
 
sub cget_chkblank; # check for unused chars in cmd line
sub cget_tagval2_gdat; # get tag=v1[,v2], generic base
sub cget_tagval_gdat; # get tag=val, generic base
sub cget_gdat; # get generic base value
sub sget_bdat; # convert 01 string -> binary value
sub get_line;
 
my $cmd_line;
my $cmd_rest;
my $dbase = 2; # use binary as default data radix
 
my @cmdfh;
my @cmdlist;
 
if (scalar(@ARGV) != 1) {
print STDERR "ticonv_rri-E: usage: ticonv_rri <filename>\n";
exit 1;
}
 
my $fnam = $ARGV[0];
my $tout = $opts{tout} || 10.;
my $cmax = $opts{cmax} || 6;
 
my $ref_sdef = 0x00; # by default check for 'hard' errors
my $msk_sdef = 0xf8; # ignore the status bits + attn flag
my $chk_ndef = 1; # dcnt default check on by default
 
my $fh = new FileHandle;
$fh->open("<$fnam") or die "failed to open '$fnam'";
push @cmdfh, $fh;
 
print "set save_config_basedata [rlc get basedata]\n";
print "set save_config_basestat [rlc get basestat]\n";
print "rlc set basedata 8\n";
print "rlc set basestat 2\n";
 
while (1) {
my $cmd = get_line();
last unless defined $cmd;
$cmd_line = $cmd;
$cmd_rest = "";
 
# .mode mode -> accept only 'rri', quit otherwise ------------------
if ($cmd =~ /^\.mode\s+(.*)$/) {
if ($1 ne "rri") {
print "# FAIL: $cmd not supported\n";
exit 1;
}
next;
 
# .dbaso n ---------------------------------------------------------
} elsif ($cmd =~ /^\.dbaso\s+(\d+)$/) {
my $dbaso = $1;
cmdlist_do();
print "rlc set basedata $dbaso\n";
 
# .cmax n ----------------------------------------------------------
} elsif ($cmd =~ /^\.cmax\s+(\d+)$/) {
$cmax = $1;
next;
 
# .eop -------------------------------------------------------------
} elsif ($cmd =~ /^\.eop/) {
cmdlist_do();
next;
 
# .sdef s=ref[,msk] ------------------------------------------------
} elsif ($cmd =~ /^\.sdef\s+s=([01]+),?([01]*)/) {
$cmd_rest = $';
cmdlist_do();
$ref_sdef = oct("0b$1");
$msk_sdef = oct("0b$2");
 
# .ndef ------------------------------------------------------------
} elsif ($cmd =~ /^\.ndef\s+([01])/) {
$cmd_rest = $';
cmdlist_do();
$chk_ndef = $1;
 
# .rlmon,.rbmon ----------------------------------------------------
} elsif ($cmd =~ /^\.(r[lb]mon)\s+(\d)/) {
$cmd_rest = $';
cmdlist_do();
print "rlc oob -$1 $2\n";
 
# .scntl -----------------------------------------------------------
} elsif ($cmd =~ /^\.scntl\s+(\d+)\s+(\d)/) {
$cmd_rest = $';
cmdlist_do();
print "rlc oob -sbcntl $1 $2\n";
 
# .reset -----------------------------------------------------------
} elsif ($cmd =~ /^\.reset/) {
$cmd_rest = $';
cmdlist_do();
print "rlc exec -init 0 1\n";
 
# .amclr -----------------------------------------------------------
} elsif ($cmd =~ /^\.amclr/) {
$cmd_rest = $';
cmdlist_do();
print "rlc amap -clear\n";
 
# .amdef -----------------------------------------------------------
} elsif ($cmd =~ /^\.amdef\s+([0-9a-z]+)\s+([01]+)/) {
$cmd_rest = $';
cmdlist_do();
my $anam = $1;
my $aval = sprintf ('0%3.3o', oct("0b$2"));
print "rlc amap -insert $anam $aval\n";
 
# .wait n ----------------------------------------------------------
# Note: simply send zeros rather true idles. both are discarded anyway
} elsif ($cmd =~ /^(\.wait)/) {
$cmd_rest = $';
my $delay = cget_gdat(16,10,1,256);
cmdlist_do();
print "rlc log \".wait $delay\"\n";
print "rlc rawio -wblk {";
for (my $i = 0; $i < $delay; $i++) {
printf " 0%3.3o", 0x00;
}
print "}\n";
 
# .wtlam n ---------------------------------------------------------
# Note: ignore n, use tout here !
} elsif ($cmd =~ /^(\.wtlam)/) {
$cmd_rest = $';
my $delay = cget_gdat(16,10,1); # currently ignores
cmdlist_do();
printf "rlc wtlam %d\n", $tout;
 
# rreg <addr> [d=g16] [s=b8] ---------------------------------------
} elsif ($cmd =~ /^rreg/) {
$cmd_rest = $';
my $act = "-rreg";
$act .= add_addr();
$act .= add_edata($dbase);
$act .= add_estat();
push @cmdlist, $act;
 
# wreg|init <addr> g16 [s=b8] --------------------------------------
} elsif ($cmd =~ /^(wreg|init)/) {
$cmd_rest = $';
my $act = "-$1";
$act .= add_addr();
$act .= add_data($dbase);
$act .= add_estat();
push @cmdlist, $act;
 
# rblk <addr> n [n=dd] [s=b8] --------------------------------------
} elsif ($cmd =~ /^rblk/) {
$cmd_rest = $';
my $act = "-rblk";
$act .= add_addr();
my $nblk = cget_gdat(16,10,1,256);
$act .= " $nblk";
$act .= add_edone($nblk);
$act .= add_estat();
cget_chkblank();
my @ref_rblk;
my @msk_rblk;
my $do_msk = 0;
for (my $i = 0; $i < $nblk; $i++) {
$cmd_rest = get_line() if ($cmd_rest eq "");
$cmd_rest =~ s/^\s*//;
my ($ref,$msk) = cget_tagval2_gdat("d",16,$dbase);
if (not defined $ref) {
$ref = 0;
$msk = 0xffff;
}
$msk = 0 unless defined $msk;
$do_msk = 1 if $msk != 0;
push @ref_rblk, sprintf("0%6.6o", $ref);
push @msk_rblk, sprintf("0%6.6o", (0xffff & ~$msk));
}
 
$act .= ' -edata {' . join(' ',@ref_rblk) . '}';
$act .= ' {' . join(' ',@msk_rblk) . '}' if $do_msk;
push @cmdlist, $act;
cmdlist_do();
 
# wblk <addr> n [n=dd] [s=b8] --------------------------------------
} elsif ($cmd =~ /^wblk/) {
$cmd_rest = $';
my $act = "-wblk";
$act .= add_addr();
my $nblk = cget_gdat(16,10,1,256);
my $edone = add_edone($nblk);
my $estat = add_estat();
cget_chkblank();
my @dat_wblk;
for (my $i = 0; $i < $nblk; $i++) {
$cmd_rest = get_line() if ($cmd_rest eq "");
$cmd_rest =~ s/^\s*//;
push @dat_wblk, sprintf('0%6.6o', cget_gdat(16,$dbase));
}
 
$act .= ' {' . join(' ',@dat_wblk) . '}';
$act .= $edone;
$act .= $estat;
push @cmdlist, $act;
cmdlist_do();
 
 
# stat|attn [d=g16] [s=b8] -----------------------------------------
} elsif ($cmd =~ /^(stat|attn)\s+/) {
$cmd_rest = $';
my $act = "-$1";
$act .= add_edata($dbase);
$act .= add_estat();
push @cmdlist, $act;
 
# unknown commands -------------------------------------------------
} else {
print "# FAIL: no match for '$cmd'\n";
exit 1;
}
 
cget_chkblank();
 
cmdlist_do() if scalar(@cmdlist) >= $cmax;
}
 
cmdlist_do();
 
print "rlc set basedata \$save_config_basedata\n";
print "rlc set basestat \$save_config_basestat\n";
 
exit 0;
 
#-------------------------------------------------------------------------------
sub add_addr {
my $addr;
 
$cmd_rest =~ s/^\s*//;
if ($cmd_rest =~ /^\.([[0-9a-z.]+)/) {
$addr = $1;
$cmd_rest = $';
} else {
$addr =sprintf('0x%4.4x', cget_gdat(16,2));
}
return " $addr";
}
 
#-------------------------------------------------------------------------------
sub add_data {
my ($dbase) = @_;
my $data = cget_gdat(16,$dbase);
return sprintf(" 0%6.6o", $data);
}
 
#-------------------------------------------------------------------------------
# Note: input has ignore mask, output has check mask now
sub add_edata {
my ($dbase) = @_;
my ($ref,$msk) = cget_tagval2_gdat("d",16,$dbase);
return "" unless defined $ref;
my $str = sprintf(" -edata 0%6.6o", $ref);
$str .= sprintf(" 0%6.6o", (0xffff & ~$msk)) if defined $msk && $msk;
return $str;
}
 
#-------------------------------------------------------------------------------
# Note: input has ignore mask, output has check mask now
# -estat always added, either from s= tag or from .sdef directive
sub add_estat {
my ($dat, $msk) = cget_tagval2_gdat("s",8,2);
unless (defined $dat) {
$dat = $ref_sdef;
$msk = $msk_sdef;
}
my $str = sprintf(" -estat 0x%2.2x", $dat);
$str .= sprintf(" 0x%2.2x", (0xff & ~$msk)) if defined $msk && $msk;
return $str;
}
 
#-------------------------------------------------------------------------------
sub add_edone {
my ($bsize) = @_;
my ($nblk) = cget_tagval_gdat("n",16,10);
$nblk = $bsize if (not defined $nblk && $chk_ndef);
return "" unless defined $nblk;
my $str = sprintf(" -edone %d", $nblk);
return $str;
}
 
#-------------------------------------------------------------------------------
sub cmdlist_do {
return unless scalar(@cmdlist);
 
print "rlc exec \\\n";
while (scalar(@cmdlist)) {
print " ";
print shift @cmdlist;
print " \\\n" if scalar(@cmdlist);
}
print "\n";
@cmdlist = ();
return;
}
 
#-------------------------------------------------------------------------------
 
sub cget_chkblank { # check for unused chars in cmd line
$cmd_rest =~ s/^\s*//;
if ($cmd_rest ne "") {
print "ticonv_rri-E: extra data ignored: \"$cmd_rest\"\n";
print " for command: \"$cmd_line\"\n";
exit 1;
}
}
 
#-------------------------------------------------------------------------------
 
sub cget_tagval2_gdat { # get tag=v1[,v2], generic base
my ($tag,$nbit,$dbase) = @_;
my $dat;
my $msk = undef;
$cmd_rest =~ s/^\s*//;
if ($cmd_rest =~ /^$tag=/) {
$cmd_rest = $';
if ($cmd_rest =~ /^-/) {
$cmd_rest = $';
my $msk = (1 << $nbit) -1;
return (0,$msk);
} else {
$dat = cget_gdat($nbit, $dbase);
if ($cmd_rest =~ /^,/) {
$cmd_rest = $';
$msk = cget_gdat($nbit, $dbase);
}
return ($dat, $msk);
}
}
return (undef, undef);
}
 
#-------------------------------------------------------------------------------
 
sub cget_tagval_gdat { # get tag=val, generic base
my ($tag,$nbit,$dbase,$min,$max) = @_;
$cmd_rest =~ s/^\s*//;
if ($cmd_rest =~ /^$tag=/) {
$cmd_rest = $';
return cget_gdat($nbit, $dbase,$min,$max);
}
return undef;
}
 
#-------------------------------------------------------------------------------
 
sub cget_gdat { # get generic base value
my ($nbit,$dbase,$min,$max) = @_;
my $dat;
 
$cmd_rest =~ s/^\s*//;
if ($cmd_rest =~ /^[xXoObBdD]"/) {
if ($cmd_rest =~ /^[xX]"([0-9a-fA-F]+)"/) {
$cmd_rest = $';
$dat = hex $1;
} elsif ($cmd_rest =~ /^[oO]"([0-7]+)"/) {
$cmd_rest = $';
$dat = oct $1;
} elsif ($cmd_rest =~ /^[bB]"([01]+)"/) {
$cmd_rest = $';
my $odat = sget_bdat($nbit, $1);
$dat = $odat if defined $odat;
} elsif ($cmd_rest =~ /^[dD]"([+-]?[0-9]+)"/) {
$cmd_rest = $';
my $odat = (int $1) & ((1<<$nbit)-1);
$dat = $odat;
}
} else {
if ($cmd_rest =~ /^([+-]?[0-9]+)\./) {
$cmd_rest = $';
my $odat = (int $1) & ((1<<$nbit)-1);
$dat = $odat;
} elsif ($dbase == 16 && $cmd_rest =~ /^([0-9a-fA-F]+)/) {
$cmd_rest = $';
$dat = hex $1;
} elsif ($dbase == 8 && $cmd_rest =~ /^([0-7]+)/) {
$cmd_rest = $';
$dat = oct $1;
} elsif ($dbase == 2 && $cmd_rest =~ /^([01]+)/) {
$cmd_rest = $';
my $odat = sget_bdat($nbit, $1);
$dat = $odat if defined $odat;
} elsif ($dbase == 10 && $cmd_rest =~ /^([0-9]+)/) {
$cmd_rest = $';
$dat = int $1;
}
}
 
if (not defined $dat) {
print "ticonv_rri-E: cget_gdat error in \"$cmd_rest\" (base=$dbase)\n";
exit 1;
}
 
if (defined $min && $dat < $min) {
print "ticonv_rri-E: cget_gdat range error, $dat < $min\n";
exit 1;
}
if (defined $max && $dat > $max) {
print "ticonv_rri-E: cget_gdat range error, $dat > $max\n";
exit 1;
}
 
return $dat;
}
 
#-------------------------------------------------------------------------------
 
sub sget_bdat { # convert 01 string -> binary value
my ($nbit,$str) = @_;
my $nchar = length($str);
my $odat = 0;
 
if ($nchar != $nbit) {
print "ticonv_rri-E: sget_bdat error \'$str\' has not length $nbit\n";
exit 1;
}
 
for (my $i = 0; $i < $nchar; $i++) {
$odat *= 2;
$odat += 1 if substr($str, $i, 1) eq "1";
}
return $odat;
}
 
#-------------------------------------------------------------------------------
 
sub get_line {
while (1) {
return undef unless scalar(@cmdfh);
my $fh = $cmdfh[$#cmdfh];
my $cmd = <$fh>;
if (not defined $cmd) {
$fh->close();
pop @cmdfh;
next;
}
 
# detect @<fname> lines
if ($cmd =~ /^@(.+)/) {
my $fnam = $1;
my $fh = new FileHandle;
$fh->open("<$fnam") or die "failed to open '$fnam'";
push @cmdfh, $fh;
next;
}
 
# write C... comment lines to rlc log
if ($cmd =~ /^C(.*)/) {
cmdlist_do();
my $msg = $1;
$msg =~ s/"/'/g;
$msg =~ s/\[/\{/g;
$msg =~ s/\]/\}/g;
print "rlc log \"C $msg\"\n";
next;
}
 
$cmd =~ s{^\s*}{}; # remove leading blanks
 
next if $cmd =~ m/^#/; # ignore "# ...." lines
next if $cmd =~ m/^;/; # ignore "; ...." lines
 
$cmd =~ s{--.*}{}; # remove comments after --
$cmd =~ s{\s*$}{}; # remove trailing blanks
next if $cmd eq ""; # ignore empty lines
 
return $cmd;
}
}
trunk/tools/bin/ticonv_rri Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/tools/bin/vbomconv =================================================================== --- trunk/tools/bin/vbomconv (revision 36) +++ trunk/tools/bin/vbomconv (revision 37) @@ -1,5 +1,5 @@ #!/usr/bin/perl -w -# $Id: vbomconv 778 2016-06-25 15:18:01Z mueller $ +# $Id: vbomconv 804 2016-08-28 17:33:50Z mueller $ # # Copyright 2007-2016 by Walter F.J. Mueller # @@ -14,6 +14,8 @@ # # Revision History: # Date Rev Version Comment +# 2016-08-28 804 1.17.3 xsim work dir now xsim.. +# 2016-07-02 782 1.17.2 add VBOMCONV_GHDL_OPTS and VBOMCONV_GHDL_GCOV # 2016-06-24 778 1.17.1 -vsyn_prj: add [rep]sim models & VBOMCONV_XSIM_LANG # -ghdl_(i|m|a): use --workdir # 2016-06-19 777 1.17 -vsyn_prj: sim and syn source sets based on -UUT @@ -144,15 +146,24 @@ my $xst_writevhdl = 1; my $xlpath=$opts{xlpath}; my $no_xlpath = ! defined $xlpath || $xlpath eq ""; -my $xsim_lang = 'verilog'; # xsim model language +my $ghdl_opts = $ENV{VBOMCONV_GHDL_OPTS}; # ghdl extra options +my $ghdl_gcov = $ENV{VBOMCONV_GHDL_GCOV}; # ghdl gcov enable +my $xsim_lang = $ENV{VBOMCONV_XSIM_LANG}; # xsim model language -$xsim_lang = $ENV{VBOMCONV_XSIM_LANG} if defined $ENV{VBOMCONV_XSIM_LANG}; +if ($ghdl_gcov) { + $ghdl_opts = '' unless defined $ghdl_opts; + $ghdl_opts .= ' ' unless $ghdl_opts eq ''; + $ghdl_opts .= '-Wc,-ftest-coverage -Wc,-fprofile-arcs -Wl,-lgcov'; +} else { + $ghdl_opts = '-O2 -g' unless defined $ghdl_opts; +} + +$xsim_lang = 'verilog' unless defined $xsim_lang; if ($xsim_lang ne 'verilog' && $xsim_lang ne 'vhdl') { print STDERR "vbomconv-E: VBOMCONV_XSIM_LANG is '$xsim_lang'\n"; print STDERR "vbomconv-E: VBOMCONV_XSIM_LANG must be 'verilog' or 'vhdl'\n"; exit 1; } - $is_veri = $xsim_lang eq 'verilog'; autoflush STDOUT 1; # autoflush, so nothing lost on exec later @@ -327,7 +338,7 @@ print STDERR " \-UUT: $uut\n" if defined $uut; } -# --ghdh_a -- ghdl analysis command ---------------------------------- +# --ghdl_a -- ghdl analysis command ---------------------------------- if (exists $opts{ghdl_a} || exists $opts{ghdl_a_cmd}) { if ($no_xlpath && ($has_unisim || $has_unimacro || $has_simprim) ) { @@ -343,6 +354,7 @@ $cmd .= " -P$xlpath/unimacro" if $has_unimacro; $cmd .= " -P$xlpath/simprim" if $has_simprim; $cmd .= " --ieee=synopsys"; + $cmd .= " ${ghdl_opts}"; $cmd .= " $file"; print "$cmd\n"; if (exists $opts{ghdl_a}) { @@ -362,7 +374,7 @@ } } -# --ghdh_i -- ghdl inspection command -------------------------------- +# --ghdl_i -- ghdl inspection command -------------------------------- if (exists $opts{ghdl_i} || exists $opts{ghdl_i_cmd}) { my $workdir = "ghdl.${sim_mode}"; @@ -408,7 +420,7 @@ } } -# --ghdh_m -- ghdl make command -------------------------------------- +# --ghdl_m -- ghdl make command -------------------------------------- # Note: the 'buildin' make used by the -m option of ghdl does not # check for object files linked with -Wl, e.g. vhpi objects. # To force a re-elaboration the old executable is deleted first. @@ -436,6 +448,7 @@ $cmd .= " -P$xlpath/unimacro" if $has_unimacro; $cmd .= " -P$xlpath/simprim" if $has_simprim; $cmd .= " --ieee=synopsys"; + $cmd .= " ${ghdl_opts}"; $cmd .= " --no-vital-checks" if $sim_mode ne 'bsim'; foreach (@srcfile_list) { @@ -551,7 +564,10 @@ # --vsim_prj --------------------------------------------------------- if (exists $opts{vsim_prj}) { - my $workdir = "xsim.${sim_mode}"; + # Note: use a separate workdir for each sim_mode and each model (given + # by stem). This allows to have all co-existant, and to delete the workdir + # each time one of them is re-build. + my $workdir = "xsim.${sim_mode}.${stem}"; my $fname_forwarder = "${stem}_XSim"; $fname_forwarder =~ s/_([sorept]sim)_XSim/_XSim_$1/;
/trunk/tools/bin/xise_ghdl_simprim
1,17 → 1,19
#!/bin/bash
# $Id: xise_ghdl_simprim 642 2015-02-06 18:53:12Z mueller $
# $Id: xise_ghdl_simprim 782 2016-07-03 08:09:36Z mueller $
#
# Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Vers Comment
# 2016-07-02 782 1.3.1 add ghdlopts as 1st option; default is -O2
# 2015-02-03 642 1.3 remove ISE 10 legacy support
# 2015-01-29 639 1.2 rename from xilinx_*; use XTWI_PATH rather XILINX
# 2009-11-08 248 1.1 adopt to ISE 11.1, use VITAL models from ./primitive
# 2007-10-26 92 1.0 Initial version
#
 
ghdlopts=${1:--O2 -g}
#
if [ -z "$XTWI_PATH" ]
then
echo "XTWI_PATH not defined"
57,15 → 59,17
popd
#
echo "# ghdl ... simprim_Vcomponents.vhd"
ghdl -a --ieee=synopsys --work=simprim --no-vital-checks simprim_Vcomponents.vhd
ghdl -a --ieee=synopsys --work=simprim --no-vital-checks $ghdlopts \
simprim_Vcomponents.vhd
echo "# ghdl ... simprim_Vpackage.vhd"
ghdl -a --ieee=synopsys --work=simprim --no-vital-checks simprim_Vpackage.vhd
ghdl -a --ieee=synopsys --work=simprim --no-vital-checks $ghdlopts \
simprim_Vpackage.vhd
 
for file in `cat primitive/vhdl_analyze_order`
do
echo "# ghdl ... primitive/$file"
ghdl -a -fexplicit --ieee=synopsys --work=simprim \
--no-vital-checks primitive/$file 2>&1 |\
--no-vital-checks $ghdlopts primitive/$file 2>&1 |\
tee primitive/$file.ghdl.log
done
#
/trunk/tools/bin/xise_ghdl_unisim
1,17 → 1,19
#!/bin/bash
# $Id: xise_ghdl_unisim 642 2015-02-06 18:53:12Z mueller $
# $Id: xise_ghdl_unisim 782 2016-07-03 08:09:36Z mueller $
#
# Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Vers Comment
# 2016-07-02 782 1.3.1 add ghdlopts as 1st option; default is -O2
# 2015-02-03 642 1.3 remove ISE 10 legacy support; add unimacro support
# 2015-01-29 639 1.2 rename from xilinx_*; use XTWI_PATH rather XILINX
# 2009-11-08 248 1.1 adopt to ISE 11.1, use VITAL models from ./primitive
# 2007-10-26 92 1.0 Initial version
#
 
ghdlopts=${1:--O2 -g}
#
if [ -z "$XTWI_PATH" ]
then
echo "XTWI_PATH not defined"
58,14 → 60,14
popd
 
echo "# ghdl ... unisim_VCOMP.vhd"
ghdl -a --ieee=synopsys --work=unisim unisim_VCOMP.vhd
ghdl -a --ieee=synopsys --work=unisim $ghdlopts unisim_VCOMP.vhd
echo "# ghdl ... unisim_VPKG.vhd"
ghdl -a --ieee=synopsys --work=unisim unisim_VPKG.vhd
ghdl -a --ieee=synopsys --work=unisim $ghdlopts unisim_VPKG.vhd
 
for file in `cat primitive/vhdl_analyze_order`
do
echo "# ghdl ... primitive/$file"
ghdl -a -fexplicit --ieee=synopsys --work=unisim \
ghdl -a -fexplicit --ieee=synopsys --work=unisim $ghdlopts \
--no-vital-checks primitive/$file 2>&1 |\
tee primitive/$file.ghdl.log
done
89,7 → 91,7
for file in *.vhd
do
echo "# ghdl ... $file"
ghdl -a -P../unisim -fexplicit --ieee=synopsys --work=unimacro \
ghdl -a -P../unisim -fexplicit --ieee=synopsys --work=unimacro $ghdlopts \
--no-vital-checks $file 2>&1 | tee $file.ghdl.log
done
#
/trunk/tools/bin/xtwi
1,5 → 1,5
#!/bin/bash
# $Id: xtwi 735 2016-02-26 22:17:42Z mueller $
# $Id: xtwi 804 2016-08-28 17:33:50Z mueller $
#
# Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
10,6 → 10,7
#
# Revision History:
# Date Rev Version Comment
# 2016-08-28 804 1.2 BUGFIX: add ":." to PATH even under BARE_PATH
# 2016-02-21 735 1.1 use BARE_PATH ect to provide clean environment
# 2013-10-12 539 1.0 Initial version
#
33,10 → 34,11
fi
 
# provide clean environment when BARE_PATH ect defined
# add only $RETROBASE/tools/bin to path
# add only $RETROBASE/tools/bin and '.' to path
# '.' is needed to start ISim tb's, which usually are in cwd
if [ -n "$BARE_PATH" ]
then
export PATH=$BARE_PATH:$RETROBASE/tools/bin
export PATH=$BARE_PATH:$RETROBASE/tools/bin:.
unset LD_LIBRARY_PATH
if [ -n "$BARE_LD_LIBRARY_PATH" ]
then
/trunk/tools/bin/xviv_ghdl_unisim
1,5 → 1,5
#!/bin/bash
# $Id: xviv_ghdl_unisim 762 2016-04-17 21:33:42Z mueller $
# $Id: xviv_ghdl_unisim 782 2016-07-03 08:09:36Z mueller $
#
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
6,10 → 6,12
#
# Revision History:
# Date Rev Vers Comment
# 2016-07-02 782 1.1.1 add ghdlopts as 1st option; default is -O2
# 2016-04-17 762 1.1 update for viv 2016.1
# 2015-02-02 642 1.0 Initial version
#
 
ghdlopts=${1:--O2 -g}
#
if [ -z "$XTWV_PATH" ]
then
echo "XTWV_PATH not defined"
79,14 → 81,14
# now compile all --------------------------------
#
echo "# ghdl ... unisim_retarget_VCOMP.vhd"
ghdl -a --ieee=synopsys --work=unisim unisim_retarget_VCOMP.vhd
ghdl -a --ieee=synopsys --work=unisim $ghdlopts unisim_retarget_VCOMP.vhd
echo "# ghdl ... unisim_VPKG.vhd"
ghdl -a --ieee=synopsys --work=unisim unisim_VPKG.vhd
ghdl -a --ieee=synopsys --work=unisim $ghdlopts unisim_VPKG.vhd
 
for file in `cat primitive/vhdl_analyze_order`
do
echo "# ghdl ... primitive/$file"
ghdl -a -fexplicit --ieee=synopsys --work=unisim \
ghdl -a -fexplicit --ieee=synopsys --work=unisim $ghdlopts \
--no-vital-checks primitive/$file 2>&1 |\
tee primitive/$file.ghdl.log
done
94,7 → 96,7
for file in `cat retarget/vhdl_analyze_order`
do
echo "# ghdl ... retarget/$file"
ghdl -a -fexplicit --ieee=synopsys --work=unisim \
ghdl -a -fexplicit --ieee=synopsys --work=unisim $ghdlopts \
--no-vital-checks retarget/$file 2>&1 |\
tee retarget/$file.ghdl.log
done
126,7 → 128,7
for file in `cat vhdl_analyze_order`
do
echo "# ghdl ... $file"
ghdl -a -P../unisim -fexplicit --ieee=synopsys --work=unimacro \
ghdl -a -P../unisim -fexplicit --ieee=synopsys --work=unimacro $ghdlopts \
--no-vital-checks $file 2>&1 | tee $file.ghdl.log
done
#
/trunk/tools/dox/w11_cpp.Doxyfile
5,7 → 5,7
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = "w11 - cpp"
PROJECT_NUMBER = 0.73
PROJECT_NUMBER = 0.74
PROJECT_BRIEF = "Backend server for Rlink and w11"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/cpp
/trunk/tools/dox/w11_tcl.Doxyfile
5,7 → 5,7
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = "w11 - tcl"
PROJECT_NUMBER = 0.73
PROJECT_NUMBER = 0.74
PROJECT_BRIEF = "Backend server for Rlink and w11"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/tcl
/trunk/tools/dox/w11_vhd_all.Doxyfile
5,7 → 5,7
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = "w11 - vhd"
PROJECT_NUMBER = 0.73
PROJECT_NUMBER = 0.74
PROJECT_BRIEF = "W11 CPU core and support modules"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/vhd
/trunk/tools/tcl/setup_packages
29,3 → 29,4
pkg_mkIndex -verbose ibd_tm11 *.tcl
#
pkg_mkIndex -verbose tst_rlink *.tcl
pkg_mkIndex -verbose tst_sram *.tcl
/trunk/tools/tcl/tst_sram/.cvsignore
0,0 → 1,4
pkgIndex.tcl
/trunk/tools/tcl/tst_sram/test_all.tcl
0,0 → 1,120
# $Id: test_all.tcl 785 2016-07-10 12:22:41Z mueller $
#
# Copyright 2014-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 2, or at your option any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
# Revision History:
# Date Rev Version Comment
# 2016-07-09 784 2.1 add test_all test driver
# 2014-11-23 606 2.0 use new rlink v4 iface
# 2014-08-14 582 1.0 Initial version
#
 
package provide tst_sram 1.0
 
package require rutiltpp
package require rutil
package require rlink
 
namespace eval tst_sram {
#
# test_all: Driver for all tst_sram tests
#
proc test_all {{tout 10.}} {
#
set errcnt 0
tst_sram::init
incr errcnt [test_regs]
incr errcnt [test_seq $tout]
 
puts "tst_sram::test_all errcnt = $errcnt --> [rutil::errcnt2txt $errcnt]"
return $errcnt
}
 
#
# test_sim: test suite for sim tests ---------------------------------------
# port of cmd_tst_sram_stress_sim.dat
#
proc test_sim {} {
rlink::anena 1; # enable attn notify
rlc exec -attn; # harvest spurious attn
init
scmd_write [test_scmdlist]
 
set lmdi {0x0000 0x0000 \
0xffff 0xffff \
0x0000 0xffff \
0xffff 0x0000 \
0xaaaa 0xaaaa \
0x5555 0x5555 }
 
set lmaddr {0x0000 0x0000 \
0x0003 0xffff \
0x0000 0xffff \
0x000f 0x0000 \
0x000a 0xaaaa \
0x0005 0x5555 }
 
set lmaddr_ran {}
for {set i 0} { $i < 3 } {incr i} {
lappend lmaddr_ran [expr {int(65536*rand()) & 0x000f}]
lappend lmaddr_ran [expr {int(65536*rand()) & 0xffff}]
}
 
srun_lists $lmdi $lmaddr
srun_lists $lmdi $lmaddr_ran
return ""
}
#
# test_fpga: test suite for fpga tests -------------------------------------
# port of cmd_tst_sram_stress_fpga.dat
#
proc test_fpga {{wide -1} {tout 1000.}} {
rlink::anena 1; # enable attn notify
rlc exec -attn; # harvest spurious attn
init
scmd_write [test_scmdlist]
 
set lmdi {0x0000 0x0000 \
0xffff 0xffff \
0x0000 0xffff \
0xffff 0x0000 \
0xaaaa 0xaaaa \
0x5555 0x5555 \
0x1e25 0x4e58 \
0xa9d8 0xd6d4 \
0xbcbd 0x0815 \
0x7424 0x7466 }
 
set lmdi_ran {}
for {set i 0} { $i < 3 } {incr i} {
lappend lmdi_ran [expr {int(65536*rand()) & 0xffff}]
lappend lmdi_ran [expr {int(65536*rand()) & 0xffff}]
}
 
if {$wide < 0} { set wide [iswide] }
 
set maddrh 0x0000
set maddrl 0x0000
if {[rlink::issim]} {
set maddrh [expr {$wide ? 0x003f : 0x0003}]
set maddrl 0xfffc
}
 
foreach {mdih mdil} $lmdi {
srun_loop $mdih $mdil $maddrh $maddrl $wide $tout
}
foreach {mdih mdil} $lmdi_ran {
srun_loop $mdih $mdil $maddrh $maddrl $wide $tout
}
return ""
}
}
/trunk/tools/tcl/tst_sram/test_regs.tcl
0,0 → 1,346
# $Id: test_regs.tcl 785 2016-07-10 12:22:41Z mueller $
#
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 2, or at your option any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
# Revision History:
# Date Rev Version Comment
# 2016-07-10 785 1.1 add memory test (touch evenly distributed addr)
# 2016-07-09 784 1.0 Initial version (ported from tb_tst_sram_stim.dat)
#
 
package provide tst_sram 1.0
 
package require rutiltpp
package require rutil
package require rlink
 
namespace eval tst_sram {
#
# test_regs: Test registers: mdi*,mdo*,maddr*,mcmd,mblk,sblk*
# and saddr,slim,sblk*
#
proc test_regs {} {
#
set errcnt 0
rlc errcnt -clear
#
rlc log "tst_sram::test_regs ---------------------------------------------"
rlc log " init: reset via init, clear sfail ect"
rlc exec -init sr.mdih 0x0003; # reset MEM,SEQ
#
#-------------------------------------------------------------------------
rlc log " test 1a: test mdi* ,maddr*"
rlc exec \
-wreg sr.mdih 0x5555 \
-wreg sr.mdil 0xaaaa \
-wreg sr.maddrh 0x0001 \
-wreg sr.maddrl 0xcccc \
-rreg sr.mdih -edata 0x5555 \
-rreg sr.mdil -edata 0xaaaa \
-rreg sr.maddrh -edata 0x0001 \
-rreg sr.maddrl -edata 0xcccc
#
#-------------------------------------------------------------------------
rlc log " test 1b: test maddrh range"
set maddrh_max [expr {[iswide] ? 0x3f : 0x03}]
rlc exec \
-wreg sr.maddrh 0xffff \
-rreg sr.maddrh -edata $maddrh_max
#
#-------------------------------------------------------------------------
rlc log " test 2: test direct memory write/read via mcmd"
# write mem(0) = 0xdeadbeaf; mem(1)=a5a55a5a
rlc exec \
-wreg sr.maddrh 0x0000 \
-wreg sr.maddrl 0x0000 \
-wreg sr.mdih 0xdead \
-wreg sr.mdil 0xbeaf \
-wreg sr.mcmd [regbld tst_sram::MCMD we {be 0xf}] \
-wreg sr.maddrl 0x0001 \
-wreg sr.mdih 0xa5a5 \
-wreg sr.mdil 0x5a5a \
-wreg sr.mcmd [regbld tst_sram::MCMD we {be 0xf}]
# read back
rlc exec \
-wreg sr.maddrl 0x0000 \
-wreg sr.mcmd [regbld tst_sram::MCMD {be 0xf}] \
-rreg sr.mdoh -edata 0xdead \
-rreg sr.mdol -edata 0xbeaf \
-wreg sr.maddrl 0x0001 \
-wreg sr.mcmd [regbld tst_sram::MCMD {be 0xf}] \
-rreg sr.mdoh -edata 0xa5a5 \
-rreg sr.mdol -edata 0x5a5a
# check that mdi* unchanged (value from last write)
rlc exec \
-rreg sr.mdih -edata 0xa5a5 \
-rreg sr.mdil -edata 0x5a5a
# verify that mcmd write only
rlc exec -rreg sr.mcmd -estaterr; # expect err on read
#
#-------------------------------------------------------------------------
rlc log " test 3: test block write/read via mblk"
# write 8 longwords, check maddrl incremented
rlc exec \
-wreg sr.maddrh 0x0000 \
-wreg sr.maddrl 0x0010 \
-wblk sr.mblk {0x3020 0x1000 \
0x3121 0x1101 \
0x3222 0x1202 \
0x3323 0x1303 \
0x3424 0x1404 \
0x3525 0x1505 \
0x3626 0x1606 \
0x3727 0x1707} \
-rreg sr.maddrh -edata 0x0000 \
-rreg sr.maddrl -edata 0x0018
# read 8 longwords, check maddrl incremented
rlc exec \
-wreg sr.maddrh 0x0000 \
-wreg sr.maddrl 0x0010 \
-rblk sr.mblk 16 -edata {0x3020 0x1000 \
0x3121 0x1101 \
0x3222 0x1202 \
0x3323 0x1303 \
0x3424 0x1404 \
0x3525 0x1505 \
0x3626 0x1606 \
0x3727 0x1707} \
-rreg sr.maddrh -edata 0x0000 \
-rreg sr.maddrl -edata 0x0018
#
#-------------------------------------------------------------------------
rlc log " test 4: mcmd: ld,inc and be functionality"
# use memory as setup by previous test
# overwrite bytes 12(0001)=42, 13(0010)=53, 14(0100)=64, 15(1000)=75
rlc exec \
-wreg sr.maddrh 0x0003 \
-wreg sr.maddrl 0x0012 \
-wreg sr.mdih 0xffff \
-wreg sr.mdil 0xff42 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0x1} {addrh 0x0}] \
-wreg sr.mdil 0x53ff \
-wreg sr.mcmd [regbld tst_sram::MCMD inc we {be 0x2} ] \
-wreg sr.mdih 0xff64 \
-wreg sr.mdil 0xffff \
-wreg sr.mcmd [regbld tst_sram::MCMD inc we {be 0x4} ] \
-wreg sr.mdih 0x75ff \
-wreg sr.mcmd [regbld tst_sram::MCMD inc we {be 0x8} ]
# check load maddrh and increment of maddrl; read back and check
rlc exec \
-rreg sr.maddrh -edata 0x0000 \
-rreg sr.maddrl -edata 0x0016 \
-wreg sr.maddrl 0x0010 \
-rblk sr.mblk 16 -edata {0x3020 0x1000 \
0x3121 0x1101 \
0x3222 0x1242 \
0x3323 0x5303 \
0x3464 0x1404 \
0x7525 0x1505 \
0x3626 0x1606 \
0x3727 0x1707}
#
#-------------------------------------------------------------------------
rlc log " test 5: test saddr,slim,sblk,sblkc,sblkd"
# write/read saddr/slim
rlc exec \
-wreg sr.slim 0x0123 \
-wreg sr.saddr 0x0345 \
-rreg sr.slim -edata 0x0123 \
-rreg sr.saddr -edata 0x0345
# sblk write of 8 lines, check saddr incremented
rlc exec \
-wreg sr.saddr 0x0000 \
-wblk sr.sblk {0x0300 0x0200 0x0100 0x0000 \
0x0301 0x0201 0x0101 0x0001 \
0x0302 0x0202 0x0102 0x0002 \
0x0303 0x0203 0x0103 0x0003 \
0x0304 0x0204 0x0104 0x0004 \
0x0305 0x0205 0x0105 0x0005 \
0x0306 0x0206 0x0106 0x0006 \
0x0307 0x0207 0x0107 0x0007 } \
-rreg sr.saddr -edata 0x0008
# sblk read back
rlc exec \
-wreg sr.saddr 0x0000 \
-rblk sr.sblk 32 -edata {0x0300 0x0200 0x0100 0x0000 \
0x0301 0x0201 0x0101 0x0001 \
0x0302 0x0202 0x0102 0x0002 \
0x0303 0x0203 0x0103 0x0003 \
0x0304 0x0204 0x0104 0x0004 \
0x0305 0x0205 0x0105 0x0005 \
0x0306 0x0206 0x0106 0x0006 \
0x0307 0x0207 0x0107 0x0007 } \
-rreg sr.saddr -edata 0x0008
# sblkc (over-)write of 4 lines (1-4)
rlc exec \
-wreg sr.saddr 0x0001 \
-wblk sr.sblkc {0x1301 0x1201 \
0x1302 0x1202 \
0x1303 0x1203 \
0x1304 0x1204 } \
-rreg sr.saddr -edata 0x0005
# sblkd (over-)write of 4 lines (3-6)
rlc exec \
-wreg sr.saddr 0x0003 \
-wblk sr.sblkd {0x2103 0x2003 \
0x2104 0x2004 \
0x2105 0x2005 \
0x2106 0x2006 } \
-rreg sr.saddr -edata 0x0007
# sblk read back of all 8 lines, verify c and d updates
rlc exec \
-wreg sr.saddr 0x0000 \
-rblk sr.sblk 32 -edata {0x0300 0x0200 0x0100 0x0000 \
0x1301 0x1201 0x0101 0x0001 \
0x1302 0x1202 0x0102 0x0002 \
0x1303 0x1203 0x2103 0x2003 \
0x1304 0x1204 0x2104 0x2004 \
0x0305 0x0205 0x2105 0x2005 \
0x0306 0x0206 0x2106 0x2006 \
0x0307 0x0207 0x0107 0x0007} \
-rreg sr.saddr -edata 0x0008
# sblkc read back of all 8 lines
rlc exec \
-wreg sr.saddr 0x0000 \
-rblk sr.sblkc 16 -edata {0x0300 0x0200 \
0x1301 0x1201 \
0x1302 0x1202 \
0x1303 0x1203 \
0x1304 0x1204 \
0x0305 0x0205 \
0x0306 0x0206 \
0x0307 0x0207} \
-rreg sr.saddr -edata 0x0008
# sblkd read back of all 8 lines
rlc exec \
-wreg sr.saddr 0x0000 \
-rblk sr.sblkd 16 -edata {0x0100 0x0000 \
0x0101 0x0001 \
0x0102 0x0002 \
0x2103 0x2003 \
0x2104 0x2004 \
0x2105 0x2005 \
0x2106 0x2006 \
0x0107 0x0007} \
-rreg sr.saddr -edata 0x0008
#
#-------------------------------------------------------------------------
rlc log " test 5: test sstat bits"
set sm [rutil::com16 [regbld tst_sram::SSTAT wide]]
rlc exec \
-wreg sr.sstat 0 \
-rreg sr.sstat -edata 0 $sm \
-wreg sr.sstat [regbld tst_sram::SSTAT veri ] \
-rreg sr.sstat -edata [regbld tst_sram::SSTAT veri ] $sm \
-wreg sr.sstat [regbld tst_sram::SSTAT xora ] \
-rreg sr.sstat -edata [regbld tst_sram::SSTAT xora ] $sm \
-wreg sr.sstat [regbld tst_sram::SSTAT xord ] \
-rreg sr.sstat -edata [regbld tst_sram::SSTAT xord ] $sm \
-wreg sr.sstat [regbld tst_sram::SSTAT loop ] \
-rreg sr.sstat -edata [regbld tst_sram::SSTAT loop ] $sm \
-wreg sr.sstat [regbld tst_sram::SSTAT wloop] \
-rreg sr.sstat -edata [regbld tst_sram::SSTAT wloop] $sm \
-wreg sr.sstat [regbld tst_sram::SSTAT wswap] \
-rreg sr.sstat -edata [regbld tst_sram::SSTAT wswap] $sm
#
#-------------------------------------------------------------------------
rlc log " test 6: test memory (touch 5(+5) evenly spaced addresses)"
# writes
# 18bit: 0x000000 0x010001 0x020002 0x030003 0x03ffff
rlc exec \
-wreg sr.mdih 0x5500 \
-wreg sr.mdil 0xaa00 \
-wreg sr.maddrl 0x0000 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x00}] \
-wreg sr.mdih 0x5501 \
-wreg sr.mdil 0xaa01 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x01}] \
-wreg sr.mdih 0x5502 \
-wreg sr.mdil 0xaa02 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x02}] \
-wreg sr.mdih 0x5503 \
-wreg sr.mdil 0xaa03 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x03}] \
-rreg sr.maddrl -edata 0x0004 \
-wreg sr.mdih 0x5504 \
-wreg sr.mdil 0xaa04 \
-wreg sr.maddrl 0xffff \
-wreg sr.mcmd [regbld tst_sram::MCMD ld we {be 0xf} {addrh 0x03}]
# 22bit: 0x040000 0x100001 0x200002 0x300003 0x3fffff
if {[iswide]} {
rlc exec \
-wreg sr.mdih 0xa500 \
-wreg sr.mdil 0x5a00 \
-wreg sr.maddrl 0x0000 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x04}] \
-wreg sr.mdih 0x5a01 \
-wreg sr.mdil 0x5a01 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x10}] \
-wreg sr.mdih 0x5a02 \
-wreg sr.mdil 0x5a02 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x20}] \
-wreg sr.mdih 0x5a03 \
-wreg sr.mdil 0x5a03 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x30}] \
-rreg sr.maddrl -edata 0x0004 \
-wreg sr.mdih 0x5a04 \
-wreg sr.mdil 0x5a04 \
-wreg sr.maddrl 0xffff \
-wreg sr.mcmd [regbld tst_sram::MCMD ld we {be 0xf} {addrh 0x3f}]
}
# reads
rlc exec \
-wreg sr.maddrl 0x0000 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x00}] \
-rreg sr.mdoh -edata 0x5500 \
-rreg sr.mdol -edata 0xaa00 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x01}] \
-rreg sr.mdoh -edata 0x5501 \
-rreg sr.mdol -edata 0xaa01 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x02}] \
-rreg sr.mdoh -edata 0x5502 \
-rreg sr.mdol -edata 0xaa02 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x03}] \
-rreg sr.mdoh -edata 0x5503 \
-rreg sr.mdol -edata 0xaa03 \
-rreg sr.maddrl -edata 0x0004 \
-wreg sr.maddrl 0xffff \
-wreg sr.mcmd [regbld tst_sram::MCMD ld {be 0xf} {addrh 0x03}] \
-rreg sr.mdoh -edata 0x5504 \
-rreg sr.mdol -edata 0xaa04
if {[iswide]} {
rlc exec \
-wreg sr.maddrl 0x0000 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x04}] \
-rreg sr.mdoh -edata 0xa500 \
-rreg sr.mdol -edata 0x5a00 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x10}] \
-rreg sr.mdoh -edata 0x5a01 \
-rreg sr.mdol -edata 0x5a01 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x20}] \
-rreg sr.mdoh -edata 0x5a02 \
-rreg sr.mdol -edata 0x5a02 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x30}] \
-rreg sr.mdoh -edata 0x5a03 \
-rreg sr.mdol -edata 0x5a03 \
-rreg sr.maddrl -edata 0x0004 \
-wreg sr.maddrl 0xffff \
-wreg sr.mcmd [regbld tst_sram::MCMD ld {be 0xf} {addrh 0x3f}] \
-rreg sr.mdoh -edata 0x5a04 \
-rreg sr.mdol -edata 0x5a04
}
#
#-------------------------------------------------------------------------
incr errcnt [rlc errcnt -clear]
return $errcnt
}
}
/trunk/tools/tcl/tst_sram/test_scmdlist.tcl
0,0 → 1,690
# $Id: test_scmdlist.tcl 784 2016-07-09 22:17:01Z mueller $
#
# Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 2, or at your option any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
# Revision History:
# Date Rev Version Comment
# 2014-08-14 582 1.0 Initial version
#
 
package provide tst_sram 1.0
 
namespace eval tst_sram {
#
# test_scmdlist: default scmd list -----------------------------------------
# was converted with conv_sblk from cmd_tst_sram_stress_sblk.dat
#
proc test_scmdlist {} {
set clist {}
## C Setup Memory stress test
## C write 16 unique byte patterns (and verify)
lappend clist { 0 w 1111 0x000000 0x30201000};
lappend clist { 0 w 1111 0x000001 0x31211101};
lappend clist { 0 w 1111 0x000002 0x32221202};
lappend clist { 0 w 1111 0x000003 0x33231303};
lappend clist { 0 w 1111 0x000004 0x34241404};
lappend clist { 0 w 1111 0x000005 0x35251505};
lappend clist { 0 w 1111 0x000006 0x36261606};
lappend clist { 0 w 1111 0x000007 0x37271707};
lappend clist { 0 w 1111 0x000008 0x38281808};
lappend clist { 0 w 1111 0x000009 0x39291909};
lappend clist { 0 w 1111 0x00000a 0x3a2a1a0a};
lappend clist { 0 w 1111 0x00000b 0x3b2b1b0b};
lappend clist { 0 w 1111 0x00000c 0x3c2c1c0c};
lappend clist { 0 w 1111 0x00000d 0x3d2d1d0d};
lappend clist { 0 w 1111 0x00000e 0x3e2e1e0e};
lappend clist { 0 w 1111 0x00000f 0x3f2f1f0f};
lappend clist { 0 r 1111 0x000000 0x30201000};
lappend clist { 0 r 1111 0x000001 0x31211101};
lappend clist { 0 r 1111 0x000002 0x32221202};
lappend clist { 0 r 1111 0x000003 0x33231303};
lappend clist { 0 r 1111 0x000004 0x34241404};
lappend clist { 0 r 1111 0x000005 0x35251505};
lappend clist { 0 r 1111 0x000006 0x36261606};
lappend clist { 0 r 1111 0x000007 0x37271707};
lappend clist { 0 r 1111 0x000008 0x38281808};
lappend clist { 0 r 1111 0x000009 0x39291909};
lappend clist { 0 r 1111 0x00000a 0x3a2a1a0a};
lappend clist { 0 r 1111 0x00000b 0x3b2b1b0b};
lappend clist { 0 r 1111 0x00000c 0x3c2c1c0c};
lappend clist { 0 r 1111 0x00000d 0x3d2d1d0d};
lappend clist { 0 r 1111 0x00000e 0x3e2e1e0e};
lappend clist { 0 r 1111 0x00000f 0x3f2f1f0f};
## C single byte writes, all 16 pattern (and verify)
lappend clist { 0 w 0000 0x000000 0x70605040};
lappend clist { 0 w 0001 0x000001 0x71615141};
lappend clist { 0 w 0010 0x000002 0x72625242};
lappend clist { 0 w 0011 0x000003 0x73635343};
lappend clist { 0 w 0100 0x000004 0x74645444};
lappend clist { 0 w 0101 0x000005 0x75655545};
lappend clist { 0 w 0110 0x000006 0x76665646};
lappend clist { 0 w 0111 0x000007 0x77675747};
lappend clist { 0 w 1000 0x000008 0x78685848};
lappend clist { 0 w 1001 0x000009 0x79695949};
lappend clist { 0 w 1010 0x00000a 0x7a6a5a4a};
lappend clist { 0 w 1011 0x00000b 0x7b6b5b4b};
lappend clist { 0 w 1100 0x00000c 0x7c6c5c4c};
lappend clist { 0 w 1101 0x00000d 0x7d6d5d4d};
lappend clist { 0 w 1110 0x00000e 0x7e6e5e4e};
lappend clist { 0 w 1111 0x00000f 0x7f6f5f4f};
lappend clist { 0 r 1111 0x000000 0x30201000};
lappend clist { 0 r 1111 0x000001 0x31211141};
lappend clist { 0 r 1111 0x000002 0x32225202};
lappend clist { 0 r 1111 0x000003 0x33235343};
lappend clist { 0 r 1111 0x000004 0x34641404};
lappend clist { 0 r 1111 0x000005 0x35651545};
lappend clist { 0 r 1111 0x000006 0x36665606};
lappend clist { 0 r 1111 0x000007 0x37675747};
lappend clist { 0 r 1111 0x000008 0x78281808};
lappend clist { 0 r 1111 0x000009 0x79291949};
lappend clist { 0 r 1111 0x00000a 0x7a2a5a0a};
lappend clist { 0 r 1111 0x00000b 0x7b2b5b4b};
lappend clist { 0 r 1111 0x00000c 0x7c6c1c0c};
lappend clist { 0 r 1111 0x00000d 0x7d6d1d4d};
lappend clist { 0 r 1111 0x00000e 0x7e6e5e0e};
lappend clist { 0 r 1111 0x00000f 0x7f6f5f4f};
## C write various 0-1 transition patterns (and verify)
lappend clist { 0 w 1111 0x000010 0x00000000};
lappend clist { 0 w 1111 0x000011 0xffffffff};
lappend clist { 0 w 1111 0x000012 0x00000000};
lappend clist { 0 w 1111 0x000013 0xa5a5a5a5};
lappend clist { 0 w 1111 0x000014 0x5a5a5a5a};
lappend clist { 0 w 1111 0x000015 0x00000000};
lappend clist { 0 w 1111 0x000016 0x0f0f0f0f};
lappend clist { 0 w 1111 0x000017 0xf0f0f0f0};
lappend clist { 0 w 1111 0x000018 0x00ff00ff};
lappend clist { 0 w 1111 0x000019 0xff00ff00};
lappend clist { 0 w 1111 0x00001a 0x0000ffff};
lappend clist { 0 w 1111 0x00001b 0xffff0000};
lappend clist { 0 w 1111 0x00001c 0x0ff00ff0};
lappend clist { 0 w 1111 0x00001d 0xf00ff00f};
lappend clist { 0 w 1111 0x00001e 0x01234567};
lappend clist { 0 w 1111 0x00001f 0x89abcdef};
lappend clist { 0 r 1111 0x000010 0x00000000};
lappend clist { 0 r 1111 0x000011 0xffffffff};
lappend clist { 0 r 1111 0x000012 0x00000000};
lappend clist { 0 r 1111 0x000013 0xa5a5a5a5};
lappend clist { 0 r 1111 0x000014 0x5a5a5a5a};
lappend clist { 0 r 1111 0x000015 0x00000000};
lappend clist { 0 r 1111 0x000016 0x0f0f0f0f};
lappend clist { 0 r 1111 0x000017 0xf0f0f0f0};
lappend clist { 0 r 1111 0x000018 0x00ff00ff};
lappend clist { 0 r 1111 0x000019 0xff00ff00};
lappend clist { 0 r 1111 0x00001a 0x0000ffff};
lappend clist { 0 r 1111 0x00001b 0xffff0000};
lappend clist { 0 r 1111 0x00001c 0x0ff00ff0};
lappend clist { 0 r 1111 0x00001d 0xf00ff00f};
lappend clist { 0 r 1111 0x00001e 0x01234567};
lappend clist { 0 r 1111 0x00001f 0x89abcdef};
## C alternate read sequence of 0-1 transition patterns
lappend clist { 0 r 1111 0x000010 0x00000000};
lappend clist { 0 r 1111 0x000011 0xffffffff};
lappend clist { 0 r 1111 0x00001a 0x0000ffff};
lappend clist { 0 r 1111 0x00001b 0xffff0000};
lappend clist { 0 r 1111 0x000012 0x00000000};
lappend clist { 0 r 1111 0x000013 0xa5a5a5a5};
lappend clist { 0 r 1111 0x000011 0xffffffff};
lappend clist { 0 r 1111 0x000014 0x5a5a5a5a};
lappend clist { 0 r 1111 0x000015 0x00000000};
lappend clist { 0 r 1111 0x000013 0xa5a5a5a5};
lappend clist { 0 r 1111 0x000015 0x00000000};
lappend clist { 0 r 1111 0x000014 0x5a5a5a5a};
lappend clist { 0 r 1111 0x000017 0xf0f0f0f0};
lappend clist { 0 r 1111 0x000016 0x0f0f0f0f};
lappend clist { 0 r 1111 0x000019 0xff00ff00};
lappend clist { 0 r 1111 0x000018 0x00ff00ff};
lappend clist { 0 r 1111 0x00001d 0xf00ff00f};
lappend clist { 0 r 1111 0x00001c 0x0ff00ff0};
lappend clist { 0 r 1111 0x000010 0x00000000};
lappend clist { 0 r 1111 0x00001e 0x01234567};
lappend clist { 0 r 1111 0x00001a 0x0000ffff};
lappend clist { 0 r 1111 0x00001f 0x89abcdef};
lappend clist { 0 r 1111 0x00001b 0xffff0000};
lappend clist { 0 r 1111 0x000012 0x00000000};
lappend clist { 0 r 1111 0x00001f 0x89abcdef};
lappend clist { 0 r 1111 0x000016 0x0f0f0f0f};
lappend clist { 0 r 1111 0x000018 0x00ff00ff};
lappend clist { 0 r 1111 0x000017 0xf0f0f0f0};
lappend clist { 0 r 1111 0x000019 0xff00ff00};
lappend clist { 0 r 1111 0x00001d 0xf00ff00f};
lappend clist { 0 r 1111 0x00001c 0x0ff00ff0};
lappend clist { 0 r 1111 0x00001e 0x01234567};
## C write alternating all-0 and all-1 at low and top addresses
lappend clist { 0 w 1111 0x000020 0x00000000};
lappend clist { 0 w 1111 0x000021 0xffffffff};
lappend clist { 0 w 1111 0x000022 0x00000000};
lappend clist { 0 w 1111 0x000023 0xffffffff};
lappend clist { 0 w 1111 0x000024 0x00000000};
lappend clist { 0 w 1111 0x000025 0xffffffff};
lappend clist { 0 w 1111 0x000026 0x00000000};
lappend clist { 0 w 1111 0x000027 0xffffffff};
lappend clist { 0 w 1111 0x000028 0x00000000};
lappend clist { 0 w 1111 0x03fff9 0xffffffff};
lappend clist { 0 w 1111 0x00002a 0x00000000};
lappend clist { 0 w 1111 0x03fffb 0xffffffff};
lappend clist { 0 w 1111 0x03fffc 0x00000000};
lappend clist { 0 w 1111 0x00002d 0xffffffff};
lappend clist { 0 w 1111 0x03fffe 0x00000000};
lappend clist { 0 w 1111 0x00002f 0xffffffff};
lappend clist { 0 w 1111 0x03fff0 0x00000000};
lappend clist { 0 w 1111 0x03fff1 0xffffffff};
lappend clist { 0 w 1111 0x03fff2 0x00000000};
lappend clist { 0 w 1111 0x03fff3 0xffffffff};
lappend clist { 0 w 1111 0x03fff4 0x00000000};
lappend clist { 0 w 1111 0x03fff5 0xffffffff};
lappend clist { 0 w 1111 0x03fff6 0x00000000};
lappend clist { 0 w 1111 0x03fff7 0xffffffff};
lappend clist { 0 w 1111 0x03fff8 0x00000000};
lappend clist { 0 w 1111 0x000029 0xffffffff};
lappend clist { 0 w 1111 0x03fffa 0x00000000};
lappend clist { 0 w 1111 0x00002b 0xffffffff};
lappend clist { 0 w 1111 0x00002c 0x00000000};
lappend clist { 0 w 1111 0x03fffd 0xffffffff};
lappend clist { 0 w 1111 0x00002e 0x00000000};
lappend clist { 0 w 1111 0x03ffff 0xffffffff};
## C read alternating all-0 and all-1 sequence, only data bounce
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000022 0x00000000};
lappend clist { 0 r 1111 0x000023 0xffffffff};
lappend clist { 0 r 1111 0x000024 0x00000000};
lappend clist { 0 r 1111 0x000025 0xffffffff};
lappend clist { 0 r 1111 0x000026 0x00000000};
lappend clist { 0 r 1111 0x000027 0xffffffff};
lappend clist { 0 r 1111 0x000028 0x00000000};
lappend clist { 0 r 1111 0x000029 0xffffffff};
lappend clist { 0 r 1111 0x00002a 0x00000000};
lappend clist { 0 r 1111 0x00002b 0xffffffff};
lappend clist { 0 r 1111 0x00002c 0x00000000};
lappend clist { 0 r 1111 0x00002d 0xffffffff};
lappend clist { 0 r 1111 0x00002e 0x00000000};
lappend clist { 0 r 1111 0x00002f 0xffffffff};
lappend clist { 0 r 1111 0x03fff0 0x00000000};
lappend clist { 0 r 1111 0x03fff1 0xffffffff};
lappend clist { 0 r 1111 0x03fff2 0x00000000};
lappend clist { 0 r 1111 0x03fff3 0xffffffff};
lappend clist { 0 r 1111 0x03fff4 0x00000000};
lappend clist { 0 r 1111 0x03fff5 0xffffffff};
lappend clist { 0 r 1111 0x03fff6 0x00000000};
lappend clist { 0 r 1111 0x03fff7 0xffffffff};
lappend clist { 0 r 1111 0x03fff8 0x00000000};
lappend clist { 0 r 1111 0x03fff9 0xffffffff};
lappend clist { 0 r 1111 0x03fffa 0x00000000};
lappend clist { 0 r 1111 0x03fffb 0xffffffff};
lappend clist { 0 r 1111 0x03fffc 0x00000000};
lappend clist { 0 r 1111 0x03fffd 0xffffffff};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
## C read alternating all-0 and all-1 sequence, addr and data bounce
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x03fff1 0xffffffff};
lappend clist { 0 r 1111 0x000022 0x00000000};
lappend clist { 0 r 1111 0x03fff3 0xffffffff};
lappend clist { 0 r 1111 0x000024 0x00000000};
lappend clist { 0 r 1111 0x03fff5 0xffffffff};
lappend clist { 0 r 1111 0x000026 0x00000000};
lappend clist { 0 r 1111 0x03fff7 0xffffffff};
lappend clist { 0 r 1111 0x000028 0x00000000};
lappend clist { 0 r 1111 0x000029 0xffffffff};
lappend clist { 0 r 1111 0x03fffa 0x00000000};
lappend clist { 0 r 1111 0x00002b 0xffffffff};
lappend clist { 0 r 1111 0x03fffc 0x00000000};
lappend clist { 0 r 1111 0x00002d 0xffffffff};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x00002f 0xffffffff};
lappend clist { 0 r 1111 0x03fff0 0x00000000};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x03fff2 0x00000000};
lappend clist { 0 r 1111 0x000023 0xffffffff};
lappend clist { 0 r 1111 0x03fff4 0x00000000};
lappend clist { 0 r 1111 0x000025 0xffffffff};
lappend clist { 0 r 1111 0x03fff6 0x00000000};
lappend clist { 0 r 1111 0x000027 0xffffffff};
lappend clist { 0 r 1111 0x03fff8 0x00000000};
lappend clist { 0 r 1111 0x03fff9 0xffffffff};
lappend clist { 0 r 1111 0x00002a 0x00000000};
lappend clist { 0 r 1111 0x03fffb 0xffffffff};
lappend clist { 0 r 1111 0x00002c 0x00000000};
lappend clist { 0 r 1111 0x03fffd 0xffffffff};
lappend clist { 0 r 1111 0x00002e 0x00000000};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
## C write 32 words with single 1 bit (and verify)
lappend clist { 0 w 1111 0x000040 0x00000001};
lappend clist { 0 w 1111 0x000041 0x00000002};
lappend clist { 0 w 1111 0x000042 0x00000004};
lappend clist { 0 w 1111 0x000043 0x00000008};
lappend clist { 0 w 1111 0x000044 0x00000010};
lappend clist { 0 w 1111 0x000045 0x00000020};
lappend clist { 0 w 1111 0x000046 0x00000040};
lappend clist { 0 w 1111 0x000047 0x00000080};
lappend clist { 0 w 1111 0x000048 0x00000100};
lappend clist { 0 w 1111 0x000049 0x00000200};
lappend clist { 0 w 1111 0x00004a 0x00000400};
lappend clist { 0 w 1111 0x00004b 0x00000800};
lappend clist { 0 w 1111 0x00004c 0x00001000};
lappend clist { 0 w 1111 0x00004d 0x00002000};
lappend clist { 0 w 1111 0x00004e 0x00004000};
lappend clist { 0 w 1111 0x00004f 0x00008000};
lappend clist { 0 w 1111 0x000050 0x00010000};
lappend clist { 0 w 1111 0x000051 0x00020000};
lappend clist { 0 w 1111 0x000052 0x00040000};
lappend clist { 0 w 1111 0x000053 0x00080000};
lappend clist { 0 w 1111 0x000054 0x00100000};
lappend clist { 0 w 1111 0x000055 0x00200000};
lappend clist { 0 w 1111 0x000056 0x00400000};
lappend clist { 0 w 1111 0x000057 0x00800000};
lappend clist { 0 w 1111 0x000058 0x01000000};
lappend clist { 0 w 1111 0x000059 0x02000000};
lappend clist { 0 w 1111 0x00005a 0x04000000};
lappend clist { 0 w 1111 0x00005b 0x08000000};
lappend clist { 0 w 1111 0x00005c 0x10000000};
lappend clist { 0 w 1111 0x00005d 0x20000000};
lappend clist { 0 w 1111 0x00005e 0x40000000};
lappend clist { 0 w 1111 0x00005f 0x80000000};
lappend clist { 0 r 1111 0x000040 0x00000001};
lappend clist { 0 r 1111 0x000041 0x00000002};
lappend clist { 0 r 1111 0x000042 0x00000004};
lappend clist { 0 r 1111 0x000043 0x00000008};
lappend clist { 0 r 1111 0x000044 0x00000010};
lappend clist { 0 r 1111 0x000045 0x00000020};
lappend clist { 0 r 1111 0x000046 0x00000040};
lappend clist { 0 r 1111 0x000047 0x00000080};
lappend clist { 0 r 1111 0x000048 0x00000100};
lappend clist { 0 r 1111 0x000049 0x00000200};
lappend clist { 0 r 1111 0x00004a 0x00000400};
lappend clist { 0 r 1111 0x00004b 0x00000800};
lappend clist { 0 r 1111 0x00004c 0x00001000};
lappend clist { 0 r 1111 0x00004d 0x00002000};
lappend clist { 0 r 1111 0x00004e 0x00004000};
lappend clist { 0 r 1111 0x00004f 0x00008000};
lappend clist { 0 r 1111 0x000050 0x00010000};
lappend clist { 0 r 1111 0x000051 0x00020000};
lappend clist { 0 r 1111 0x000052 0x00040000};
lappend clist { 0 r 1111 0x000053 0x00080000};
lappend clist { 0 r 1111 0x000054 0x00100000};
lappend clist { 0 r 1111 0x000055 0x00200000};
lappend clist { 0 r 1111 0x000056 0x00400000};
lappend clist { 0 r 1111 0x000057 0x00800000};
lappend clist { 0 r 1111 0x000058 0x01000000};
lappend clist { 0 r 1111 0x000059 0x02000000};
lappend clist { 0 r 1111 0x00005a 0x04000000};
lappend clist { 0 r 1111 0x00005b 0x08000000};
lappend clist { 0 r 1111 0x00005c 0x10000000};
lappend clist { 0 r 1111 0x00005d 0x20000000};
lappend clist { 0 r 1111 0x00005e 0x40000000};
lappend clist { 0 r 1111 0x00005f 0x80000000};
## C alternating read of 1 bit and all-1 word
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000040 0x00000001};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000041 0x00000002};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000042 0x00000004};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000043 0x00000008};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000044 0x00000010};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000045 0x00000020};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000046 0x00000040};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000047 0x00000080};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000048 0x00000100};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000049 0x00000200};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x00004a 0x00000400};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x00004b 0x00000800};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x00004c 0x00001000};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x00004d 0x00002000};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x00004e 0x00004000};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x00004f 0x00008000};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000050 0x00010000};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000051 0x00020000};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000052 0x00040000};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000053 0x00080000};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000054 0x00100000};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000055 0x00200000};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000056 0x00400000};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000057 0x00800000};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000058 0x01000000};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000059 0x02000000};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x00005a 0x04000000};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x00005b 0x08000000};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x00005c 0x10000000};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x00005d 0x20000000};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x00005e 0x40000000};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x00005f 0x80000000};
## C write 32 words with thermometer code (and verify)
lappend clist { 0 w 1111 0x000060 0x00000001};
lappend clist { 0 w 1111 0x000061 0x00000003};
lappend clist { 0 w 1111 0x000062 0x00000007};
lappend clist { 0 w 1111 0x000063 0x0000000f};
lappend clist { 0 w 1111 0x000064 0x0000001f};
lappend clist { 0 w 1111 0x000065 0x0000003f};
lappend clist { 0 w 1111 0x000066 0x0000007f};
lappend clist { 0 w 1111 0x000067 0x000000ff};
lappend clist { 0 w 1111 0x000068 0x000001ff};
lappend clist { 0 w 1111 0x000069 0x000003ff};
lappend clist { 0 w 1111 0x00006a 0x000007ff};
lappend clist { 0 w 1111 0x00006b 0x00000fff};
lappend clist { 0 w 1111 0x00006c 0x00001fff};
lappend clist { 0 w 1111 0x00006d 0x00003fff};
lappend clist { 0 w 1111 0x00006e 0x00007fff};
lappend clist { 0 w 1111 0x00006f 0x0000ffff};
lappend clist { 0 w 1111 0x000070 0x0001ffff};
lappend clist { 0 w 1111 0x000071 0x0003ffff};
lappend clist { 0 w 1111 0x000072 0x0007ffff};
lappend clist { 0 w 1111 0x000073 0x000fffff};
lappend clist { 0 w 1111 0x000074 0x001fffff};
lappend clist { 0 w 1111 0x000075 0x003fffff};
lappend clist { 0 w 1111 0x000076 0x007fffff};
lappend clist { 0 w 1111 0x000077 0x00ffffff};
lappend clist { 0 w 1111 0x000078 0x01ffffff};
lappend clist { 0 w 1111 0x000079 0x03ffffff};
lappend clist { 0 w 1111 0x00007a 0x07ffffff};
lappend clist { 0 w 1111 0x00007b 0x0fffffff};
lappend clist { 0 w 1111 0x00007c 0x1fffffff};
lappend clist { 0 w 1111 0x00007d 0x3fffffff};
lappend clist { 0 w 1111 0x00007e 0x7fffffff};
lappend clist { 0 w 1111 0x00007f 0xffffffff};
lappend clist { 0 r 1111 0x000060 0x00000001};
lappend clist { 0 r 1111 0x000061 0x00000003};
lappend clist { 0 r 1111 0x000062 0x00000007};
lappend clist { 0 r 1111 0x000063 0x0000000f};
lappend clist { 0 r 1111 0x000064 0x0000001f};
lappend clist { 0 r 1111 0x000065 0x0000003f};
lappend clist { 0 r 1111 0x000066 0x0000007f};
lappend clist { 0 r 1111 0x000067 0x000000ff};
lappend clist { 0 r 1111 0x000068 0x000001ff};
lappend clist { 0 r 1111 0x000069 0x000003ff};
lappend clist { 0 r 1111 0x00006a 0x000007ff};
lappend clist { 0 r 1111 0x00006b 0x00000fff};
lappend clist { 0 r 1111 0x00006c 0x00001fff};
lappend clist { 0 r 1111 0x00006d 0x00003fff};
lappend clist { 0 r 1111 0x00006e 0x00007fff};
lappend clist { 0 r 1111 0x00006f 0x0000ffff};
lappend clist { 0 r 1111 0x000070 0x0001ffff};
lappend clist { 0 r 1111 0x000071 0x0003ffff};
lappend clist { 0 r 1111 0x000072 0x0007ffff};
lappend clist { 0 r 1111 0x000073 0x000fffff};
lappend clist { 0 r 1111 0x000074 0x001fffff};
lappend clist { 0 r 1111 0x000075 0x003fffff};
lappend clist { 0 r 1111 0x000076 0x007fffff};
lappend clist { 0 r 1111 0x000077 0x00ffffff};
lappend clist { 0 r 1111 0x000078 0x01ffffff};
lappend clist { 0 r 1111 0x000079 0x03ffffff};
lappend clist { 0 r 1111 0x00007a 0x07ffffff};
lappend clist { 0 r 1111 0x00007b 0x0fffffff};
lappend clist { 0 r 1111 0x00007c 0x1fffffff};
lappend clist { 0 r 1111 0x00007d 0x3fffffff};
lappend clist { 0 r 1111 0x00007e 0x7fffffff};
lappend clist { 0 r 1111 0x00007f 0xffffffff};
## C alternating read of thermometer code and all-1 word
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000060 0x00000001};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000061 0x00000003};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000062 0x00000007};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000063 0x0000000f};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000064 0x0000001f};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000065 0x0000003f};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000066 0x0000007f};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000067 0x000000ff};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000068 0x000001ff};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000069 0x000003ff};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x00006a 0x000007ff};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x00006b 0x00000fff};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x00006c 0x00001fff};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x00006d 0x00003fff};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x00006e 0x00007fff};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x00006f 0x0000ffff};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000070 0x0001ffff};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000071 0x0003ffff};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000072 0x0007ffff};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000073 0x000fffff};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000074 0x001fffff};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000075 0x003fffff};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000076 0x007fffff};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x000077 0x00ffffff};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000078 0x01ffffff};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x000079 0x03ffffff};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x00007a 0x07ffffff};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x00007b 0x0fffffff};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x00007c 0x1fffffff};
lappend clist { 0 r 1111 0x000021 0xffffffff};
lappend clist { 0 r 1111 0x00007d 0x3fffffff};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x00007e 0x7fffffff};
lappend clist { 0 r 1111 0x03ffff 0xffffffff};
lappend clist { 0 r 1111 0x00007f 0xffffffff};
## C alternating read of thermometer code and all-0 word
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x000060 0x00000001};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x000061 0x00000003};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x000062 0x00000007};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x000063 0x0000000f};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x000064 0x0000001f};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x000065 0x0000003f};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x000066 0x0000007f};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x000067 0x000000ff};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x000068 0x000001ff};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x000069 0x000003ff};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x00006a 0x000007ff};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x00006b 0x00000fff};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x00006c 0x00001fff};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x00006d 0x00003fff};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x00006e 0x00007fff};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x00006f 0x0000ffff};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x000070 0x0001ffff};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x000071 0x0003ffff};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x000072 0x0007ffff};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x000073 0x000fffff};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x000074 0x001fffff};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x000075 0x003fffff};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x000076 0x007fffff};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x000077 0x00ffffff};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x000078 0x01ffffff};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x000079 0x03ffffff};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x00007a 0x07ffffff};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x00007b 0x0fffffff};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x00007c 0x1fffffff};
lappend clist { 0 r 1111 0x000020 0x00000000};
lappend clist { 0 r 1111 0x00007d 0x3fffffff};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x00007e 0x7fffffff};
lappend clist { 0 r 1111 0x03fffe 0x00000000};
lappend clist { 0 r 1111 0x00007f 0xffffffff};
## # random sequence generated with gen_tst_sram_ranseq 64
## C now do some write/read tests with random addr/data
## C 16 writes
lappend clist { 0 w 1111 0x0039dc 0x96d0e73e};
lappend clist { 0 w 1111 0x006d4a 0xbbbb4372};
lappend clist { 0 w 1111 0x0092b6 0xf58ace40};
lappend clist { 0 w 1111 0x01393e 0xeb748a98};
lappend clist { 0 w 1111 0x019b4c 0x69281826};
lappend clist { 0 w 1111 0x02a8ba 0xdae538d7};
lappend clist { 0 w 1111 0x00341a 0x8f42ffbd};
lappend clist { 0 w 1111 0x01b18a 0x5b523e97};
lappend clist { 0 w 1111 0x039bb7 0x46eea237};
lappend clist { 0 w 1111 0x03f294 0x8824fcef};
lappend clist { 0 w 1111 0x036375 0xd1c10ba8};
lappend clist { 0 w 1111 0x0067f6 0xfc93d1dc};
lappend clist { 0 w 1111 0x01242e 0x1316562d};
lappend clist { 0 w 1111 0x00a090 0x0779b757};
lappend clist { 0 w 1111 0x01aebe 0xe06ae43f};
lappend clist { 0 w 1111 0x019109 0xf558ccb4};
## C 16 writes and 16 reads mixed
lappend clist { 0 w 1111 0x03c4a6 0x96dbbcff};
lappend clist { 0 r 1111 0x0039dc 0x96d0e73e};
lappend clist { 0 w 1111 0x016ea6 0x14010c8f};
lappend clist { 0 r 1111 0x006d4a 0xbbbb4372};
lappend clist { 0 r 1111 0x0092b6 0xf58ace40};
lappend clist { 0 w 1111 0x037728 0xe4b4e052};
lappend clist { 0 w 1111 0x0265d5 0x9d612c95};
lappend clist { 0 r 1111 0x01393e 0xeb748a98};
lappend clist { 0 w 1111 0x017b76 0xfe2576be};
lappend clist { 0 r 1111 0x019b4c 0x69281826};
lappend clist { 0 w 1111 0x0172cc 0x4f67af1f};
lappend clist { 0 w 1111 0x005b4b 0x8f7e559d};
lappend clist { 0 w 1111 0x019341 0xa829717d};
lappend clist { 0 r 1111 0x02a8ba 0xdae538d7};
lappend clist { 0 r 1111 0x00341a 0x8f42ffbd};
lappend clist { 0 r 1111 0x01b18a 0x5b523e97};
lappend clist { 0 w 1111 0x034de2 0xd53f120f};
lappend clist { 0 r 1111 0x039bb7 0x46eea237};
lappend clist { 0 w 1111 0x02119e 0x6253f647};
lappend clist { 0 r 1111 0x03f294 0x8824fcef};
lappend clist { 0 w 1111 0x00f1ac 0x936c2522};
lappend clist { 0 r 1111 0x036375 0xd1c10ba8};
lappend clist { 0 w 1111 0x00716b 0x2db9e1fa};
lappend clist { 0 r 1111 0x0067f6 0xfc93d1dc};
lappend clist { 0 w 1111 0x01781f 0xae31b1e7};
lappend clist { 0 r 1111 0x01242e 0x1316562d};
lappend clist { 0 w 1111 0x0187bf 0xccdbf8e7};
lappend clist { 0 w 1111 0x029b82 0x95274e53};
lappend clist { 0 r 1111 0x00a090 0x0779b757};
lappend clist { 0 r 1111 0x01aebe 0xe06ae43f};
lappend clist { 0 w 1111 0x0244c7 0x5fd2ee97};
lappend clist { 0 r 1111 0x019109 0xf558ccb4};
## C 16 writes and 16 reads mixed, with waits
lappend clist { 0 w 1111 0x0239b6 0x8f147909};
lappend clist { 1 r 1111 0x03c4a6 0x96dbbcff};
lappend clist { 0 w 1111 0x03b485 0x9f2c58f4};
lappend clist { 2 r 1111 0x016ea6 0x14010c8f};
lappend clist { 0 w 1111 0x01e384 0xde6a4ad3};
lappend clist { 0 r 1111 0x037728 0xe4b4e052};
lappend clist { 1 w 1111 0x00abc1 0x4a3aafbe};
lappend clist { 0 r 1111 0x0265d5 0x9d612c95};
lappend clist { 2 w 1111 0x03cbb0 0x0adff6f0};
lappend clist { 0 r 1111 0x017b76 0xfe2576be};
lappend clist { 2 r 1111 0x0172cc 0x4f67af1f};
lappend clist { 0 w 1111 0x0128cc 0x94959a76};
lappend clist { 1 r 1111 0x005b4b 0x8f7e559d};
lappend clist { 0 r 1111 0x019341 0xa829717d};
lappend clist { 2 w 1111 0x029a71 0xad031981};
lappend clist { 0 r 1111 0x034de2 0xd53f120f};
lappend clist { 3 r 1111 0x02119e 0x6253f647};
lappend clist { 0 w 1111 0x004b60 0xcb3cfc9a};
lappend clist { 1 r 1111 0x00f1ac 0x936c2522};
lappend clist { 0 w 1111 0x03dc56 0x1bd4948d};
lappend clist { 2 w 1111 0x01a28a 0x9b8c1f3d};
lappend clist { 0 r 1111 0x00716b 0x2db9e1fa};
lappend clist { 3 w 1111 0x037682 0x4f8e2aca};
lappend clist { 0 w 1111 0x00d920 0xb6f4fdfc};
lappend clist { 1 r 1111 0x01781f 0xae31b1e7};
lappend clist { 0 w 1111 0x024aed 0x289e121a};
lappend clist { 2 w 1111 0x037d2d 0x43b8b430};
lappend clist { 0 r 1111 0x0187bf 0xccdbf8e7};
lappend clist { 3 w 1111 0x008798 0x19a1600a};
lappend clist { 0 w 1111 0x02eb94 0xda68509a};
lappend clist { 1 r 1111 0x029b82 0x95274e53};
lappend clist { 2 r 1111 0x0244c7 0x5fd2ee97};
## C finally 16 reads
lappend clist { 0 r 1111 0x0239b6 0x8f147909};
lappend clist { 0 r 1111 0x03b485 0x9f2c58f4};
lappend clist { 0 r 1111 0x01e384 0xde6a4ad3};
lappend clist { 0 r 1111 0x00abc1 0x4a3aafbe};
lappend clist { 0 r 1111 0x03cbb0 0x0adff6f0};
lappend clist { 0 r 1111 0x0128cc 0x94959a76};
lappend clist { 0 r 1111 0x029a71 0xad031981};
lappend clist { 0 r 1111 0x004b60 0xcb3cfc9a};
lappend clist { 0 r 1111 0x03dc56 0x1bd4948d};
lappend clist { 0 r 1111 0x01a28a 0x9b8c1f3d};
lappend clist { 0 r 1111 0x037682 0x4f8e2aca};
lappend clist { 0 r 1111 0x00d920 0xb6f4fdfc};
lappend clist { 0 r 1111 0x024aed 0x289e121a};
lappend clist { 0 r 1111 0x037d2d 0x43b8b430};
lappend clist { 0 r 1111 0x008798 0x19a1600a};
lappend clist { 0 r 1111 0x02eb94 0xda68509a};
 
return $clist
}
}
/trunk/tools/tcl/tst_sram/test_seq.tcl
0,0 → 1,634
# $Id: test_seq.tcl 785 2016-07-10 12:22:41Z mueller $
#
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 2, or at your option any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
# Revision History:
# Date Rev Version Comment
# 2016-07-10 785 1.1 add wswap and wloop tests
# 2016-07-09 784 1.0 Initial version (ported from tb_tst_sram_stim.dat)
#
 
package provide tst_sram 1.0
 
package require rutiltpp
package require rutil
package require rlink
 
namespace eval tst_sram {
#
# test_seq_srum: helper: run sequencer and check status
#
proc test_seq_srun {{sstat 0} {tout 10.} {seaddr 0} {sedath 0} {sedatl 0}} {
variable nscmd
if {$nscmd == 0} {error "no or empty scmd list loaded"}
#
# set slim, sstat and start sequencer
rlc exec \
-wreg sr.slim [expr {$nscmd-1}] \
-wreg sr.sstat $sstat \
-wreg sr.sstart 0
# wait for completion
rlc wtlam $tout
# harvest attn and check sequencer status
# also check rlink command status (RB_STAT(1) <= R_REGS.sfail)
set seqmsk [rutil::com16 [regbld tst_sram::SSTAT wide]]; # ign sstat.wide !
set stamsk [regbld rlink::STAT {stat -1} rbtout rbnak rberr];
 
if {$seaddr == 0} { # fail=0 --> check saddr
rlc exec \
-attn -edata 0x0001 \
-rreg sr.sstat -edata $sstat $seqmsk -estat 0 $stamsk \
-rreg sr.saddr -edata $nscmd -estat 0 $stamsk
} else { # fail=1 --> check seaddr
set sstat_exp [expr {$sstat | [regbld tst_sram::SSTAT fail]}]
set stabad [regbld rlink::STAT {stat 2}]; # expect status.stat = 0x2
rlc exec \
-attn -edata 0x0001 \
-rreg sr.sstat -edata $sstat_exp $seqmsk -estat $stabad $stamsk \
-rreg sr.seaddr -edata $seaddr -estat $stabad $stamsk \
-rreg sr.sedath -edata $sedath -estat $stabad $stamsk \
-rreg sr.sedatl -edata $sedatl -estat $stabad $stamsk
}
return ""
}
 
#
# test_seq_setxor: helper: setup maddr* and mdi*
#
proc test_seq_setxor {maddrh maddrl mdih mdil} {
rlc exec \
-wreg sr.maddrh $maddrh \
-wreg sr.maddrl $maddrl \
-wreg sr.mdih $mdih \
-wreg sr.mdil $mdil
}
 
#
# test_seq: Test sequencer, basic 18 bit mode
#
proc test_seq {{tout 10.}} {
variable nscmd
#
set errcnt 0
rlc errcnt -clear
set sm [rutil::com16 [regbld tst_sram::SSTAT wide]]
 
rlink::anena 1; # enable attn notify
 
#
rlc log "tst_sram::test_seq ----------------------------------------------"
#
#-------------------------------------------------------------------------
rlc log " test 1: list of write commands"
# load list of 8 mem write commands
set clist {}
lappend clist { 0 w 1111 0x000110 0x70605040};
lappend clist { 0 w 1111 0x000111 0x71615141};
lappend clist { 0 w 1111 0x000112 0x72625242};
lappend clist { 0 w 1111 0x000113 0x73635343};
lappend clist { 0 w 1111 0x000114 0x74645444};
lappend clist { 0 w 1111 0x000115 0x75655545};
lappend clist { 0 w 1111 0x000116 0x76665646};
lappend clist { 0 w 1111 0x000117 0x77675747};
scmd_write $clist
 
# run sequencer (plain xord=0 xora=0 veri=0)
test_seq_srun 0 $tout
# read back 8 longwords
rlc exec \
-wreg sr.maddrh 0x0000 \
-wreg sr.maddrl 0x0110 \
-wblk sr.mblk {0x7060 0x5040 \
0x7161 0x5141 \
0x7262 0x5242 \
0x7363 0x5343 \
0x7464 0x5444 \
0x7565 0x5545 \
0x7666 0x5646 \
0x7767 0x5747}
#
#-------------------------------------------------------------------------
rlc log " test 2: list of read commands"
# load list of 8 mem read commands
set clist {}
lappend clist { 0 r 1111 0x000110 0xdead0000};
lappend clist { 0 r 1111 0x000111 0xbeaf1111};
lappend clist { 0 r 1111 0x000112 0xdead2222};
lappend clist { 0 r 1111 0x000113 0xbeaf3333};
lappend clist { 0 r 1111 0x000114 0xdead4444};
lappend clist { 0 r 1111 0x000115 0xbeaf5555};
lappend clist { 0 r 1111 0x000116 0xdead6666};
lappend clist { 0 r 1111 0x000117 0xbeaf7777};
scmd_write $clist
 
# run sequencer (plain xord=0 xora=0 veri=0)
test_seq_srun 0 $tout
# read back data part of sequencer
rlc exec \
-wreg sr.saddr 0x0000 \
-rblk sr.sblkd 16 -edata {0x7060 0x5040
0x7161 0x5141 \
0x7262 0x5242 \
0x7363 0x5343 \
0x7464 0x5444 \
0x7565 0x5545 \
0x7666 0x5646 \
0x7767 0x5747}
#
#-------------------------------------------------------------------------
rlc log " test 3: mixed list of writes (some byte wise) and reads"
# this list modifies the memory left from previous test !
set clist {}
lappend clist { 0 w 0001 0x000112 0x00000082}; # wr 12 0001
lappend clist { 0 w 0010 0x000113 0x00009300}; # wr 13 0010
lappend clist { 0 r 1111 0x000110 0x00000000}; # rd 10
lappend clist { 0 w 0100 0x000114 0x00a40000}; # wr 14 0100
lappend clist { 0 r 1111 0x000111 0x00000000}; # rd 11
lappend clist { 0 w 1000 0x000115 0xb5000000}; # wr 15 1000
lappend clist { 0 r 1111 0x000112 0x00000000}; # rd 12
lappend clist { 0 r 1111 0x000113 0x00000000}; # rd 13
lappend clist { 0 w 1111 0x000118 0x78685848}; # wr 18
lappend clist { 0 r 1111 0x000114 0x00000000}; # rd 14
lappend clist { 0 w 1111 0x000119 0x79695949}; # wr 19
lappend clist { 0 w 1111 0x00011a 0x7a6a5a4a}; # wr 1a
lappend clist { 0 r 1111 0x000115 0x00000000}; # rd 15
lappend clist { 0 w 1111 0x00011b 0x7b6b5b4b}; # wr 1b
lappend clist { 0 r 1111 0x000116 0x00000000}; # rd 16
lappend clist { 0 w 1111 0x00011c 0x7c6c5c4c}; # wr 1c
lappend clist { 0 w 1111 0x00011d 0x7d6d5d4d}; # wr 1d
lappend clist { 0 r 1111 0x000117 0x00000000}; # rd 17
lappend clist { 0 r 1111 0x000118 0x00000000}; # rd 18
lappend clist { 0 w 1111 0x00011e 0x7e6e5e4e}; # wr 1e
lappend clist { 0 w 1111 0x00011f 0x7f6f5f4f}; # wr 1f
lappend clist { 0 r 1111 0x000119 0x00000000}; # rd 19
lappend clist { 0 r 1111 0x00011a 0x00000000}; # rd 1a
lappend clist { 0 r 1111 0x00011b 0x00000000}; # rd 1b
lappend clist { 0 r 1111 0x00011c 0x00000000}; # rd 1c
lappend clist { 0 r 1111 0x00011d 0x00000000}; # rd 1d
lappend clist { 0 r 1111 0x00011e 0x00000000}; # rd 1e
lappend clist { 0 r 1111 0x00011f 0x00000000}; # rd 1f
scmd_write $clist
 
# run sequencer (plain xord=0 xora=0 veri=0)
test_seq_srun 0 $tout
# read back data part of sequencer
rlc exec \
-wreg sr.saddr 0x0000 \
-rblk sr.sblkd 56 -edata {0x0000 0x0082 \
0x0000 0x9300 \
0x7060 0x5040 \
0x00a4 0x0000 \
0x7161 0x5141 \
0xb500 0x0000 \
0x7262 0x5282 \
0x7363 0x9343 \
0x7868 0x5848 \
0x74a4 0x5444 \
0x7969 0x5949 \
0x7a6a 0x5a4a \
0xb565 0x5545 \
0x7b6b 0x5b4b \
0x7666 0x5646 \
0x7c6c 0x5c4c \
0x7d6d 0x5d4d \
0x7767 0x5747 \
0x7868 0x5848 \
0x7e6e 0x5e4e \
0x7f6f 0x5f4f \
0x7969 0x5949 \
0x7a6a 0x5a4a \
0x7b6b 0x5b4b \
0x7c6c 0x5c4c \
0x7d6d 0x5d4d \
0x7e6e 0x5e4e \
0x7f6f 0x5f4f}
 
#
#-------------------------------------------------------------------------
rlc log " test 4: sequencer verify mode"
# list of 4 mem write and 4 read commands
set clist {}
lappend clist { 0 w 1111 0x000220 0xb0a09080};
lappend clist { 0 w 1111 0x000221 0xb1a19181};
lappend clist { 0 r 1111 0x000220 0xb0a09080};
lappend clist { 0 w 1111 0x000222 0xb2a29282};
lappend clist { 0 r 1111 0x000221 0xb1a19181};
lappend clist { 0 w 1111 0x000223 0xb3a39383};
lappend clist { 0 r 1111 0x000222 0xb2a29282};
lappend clist { 0 r 1111 0x000223 0xb3a39383};
scmd_write $clist
 
# run sequencer (veri=1)
test_seq_srun [regbld tst_sram::SSTAT veri] $tout
 
# again, but with mismatch on 2nd read
set clist {}
lappend clist { 0 w 1111 0x000230 0xb0a09080}; # 0
lappend clist { 0 w 1111 0x000231 0xb1a19181}; # 1
lappend clist { 0 r 1111 0x000230 0xb0a09080}; # 2
lappend clist { 0 w 1111 0x000232 0xb2a29282}; # 3
lappend clist { 0 r 1111 0x000231 0x00000000}; # 4 <-- read mismatch here
lappend clist { 0 w 1111 0x000233 0xb3a39383}; # 5
lappend clist { 0 r 1111 0x000232 0xb2a29282}; # 6
lappend clist { 0 r 1111 0x000233 0xb3a39383}; # 7
scmd_write $clist
 
# run sequencer (veri=1, expect fail)
test_seq_srun [regbld tst_sram::SSTAT veri] $tout 4 0xb1a1 0x9181
 
# sblkd re-read data, check that data part wasn't overwritten
rlc exec \
-wreg sr.saddr 0 \
-rblk sr.sblkd 16 -edata {0xb0a0 0x9080 \
0xb1a1 0x9181 \
0xb0a0 0x9080 \
0xb2a2 0x9282 \
0x0000 0x0000 \
0xb3a3 0x9383 \
0xb2a2 0x9282 \
0xb3a3 0x9383}
#
#-------------------------------------------------------------------------
rlc log " test 5: test reset via init"
# expects state from fail srun of previous test with
# seaddr=0x0004 sedath=0xb1a1 sedatl=0x9181
# re-check fail bit status bit set from previous test
rlc exec \
-rreg sr.sstat -edata [regbld tst_sram::SSTAT veri fail] $sm \
-rreg sr.seaddr -edata 0x0004 \
-rreg sr.sedath -edata 0xb1a1 \
-rreg sr.sedatl -edata 0x9181
# init 0x0 --> noop
rlc exec \
-init sr.mdih 0x0000 \
-rreg sr.sstat -edata [regbld tst_sram::SSTAT veri fail] $sm \
-rreg sr.seaddr -edata 0x0004 \
-rreg sr.sedath -edata 0xb1a1 \
-rreg sr.sedatl -edata 0x9181
# init 0x2 --> reset MEM, no effect on SEQ state
rlc exec \
-init sr.mdih 0x0002 \
-rreg sr.sstat -edata [regbld tst_sram::SSTAT veri fail] $sm \
-rreg sr.seaddr -edata 0x0004 \
-rreg sr.sedath -edata 0xb1a1 \
-rreg sr.sedatl -edata 0x9181
# init 0x1 --> reset SEQ, add registers cleared
rlc exec \
-init sr.mdih 0x0001 \
-rreg sr.sstat -edata 0 $sm \
-rreg sr.seaddr -edata 0 \
-rreg sr.sedath -edata 0 \
-rreg sr.sedatl -edata 0
#
#-------------------------------------------------------------------------
rlc log " test 6: xord and xora options"
# list of 4 mem write and 4 read commands
set clist {}
lappend clist { 0 w 1111 0x000440 0xc0b0a090};
lappend clist { 0 w 1111 0x000441 0xc1b1a191};
lappend clist { 0 r 1111 0x000440 0xc0b0a090};
lappend clist { 0 w 1111 0x000442 0xc2b2a292};
lappend clist { 0 r 1111 0x000441 0xc1b1a191};
lappend clist { 0 w 1111 0x000443 0xc3b3a393};
lappend clist { 0 r 1111 0x000442 0xc2b2a292};
lappend clist { 0 r 1111 0x000443 0xc3b3a393};
scmd_write $clist
 
# run sequencer (xord=1,xora=1,veri=1) and maddr=0 mdi=0
test_seq_setxor 0x00 0x0000 0x0000 0x0000
test_seq_srun [regbld tst_sram::SSTAT xord xora veri] $tout
 
# read and check mem data (in 440...443, data as in smem)
rlc exec \
-wreg sr.maddrh 0x0000 \
-wreg sr.maddrl 0x0440 \
-rblk sr.mblk 8 -edata {0xc0b0 0xa090 \
0xc1b1 0xa191 \
0xc2b2 0xa292 \
0xc3b3 0xa393}
 
# start sequencer with xord=1 and mdi=f0f0f0f0
# now 9=1001 <-> 6=0110
# now a=1010 <-> 5=0101
# now b=1011 <-> 4=0100
# now c=1100 <-> 3=0011
test_seq_setxor 0x00 0x0000 0xf0f0 0xf0f0
test_seq_srun [regbld tst_sram::SSTAT xord veri] $tout
# read and check mem data (in 440...443, now xord'ed)
rlc exec \
-wreg sr.maddrh 0x0000 \
-wreg sr.maddrl 0x0440 \
-rblk sr.mblk 8 -edata {0x3040 0x5060 \
0x3141 0x5161 \
0x3242 0x5262 \
0x3343 0x5363}
 
# start sequencer with xord=1 and mdi=0f0f0f0f
# now 0=0000 -> f=1111
# now 1=0001 -> e=1110
# now 2=0010 -> d=1101
# now 3=0011 -> c=1100
test_seq_setxor 0x00 0x0000 0x0f0f 0x0f0f
test_seq_srun [regbld tst_sram::SSTAT xord veri] $tout
rlc exec \
-wreg sr.maddrh 0x0000 \
-wreg sr.maddrl 0x0440 \
-rblk sr.mblk 8 -edata {0xcfbf 0xaf9f \
0xcebe 0xae9e \
0xcdbd 0xad9d \
0xccbc 0xac9c}
 
# start sequencer with xora=1 and maddr=1000
test_seq_setxor 0x00 0x1000 0x0000 0x0000
test_seq_srun [regbld tst_sram::SSTAT xora veri] $tout
# read and check mem data (in 1440...1443, data as in smem)
rlc exec \
-wreg sr.maddrh 0x0000 \
-wreg sr.maddrl 0x1440 \
-rblk sr.mblk 8 -edata {0xc0b0 0xa090 \
0xc1b1 0xa191 \
0xc2b2 0xa292 \
0xc3b3 0xa393}
 
# start sequencer with xord=1,xora=1 and maddr=2000,mdi=f0f0f0f0
test_seq_setxor 0x00 0x2000 0xf0f0 0xf0f0
test_seq_srun [regbld tst_sram::SSTAT xord xora veri] $tout
# read and check mem data (in 2440...2443, data xord'ed)
rlc exec \
-wreg sr.maddrh 0x0000 \
-wreg sr.maddrl 0x2440 \
-rblk sr.mblk 8 -edata {0x3040 0x5060 \
0x3141 0x5161 \
0x3242 0x5262 \
0x3343 0x5363}
 
# finally check, that sedat hold pure mem data
# list of 4 mem write and 4 read commands
set clist {}
lappend clist { 0 w 1111 0x000550 0xc0b0a090};
lappend clist { 0 w 1111 0x000551 0xc1b1a191};
lappend clist { 0 w 1111 0x000552 0xc2b2a292};
lappend clist { 0 w 1111 0x000553 0xc3b3a393};
lappend clist { 0 r 1111 0x000550 0x00000000}; # add read deta wrong
lappend clist { 0 r 1111 0x000551 0x00000000};
lappend clist { 0 r 1111 0x000552 0x00000000};
lappend clist { 0 r 1111 0x000553 0x00000000};
scmd_write $clist
 
# start sequencer with xord=1,xora=1 and maddr=4000,mdi=f0f0f0f0
# check that data in sedat is xor'ed !!
test_seq_setxor 0x00 0x4000 0xf0f0 0xf0f0
test_seq_srun [regbld tst_sram::SSTAT xord xora veri] $tout \
4 0x3040 0x5060
# read and check mem data (in 4550...4553, data xord'ed)
rlc exec \
-wreg sr.maddrh 0x0000 \
-wreg sr.maddrl 0x4550 \
-rblk sr.mblk 8 -edata {0x3040 0x5060 \
0x3141 0x5161 \
0x3242 0x5262 \
0x3343 0x5363}
 
# finally clear veri error
rlc exec -init sr.mdih 0x1; # reset SEQ
#
#-------------------------------------------------------------------------
rlc log " test 7: loop option (with xora)"
# list of 4 mem write and 4 read commands
set clist {}
lappend clist { 0 w 1111 0x000000 0x00102030};
lappend clist { 0 w 1111 0x000001 0x01112131};
lappend clist { 0 r 1111 0x000000 0x00102030};
lappend clist { 0 w 1111 0x000002 0x02122232};
lappend clist { 0 r 1111 0x000001 0x01112131};
lappend clist { 0 w 1111 0x000003 0x03132333};
lappend clist { 0 r 1111 0x000002 0x02122232};
lappend clist { 0 r 1111 0x000003 0x03132333};
scmd_write $clist
 
# start sequencer with loop=1,xora=1 and maddr=3fff0 (will loop to 3ffff)
test_seq_setxor 0x03 0xfff0 0x0000 0x0000
test_seq_srun [regbld tst_sram::SSTAT loop xora veri] $tout
# check that maddr incremented
rlc exec \
-rreg sr.maddrh -edata 0x0003 \
-rreg sr.maddrl -edata 0xffff
# last iteration will write into
# 00000 xor 03ffff -> 03ffff (00102030)
# 00001 xor 03ffff -> 03fffe (01112131)
# 00002 xor 03ffff -> 03fffd (02122232)
# 00003 xor 03ffff -> 03fffc (03132333)
# read back 4 longwords 03fffc..03ffff
rlc exec \
-wreg sr.maddrh 0x0003 \
-wreg sr.maddrl 0xfffc \
-rblk sr.mblk 8 -edata {0x0313 0x2333 \
0x0212 0x2232 \
0x0111 0x2131 \
0x0010 0x2030}
 
#
#-------------------------------------------------------------------------
rlc log " test 8: loop option (with xora), verify fail case"
# list of 4 mem write and 4 read commands, 2nd read will fail
set clist {}
lappend clist { 0 w 1111 0x000100 0x00102030};
lappend clist { 0 w 1111 0x000101 0x01112131};
lappend clist { 0 w 1111 0x000102 0x02122232};
lappend clist { 0 w 1111 0x000103 0x03132333};
lappend clist { 0 r 1111 0x000100 0x00102030};
lappend clist { 0 r 1111 0x000101 0x00000000}; # <-- will fail
lappend clist { 0 r 1111 0x000102 0x00000000};
lappend clist { 0 r 1111 0x000103 0x00000000};
scmd_write $clist
 
# start with loop=1,xora=1 and maddr=03fff0 (tried to loop to 03ffff)
test_seq_setxor 0x03 0xfff0 0x0000 0x0000
test_seq_srun [regbld tst_sram::SSTAT loop xora veri] $tout \
5 0x0111 0x2131
# check that maddr do not increment (fail on first loop !)
rlc exec \
-rreg sr.maddrh -edata 0x0003 \
-rreg sr.maddrl -edata 0xfff0
 
# finally clear veri error
rlc exec -init sr.mdih 0x1; # reset SEQ
#
#-------------------------------------------------------------------------
rlc log " test 9: wait field in sequencer"
# list of 16 writes and 16 reads, with increasing waits
set clist {}
lappend clist { 0x0 w 1111 0x000110 0x20001000}; # writes
lappend clist { 0x1 w 1111 0x000111 0x20011001};
lappend clist { 0x2 w 1111 0x000112 0x20021002};
lappend clist { 0x3 w 1111 0x000113 0x20031003};
lappend clist { 0x4 w 1111 0x000114 0x20041004};
lappend clist { 0x5 w 1111 0x000115 0x20051005};
lappend clist { 0x6 w 1111 0x000116 0x20061006};
lappend clist { 0x7 w 1111 0x000117 0x20071007};
lappend clist { 0x8 w 1111 0x000118 0x20081008};
lappend clist { 0x9 w 1111 0x000119 0x20091009};
lappend clist { 0xa w 1111 0x00011a 0x200a100a};
lappend clist { 0xb w 1111 0x00011b 0x200b100b};
lappend clist { 0xc w 1111 0x00011c 0x200c100c};
lappend clist { 0xd w 1111 0x00011d 0x200d100d};
lappend clist { 0xe w 1111 0x00011e 0x200e100e};
lappend clist { 0xf w 1111 0x00011f 0x200f100f};
lappend clist { 0x0 r 1111 0x000110 0x20001000}; # read
lappend clist { 0x1 r 1111 0x000111 0x20011001};
lappend clist { 0x2 r 1111 0x000112 0x20021002};
lappend clist { 0x3 r 1111 0x000113 0x20031003};
lappend clist { 0x4 r 1111 0x000114 0x20041004};
lappend clist { 0x5 r 1111 0x000115 0x20051005};
lappend clist { 0x6 r 1111 0x000116 0x20061006};
lappend clist { 0x7 r 1111 0x000117 0x20071007};
lappend clist { 0x8 r 1111 0x000118 0x20081008};
lappend clist { 0x9 r 1111 0x000119 0x20091009};
lappend clist { 0xa r 1111 0x00011a 0x200a100a};
lappend clist { 0xb r 1111 0x00011b 0x200b100b};
lappend clist { 0xc r 1111 0x00011c 0x200c100c};
lappend clist { 0xd r 1111 0x00011d 0x200d100d};
lappend clist { 0xe r 1111 0x00011e 0x200e100e};
lappend clist { 0xf r 1111 0x00011f 0x200f100f};
scmd_write $clist
 
# start sequencer with xora=1 and maddr=11000
test_seq_setxor 0x01 0x1000 0x0000 0x0000
test_seq_srun [regbld tst_sram::SSTAT xora veri] $tout
 
# list of groups of 2 write / 2 read, with increasing wait
set clist {}
lappend clist { 0x0 w 1111 0x000120 0x30002000}; # write
lappend clist { 0x0 w 1111 0x000121 0x30012001};
lappend clist { 0x0 r 1111 0x000120 0x30002000}; # read
lappend clist { 0x0 r 1111 0x000121 0x30012001};
lappend clist { 0x1 w 1111 0x000122 0x30022002}; # write
lappend clist { 0x1 w 1111 0x000123 0x30032003};
lappend clist { 0x1 r 1111 0x000122 0x30022002}; # read
lappend clist { 0x1 r 1111 0x000123 0x30032003};
lappend clist { 0x2 w 1111 0x000124 0x30042004}; # write
lappend clist { 0x2 w 1111 0x000125 0x30052005};
lappend clist { 0x2 r 1111 0x000124 0x30042004}; # read
lappend clist { 0x2 r 1111 0x000125 0x30052005};
lappend clist { 0x3 w 1111 0x000126 0x30062006}; # write
lappend clist { 0x3 w 1111 0x000127 0x30072007};
lappend clist { 0x3 r 1111 0x000126 0x30062006}; # read
lappend clist { 0x3 r 1111 0x000127 0x30072007};
lappend clist { 0x4 w 1111 0x000128 0x30082008}; # write
lappend clist { 0x4 w 1111 0x000129 0x30092009};
lappend clist { 0x4 r 1111 0x000128 0x30082008}; # read
lappend clist { 0x4 r 1111 0x000129 0x30092009};
lappend clist { 0x5 w 1111 0x00012a 0x300a200a}; # write
lappend clist { 0x5 w 1111 0x00012b 0x300b200b};
lappend clist { 0x5 r 1111 0x00012a 0x300a200a}; # read
lappend clist { 0x5 r 1111 0x00012b 0x300b200b};
lappend clist { 0x6 w 1111 0x00012c 0x300c200c}; # write
lappend clist { 0x6 w 1111 0x00012d 0x300d200d};
lappend clist { 0x6 r 1111 0x00012c 0x300c200c}; # read
lappend clist { 0x6 r 1111 0x00012d 0x300d200d};
lappend clist { 0x7 w 1111 0x00012e 0x300e200e}; # write
lappend clist { 0x7 w 1111 0x00012f 0x300f200f};
lappend clist { 0x7 r 1111 0x00012e 0x300e200e}; # read
lappend clist { 0x7 r 1111 0x00012f 0x300f200f};
scmd_write $clist
 
# start sequencer with xora=1 and maddr=22000
test_seq_setxor 0x02 0x2000 0x0000 0x0000
test_seq_srun [regbld tst_sram::SSTAT xora veri] $tout
 
#
#-------------------------------------------------------------------------
if {[iswide]} {
rlc log " test 10: wswap option"
# write with sequencer
# list of writes, top 2 bits of seq address change; do read back
set clist {}
lappend clist { 0x0 w 1111 0x000000 0x12340000}; # -> 0x001000
lappend clist { 0x0 w 1111 0x010011 0x12340011}; # -> 0x101011
lappend clist { 0x0 w 1111 0x020022 0x12340022}; # -> 0x201022
lappend clist { 0x0 w 1111 0x030033 0x12340033}; # -> 0x301033
lappend clist { 0x0 r 1111 0x000000 0x12340000}; # <- 0x001000
lappend clist { 0x0 r 1111 0x010011 0x12340011}; # <- 0x101011
lappend clist { 0x0 r 1111 0x020022 0x12340022}; # <- 0x201022
lappend clist { 0x0 r 1111 0x030033 0x12340033}; # <- 0x301033
scmd_write $clist
 
# start sequencer with xora=1 and maddr=001000
test_seq_setxor 0x00 0x1000 0x0000 0x0000
test_seq_srun [regbld tst_sram::SSTAT wswap xora veri] $tout
 
# check memory via mcmd reads
rlc exec \
-wreg sr.maddrl 0x1000 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld {be 0xf} {addrh 0x00}] \
-rreg sr.mdoh -edata 0x1234 \
-rreg sr.mdol -edata 0x0000 \
-wreg sr.maddrl 0x1011 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld {be 0xf} {addrh 0x10}] \
-rreg sr.mdoh -edata 0x1234 \
-rreg sr.mdol -edata 0x0011 \
-wreg sr.maddrl 0x1022 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld {be 0xf} {addrh 0x20}] \
-rreg sr.mdoh -edata 0x1234 \
-rreg sr.mdol -edata 0x0022 \
-wreg sr.maddrl 0x1033 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld {be 0xf} {addrh 0x30}] \
-rreg sr.mdoh -edata 0x1234 \
-rreg sr.mdol -edata 0x0033
}
#
#-------------------------------------------------------------------------
if {[iswide]} {
rlc log " test 11: wloop option"
# like test previous test 7, but now using wloop
# list of 4 mem write and 4 read commands
set clist {}
lappend clist { 0 w 1111 0x000000 0x00102030};
lappend clist { 0 w 1111 0x000001 0x01112131};
lappend clist { 0 r 1111 0x000000 0x00102030};
lappend clist { 0 w 1111 0x000002 0x02122232};
lappend clist { 0 r 1111 0x000001 0x01112131};
lappend clist { 0 w 1111 0x000003 0x03132333};
lappend clist { 0 r 1111 0x000002 0x02122232};
lappend clist { 0 r 1111 0x000003 0x03132333};
scmd_write $clist
# start with wloop=1,loop=1,xora=1 and maddr=3ffff0 (will loop to 3fffff)
test_seq_setxor 0x3f 0xfff0 0x0000 0x0000
test_seq_srun [regbld tst_sram::SSTAT wloop loop xora veri] $tout
# check that maddr incremented
rlc exec \
-rreg sr.maddrh -edata 0x003f \
-rreg sr.maddrl -edata 0xffff
# last iteration will write into
# 00000 xor 3fffff -> 3fffff (00102030)
# 00001 xor 3fffff -> 3ffffe (01112131)
# 00002 xor 3fffff -> 3ffffd (02122232)
# 00003 xor 3fffff -> 3ffffc (03132333)
# read back 4 longwords 3ffffc..3fffff
rlc exec \
-wreg sr.maddrh 0x003f \
-wreg sr.maddrl 0xfffc \
-rblk sr.mblk 8 -edata {0x0313 0x2333 \
0x0212 0x2232 \
0x0111 0x2131 \
0x0010 0x2030}
}
#
#-------------------------------------------------------------------------
incr errcnt [rlc errcnt -clear]
return $errcnt
}
}
/trunk/tools/tcl/tst_sram/util.tcl
0,0 → 1,244
# $Id: util.tcl 785 2016-07-10 12:22:41Z mueller $
#
# Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 2, or at your option any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
# Revision History:
# Date Rev Version Comment
# 2016-07-09 784 1.2 22bit support: mask sstat(wide); add iswide
# 2015-04-03 661 1.1 drop estatdef (stat err check default now)
# 2014-08-14 582 1.0.1 add srun* procs; add nscmd and tout variables
# 2014-08-10 581 1.0 Initial version
# 2011-07-03 387 0.1 Frist draft
#
 
package provide tst_sram 1.0
 
package require rutiltpp
package require rutil
package require rlink
 
namespace eval tst_sram {
# name space variables
#
variable nscmd 0; # length of current sequencer command list
variable tout 10.; # default time out
variable iswide -1; # sstat.wide cache
#
# setup register descriptions for tst_sram core design ---------------------
#
regdsc MCMD {ld 14} {inc 13} {we 12} {be 11 4} {addrh 5 6}
regdsc SSTAT {wide 15} {wswap 9} {wloop 8} \
{loop 7} {xord 6} {xora 5} {veri 4} {fail 1} {run 0}
regdsc SCMD {wait 31 4} {we 24} {be 23 4} {addr 17 18}
#
# setup: amap definitions for tst_sram core design -------------------------
#
proc setup {{base 0x0000}} {
rlc amap -insert sr.mdih [expr {$base + 0x00}]
rlc amap -insert sr.mdil [expr {$base + 0x01}]
rlc amap -insert sr.mdoh [expr {$base + 0x02}]
rlc amap -insert sr.mdol [expr {$base + 0x03}]
rlc amap -insert sr.maddrh [expr {$base + 0x04}]
rlc amap -insert sr.maddrl [expr {$base + 0x05}]
rlc amap -insert sr.mcmd [expr {$base + 0x06}]
rlc amap -insert sr.mblk [expr {$base + 0x07}]
rlc amap -insert sr.slim [expr {$base + 0x08}]
rlc amap -insert sr.saddr [expr {$base + 0x09}]
rlc amap -insert sr.sblk [expr {$base + 0x0a}]
rlc amap -insert sr.sblkc [expr {$base + 0x0b}]
rlc amap -insert sr.sblkd [expr {$base + 0x0c}]
rlc amap -insert sr.sstat [expr {$base + 0x0d}]
rlc amap -insert sr.sstart [expr {$base + 0x0e}]
rlc amap -insert sr.sstop [expr {$base + 0x0f}]
rlc amap -insert sr.seaddr [expr {$base + 0x10}]
rlc amap -insert sr.sedath [expr {$base + 0x11}]
rlc amap -insert sr.sedatl [expr {$base + 0x12}]
}
#
# init: reset tst_sram -----------------------------------------------------
#
proc init {} {
rlc exec \
-wreg sr.sstop 1 \
-wreg sr.sstat 0
}
#
# iswide: 1 if 22bit system ------------------------------------------------
#
proc iswide {} {
variable iswide
if {$iswide < 0} {
rlc exec -rreg sr.sstat sstat
set iswide [regget tst_sram::SSTAT(wide) $sstat]
}
return $iswide
}
#
# scmd_write: write a scmd list --------------------------------------------
#
proc scmd_write {scmdlist} {
variable nscmd
set buf {}
set nscmd 0
rlc exec -wreg sr.saddr 0
 
foreach scmditem $scmdlist {
set wait [lindex $scmditem 0]
set wec [lindex $scmditem 1]
set bec [lindex $scmditem 2]
set addr [lindex $scmditem 3]
set mval [lindex $scmditem 4]
set we [expr {($wec eq "w") ? 1 : 0}]
set scmd [regbld tst_sram::SCMD \
[list wait $wait] \
[list we $we] \
[list be [bvi b $bec]] \
[list addr $addr] ]
set scmdh [expr {($scmd>>16) & 0xffff}]
set scmdl [expr { $scmd & 0xffff}]
set mvalh [expr {($mval>>16) & 0xffff}]
set mvall [expr { $mval & 0xffff}]
lappend buf $scmdh $scmdl $mvalh $mvall
if {[llength $buf] == 256} {
rlc exec -wblk sr.sblk $buf
set buf {}
}
incr nscmd
}
if {[llength $buf] > 0} {
rlc exec -wblk sr.sblk $buf
}
return ""
}
 
#
# scmd_read: read a scmd list ---------------------------------------------
#
proc scmd_read {length} {
set scmdlist {}
if {$length == 0} {return $scmdlist}
 
rlc exec -rreg sr.saddr saddr_save \
-wreg sr.saddr 0
while {$length > 0} {
set chunk $length
if {$chunk > 64} {set chunk 64}
set length [expr {$length - $chunk}]
rlc exec -rblk sr.sblk [expr {4*$chunk}] buf
foreach {scmdh scmdl mvalh mvall} $buf {
set scmd [expr {($scmdh<<16) | $scmdl}]
set mval [expr {($mvalh<<16) | $mvall}]
set wait [regget tst_sram::SCMD(wait) $scmd]
set we [regget tst_sram::SCMD(we) $scmd]
set be [regget tst_sram::SCMD(be) $scmd]
set addr [regget tst_sram::SCMD(addr) $scmd]
set wec [expr {($we) ? "w" : "r"}]
set bec [pbvi b4 $be]
lappend scmdlist [list $wait $wec $bec $addr $mval]
}
}
rlc exec -wreg sr.saddr $saddr_save
return $scmdlist
}
 
#
# scmd_print: print a scmd list -------------------------------------------
#
proc scmd_print {scmdlist} {
set rval " ind: dly we be addr mval"
set ind 0
foreach scmditem $scmdlist {
set wait [lindex $scmditem 0]
set wec [lindex $scmditem 1]
set bec [lindex $scmditem 2]
set addr [lindex $scmditem 3]
set mval [lindex $scmditem 4]
append rval "\n"
append rval [format "%4d: %2d %s %s 0x%6.6x 0x%8.8x" \
$ind $wait $wec $bec $addr $mval]
incr ind
}
return $rval
}
 
#
# srun: single pass run of sequencer ---------------------------------------
#
proc srun {mdih mdil maddrh maddrl {tout 0.}} {
variable nscmd
if {$tout == 0} {set tout $tst_sram::tout}
if {$nscmd == 0} {error "no or empty scmd list loaded"}
set sm [rutil::com16 [regbld tst_sram::SSTAT wide]]
rlc exec -init 0 1
rlc exec -wreg sr.sstat [regbld tst_sram::SSTAT xord xora veri] \
-wreg sr.mdih $mdih \
-wreg sr.mdil $mdil \
-wreg sr.maddrh $maddrh \
-wreg sr.maddrl $maddrl \
-wreg sr.slim [expr {$nscmd-1}] \
-wreg sr.sstart 0x0000
rlc wtlam $tout
rlc exec -attn -edata 0x0001
rlc exec -rreg sr.sstat -edata [regbld tst_sram::SSTAT xord xora veri] $sm \
-rreg sr.seaddr -edata 0x0000 \
-rreg sr.sedath -edata 0x0000 \
-rreg sr.sedatl -edata 0x0000
return ""
}
#
# srun_lists: call srun for mdi and maddr lists ----------------------------
#
proc srun_lists {lmdi lmaddr {tout 0.}} {
foreach {maddrh maddrl} $lmaddr {
foreach {mdih mdil} $lmdi {
srun $mdih $mdil $maddrh $maddrl $tout
}
}
return ""
}
#
# srun_loop: full maddr* loop of sequencer ---------------------------------
#
proc srun_loop {mdih mdil maddrh maddrl {wide 0} {tout 0.}} {
variable nscmd
if {$tout == 0} {set tout $tst_sram::tout}
if {$nscmd == 0} {error "no or empty scmd list loaded"}
set sm [rutil::com16 [regbld tst_sram::SSTAT wide]]
set sstat [regbldkv tst_sram::SSTAT wswap $wide wloop $wide loop 1 \
xord 1 xora 1 veri 1]
rlc exec -init 0 1
rlc exec -wreg sr.sstat $sstat \
-wreg sr.mdih $mdih \
-wreg sr.mdil $mdil \
-wreg sr.maddrh $maddrh \
-wreg sr.maddrl $maddrl \
-wreg sr.slim [expr {$nscmd-1}] \
-wreg sr.sstart 0x0000
 
set tbeg [clock milliseconds]
rlc wtlam $tout
set tend [clock milliseconds]
 
rlc exec -attn -edata 0x0001
rlc exec -rreg sr.sstat -edata $sstat $sm \
-rreg sr.seaddr -edata 0x0000 \
-rreg sr.sedath -edata 0x0000 \
-rreg sr.sedatl -edata 0x0000
 
set trun [expr {($tend-$tbeg)/1000.}]
set line [format "loop done maddr=%2.2x %4.4x mdi=%4.4x %4.4x in %7.2f s" \
$maddrh $maddrl $mdih $mdil $trun]
rlc log $line
return ""
}
}
 
/trunk/tools/tcl/tst_sram
trunk/tools/tcl/tst_sram Property changes : Added: svn:ignore ## -0,0 +1,43 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb +pkgIndex.tcl Index: trunk/tools/vivado/viv_default_build.tcl =================================================================== --- trunk/tools/vivado/viv_default_build.tcl (nonexistent) +++ trunk/tools/vivado/viv_default_build.tcl (revision 37) @@ -0,0 +1,12 @@ +# $Id: viv_default_build.tcl 792 2016-07-23 18:05:40Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-02-14 646 1.0 Initial version +# 2015-01-25 637 0.1 First draft +# + +rvtb_default_build [lindex $::argv 0] [lindex $::argv 1] Index: trunk/tools/vivado/viv_default_config.tcl =================================================================== --- trunk/tools/vivado/viv_default_config.tcl (nonexistent) +++ trunk/tools/vivado/viv_default_config.tcl (revision 37) @@ -0,0 +1,12 @@ +# $Id: viv_default_config.tcl 792 2016-07-23 18:05:40Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-02-14 646 1.0 Initial version +# 2015-01-25 637 0.1 First draft +# + +rvtb_default_config [lindex $::argv 0] Index: trunk/tools/vivado/viv_default_model.tcl =================================================================== --- trunk/tools/vivado/viv_default_model.tcl (nonexistent) +++ trunk/tools/vivado/viv_default_model.tcl (revision 37) @@ -0,0 +1,11 @@ +# $Id: viv_default_model.tcl 792 2016-07-23 18:05:40Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-02-14 646 1.0 Initial version +# + +rvtb_default_model [lindex $::argv 0] [lindex $::argv 1] Index: trunk/tools/vivado/viv_init.tcl =================================================================== --- trunk/tools/vivado/viv_init.tcl (nonexistent) +++ trunk/tools/vivado/viv_init.tcl (revision 37) @@ -0,0 +1,14 @@ +# $Id: viv_init.tcl 792 2016-07-23 18:05:40Z mueller $ +# +# Copyright 2015-2016 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2016-07-22 792 1.1 relocate viv tcl code to tools/vivado +# 2015-02-14 646 1.0 Initial version +# 2015-01-25 637 0.1 First draft +# +source -notrace "$::env(RETROBASE)/tools/vivado/viv_tools_build.tcl" +source -notrace "$::env(RETROBASE)/tools/vivado/viv_tools_config.tcl" +source -notrace "$::env(RETROBASE)/tools/vivado/viv_tools_model.tcl" Index: trunk/tools/vivado/viv_tools_build.tcl =================================================================== --- trunk/tools/vivado/viv_tools_build.tcl (nonexistent) +++ trunk/tools/vivado/viv_tools_build.tcl (revision 37) @@ -0,0 +1,305 @@ +# $Id: viv_tools_build.tcl 809 2016-09-18 19:49:14Z mueller $ +# +# Copyright 2015-2016 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2016-09-18 809 1.2.1 keep hierarchy for synthesis only runs +# 2016-05-22 767 1.2 cleaner setup handling; use explore flows +# add 2016.1 specific setups +# 2016-04-02 758 1.1.5 remove USR_ACCESS setup, must be done in xdc +# 2016-03-26 752 1.1.4 more steps supported: prj,opt,pla +# 2016-03-25 751 1.1.3 suppress some messages +# 2016-03-19 748 1.1.2 set bitstream USR_ACCESS to TIMESTAMP +# 2016-02-28 738 1.1.1 add 2015.4 specific setups +# 2015-02-21 649 1.1 add 2014.4 specific setups +# 2015-02-14 646 1.0 Initial version +# + +# +# -------------------------------------------------------------------- +# +proc rvtb_trace_cmd {cmd} { + puts "# $cmd" + eval $cmd + return "" +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_locate_setup_file {stem} { + set name "${stem}_setup.tcl" + if {[file readable $name]} {return $name} + set name "$../{stem}_setup.tcl" + if {[file readable $name]} {return $name} + return "" +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_mv_file {src dst} { + if {[file readable $src]} { + exec mv $src $dst + } else { + puts "rvtb_mv_file-W: file '$src' not existing" + } + return "" +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_rm_file {src} { + exec rm -f $src +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_cp_file {src dst} { + if {[file readable $src]} { + exec cp -p $src $dst + } else { + puts "rvtb_cp_file-W: file '$src' not existing" + } + return "" +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_build_check {step} { + return "" +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_version_is {val} { + set vers [version -short] + return [expr {$vers eq $val}] +} +# +# -------------------------------------------------------------------- +# +proc rvtb_version_min {val} { + set vers [version -short] + return [expr {[string compare $vers $val] >= 0}] +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_version_max {val} { + set vers [version -short] + return [expr {[string compare $vers $val] <= 0}] +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_version_in {min max} { + set vers [version -short] + return [expr {[string compare $vers $min] >= 0 && \ + [string compare $vers $max] <= 0}] +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_default_build {stem step} { + # supported step values + # prj setup project + # syn run synthesis + # opt run synthesis + implementation up to step opt_design + # pla run synthesis + implementation up to step place_design + # imp run synthesis + implementation (but not bit file generation) + # bit Synthesize + Implement + generate bit file + + if {![regexp -- {^(prj|syn|opt|pla|imp|bit)$} $step]} { + error "bad step name $step" + } + + # general setups (prior to project creation) ------------------ + # version dependent setups + if {[rvtb_version_is "2014.4"]} { + # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages + # set here to avoid messages during create_project + set_msg_config -suppress -id {Board 49-26} + } + + # read setup + set setup_file [rvtb_locate_setup_file $stem] + if {$setup_file ne ""} {source -notrace $setup_file} + + # Create project ---------------------------------------------- + rvtb_trace_cmd "create_project project_mflow ./project_mflow" + + # Setup project properties ------------------------------- + set obj [get_projects project_mflow] + set_property "default_lib" "xil_defaultlib" $obj + set_property "part" $::rvtb_part $obj + set_property "simulator_language" "Mixed" $obj + set_property "target_language" "VHDL" $obj + + # general setups ----------------------------------------- + # suppress message which don't convey useful information + set_msg_config -suppress -id {DRC 23-20}; # DSP48 output pilelining + set_msg_config -suppress -id {Project 1-120}; # WebTalk mandatory + set_msg_config -suppress -id {Common 17-186}; # WebTalk info send + + # Setup list of extra synthesis options (for later rodinMoreOptions) + set synth_more_opts {} + + # version independent setups ----------------------------- + + # setup synthesis strategy and options -------------- + set_property strategy Flow_PerfOptimized_high [get_runs synth_1] + # for synthesis only: keep hierarchy for easier debug + if {$step eq "syn"} { + set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none \ + [get_runs synth_1] + } + # FSM recognition threshold (default is 5) + # see http://www.xilinx.com/support/answers/58574.html + lappend synth_more_opts {rt::set_parameter minFsmStates 3} + + # setup implementation strategy and options --------- + set_property strategy Performance_Explore [get_runs impl_1] + + # version dependent setups ------------------------------- + if {[rvtb_version_is "2014.4"]} { + # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages + # repeated here because create_project apparently clears msg_config + set_msg_config -suppress -id {Board 49-26} + } + + if {[rvtb_version_is "2015.4"]} { + # enable vhdl asserts, see http://www.xilinx.com/support/answers/65415.html + lappend synth_more_opts {rt::set_parameter ignoreVhdlAssertStmts false} + } + + if {[rvtb_version_min "2016.1"]} { + # enable vhdl asserts via global option (after 2016.1) + set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1] + } + + # now setup extra synthesis options + # see http://www.xilinx.com/support/answers/58248.html + # -> since used via 'set_param' it's a parameter + # -> only last definition counts + # -> use ';' separated list + # -> these options are **NOT** preserved in project file !! + if {[llength $synth_more_opts]} { + puts "# extra synthesis options:" + foreach opt $synth_more_opts { puts "# $opt"} + set_param synth.elaboration.rodinMoreOptions [join $synth_more_opts "; "] + } + + # Setup filesets + set vbom_prj [exec vbomconv -vsyn_prj "${stem}.vbom"] + eval $vbom_prj + update_compile_order -fileset sources_1 + + if {$step eq "prj"} { + puts "rvtb_default_build-I: new project setup for ${stem}" + return "" + } + + # some handy variables + set path_runs "project_mflow/project_mflow.runs" + set path_syn1 "${path_runs}/synth_1" + set path_imp1 "${path_runs}/impl_1" + + # build: synthesize ------------------------------------------------ + puts "# current rodinMoreOptions:" + puts [get_param synth.elaboration.rodinMoreOptions] + + rvtb_trace_cmd "launch_runs synth_1" + rvtb_trace_cmd "wait_on_run synth_1" + + rvtb_mv_file "$path_syn1/runme.log" "${stem}_syn.log" + + rvtb_cp_file "$path_syn1/${stem}_utilization_synth.rpt" "${stem}_syn_util.rpt" + rvtb_cp_file "$path_syn1/${stem}.dcp" "${stem}_syn.dcp" + + if {$step eq "syn"} {return [rvtb_build_check $step]} + + # build: implement ------------------------------------------------- + set launch_opt "" + if {$step eq "opt"} {set launch_opt "-to_step opt_design"} + if {$step eq "pla"} {set launch_opt "-to_step place_design"} + + rvtb_trace_cmd "launch_runs ${launch_opt} impl_1" + rvtb_trace_cmd "wait_on_run impl_1" + + rvtb_cp_file "$path_imp1/runme.log" "${stem}_imp.log" + + rvtb_cp_file "$path_imp1/${stem}_opt.dcp" "${stem}_opt.dcp" + rvtb_cp_file "$path_imp1/${stem}_drc_opted.rpt" "${stem}_opt_drc.rpt" + + if {$step eq "opt"} { + rvtb_trace_cmd "open_checkpoint $path_imp1/${stem}_opt.dcp" + report_utilization -file "${stem}_opt_util.rpt" + report_utilization -hierarchical -file "${stem}_opt_util_h.rpt" + return [rvtb_build_check $step] + } + + rvtb_cp_file "$path_imp1/${stem}_placed.dcp" "${stem}_pla.dcp" + rvtb_cp_file "$path_imp1/${stem}_io_placed.rpt" "${stem}_pla_io.rpt" + rvtb_cp_file "$path_imp1/${stem}_utilization_placed.rpt" \ + "${stem}_pla_util.rpt" + rvtb_cp_file "$path_imp1/${stem}_control_sets_placed.rpt" \ + "${stem}_pla_clk_set.rpt" + + if {$step eq "pla"} { + return [rvtb_build_check $step] + } + + rvtb_cp_file "$path_imp1/${stem}_routed.dcp" "${stem}_rou.dcp" + rvtb_cp_file "$path_imp1/${stem}_route_status.rpt" "${stem}_rou_sta.rpt" + rvtb_cp_file "$path_imp1/${stem}_drc_routed.rpt" "${stem}_rou_drc.rpt" + rvtb_cp_file "$path_imp1/${stem}_timing_summary_routed.rpt" \ + "${stem}_rou_tim.rpt" + rvtb_cp_file "$path_imp1/${stem}_power_routed.rpt" "${stem}_rou_pwr.rpt" + rvtb_cp_file "$path_imp1/${stem}_clock_utilization_routed.rpt" \ + "${stem}_rou_clk_util.rpt" + + # additional reports + rvtb_trace_cmd "open_run impl_1" + report_utilization -file "${stem}_rou_util.rpt" + report_utilization -hierarchical -file "${stem}_rou_util_h.rpt" + report_datasheet -file "${stem}_rou_ds.rpt" + report_cdc -file "${stem}_rou_cdc.rpt" + report_clock_interaction -delay_type min_max -significant_digits 3 \ + -file "${stem}_rou_clk_int.rpt" + if {[get_property SSN_REPORT [get_property PART [current_project]]]} { + report_ssn -format TXT -file "${stem}_rou_ssn.rpt" + } + + if {$step eq "imp"} {return [rvtb_build_check $step]} + + # build: bitstream ------------------------------------------------- + # check for critical warnings, e.g. + # [Timing 38-282] The design failed to meet the timing requirements. + # in that case abort build + + rvtb_rm_file "./${stem}.bit" + + if {[get_msg_config -severity {critical warning} -count]} { + puts "rvtb_default_build-E: abort due to critical warnings seen before" + puts "rvtb_default_build-E: no bitfile generated" + return [rvtb_build_check $step] + } + + rvtb_trace_cmd "launch_runs impl_1 -to_step write_bitstream" + rvtb_trace_cmd "wait_on_run impl_1" + + rvtb_mv_file "$path_imp1/runme.log" "${stem}_bit.log" + rvtb_mv_file "$path_imp1/${stem}.bit" "." + + return [rvtb_build_check $step] +} Index: trunk/tools/vivado/viv_tools_config.tcl =================================================================== --- trunk/tools/vivado/viv_tools_config.tcl (nonexistent) +++ trunk/tools/vivado/viv_tools_config.tcl (revision 37) @@ -0,0 +1,51 @@ +# $Id: viv_tools_config.tcl 792 2016-07-23 18:05:40Z mueller $ +# +# Copyright 2015-2016 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2016-04-02 758 1.1 add USR_ACCESS readback +# 2015-02-14 646 1.0 Initial version +# + +# +# -------------------------------------------------------------------- +# +proc rvtb_format_usracc {usracc} { + set sec [expr { ($usracc >> 0) & 0x3f } ]; # 6 bit 05:00 + set min [expr { ($usracc >> 6) & 0x3f } ]; # 6 bit 11:06 + set hr [expr { ($usracc >> 12) & 0x1f } ]; # 5 bit 16:12 + set yr [expr {(($usracc >> 17) & 0x3f)+2000} ]; # 6 bit 22:17 + set mo [expr { ($usracc >> 23) & 0x0f } ]; # 4 bit 26:23 + set day [expr { ($usracc >> 27) & 0x1f } ]; # 5 bit 31:27 + return [format "%04d-%02d-%02d %02d:%02d:%02d" $yr $mo $day $hr $min $sec] +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_default_config {stem} { + # open and connect to hardware server + open_hw + connect_hw_server + + # connect to target + open_hw_target [lindex [get_hw_targets -of_objects [get_hw_servers localhost]] 0] + + # setup bitfile + set_property PROGRAM.FILE "${stem}.bit" [lindex [get_hw_devices] 0] + + # and configure FPGA + program_hw_devices [lindex [get_hw_devices] 0] + + # and check USR_ACCESS setting + set usracc_raw [get_property REGISTER.USR_ACCESS [lindex [get_hw_devices] 0] ] + set usracc_num "0x$usracc_raw" + set usracc_fmt [rvtb_format_usracc $usracc_num] + puts "" + puts "USR_ACCESS: 0x$usracc_raw $usracc_fmt" + puts "" + + return ""; +} Index: trunk/tools/vivado/viv_tools_model.tcl =================================================================== --- trunk/tools/vivado/viv_tools_model.tcl (nonexistent) +++ trunk/tools/vivado/viv_tools_model.tcl (revision 37) @@ -0,0 +1,59 @@ +# $Id: viv_tools_model.tcl 792 2016-07-23 18:05:40Z mueller $ +# +# Copyright 2015-2016 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2016-06-24 778 1.1 support mode [sor]sim_vhdl [sorepd]sim_veri +# 2016-06-19 777 1.0.1 use full absolute path name for sdf annotate +# 2015-02-14 646 1.0 Initial version +# +# -------------------------------------------------------------------- +# supported modes +# base ----- func ----- timing +# vhdl veri veri +# post synth _syn.dcp ssim_vhd ssim_v esim_v +# post phys_opt _opt.dcp osim_vhd osim_v psim_v +# post route _rou.dcp rsim_vhd rsim_v tsim_v +# +proc rvtb_default_model {stem mode} { + + if {[regexp -- {^([sor])sim_(vhd|v)$} $mode matched type lang] || + [regexp -- {^([ept])sim_(v)$} $mode matched type lang]} { + + switch $type { + s - + e {open_checkpoint "${stem}_syn.dcp"} + o - + p {open_checkpoint "${stem}_opt.dcp"} + r - + t {open_checkpoint "${stem}_rou.dcp"} + } + + if {$lang eq "vhd"} { + write_vhdl -mode funcsim -force "${stem}_${type}sim.vhd" + } else { + if {$type eq "s" || $type eq "o" || $type eq "r"} { + write_verilog -mode funcsim -force "${stem}_${type}sim.v" + } else { + # use full absolute path name for sdf annotate + # reason: the _tsim.v is sometimes generated in system path and + # used from the tb path. xelab doesn't find the sdf in that case + # Solution are absolute path (ugly) or symlink (ugly, who does setup..) + write_verilog -mode timesim -force \ + -sdf_anno true \ + -sdf_file "[pwd]/${stem}_${type}sim.sdf" \ + "${stem}_${type}sim.v" + write_sdf -mode timesim -force \ + -process_corner slow \ + "${stem}_${type}sim.sdf" + } + } + + } else { + error "rvtb_default_model-E: bad mode: $mode"; + } + + return ""; +} Index: trunk/tools/vivado =================================================================== --- trunk/tools/vivado (nonexistent) +++ trunk/tools/vivado (revision 37)
trunk/tools/vivado Property changes : Added: svn:ignore ## -0,0 +1,42 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb

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