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Rev 6 → Rev 7

/test/vpi_images.c
0,0 → 1,228
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free and excepted software; you can use it, redistribute it
* and/or modify it under the terms of the Exception General Public License as
* published by the Exception License Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
* FOR A PARTICULAR PURPOSE. See the Exception General Public License for more
* details.
*
* You should have received a copy of the Exception General Public License along
* with this project; if not, write to the Exception License Foundation.
*/
 
#include <vpi_user.h>
#include <stdio.h>
#include <stdlib.h>
#include <gd.h>
 
static gdImagePtr src;
static gdImagePtr dst;
 
/*
* Open both input and output images.
*
* Use from Verilog:
* call $image_open at the beginning of the testbench.
*/
static int open_calltf(char *user_data)
{
FILE *fd;
 
fd = fopen("lena.jpg", "rb");
if(fd == NULL) {
perror("Unable to open input picture");
exit(1);
}
src = gdImageCreateFromJpeg(fd);
if(src == NULL) {
fprintf(stderr, "Unable to read input picture\n");
exit(1);
}
fclose(fd);
dst = gdImageCreateTrueColor(src->sx, src->sy);
if(src == NULL) {
fprintf(stderr, "Unable to create output picture\n");
exit(1);
}
return 0;
}
 
/*
* Get a RGB565 pixel from the source image.
*
* Use from Verilog:
* $image_get(x, y, color);
* color will be modified to reflect the
* pixel's color ; x and y are unmodified.
*/
static int get_calltf(char *user_data)
{
vpiHandle sys;
vpiHandle argv;
vpiHandle item;
s_vpi_value value;
s_vpi_vecval vec;
unsigned int x, y;
unsigned int c;
unsigned int red, green, blue;
unsigned int r;
sys = vpi_handle(vpiSysTfCall, 0);
argv = vpi_iterate(vpiArgument, sys);
/* get x */
item = vpi_scan(argv);
value.format = vpiIntVal;
vpi_get_value(item, &value);
x = value.value.integer;
 
/* get y */
item = vpi_scan(argv);
value.format = vpiIntVal;
vpi_get_value(item, &value);
y = value.value.integer;
 
/* do the job */
c = gdImageGetTrueColorPixel(src, x, y);
red = gdTrueColorGetRed(c);
green = gdTrueColorGetGreen(c);
blue = gdTrueColorGetBlue(c);
r = ((red & 0xf8) << 8) | ((green & 0xfc) << 3) | ((blue & 0xf8) >> 3);
/* write to the destination */
item = vpi_scan(argv);
value.format = vpiVectorVal;
vec.aval = r;
vec.bval = 0;
value.value.vector = &vec;
vpi_put_value(item, &value, 0, vpiNoDelay);
vpi_free_object(argv);
return 0;
}
 
/*
* Set a RGB565 pixel in the destination image.
*
* Use from Verilog:
* $image_get(x, y, color);
* Parameters are not modified.
*/
static int set_calltf(char *user_data)
{
vpiHandle sys;
vpiHandle argv;
vpiHandle item;
s_vpi_value value;
unsigned int x, y;
unsigned int c;
unsigned int red, green, blue;
sys = vpi_handle(vpiSysTfCall, 0);
argv = vpi_iterate(vpiArgument, sys);
/* get x */
item = vpi_scan(argv);
value.format = vpiIntVal;
vpi_get_value(item, &value);
x = value.value.integer;
 
/* get y */
item = vpi_scan(argv);
value.format = vpiIntVal;
vpi_get_value(item, &value);
y = value.value.integer;
 
/* get color */
item = vpi_scan(argv);
value.format = vpiIntVal;
vpi_get_value(item, &value);
c = value.value.integer;
 
vpi_free_object(argv);
 
/* do the job */
/* extract raw 5, 6 and 5-bit components */
red = (c & 0xf800) >> 11;
green = (c & 0x07e0) >> 5;
blue = c & 0x001f;
/* shift right and complete with MSBs */
red = (red << 3) | ((red & 0x1c) >> 2);
green = (green << 2) | ((green & 0x30) >> 4);
blue = (blue << 3) | ((blue & 0x1c) >> 2);
//printf("Set Pixel (%d,%d), %02x%02x%02x\n", x, y, red, green, blue);
gdImageSetPixel(dst, x, y,
gdImageColorAllocate(dst, red, green, blue));
return 0;
}
 
/*
* Close both input and output images.
*
* Use from Verilog:
* call $image_close at the end of the testbench.
* Don't forget it, or the destination file will
* not be written !
*/
static int close_calltf(char *user_data)
{
FILE *fd;
gdImageDestroy(src);
fd = fopen("out.png", "wb");
gdImagePng(dst, fd);
fclose(fd);
gdImageDestroy(dst);
return 0;
}
 
void vpi_register()
{
s_vpi_systf_data tf_data;
tf_data.type = vpiSysTask;
tf_data.tfname = "$image_open";
tf_data.calltf = open_calltf;
tf_data.compiletf = 0;
tf_data.sizetf = 0;
tf_data.user_data = 0;
vpi_register_systf(&tf_data);
tf_data.type = vpiSysTask;
tf_data.tfname = "$image_get";
tf_data.calltf = get_calltf;
tf_data.compiletf = 0;
tf_data.sizetf = 0;
tf_data.user_data = 0;
vpi_register_systf(&tf_data);
tf_data.type = vpiSysTask;
tf_data.tfname = "$image_set";
tf_data.calltf = set_calltf;
tf_data.compiletf = 0;
tf_data.sizetf = 0;
tf_data.user_data = 0;
vpi_register_systf(&tf_data);
tf_data.type = vpiSysTask;
tf_data.tfname = "$image_close";
tf_data.calltf = close_calltf;
tf_data.compiletf = 0;
tf_data.sizetf = 0;
tf_data.user_data = 0;
vpi_register_systf(&tf_data);
printf("PLI Image I/O functions registered\n");
}
/test/Makefile
0,0 → 1,17
SOURCES=tb_tmu.v $(wildcard ../rtl/*.v)
 
all: sim
 
sim: vpi_images.so
cver +loadvpi=./vpi_images.so:vpi_register $(SOURCES)
 
vpi_images.so: vpi_images.o
$(LD) -G -shared -export-dynamic -o vpi_images.so vpi_images.o -lgd -lpng -lz -ljpeg -lfreetype -lm
 
vpi_images.o: vpi_images.c
$(CC) -fPIC -Wall -g -O2 -c -o vpi_images.o vpi_images.c
 
clean:
rm -f verilog.log vpi_images.o vpi_images.so out.png
 
.PHONY: clean sim
/test/lena.jpg Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/test/lena.jpg
test/lena.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: test/tb_tmu.v =================================================================== --- test/tb_tmu.v (nonexistent) +++ test/tb_tmu.v (revision 7) @@ -0,0 +1,273 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tb_tmu(); + +parameter fml_depth = 26; +parameter wbm_depth = 26; + +reg sys_clk; +reg sys_rst; + +reg [13:0] csr_a; +reg csr_we; +reg [31:0] csr_di; +wire [31:0] csr_do; + +wire irq; + +wire [31:0] wbm_adr_o; +wire [2:0] wbm_cti_o; +wire wbm_cyc_o; +wire wbm_stb_o; +reg wbm_ack_i; +reg [31:0] wbm_dat_i; + +wire [fml_depth-1:0] fmlr_adr; +wire fmlr_stb; +reg fmlr_ack; +reg [63:0] fmlr_di; + +wire [fml_depth-1:0] fmlw_adr; +wire fmlw_stb; +reg fmlw_ack; +wire [7:0] fmlw_sel; +wire [63:0] fmlw_do; + +/* 100MHz system clock */ +initial sys_clk = 1'b0; +always #5 sys_clk = ~sys_clk; + +tmu #( + .fml_depth(fml_depth), + .pixin_cache_depth(12) +) dut ( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .csr_a(csr_a), + .csr_we(csr_we), + .csr_di(csr_di), + .csr_do(csr_do), + + .irq(irq), + + .wbm_adr_o(wbm_adr_o), + .wbm_cti_o(wbm_cti_o), + .wbm_cyc_o(wbm_cyc_o), + .wbm_stb_o(wbm_stb_o), + .wbm_ack_i(wbm_ack_i), + .wbm_dat_i(wbm_dat_i), + + .fmlr_adr(fmlr_adr), + .fmlr_stb(fmlr_stb), + .fmlr_ack(fmlr_ack), + .fmlr_di(fmlr_di), + + .fmlw_adr(fmlw_adr), + .fmlw_stb(fmlw_stb), + .fmlw_ack(fmlw_ack), + .fmlw_sel(fmlw_sel), + .fmlw_do(fmlw_do) +); + +task waitclock; +begin + @(posedge sys_clk); + #1; +end +endtask + +task csrwrite; +input [31:0] address; +input [31:0] data; +begin + csr_a = address[16:2]; + csr_di = data; + csr_we = 1'b1; + waitclock; + $display("Configuration Write: %x=%x", address, data); + csr_we = 1'b0; +end +endtask + +task csrread; +input [31:0] address; +begin + csr_a = address[16:2]; + waitclock; + $display("Configuration Read : %x=%x", address, csr_do); +end +endtask + +/* Handle WB master for mesh reads */ +reg [6:0] x; +reg [6:0] y; +always @(posedge sys_clk) begin + if(wbm_stb_o & ~wbm_ack_i) begin + x = wbm_adr_o[8:2]; + y = wbm_adr_o[15:9]; + wbm_dat_i[15:0] = x*20+y*7; + wbm_dat_i[31:16] = y*20; + $display("Mesh Read: %d,%d", x, y); + wbm_ack_i = 1'b1; + end else + wbm_ack_i = 1'b0; +end + +/* Handle FML master for pixel reads */ +integer read_burstcount; +integer read_addr; + +task handle_read; +integer read_addr2; +integer x; +integer y; +reg [15:0] p1; /* work around bugs/problems if we assign */ +reg [15:0] p2; /* directly to fmlr_di[xx:xx] in $image_get... */ +reg [15:0] p3; +reg [15:0] p4; +begin + read_addr2 = read_addr[20:0]/2; + x = read_addr2 % 640; + y = read_addr2 / 640; + $image_get(x + 0, y, p1); + $image_get(x + 1, y, p2); + $image_get(x + 2, y, p3); + $image_get(x + 3, y, p4); + fmlr_di = {p1, p2, p3, p4}; +end +endtask + +initial read_burstcount = 0; +always @(posedge sys_clk) begin + fmlr_ack = 1'b0; + if(read_burstcount == 0) begin + if(fmlr_stb) begin + read_burstcount = 1; + read_addr = fmlr_adr; + + handle_read; + + //$display("Starting FML burst READ at address %x", read_addr); + + fmlr_ack = 1'b1; + end + end else begin + read_addr = read_addr + 8; + read_burstcount = read_burstcount + 1; + + handle_read; + + //$display("Continuing FML burst READ at address %x", read_addr); + + if(read_burstcount == 4) + read_burstcount = 0; + end +end + +/* Handle FML master for pixel writes */ +integer write_burstcount; +integer write_addr; + +task handle_write; +integer write_addr2; +integer x; +integer y; +begin + write_addr2 = write_addr[20:0]/2; + x = write_addr2 % 640; + y = write_addr2 / 640; + if(fmlw_sel[7]) + $image_set(x + 0, y, fmlw_do[63:48]); + if(fmlw_sel[5]) + $image_set(x + 1, y, fmlw_do[47:32]); + if(fmlw_sel[3]) + $image_set(x + 2, y, fmlw_do[31:16]); + if(fmlw_sel[1]) + $image_set(x + 3, y, fmlw_do[15:0]); +end +endtask + +initial write_burstcount = 0; +always @(posedge sys_clk) begin + fmlw_ack = 1'b0; + if(write_burstcount == 0) begin + if(fmlw_stb) begin + write_burstcount = 1; + write_addr = fmlw_adr; + + //$display("Starting FML burst WRITE at address %x", write_addr); + handle_write; + + fmlw_ack = 1'b1; + end + end else begin + write_addr = write_addr + 8; + write_burstcount = write_burstcount + 1; + + //$display("Continuing FML burst WRITE at address %x", write_addr); + handle_write; + + if(write_burstcount == 4) + write_burstcount = 0; + end +end + +always begin + $image_open; + + /* Reset / Initialize our logic */ + sys_rst = 1'b1; + + csr_a = 14'd0; + csr_di = 32'd0; + csr_we = 1'b0; + + fmlr_di = 64'd0; + fmlr_ack = 1'b0; + + fmlw_ack = 1'b0; + + waitclock; + + sys_rst = 1'b0; + + waitclock; + + /* Setup */ + csrwrite(32'h24, 32'h01000000); /* dst addr */ + + /* Mesh count */ + //csrwrite(32'h08, 32'd1); + //csrwrite(32'h10, 32'd1); + + /* Mesh size */ + //csrwrite(32'h0c, 32'd20); + //csrwrite(32'h14, 32'd20); + + /* Start */ + csrwrite(32'h00, 32'd1); + + @(posedge irq); + + $image_close; + $finish; +end + +endmodule Index: rtl/tmu_meshgen.v =================================================================== --- rtl/tmu_meshgen.v (nonexistent) +++ rtl/tmu_meshgen.v (revision 7) @@ -0,0 +1,432 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_meshgen( + input sys_clk, + input sys_rst, + + output reg [31:0] wbm_adr_o, + output [2:0] wbm_cti_o, + output wbm_cyc_o, + output reg wbm_stb_o, + input wbm_ack_i, + input [31:0] wbm_dat_i, + + input start, + output reg busy, + + input [29:0] mesh_base, /* in 32-bit words */ + input [6:0] hmesh_count, + input [6:0] hmesh_size, + input [6:0] vmesh_count, + input [6:0] vmesh_size, + + output reg pipe_stb, + input pipe_ack, + output reg [10:0] A_S_X, + output reg [10:0] A_S_Y, + output reg [10:0] B_S_X, + output reg [10:0] B_S_Y, + output reg [10:0] C_S_X, + output reg [10:0] C_S_Y, + output reg [10:0] A_D_X, + output reg [10:0] A_D_Y, + output reg [10:0] B_D_X, + output reg [10:0] B_D_Y, + output reg [10:0] C_D_X, + output reg [10:0] C_D_Y +); + +/* Burst support for later */ +assign wbm_cti_o = 3'b000; + +assign wbm_cyc_o = wbm_stb_o; + +/* DATAPATH: Logo-like graphics in Verilog. */ + +/* move turtle to the origin */ +reg move_origin; +/* move turtle to the beginning of the line */ +reg move_linestart; +/* move turtle to the right */ +reg move_right; +/* move turtle down */ +reg move_down; +/* move turtle diagonally to the left and down */ +reg move_leftdown; +/* move turtle diagonally to the right and up */ +reg move_rightup; + +/* position of the turtle expressed in mesh coordinates */ +reg [6:0] turtle_ix; +reg [6:0] turtle_iy; +/* position of the turtle expressed in source image coordinates + * At all times : + * turtle_x = turtle_ix*hmesh_size + * turtle_y = turtle_iy*vmesh_size + * We generate them concurrently to avoid using a multiplier. + */ +reg [10:0] turtle_x; +reg [10:0] turtle_y; + +/* Register the control signals as they tend to be in the critical + * path because of the delay in the ack signal of the bus. + */ +reg move_origin_r; +reg move_linestart_r; +reg move_right_r; +reg move_down_r; +reg move_leftdown_r; +reg move_rightup_r; + +always @(posedge sys_clk) begin + move_origin_r <= move_origin; + move_linestart_r <= move_linestart; + move_right_r <= move_right; + move_down_r <= move_down; + move_leftdown_r <= move_leftdown; + move_rightup_r <= move_rightup; +end + +always @(posedge sys_clk) begin + case({move_origin_r, move_linestart_r, move_right_r, move_down_r, move_leftdown_r, move_rightup_r}) + 6'b100000: begin /* move_origin */ + turtle_ix <= 7'd0; + turtle_x <= 11'd0; + turtle_iy <= 7'd0; + turtle_y <= 11'd0; + end + 6'b010000: begin /* move_linestart */ + turtle_ix <= 7'd0; + turtle_x <= 11'd0; + end + 6'b001000: begin /* move_right */ + turtle_ix <= turtle_ix + 7'd1; + turtle_x <= turtle_x + hmesh_size; + end + 6'b000100: begin /* move_down */ + turtle_iy <= turtle_iy + 7'd1; + turtle_y <= turtle_y + vmesh_size; + end + 6'b000010: begin /* move_leftdown */ + turtle_ix <= turtle_ix - 7'd1; + turtle_x <= turtle_x - hmesh_size; + turtle_iy <= turtle_iy + 7'd1; + turtle_y <= turtle_y + vmesh_size; + end + 6'b000001: begin /* move_rightup */ + turtle_ix <= turtle_ix + 7'd1; + turtle_x <= turtle_x + hmesh_size; + turtle_iy <= turtle_iy - 7'd1; + turtle_y <= turtle_y - vmesh_size; + end + default:; + endcase +end + +/* Detect mesh boundaries */ +wire hlast = turtle_ix == hmesh_count; +wire vlast = turtle_iy == vmesh_count; + +/* DATAPATH: registered computation of the WB mesh address */ +wire [31:0] mesh_base32 = {mesh_base, 2'b00}; +always @(posedge sys_clk) + wbm_adr_o <= mesh_base32 + {turtle_iy, turtle_ix, 2'b00}; + +reg loadA; +reg loadB; +reg loadC; +always @(posedge sys_clk) begin + if(loadA) begin + A_S_X = turtle_x; + A_S_Y = turtle_y; + A_D_X = wbm_dat_i[10:0]; + A_D_Y = wbm_dat_i[26:16]; + end + if(loadB) begin + B_S_X = turtle_x; + B_S_Y = turtle_y; + B_D_X = wbm_dat_i[10:0]; + B_D_Y = wbm_dat_i[26:16]; + end + if(loadC) begin + C_S_X = turtle_x; + C_S_Y = turtle_y; + C_D_X = wbm_dat_i[10:0]; + C_D_Y = wbm_dat_i[26:16]; + end +end + +/* THE FSM FROM HELL */ + +parameter IDLE = 6'd0; + +parameter LS_WAIT_AADR = 6'd1; +parameter LS_WAIT2_AADR = 6'd2; +parameter LS_LOAD_A = 6'd3; +parameter LS_WAIT_BADR = 6'd4; +parameter LS_WAIT2_BADR = 6'd5; +parameter LS_LOAD_B = 6'd6; +parameter LS_WAIT_CADR = 6'd7; +parameter LS_WAIT2_CADR = 6'd8; +parameter LS_LOAD_C = 6'd9; + +parameter IL1T_WAIT_BADR = 6'd10; +parameter IL1T_WAIT2_BADR = 6'd11; +parameter IL1T_LOAD_B = 6'd12; +parameter IL1T_PIPEOUT = 6'd13; + +parameter IL1B_WAIT_AADR = 6'd14; +parameter IL1B_WAIT2_AADR = 6'd15; +parameter IL1B_LOAD_A = 6'd16; +parameter IL1B_PIPEOUT = 6'd17; + +parameter IL2T_WAIT_CADR = 6'd18; +parameter IL2T_WAIT2_CADR = 6'd19; +parameter IL2T_LOAD_C = 6'd20; +parameter IL2T_PIPEOUT = 6'd21; + +parameter IL2B_WAIT_BADR = 6'd22; +parameter IL2B_WAIT2_BADR = 6'd23; +parameter IL2B_LOAD_B = 6'd24; +parameter IL2B_PIPEOUT = 6'd25; + +parameter IL3T_WAIT_AADR = 6'd26; +parameter IL3T_WAIT2_AADR = 6'd27; +parameter IL3T_LOAD_A = 6'd28; +parameter IL3T_PIPEOUT = 6'd29; + +parameter IL3B_WAIT_CADR = 6'd30; +parameter IL3B_WAIT2_CADR = 6'd31; +parameter IL3B_LOAD_C = 6'd32; +parameter IL3B_PIPEOUT = 6'd33; + +reg [5:0] state; +reg [5:0] next_state; + +always @(posedge sys_clk) begin + if(sys_rst) + state <= IDLE; + else + state <= next_state; +end + +always @(*) begin + next_state = state; + + move_origin = 1'b0; + move_linestart = 1'b0; + move_right = 1'b0; + move_down = 1'b0; + move_leftdown = 1'b0; + move_rightup = 1'b0; + + loadA = 1'b0; + loadB = 1'b0; + loadC = 1'b0; + + wbm_stb_o = 1'b0; + busy = 1'b1; + + pipe_stb = 1'b0; + + case(state) + IDLE: begin + busy = 1'b0; + move_origin = 1'b1; + if(start) + next_state = LS_WAIT_AADR; + end + + /* Line Start */ + /* wait for the registered computation of WB address to complete */ + LS_WAIT_AADR: next_state = LS_WAIT2_AADR; + LS_WAIT2_AADR: next_state = LS_LOAD_A; + LS_LOAD_A: begin + wbm_stb_o = 1'b1; + loadA = 1'b1; + if(wbm_ack_i) begin + move_right = 1'b1; + next_state = LS_WAIT_BADR; + end + end + LS_WAIT_BADR: next_state = LS_WAIT2_BADR; + LS_WAIT2_BADR: next_state = LS_LOAD_B; + LS_LOAD_B: begin + wbm_stb_o = 1'b1; + loadB = 1'b1; + if(wbm_ack_i) begin + move_leftdown = 1'b1; + next_state = LS_WAIT_CADR; + end + end + LS_WAIT_CADR: next_state = LS_WAIT2_CADR; + LS_WAIT2_CADR: next_state = LS_LOAD_C; + LS_LOAD_C: begin + wbm_stb_o = 1'b1; + loadC = 1'b1; + if(wbm_ack_i) + next_state = IL1T_PIPEOUT; + end + + /* In Line */ + /* Configuration 1, Top triangle */ + + /* Enter this state by moving RIGHT-UP to fetch B, + * after checking for end-of-line and end-of-picture + */ + IL1T_WAIT_BADR: next_state = IL1T_WAIT2_BADR; + IL1T_WAIT2_BADR: next_state = IL1T_LOAD_B; + IL1T_LOAD_B: begin + wbm_stb_o = 1'b1; + loadB = 1'b1; + if(wbm_ack_i) begin + move_leftdown = 1'b1; /* Go to C not to break the cycle */ + next_state = IL1T_PIPEOUT; + end + end + IL1T_PIPEOUT: begin + pipe_stb = 1'b1; + if(pipe_ack) begin + move_right = 1'b1; + next_state = IL1B_WAIT_AADR; + end + end + + /* Configuration 1, Bottom triangle */ + + /* Enter this state by moving RIGHT to fetch A */ + IL1B_WAIT_AADR: next_state = IL1B_WAIT2_AADR; + IL1B_WAIT2_AADR: next_state = IL1B_LOAD_A; + IL1B_LOAD_A: begin + wbm_stb_o = 1'b1; + loadA = 1'b1; + if(wbm_ack_i) + next_state = IL1B_PIPEOUT; + end + IL1B_PIPEOUT: begin + pipe_stb = 1'b1; + if(pipe_ack) begin + if(hlast) begin + move_linestart = 1'b1; + if(vlast) + next_state = IDLE; + else + next_state = LS_WAIT_AADR; + end else begin + move_rightup = 1'b1; + next_state = IL2T_WAIT_CADR; + end + end + end + + /* Configuration 2, Top triangle */ + + /* Enter this state by moving RIGHT-UP to fetch C */ + IL2T_WAIT_CADR: next_state = IL2T_WAIT2_CADR; + IL2T_WAIT2_CADR: next_state = IL2T_LOAD_C; + IL2T_LOAD_C: begin + wbm_stb_o = 1'b1; + loadC = 1'b1; + if(wbm_ack_i) + next_state = IL2T_PIPEOUT; + end + IL2T_PIPEOUT: begin + pipe_stb = 1'b1; + if(pipe_ack) begin + move_down = 1'b1; + next_state = IL2B_WAIT_BADR; + end + end + + /* Configuration 2, Bottom triangle */ + + /* Enter this state by moving DOWN to fetch B */ + IL2B_WAIT_BADR: next_state = IL2B_WAIT2_BADR; + IL2B_WAIT2_BADR: next_state = IL2B_LOAD_B; + IL2B_LOAD_B: begin + wbm_stb_o = 1'b1; + loadB = 1'b1; + if(wbm_ack_i) + next_state = IL2B_PIPEOUT; + end + IL2B_PIPEOUT: begin + pipe_stb = 1'b1; + if(pipe_ack) begin + if(hlast) begin + move_linestart = 1'b1; + if(vlast) + next_state = IDLE; + else + next_state = LS_WAIT_AADR; + end else begin + move_rightup = 1'b1; + next_state = IL3T_WAIT_AADR; + end + end + end + + /* Configuration 3, Top triangle */ + + /* Enter this state by moving RIGHT UP to fetch A */ + IL3T_WAIT_AADR: next_state = IL3T_WAIT2_AADR; + IL3T_WAIT2_AADR: next_state = IL3T_LOAD_A; + IL3T_LOAD_A: begin + wbm_stb_o = 1'b1; + loadA = 1'b1; + if(wbm_ack_i) + next_state = IL3T_PIPEOUT; + end + IL3T_PIPEOUT: begin + pipe_stb = 1'b1; + if(pipe_ack) begin + move_down = 1'b1; + next_state = IL3B_WAIT_CADR; + end + end + + /* Configuration 3, Bottom triangle */ + + /* Enter this state by moving DOWN to fetch C */ + IL3B_WAIT_CADR: next_state = IL3B_WAIT2_CADR; + IL3B_WAIT2_CADR: next_state = IL3B_LOAD_C; + IL3B_LOAD_C: begin + wbm_stb_o = 1'b1; + loadC = 1'b1; + if(wbm_ack_i) + next_state = IL3B_PIPEOUT; + end + IL3B_PIPEOUT: begin + pipe_stb = 1'b1; + if(pipe_ack) begin + if(hlast) begin + move_linestart = 1'b1; + if(vlast) + next_state = IDLE; + else + next_state = LS_WAIT_AADR; + end else begin + move_rightup = 1'b1; + next_state = IL1T_WAIT_BADR; + end + end + end + endcase +end + +endmodule Index: rtl/tmu_pixin.v =================================================================== --- rtl/tmu_pixin.v (nonexistent) +++ rtl/tmu_pixin.v (revision 7) @@ -0,0 +1,337 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_pixin #( + parameter fml_depth = 26, + parameter cache_depth = 12 +) ( + input sys_clk, + input sys_rst, + + output reg [fml_depth-1:0] fml_adr, + output reg fml_stb, + input fml_ack, + input [63:0] fml_di, + + input flush, + output reg busy, + + input pipe_stb_i, + output reg pipe_ack_o, + input [fml_depth-1-1:0] src_addr, /* in 16-bit words */ + input [fml_depth-1-1:0] dst_addr, /* in 16-bit words, pass-through */ + + output reg pipe_stb_o, + input pipe_ack_i, + output reg [15:0] src_pixel, + output reg [fml_depth-1-1:0] dst_addr1, /* in 16-bit words */ + + output reg inc_misses +); + +/* Work on 8-bit addresses to reduce the probability of + * spending hours fixing typos in indices. + * The synthesizer should optimize the trailing 0 away. + */ +wire [fml_depth-1:0] src_addr8 = {src_addr, 1'b0}; + +reg memorize_src_address; +reg [fml_depth-1:0] src_addr8_r; +always @(posedge sys_clk) begin + if(memorize_src_address) + src_addr8_r = src_addr8; +end + +/* + * Line length is the burst length, that is 4*64 bits, or 32 bytes + * Address split up : + * + * | TAG | INDEX | OFFSET | + * |fml_depth-1 cache_depth|cache_depth-1 5|4 0| + * + */ + +wire [4:0] offset = src_addr8[4:0]; +wire [cache_depth-1-5:0] index = src_addr8[cache_depth-1:5]; +wire [fml_depth-cache_depth-1:0] tag = src_addr8[fml_depth-1:cache_depth]; + +wire [4:0] offset_r = src_addr8_r[4:0]; +wire [cache_depth-1-5:0] index_r = src_addr8_r[cache_depth-1:5]; +wire [fml_depth-cache_depth-1:0] tag_r = src_addr8_r[fml_depth-1:cache_depth]; + +/* When we access FML, it's always because of a cache miss, and + * therefore using the memorized address. Connect the address lines + * straight to the output of the register to improve timing. + * And add another register since that was not enough. + */ +always @(posedge sys_clk) + fml_adr <= {tag_r, index_r, 5'd0}; + +/* Use the memorized address as the index for the tag and data memories */ +reg use_memorized; + +/* + * TAG MEMORY + * + * Addressed by index (length cache_depth-5) + * Contains valid bit + tag + */ + +wire [cache_depth-1-5:0] tagmem_a; +reg tagmem_we; +wire [fml_depth-cache_depth-1+1:0] tagmem_di; +reg [fml_depth-cache_depth-1+1:0] tagmem_do; + +reg [fml_depth-cache_depth-1+1:0] tags[0:(1 << (cache_depth-5))-1]; + +always @(posedge sys_clk) begin + if(tagmem_we) + tags[tagmem_a] <= tagmem_di; + tagmem_do <= tags[tagmem_a]; +end + +reg flushmode; +reg flush_a_reset; + +reg [cache_depth-1-5:0] flush_a; +always @(posedge sys_clk) begin + if(flush_a_reset) + flush_a <= {cache_depth-5{1'b0}}; + else + flush_a <= flush_a + {{cache_depth-5-1{1'b0}}, 1'b1}; +end + +wire flush_last = (flush_a == {cache_depth-5{1'b1}}); + +assign tagmem_a = flushmode ? flush_a : (use_memorized ? index_r : index); + +wire di_valid; +/* we always write tags from addresses missing the cache, + * therefore with the memorized address. + */ +assign tagmem_di = {di_valid, tag_r}; + +assign di_valid = ~flushmode; + +wire do_valid; +wire [fml_depth-cache_depth-1:0] do_tag; +assign do_valid = tagmem_do[fml_depth-cache_depth-1+1]; +assign do_tag = tagmem_do[fml_depth-cache_depth-1:0]; + +/* + * DATA MEMORY + * + * Addressed by index+offset in 64-bit words (length cache_depth-3) + */ +wire [cache_depth-3-1:0] datamem_a; +reg datamem_we; +wire [63:0] datamem_di; +reg [63:0] datamem_do; + +reg [63:0] data[0:(1 << (cache_depth-3))-1]; + +always @(posedge sys_clk) begin + if(datamem_we) + data[datamem_a] <= datamem_di; + datamem_do <= data[datamem_a]; +end + +assign datamem_di = fml_di; +always @(*) begin + case(offset_r[2:1]) + 2'd0: src_pixel = datamem_do[63:48]; + 2'd1: src_pixel = datamem_do[47:32]; + 2'd2: src_pixel = datamem_do[31:16]; + 2'd3: src_pixel = datamem_do[15:0]; + endcase +end + +reg bcounter_reset; +reg [1:0] bcounter; +always @(posedge sys_clk) begin + if(bcounter_reset) + bcounter <= 2'd0; + else + bcounter <= bcounter + 2'd1; +end + +reg datamem_aswitch; +assign datamem_a = { + (use_memorized ? index_r : index), + datamem_aswitch ? bcounter : (use_memorized ? offset_r[4:3] : offset[4:3]) + }; + +/* FSM */ + +wire cache_hit = do_valid & (do_tag == tag_r); + +reg [3:0] state; +reg [3:0] next_state; + +parameter IDLE = 4'd0; +parameter RUNNING = 4'd1; +parameter WAIT_DOWNSTREAM = 4'd2; +parameter CACHEMISS = 4'd3; +parameter BURST2 = 4'd4; +parameter BURST3 = 4'd5; +parameter BURST4 = 4'd6; +parameter READOFFSET = 4'd7; +parameter FLUSH = 4'd8; + +always @(posedge sys_clk) begin + if(sys_rst) + state <= IDLE; + else begin + state <= next_state; + end +end + +always @(*) begin + next_state = state; + + memorize_src_address = 1'b0; + use_memorized = 1'b0; + + tagmem_we = 1'b0; + datamem_we = 1'b0; + flush_a_reset = 1'b0; + flushmode = 1'b0; + bcounter_reset = 1'b1; + datamem_aswitch = 1'b0; + + busy = 1'b1; + pipe_ack_o = 1'b0; + pipe_stb_o = 1'b0; + + fml_stb = 1'b0; + + inc_misses = 1'b0; + + case(state) + IDLE: begin + memorize_src_address = 1'b1; + busy = 1'b0; + if(flush) begin + flush_a_reset = 1'b1; + next_state = FLUSH; + end else begin + pipe_ack_o = 1'b1; + if(pipe_stb_i) + next_state = RUNNING; + end + end + RUNNING: begin + if(cache_hit) begin + pipe_stb_o = 1'b1; + pipe_ack_o = 1'b1; + memorize_src_address = 1'b1; + + if(~pipe_ack_i) begin + pipe_ack_o = 1'b0; + memorize_src_address = 1'b0; + use_memorized = 1'b1; + next_state = WAIT_DOWNSTREAM; + end else if(pipe_stb_i) + next_state = RUNNING; + else + next_state = IDLE; + end else begin + memorize_src_address = 1'b0; + next_state = CACHEMISS; + end + end + WAIT_DOWNSTREAM: begin + pipe_stb_o = 1'b1; + if(pipe_ack_i) begin + memorize_src_address = 1'b1; + use_memorized = 1'b0; + + pipe_ack_o = 1'b1; + if(pipe_stb_i) begin + next_state = RUNNING; + end else + next_state = IDLE; + end else begin + memorize_src_address = 1'b0; + use_memorized = 1'b1; + end + end + CACHEMISS: begin + memorize_src_address = 1'b0; + use_memorized = 1'b1; + fml_stb = 1'b1; + tagmem_we = 1'b1; + datamem_aswitch = 1'b1; + datamem_we = 1'b1; + if(fml_ack) begin + bcounter_reset = 1'b0; + next_state = BURST2; + end + end + BURST2: begin + inc_misses = 1'b1; + memorize_src_address = 1'b0; + use_memorized = 1'b1; + datamem_aswitch = 1'b1; + datamem_we = 1'b1; + bcounter_reset = 1'b0; + next_state = BURST3; + end + BURST3: begin + memorize_src_address = 1'b0; + use_memorized = 1'b1; + datamem_aswitch = 1'b1; + datamem_we = 1'b1; + bcounter_reset = 1'b0; + next_state = BURST4; + end + BURST4: begin + memorize_src_address = 1'b0; + use_memorized = 1'b1; + datamem_aswitch = 1'b1; + datamem_we = 1'b1; + + next_state = READOFFSET; + end + READOFFSET: begin + /* Before asserting the downstream data strobe, + * we need to read the Data Memory at the correct offset + * by deasserting datamem_aswitch. + */ + memorize_src_address = 1'b0; + use_memorized = 1'b1; + + next_state = WAIT_DOWNSTREAM; + end + FLUSH: begin + flushmode = 1'b1; + tagmem_we = 1'b1; + if(flush_last) + next_state = IDLE; + end + endcase +end + +/* Pass-through */ + +always @(posedge sys_clk) begin + if(pipe_stb_i & pipe_ack_o) + dst_addr1 = dst_addr; +end + +endmodule Index: rtl/tmu_scandiv.v =================================================================== --- rtl/tmu_scandiv.v (nonexistent) +++ rtl/tmu_scandiv.v (revision 7) @@ -0,0 +1,141 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_scandiv( + input sys_clk, + input sys_rst, + + output busy, + + input pipe_stb_i, + output reg pipe_ack_o, + input [10:0] Y0, + input [10:0] S_X0, + input [10:0] S_U0, + input [10:0] S_V0, + input [10:0] E_X0, + input du0_positive, + input [10:0] du0, + input dv0_positive, + input [10:0] dv0, + input [10:0] divisor0, + + output reg pipe_stb_o, + input pipe_ack_i, + output reg [10:0] Y, + output reg [10:0] S_X, + output reg [10:0] S_U, + output reg [10:0] S_V, + output reg [10:0] E_X, + output reg du_positive, + output [10:0] du_q, + output [10:0] du_r, + output reg dv_positive, + output [10:0] dv_q, + output [10:0] dv_r, + output reg [10:0] divisor +); + +/* Divider bank */ + +reg start; +wire ready; + +tmu_divider11 d_du( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .start(start), + .dividend(du0), + .divisor(divisor0), + + .ready(ready), + .quotient(du_q), + .remainder(du_r) +); +tmu_divider11 d_dv( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .start(start), + .dividend(dv0), + .divisor(divisor0), + + .ready(), + .quotient(dv_q), + .remainder(dv_r) +); + +/* Pipeline pass-through */ + +always @(posedge sys_clk) begin + if(start) begin + Y <= Y0; + S_X <= S_X0; + S_U <= S_U0; + S_V <= S_V0; + E_X <= E_X0; + du_positive <= du0_positive; + dv_positive <= dv0_positive; + divisor <= divisor0; + end +end + +/* Glue logic */ + +reg state; +reg next_state; + +parameter IDLE = 1'b0; +parameter WAIT = 1'b1; + +always @(posedge sys_clk) begin + if(sys_rst) + state = IDLE; + else + state = next_state; +end + +assign busy = state; + +always @(*) begin + next_state = state; + + start = 1'b0; + pipe_stb_o = 1'b0; + pipe_ack_o = 1'b0; + + case(state) + IDLE: begin + pipe_ack_o = 1'b1; + if(pipe_stb_i) begin + start = 1'b1; + next_state = WAIT; + end + end + WAIT: begin + if(ready) begin + pipe_stb_o = 1'b1; + if(pipe_ack_i) + next_state = IDLE; + end + end + endcase +end + +endmodule Index: rtl/tmu_divider11.v =================================================================== --- rtl/tmu_divider11.v (nonexistent) +++ rtl/tmu_divider11.v (revision 7) @@ -0,0 +1,66 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +/* 11-bit, 11-cycle integer divider, non pipelined */ + +module tmu_divider11( + input sys_clk, + input sys_rst, + + input start, + input [10:0] dividend, + input [10:0] divisor, + + output ready, + output [10:0] quotient, + output [10:0] remainder +); + +reg [21:0] qr; + +assign remainder = qr[21:11]; +assign quotient = qr[10:0]; + +reg [3:0] counter; +assign ready = (counter == 4'd0); + +reg [10:0] divisor_r; + +wire [11:0] diff = qr[21:10] - {1'b0, divisor_r}; + +always @(posedge sys_clk) begin + if(sys_rst) + counter = 4'd0; + else begin + if(start) begin + counter = 4'd11; + qr = {11'd0, dividend}; + divisor_r = divisor; + end else begin + if(~ready) begin + if(diff[11]) + qr = {qr[20:0], 1'b0}; + else + qr = {diff[10:0], qr[9:0], 1'b1}; + counter = counter - 4'd1; + end + end + end +end + +endmodule Index: rtl/tmu_pixout.v =================================================================== --- rtl/tmu_pixout.v (nonexistent) +++ rtl/tmu_pixout.v (revision 7) @@ -0,0 +1,148 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_pixout #( + parameter fml_depth = 26 +) ( + input sys_clk, + input sys_rst, + + output reg busy, + + input pipe_stb_i, + output reg pipe_ack_o, + input [fml_depth-5-1:0] burst_addr, + input [15:0] burst_sel, + input [255:0] burst_do, + + output reg [fml_depth-1:0] fml_adr, + output reg fml_stb, + input fml_ack, + output reg [7:0] fml_sel, + output reg [63:0] fml_do +); + +reg [15:0] burst_sel_r; +reg [255:0] burst_do_r; + +reg load; +always @(posedge sys_clk) begin + if(load) begin + fml_adr = {burst_addr, 5'd0}; + burst_sel_r = burst_sel; + burst_do_r = burst_do; + end +end + +reg [1:0] bcounter; +always @(posedge sys_clk) begin + case(bcounter) + 2'd0: begin + fml_sel <= { + burst_sel_r[15], burst_sel_r[15], + burst_sel_r[14], burst_sel_r[14], + burst_sel_r[13], burst_sel_r[13], + burst_sel_r[12], burst_sel_r[12] + }; + fml_do <= burst_do_r[255:192]; + end + 2'd1: begin + fml_sel <= { + burst_sel_r[11], burst_sel_r[11], + burst_sel_r[10], burst_sel_r[10], + burst_sel_r[ 9], burst_sel_r[ 9], + burst_sel_r[ 8], burst_sel_r[ 8] + }; + fml_do <= burst_do_r[191:128]; + end + 2'd2: begin + fml_sel <= { + burst_sel_r[ 7], burst_sel_r[ 7], + burst_sel_r[ 6], burst_sel_r[ 6], + burst_sel_r[ 5], burst_sel_r[ 5], + burst_sel_r[ 4], burst_sel_r[ 4] + }; + fml_do <= burst_do_r[127: 64]; + end + 2'd3: begin + fml_sel <= { + burst_sel_r[ 3], burst_sel_r[ 3], + burst_sel_r[ 2], burst_sel_r[ 2], + burst_sel_r[ 1], burst_sel_r[ 1], + burst_sel_r[ 0], burst_sel_r[ 0] + }; + fml_do <= burst_do_r[ 63: 0]; + end + endcase +end + +reg [1:0] state; +reg [1:0] next_state; + +parameter IDLE = 2'd0; +parameter WAIT = 2'd1; +parameter XFER2 = 2'd2; +parameter XFER3 = 2'd3; + +always @(posedge sys_clk) begin + if(sys_rst) + state <= IDLE; + else + state <= next_state; +end + +always @(*) begin + next_state = state; + + busy = 1'b1; + pipe_ack_o = 1'b0; + fml_stb = 1'b0; + + load = 1'b0; + bcounter = 2'bxx; + + case(state) + IDLE: begin + busy = 1'b0; + pipe_ack_o = 1'b1; + bcounter = 2'd0; + if(pipe_stb_i) begin + load = 1'b1; + next_state = WAIT; + end + end + WAIT: begin + fml_stb = 1'b1; + bcounter = 2'd0; + if(fml_ack) begin + bcounter = 2'd1; + next_state = XFER2; + end + end + XFER2: begin + bcounter = 2'd2; + next_state = XFER3; + end + XFER3: begin + bcounter = 2'd3; + next_state = IDLE; + end + endcase +end + +endmodule Index: rtl/tmu_edgedivops.v =================================================================== --- rtl/tmu_edgedivops.v (nonexistent) +++ rtl/tmu_edgedivops.v (revision 7) @@ -0,0 +1,189 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_edgedivops( + input sys_clk, + input sys_rst, + + output busy, + + input pipe_stb_i, + output pipe_ack_o, + input [10:0] A0_S_X, + input [10:0] A0_S_Y, + input [10:0] B0_S_X, + input [10:0] B0_S_Y, + input [10:0] C0_S_X, + input [10:0] C0_S_Y, + input [10:0] A0_D_X, + input [10:0] A0_D_Y, + input [10:0] B0_D_X, + input [10:0] B0_D_Y, + input [10:0] C0_D_X, + input [10:0] C0_D_Y, + + output pipe_stb_o, + input pipe_ack_i, + /* Points pass-through */ + output reg [10:0] A_S_X, + output reg [10:0] A_S_Y, + output reg [10:0] A_D_X, + output reg [10:0] A_D_Y, + output reg [10:0] B_D_Y, + output reg [10:0] C_D_Y, + + /* Dividends */ + output reg dx1_positive, + output reg [10:0] dx1, + output reg dx2_positive, + output reg [10:0] dx2, + output reg dx3_positive, + output reg [10:0] dx3, + + output reg du1_positive, + output reg [10:0] du1, + output reg du2_positive, + output reg [10:0] du2, + output reg du3_positive, + output reg [10:0] du3, + + output reg dv1_positive, + output reg [10:0] dv1, + output reg dv2_positive, + output reg [10:0] dv2, + output reg dv3_positive, + output reg [10:0] dv3, + + /* Common divisors */ + output reg [10:0] divisor1, + output reg [10:0] divisor2, + output reg [10:0] divisor3 +); + +wire en; +wire s0_valid; +reg s1_valid; + +always @(posedge sys_clk) begin + if(sys_rst) + s1_valid = 1'b0; + else if(en) + s1_valid = s0_valid; +end + +always @(posedge sys_clk) begin + if(en) begin + /* Find signs (whether we will increment or decrement later on) */ + dx1_positive = B0_D_X > A0_D_X; + dx2_positive = C0_D_X > A0_D_X; + dx3_positive = C0_D_X > B0_D_X; + + du1_positive = B0_S_X > A0_S_X; + du2_positive = C0_S_X > A0_S_X; + du3_positive = C0_S_X > B0_S_X; + + dv1_positive = B0_S_Y > A0_S_Y; + dv2_positive = C0_S_Y > A0_S_Y; + dv3_positive = C0_S_Y > B0_S_Y; + + /* First edge */ + if(dx1_positive) + dx1 = B0_D_X - A0_D_X; + else + dx1 = A0_D_X - B0_D_X; + if(du1_positive) + du1 = B0_S_X - A0_S_X; + else + du1 = A0_S_X - B0_S_X; + if(dv1_positive) + dv1 = B0_S_Y - A0_S_Y; + else + dv1 = A0_S_Y - B0_S_Y; + if(B0_D_Y != A0_D_Y) + divisor1 = B0_D_Y - A0_D_Y; + else + divisor1 = 11'd1; + + /* Second edge */ + if(C0_D_Y != A0_D_Y) begin + if(dx2_positive) + dx2 = C0_D_X - A0_D_X; + else + dx2 = A0_D_X - C0_D_X; + if(du2_positive) + du2 = C0_S_X - A0_S_X; + else + du2 = A0_S_X - C0_S_X; + if(dv2_positive) + dv2 = C0_S_Y - A0_S_Y; + else + dv2 = A0_S_Y - C0_S_Y; + divisor2 = C0_D_Y - A0_D_Y; + end else begin + dx2 = 11'd0; + du2 = 11'd0; + dv2 = 11'd0; + divisor2 = 11'd1; + end + + /* Third edge */ + if(C0_D_Y != B0_D_Y) begin + if(dx3_positive) + dx3 = C0_D_X - B0_D_X; + else + dx3 = B0_D_X - C0_D_X; + if(du3_positive) + du3 = C0_S_X - B0_S_X; + else + du3 = B0_S_X - C0_S_X; + if(dv3_positive) + dv3 = C0_S_Y - B0_S_Y; + else + dv3 = B0_S_Y - C0_S_Y; + divisor3 = C0_D_Y - B0_D_Y; + end else begin + dx3 = 11'd0; + du3 = 11'd0; + dv3 = 11'd0; + divisor3 = 11'd1; + end + end +end + +always @(posedge sys_clk) begin + if(en) begin + A_S_X <= A0_S_X; + A_S_Y <= A0_S_Y; + A_D_X <= A0_D_X; + A_D_Y <= A0_D_Y; + B_D_Y <= B0_D_Y; + C_D_Y <= C0_D_Y; + end +end + +/* Pipeline management */ + +assign busy = s1_valid; + +assign s0_valid = pipe_stb_i; +assign pipe_ack_o = pipe_ack_i; + +assign en = pipe_ack_i; +assign pipe_stb_o = s1_valid; + +endmodule Index: rtl/tmu_burst.v =================================================================== --- rtl/tmu_burst.v (nonexistent) +++ rtl/tmu_burst.v (revision 7) @@ -0,0 +1,166 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_burst #( + parameter fml_depth = 26 +) ( + input sys_clk, + input sys_rst, + + input flush, + output reg busy, + + input pipe_stb_i, + output pipe_ack_o, + input [15:0] src_pixel_d, + input [fml_depth-1-1:0] dst_addr, /* in 16-bit words */ + + output reg pipe_stb_o, + input pipe_ack_i, + output reg [fml_depth-5-1:0] burst_addr, /* in 256-bit words */ + /* 16-bit granularity selection that needs to be expanded + * to 8-bit granularity selection to drive the FML lines. + */ + output reg [15:0] burst_sel, + output reg [255:0] burst_do +); + +wire burst_hit = dst_addr[fml_depth-1-1:4] == burst_addr; + +/* Always memorize input in case we have to ack a cycle we cannot immediately handle */ +reg [15:0] src_pixel_d_r; +reg [fml_depth-1-1:0] dst_addr_r; +always @(posedge sys_clk) begin + if(pipe_stb_i & pipe_ack_o) begin + src_pixel_d_r <= src_pixel_d; + dst_addr_r <= dst_addr; + end +end + +/* Write to the burst storage registers */ +reg clear_en; +reg write_en; +reg use_memorized; +wire [15:0] src_pixel_d_mux = use_memorized ? src_pixel_d_r : src_pixel_d; +wire [fml_depth-1-1:0] dst_addr_mux = use_memorized ? dst_addr_r : dst_addr; +always @(posedge sys_clk) begin + if(sys_rst) + burst_sel = 16'd0; + else begin + if(clear_en) + burst_sel = 16'd0; + if(write_en) begin + burst_addr = dst_addr_mux[fml_depth-1-1:4]; /* update tag */ + case(dst_addr_mux[3:0]) /* unmask */ + 4'd00: burst_sel = burst_sel | 16'h8000; + 4'd01: burst_sel = burst_sel | 16'h4000; + 4'd02: burst_sel = burst_sel | 16'h2000; + 4'd03: burst_sel = burst_sel | 16'h1000; + 4'd04: burst_sel = burst_sel | 16'h0800; + 4'd05: burst_sel = burst_sel | 16'h0400; + 4'd06: burst_sel = burst_sel | 16'h0200; + 4'd07: burst_sel = burst_sel | 16'h0100; + 4'd08: burst_sel = burst_sel | 16'h0080; + 4'd09: burst_sel = burst_sel | 16'h0040; + 4'd10: burst_sel = burst_sel | 16'h0020; + 4'd11: burst_sel = burst_sel | 16'h0010; + 4'd12: burst_sel = burst_sel | 16'h0008; + 4'd13: burst_sel = burst_sel | 16'h0004; + 4'd14: burst_sel = burst_sel | 16'h0002; + 4'd15: burst_sel = burst_sel | 16'h0001; + endcase + case(dst_addr_mux[3:0]) /* register data */ + 4'd00: burst_do[255:240] = src_pixel_d_mux; + 4'd01: burst_do[239:224] = src_pixel_d_mux; + 4'd02: burst_do[223:208] = src_pixel_d_mux; + 4'd03: burst_do[207:192] = src_pixel_d_mux; + 4'd04: burst_do[191:176] = src_pixel_d_mux; + 4'd05: burst_do[175:160] = src_pixel_d_mux; + 4'd06: burst_do[159:144] = src_pixel_d_mux; + 4'd07: burst_do[143:128] = src_pixel_d_mux; + 4'd08: burst_do[127:112] = src_pixel_d_mux; + 4'd09: burst_do[111: 96] = src_pixel_d_mux; + 4'd10: burst_do[ 95: 80] = src_pixel_d_mux; + 4'd11: burst_do[ 79: 64] = src_pixel_d_mux; + 4'd12: burst_do[ 63: 48] = src_pixel_d_mux; + 4'd13: burst_do[ 47: 32] = src_pixel_d_mux; + 4'd14: burst_do[ 31: 16] = src_pixel_d_mux; + 4'd15: burst_do[ 15: 0] = src_pixel_d_mux; + endcase + end + end +end + +wire empty = (burst_sel == 16'd0); + +reg state; +reg next_state; + +parameter RUNNING = 1'b0; +parameter DOWNSTREAM = 1'b1; + +always @(posedge sys_clk) begin + if(sys_rst) + state <= RUNNING; + else + state <= next_state; +end + +/* + * generate pipe_ack_o using an assign statement to work around a bug in CVER + */ + +assign pipe_ack_o = (state == RUNNING) & (~flush | empty); + +always @(*) begin + next_state = state; + busy = 1'b1; + // CVER WA (see above) pipe_ack_o = 1'b0; + pipe_stb_o = 1'b0; + write_en = 1'b0; + clear_en = 1'b0; + use_memorized = 1'b0; + + case(state) + RUNNING: begin + busy = 1'b0; + if(flush & ~empty) + next_state = DOWNSTREAM; + else begin + // CVER WA (see above) pipe_ack_o = 1'b1; + if(pipe_stb_i) begin + if(burst_hit | empty) + write_en = 1'b1; + else + next_state = DOWNSTREAM; + end + end + end + DOWNSTREAM: begin + pipe_stb_o = 1'b1; + use_memorized = 1'b1; + if(pipe_ack_i) begin + clear_en = 1'b1; + write_en = 1'b1; + next_state = RUNNING; + end + end + endcase +end + +endmodule Index: rtl/tmu_ctlif.v =================================================================== --- rtl/tmu_ctlif.v (nonexistent) +++ rtl/tmu_ctlif.v (revision 7) @@ -0,0 +1,168 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_ctlif #( + parameter csr_addr = 4'h0, + parameter fml_depth = 26 +) ( + input sys_clk, + input sys_rst, + + input [13:0] csr_a, + input csr_we, + input [31:0] csr_di, + output reg [31:0] csr_do, + + output reg irq, + + output reg start, + input busy, + + output reg [29:0] mesh_base, /* in 32-bit words */ + output reg [6:0] hmesh_count, + output reg [6:0] hmesh_size, + output reg [6:0] vmesh_count, + output reg [6:0] vmesh_size, + + output reg [fml_depth-1-1:0] src_base, /* in 16-bit words */ + output reg [10:0] src_hres, + output reg [10:0] src_vres, + + output reg [fml_depth-1-1:0] dst_base, /* in 16-bit words */ + output reg [10:0] dst_hres, + output reg [10:0] dst_vres, + output reg [10:0] hoffset, + output reg [10:0] voffset, + + output reg [5:0] brightness, + + input [31:0] perf_pixels, + input [31:0] perf_clocks, + input [31:0] perf_stall1, + input [31:0] perf_complete1, + input [31:0] perf_stall2, + input [31:0] perf_complete2, + input [31:0] perf_misses +); + +reg old_busy; +always @(posedge sys_clk) begin + if(sys_rst) + old_busy <= 1'b0; + else + old_busy <= busy; +end + +wire trigger_irq = old_busy & ~busy; + +wire csr_selected = csr_a[13:10] == csr_addr; + +always @(posedge sys_clk) begin + if(sys_rst) begin + csr_do <= 32'd0; + irq <= 1'b0; + start <= 1'b0; + + mesh_base <= 30'd0; + hmesh_count <= 7'd32; + hmesh_size <= 7'd20; + vmesh_count <= 7'd24; + vmesh_size <= 7'd20; + + src_base <= {fml_depth{1'b0}}; + src_hres <= 11'd640; + src_vres <= 11'd480; + + dst_base <= {fml_depth{1'b0}}; + dst_hres <= 11'd640; + dst_vres <= 11'd480; + hoffset <= 11'd0; + voffset <= 11'd0; + + brightness <= 6'd63; + end else begin + if(trigger_irq) irq <= 1'b1; + + csr_do <= 32'd0; + start <= 1'b0; + if(csr_selected) begin + if(csr_we) begin + case(csr_a[3:0]) + 4'b0000: begin + start <= csr_di[0]; + irq <= 1'b0; + end + + 4'b0001: mesh_base <= csr_di[31:2]; + 4'b0010: hmesh_count <= csr_di[6:0]; + 4'b0011: hmesh_size <= csr_di[6:0]; + 4'b0100: vmesh_count <= csr_di[6:0]; + 4'b0101: vmesh_size <= csr_di[6:0]; + + 4'b0110: src_base <= csr_di[fml_depth-1:1]; + 4'b0111: src_hres <= csr_di[10:0]; + 4'b1000: src_vres <= csr_di[10:0]; + + 4'b1001: dst_base <= csr_di[fml_depth-1:1]; + 4'b1010: dst_hres <= csr_di[10:0]; + 4'b1011: dst_vres <= csr_di[10:0]; + 4'b1100: hoffset <= csr_di[10:0]; + 4'b1101: voffset <= csr_di[10:0]; + + 4'b1110: brightness <= csr_di[5:0]; + default:; + endcase + end + case(csr_a[4:0]) + 5'b00000: csr_do <= {irq, busy}; + + 5'b00001: csr_do <= {mesh_base, 2'b00}; + 5'b00010: csr_do <= hmesh_count; + 5'b00011: csr_do <= hmesh_size; + 5'b00100: csr_do <= vmesh_count; + 5'b00101: csr_do <= vmesh_size; + + 5'b00110: csr_do <= {src_base, 1'b0}; + 5'b00111: csr_do <= src_hres; + 5'b01000: csr_do <= src_vres; + + 5'b01001: csr_do <= {dst_base, 1'b0}; + 5'b01010: csr_do <= dst_hres; + 5'b01011: csr_do <= dst_vres; + 5'b01100: csr_do <= hoffset; + 5'b01101: csr_do <= voffset; + + 5'b01110: csr_do <= brightness; + + /* Performance counters */ + 5'b10000: csr_do <= perf_pixels; + 5'b10001: csr_do <= perf_clocks; + + 5'b10010: csr_do <= perf_stall1; + 5'b10011: csr_do <= perf_complete1; + 5'b10100: csr_do <= perf_stall2; + 5'b10101: csr_do <= perf_complete2; + + 5'b10110: csr_do <= perf_misses; + default: csr_do <= 32'bx; + endcase + end + end +end + +endmodule Index: rtl/tmu_reorder.v =================================================================== --- rtl/tmu_reorder.v (nonexistent) +++ rtl/tmu_reorder.v (revision 7) @@ -0,0 +1,224 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_reorder( + input sys_clk, + input sys_rst, + + output busy, + + input pipe_stb_i, + output pipe_ack_o, + input [10:0] A0_S_X, + input [10:0] A0_S_Y, + input [10:0] B0_S_X, + input [10:0] B0_S_Y, + input [10:0] C0_S_X, + input [10:0] C0_S_Y, + input [10:0] A0_D_X, + input [10:0] A0_D_Y, + input [10:0] B0_D_X, + input [10:0] B0_D_Y, + input [10:0] C0_D_X, + input [10:0] C0_D_Y, + + output pipe_stb_o, + input pipe_ack_i, + output reg [10:0] A_S_X, + output reg [10:0] A_S_Y, + output reg [10:0] B_S_X, + output reg [10:0] B_S_Y, + output reg [10:0] C_S_X, + output reg [10:0] C_S_Y, + output reg [10:0] A_D_X, + output reg [10:0] A_D_Y, + output reg [10:0] B_D_X, + output reg [10:0] B_D_Y, + output reg [10:0] C_D_X, + output reg [10:0] C_D_Y +); + +/* + * See http://www.geocities.com/wronski12/3d_tutor/tri_fillers.html + * The purpose of this module is to reorder the destination triangle + * points so that A_Y <= B_Y <= C_Y + */ + +wire en; + +/* Stage 1: Compare Y coordinates */ +wire s0_valid; +reg s1_valid; +reg s1_A_over_B; +reg s1_A_over_C; +reg s1_B_over_A; +reg s1_B_over_C; +reg s1_C_over_A; +reg s1_C_over_B; +reg [10:0] s1_A_S_X; +reg [10:0] s1_A_S_Y; +reg [10:0] s1_B_S_X; +reg [10:0] s1_B_S_Y; +reg [10:0] s1_C_S_X; +reg [10:0] s1_C_S_Y; +reg [10:0] s1_A_D_X; +reg [10:0] s1_A_D_Y; +reg [10:0] s1_B_D_X; +reg [10:0] s1_B_D_Y; +reg [10:0] s1_C_D_X; +reg [10:0] s1_C_D_Y; + +always @(posedge sys_clk) begin + if(sys_rst) + s1_valid <= 1'b0; + else if(en) + s1_valid <= s0_valid; +end + +always @(posedge sys_clk) begin + if(en) begin + s1_A_over_B <= (A0_D_Y <= B0_D_Y); + s1_A_over_C <= (A0_D_Y <= C0_D_Y); + s1_B_over_A <= (B0_D_Y <= A0_D_Y); + s1_B_over_C <= (B0_D_Y <= C0_D_Y); + s1_C_over_A <= (C0_D_Y <= A0_D_Y); + s1_C_over_B <= (C0_D_Y <= B0_D_Y); + + s1_A_S_X <= A0_S_X; + s1_A_S_Y <= A0_S_Y; + s1_B_S_X <= B0_S_X; + s1_B_S_Y <= B0_S_Y; + s1_C_S_X <= C0_S_X; + s1_C_S_Y <= C0_S_Y; + s1_A_D_X <= A0_D_X; + s1_A_D_Y <= A0_D_Y; + s1_B_D_X <= B0_D_X; + s1_B_D_Y <= B0_D_Y; + s1_C_D_X <= C0_D_X; + s1_C_D_Y <= C0_D_Y; + end +end + +/* Stage 2: Make the point order choice and mux accordingly. */ +reg s2_valid; + +always @(posedge sys_clk) begin + if(sys_rst) + s2_valid <= 1'b0; + else if(en) + s2_valid <= s1_valid; +end + +always @(posedge sys_clk) begin + if(en) begin + if(s1_A_over_B & s1_A_over_C) begin + A_S_X <= s1_A_S_X; + A_S_Y <= s1_A_S_Y; + A_D_X <= s1_A_D_X; + A_D_Y <= s1_A_D_Y; + + if(s1_B_over_C) begin + B_S_X <= s1_B_S_X; + B_S_Y <= s1_B_S_Y; + B_D_X <= s1_B_D_X; + B_D_Y <= s1_B_D_Y; + + C_S_X <= s1_C_S_X; + C_S_Y <= s1_C_S_Y; + C_D_X <= s1_C_D_X; + C_D_Y <= s1_C_D_Y; + end else begin + B_S_X <= s1_C_S_X; + B_S_Y <= s1_C_S_Y; + B_D_X <= s1_C_D_X; + B_D_Y <= s1_C_D_Y; + + C_S_X <= s1_B_S_X; + C_S_Y <= s1_B_S_Y; + C_D_X <= s1_B_D_X; + C_D_Y <= s1_B_D_Y; + end + end else if(s1_B_over_A & s1_B_over_C) begin + A_S_X <= s1_B_S_X; + A_S_Y <= s1_B_S_Y; + A_D_X <= s1_B_D_X; + A_D_Y <= s1_B_D_Y; + + if(s1_A_over_C) begin + B_S_X <= s1_A_S_X; + B_S_Y <= s1_A_S_Y; + B_D_X <= s1_A_D_X; + B_D_Y <= s1_A_D_Y; + + C_S_X <= s1_C_S_X; + C_S_Y <= s1_C_S_Y; + C_D_X <= s1_C_D_X; + C_D_Y <= s1_C_D_Y; + end else begin + B_S_X <= s1_C_S_X; + B_S_Y <= s1_C_S_Y; + B_D_X <= s1_C_D_X; + B_D_Y <= s1_C_D_Y; + + C_S_X <= s1_A_S_X; + C_S_Y <= s1_A_S_Y; + C_D_X <= s1_A_D_X; + C_D_Y <= s1_A_D_Y; + end + end else begin /* s1_C_over_A & s1_C_over_B */ + A_S_X <= s1_C_S_X; + A_S_Y <= s1_C_S_Y; + A_D_X <= s1_C_D_X; + A_D_Y <= s1_C_D_Y; + + if(s1_A_over_B) begin + B_S_X <= s1_A_S_X; + B_S_Y <= s1_A_S_Y; + B_D_X <= s1_A_D_X; + B_D_Y <= s1_A_D_Y; + + C_S_X <= s1_B_S_X; + C_S_Y <= s1_B_S_Y; + C_D_X <= s1_B_D_X; + C_D_Y <= s1_B_D_Y; + end else begin + B_S_X <= s1_B_S_X; + B_S_Y <= s1_B_S_Y; + B_D_X <= s1_B_D_X; + B_D_Y <= s1_B_D_Y; + + C_S_X <= s1_A_S_X; + C_S_Y <= s1_A_S_Y; + C_D_X <= s1_A_D_X; + C_D_Y <= s1_A_D_Y; + end + end + end +end + +/* Pipeline management */ + +assign busy = s1_valid|s2_valid; + +assign s0_valid = pipe_stb_i; +assign pipe_ack_o = pipe_ack_i; + +assign en = pipe_ack_i; +assign pipe_stb_o = s2_valid; + +endmodule Index: rtl/tmu_scantrace.v =================================================================== --- rtl/tmu_scantrace.v (nonexistent) +++ rtl/tmu_scantrace.v (revision 7) @@ -0,0 +1,175 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_scantrace( + input sys_clk, + input sys_rst, + + output busy, + + input pipe_stb_i, + output pipe_ack_o, + input [10:0] Y, + input [10:0] S_X, + input [10:0] S_U, + input [10:0] S_V, + input [10:0] E_X, + input du_positive, + input [10:0] du_q, + input [10:0] du_r, + input dv_positive, + input [10:0] dv_q, + input [10:0] dv_r, + input [10:0] divisor, + + output pipe_stb_o, + input pipe_ack_i, + output reg [10:0] P_X, + output reg [10:0] P_Y, + output reg [10:0] P_U, + output reg [10:0] P_V +); + +reg load; + +/* Register some inputs */ +reg [10:0] E_X_r; +reg du_positive_r; +reg [10:0] du_q_r; +reg [10:0] du_r_r; +reg dv_positive_r; +reg [10:0] dv_q_r; +reg [10:0] dv_r_r; +reg [10:0] divisor_r; + +always @(posedge sys_clk) begin + if(load) begin + P_Y <= Y; + E_X_r <= E_X; + du_positive_r <= du_positive; + du_q_r <= du_q; + du_r_r <= du_r; + dv_positive_r <= dv_positive; + dv_q_r <= dv_q; + dv_r_r <= dv_r; + divisor_r <= divisor; + end +end + +/* Current point datapath */ +reg addD; +reg [11:0] errU; +reg correctU; +reg [11:0] errV; +reg correctV; +always @(posedge sys_clk) begin + if(load) begin + P_U = S_U; + errU = 12'd0; + P_V = S_V; + errV = 12'd0; + end else begin + if(addD) begin + errU = errU + du_r_r; + correctU = (errU[10:0] > {1'b0, divisor_r[10:1]}) & ~errU[11]; + if(du_positive_r) begin + P_U = P_U + du_q_r; + if(correctU) + P_U = P_U + 11'd1; + end else begin + P_U = P_U - du_q_r; + if(correctU) + P_U = P_U - 11'd1; + end + if(correctU) + errU = errU - {1'b0, divisor_r}; + + errV = errV + dv_r_r; + correctV = (errV[10:0] > {1'b0, divisor_r[10:1]}) & ~errV[11]; + if(dv_positive_r) begin + P_V = P_V + dv_q_r; + if(correctV) + P_V = P_V + 11'd1; + end else begin + P_V = P_V - dv_q_r; + if(correctV) + P_V = P_V - 11'd1; + end + if(correctV) + errV = errV - {1'b0, divisor_r}; + end + end +end + +/* X datapath */ +reg incX; +always @(posedge sys_clk) begin + if(load) + P_X <= S_X; + else if(incX) + P_X <= P_X + 11'd1; +end + +wire reachedE = (P_X == E_X_r); + +/* FSM-based controller */ + +reg state; +reg next_state; + +parameter IDLE = 1'b0; +parameter BUSY = 1'b1; + +always @(posedge sys_clk) begin + if(sys_rst) + state <= IDLE; + else + state <= next_state; +end + +assign busy = state; +assign pipe_ack_o = ~state; +assign pipe_stb_o = state; + +always @(*) begin + next_state = state; + load = 1'b0; + addD = 1'b0; + incX = 1'b0; + + case(state) + IDLE: begin + if(pipe_stb_i) begin + load = 1'b1; + next_state = BUSY; + end + end + BUSY: begin + if(pipe_ack_i) begin + if(reachedE) + next_state = IDLE; + else begin + incX = 1'b1; + addD = 1'b1; + end + end + end + endcase +end + +endmodule Index: rtl/tmu_edgediv.v =================================================================== --- rtl/tmu_edgediv.v (nonexistent) +++ rtl/tmu_edgediv.v (revision 7) @@ -0,0 +1,287 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_edgediv( + input sys_clk, + input sys_rst, + + output busy, + + input pipe_stb_i, + output reg pipe_ack_o, + /* Points pass-through */ + input [10:0] A0_S_X, + input [10:0] A0_S_Y, + input [10:0] A0_D_X, + input [10:0] A0_D_Y, + input [10:0] B0_D_Y, + input [10:0] C0_D_Y, + input dx10_positive, + input [10:0] dx10, + input dx20_positive, + input [10:0] dx20, + input dx30_positive, + input [10:0] dx30, + input du10_positive, + input [10:0] du10, + input du20_positive, + input [10:0] du20, + input du30_positive, + input [10:0] du30, + input dv10_positive, + input [10:0] dv10, + input dv20_positive, + input [10:0] dv20, + input dv30_positive, + input [10:0] dv30, + input [10:0] divisor10, + input [10:0] divisor20, + input [10:0] divisor30, + + output reg pipe_stb_o, + input pipe_ack_i, + output reg [10:0] A_S_X, + output reg [10:0] A_S_Y, + output reg [10:0] A_D_X, + output reg [10:0] A_D_Y, + output reg [10:0] B_D_Y, + output reg [10:0] C_D_Y, + + output reg dx1_positive, + output [10:0] dx1_q, + output [10:0] dx1_r, + output reg dx2_positive, + output [10:0] dx2_q, + output [10:0] dx2_r, + output reg dx3_positive, + output [10:0] dx3_q, + output [10:0] dx3_r, + + output reg du1_positive, + output [10:0] du1_q, + output [10:0] du1_r, + output reg du2_positive, + output [10:0] du2_q, + output [10:0] du2_r, + output reg du3_positive, + output [10:0] du3_q, + output [10:0] du3_r, + + output reg dv1_positive, + output [10:0] dv1_q, + output [10:0] dv1_r, + output reg dv2_positive, + output [10:0] dv2_q, + output [10:0] dv2_r, + output reg dv3_positive, + output [10:0] dv3_q, + output [10:0] dv3_r, + + /* Divisors pass-through (needed for Bresenham algorithm) */ + output reg [10:0] divisor1, + output reg [10:0] divisor2, + output reg [10:0] divisor3 +); + +/* Divider bank */ + +reg start; +wire ready; + +/* X (destination X) */ +tmu_divider11 d_dx1( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .start(start), + .dividend(dx10), + .divisor(divisor10), + + .ready(ready), + .quotient(dx1_q), + .remainder(dx1_r) +); +tmu_divider11 d_dx2( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .start(start), + .dividend(dx20), + .divisor(divisor20), + + .ready(), + .quotient(dx2_q), + .remainder(dx2_r) +); +tmu_divider11 d_dx3( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .start(start), + .dividend(dx30), + .divisor(divisor30), + + .ready(), + .quotient(dx3_q), + .remainder(dx3_r) +); + +/* U (source X) */ +tmu_divider11 d_du1( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .start(start), + .dividend(du10), + .divisor(divisor10), + + .ready(), + .quotient(du1_q), + .remainder(du1_r) +); +tmu_divider11 d_du2( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .start(start), + .dividend(du20), + .divisor(divisor20), + + .ready(), + .quotient(du2_q), + .remainder(du2_r) +); +tmu_divider11 d_du3( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .start(start), + .dividend(du30), + .divisor(divisor30), + + .ready(), + .quotient(du3_q), + .remainder(du3_r) +); + +/* V (source Y) */ +tmu_divider11 d_dv1( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .start(start), + .dividend(dv10), + .divisor(divisor10), + + .ready(), + .quotient(dv1_q), + .remainder(dv1_r) +); +tmu_divider11 d_dv2( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .start(start), + .dividend(dv20), + .divisor(divisor20), + + .ready(), + .quotient(dv2_q), + .remainder(dv2_r) +); +tmu_divider11 d_dv3( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .start(start), + .dividend(dv30), + .divisor(divisor30), + + .ready(), + .quotient(dv3_q), + .remainder(dv3_r) +); + +/* Pipeline pass-through */ + +always @(posedge sys_clk) begin + if(start) begin + A_S_X <= A0_S_X; + A_S_Y <= A0_S_Y; + A_D_X <= A0_D_X; + A_D_Y <= A0_D_Y; + B_D_Y <= B0_D_Y; + C_D_Y <= C0_D_Y; + dx1_positive <= dx10_positive; + dx2_positive <= dx20_positive; + dx3_positive <= dx30_positive; + du1_positive <= du10_positive; + du2_positive <= du20_positive; + du3_positive <= du30_positive; + dv1_positive <= dv10_positive; + dv2_positive <= dv20_positive; + dv3_positive <= dv30_positive; + divisor1 <= divisor10; + divisor2 <= divisor20; + divisor3 <= divisor30; + end +end + +/* Glue logic */ + +reg state; +reg next_state; + +parameter IDLE = 1'b0; +parameter WAIT = 1'b1; + +always @(posedge sys_clk) begin + if(sys_rst) + state = IDLE; + else + state = next_state; +end + +assign busy = state; + +always @(*) begin + next_state = state; + + start = 1'b0; + pipe_stb_o = 1'b0; + pipe_ack_o = 1'b0; + + case(state) + IDLE: begin + pipe_ack_o = 1'b1; + if(pipe_stb_i) begin + start = 1'b1; + next_state = WAIT; + end + end + WAIT: begin + if(ready) begin + pipe_stb_o = 1'b1; + if(pipe_ack_i) + next_state = IDLE; + end + end + endcase +end + +endmodule Index: rtl/tmu_scandivops.v =================================================================== --- rtl/tmu_scandivops.v (nonexistent) +++ rtl/tmu_scandivops.v (revision 7) @@ -0,0 +1,105 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_scandivops( + input sys_clk, + input sys_rst, + + output busy, + + input pipe_stb_i, + output pipe_ack_o, + input [10:0] Y0, + input [10:0] S_X0, + input [10:0] S_U0, + input [10:0] S_V0, + input [10:0] E_X0, + input [10:0] E_U0, + input [10:0] E_V0, + + output pipe_stb_o, + input pipe_ack_i, + /* Points pass-through */ + output reg [10:0] Y, + output reg [10:0] S_X, + output reg [10:0] S_U, + output reg [10:0] S_V, + output reg [10:0] E_X, + /* Dividends */ + output reg du_positive, + output reg [10:0] du, + output reg dv_positive, + output reg [10:0] dv, + /* Common divisor */ + output reg [10:0] divisor +); + +wire en; +wire s0_valid; +reg s1_valid; + +always @(posedge sys_clk) begin + if(sys_rst) + s1_valid = 1'b0; + else if(en) + s1_valid = s0_valid; +end + +always @(posedge sys_clk) begin + if(en) begin + /* Find signs (whether we will increment or decrement later on) */ + du_positive = E_U0 > S_U0; + dv_positive = E_V0 > S_V0; + + if(du_positive) + du = E_U0 - S_U0; + else + du = S_U0 - E_U0; + if(dv_positive) + dv = E_V0 - S_V0; + else + dv = S_V0 - E_V0; + + if(E_X0 != S_X0) + divisor = E_X0 - S_X0; + else + divisor = 11'd1; + end +end + +always @(posedge sys_clk) begin + if(en) begin + Y <= Y0; + S_X <= S_X0; + S_U <= S_U0; + S_V <= S_V0; + E_X <= E_X0; + end +end + +/* Pipeline management */ + +assign busy = s1_valid; + +assign s0_valid = pipe_stb_i; +assign pipe_ack_o = pipe_ack_i; + +assign en = pipe_ack_i; +assign pipe_stb_o = s1_valid; + +endmodule Index: rtl/tmu_addresses.v =================================================================== --- rtl/tmu_addresses.v (nonexistent) +++ rtl/tmu_addresses.v (revision 7) @@ -0,0 +1,94 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_addresses #( + parameter fml_depth = 26 +) ( + input sys_clk, + input sys_rst, + + output busy, + + input [fml_depth-1-1:0] src_base, /* in 16-bit words */ + input [10:0] src_hres, + input [fml_depth-1-1:0] dst_base, /* in 16-bit words */ + input [10:0] dst_hres, + + input pipe_stb_i, + output pipe_ack_o, + input [10:0] P_X, + input [10:0] P_Y, + input [10:0] P_U, + input [10:0] P_V, + + output pipe_stb_o, + input pipe_ack_i, + output reg [fml_depth-1-1:0] src_addr, /* in 16-bit words */ + output reg [fml_depth-1-1:0] dst_addr /* in 16-bit words */ +); + +wire en; +wire s0_valid; +reg s1_valid; +reg s2_valid; + +always @(posedge sys_clk) begin + if(sys_rst) begin + s1_valid <= 1'b0; + s2_valid <= 1'b0; + end else if(en) begin + s1_valid <= s0_valid; + s2_valid <= s1_valid; + end +end + +/* Pipeline MAC operation on two stages. + * The synthesis tool automatically retimes and pushes + * the registers into the hardwired fast DSP macros. + */ + +reg [fml_depth-1-1:0] s1_src_addr; +reg [fml_depth-1-1:0] s1_dst_addr; + +/* WA for strange behaviour/bug in Verilator 3.700 : + * if we directly put the multiplications in the + * reg assignments, it thinks the results are 11 bits... + */ +wire [21:0] s0_expanded_pv = src_hres*P_V; +wire [21:0] s0_expanded_py = dst_hres*P_Y; + +always @(posedge sys_clk) begin + if(en) begin + s1_src_addr <= src_base + {{fml_depth-22-1{1'b0}}, s0_expanded_pv} + {{fml_depth-11-1{1'b0}}, P_U}; + s1_dst_addr <= dst_base + {{fml_depth-22-1{1'b0}}, s0_expanded_py} + {{fml_depth-11-1{1'b0}}, P_X}; + src_addr <= s1_src_addr; + dst_addr <= s1_dst_addr; + end +end + +/* Pipeline management */ + +assign busy = s1_valid|s2_valid; + +assign s0_valid = pipe_stb_i; +assign pipe_ack_o = pipe_ack_i; + +assign en = pipe_ack_i; +assign pipe_stb_o = s2_valid; + +endmodule Index: rtl/tmu_perfcounters.v =================================================================== --- rtl/tmu_perfcounters.v (nonexistent) +++ rtl/tmu_perfcounters.v (revision 7) @@ -0,0 +1,92 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_perfcounters( + input sys_clk, + input sys_rst, + + input start, + input busy, + + input inc_pixels, + + input stb1, + input ack1, + + input stb2, + input ack2, + + input inc_misses, + + output reg [31:0] perf_pixels, + output reg [31:0] perf_clocks, + + output reg [31:0] perf_stall1, + output reg [31:0] perf_complete1, + output reg [31:0] perf_stall2, + output reg [31:0] perf_complete2, + + output reg [31:0] perf_misses +); + +always @(posedge sys_clk) begin + if(sys_rst|start) begin + perf_pixels <= 32'd0; + perf_clocks <= 32'd0; + end else begin + if(busy) perf_clocks <= perf_clocks + 32'd1; + if(inc_pixels) perf_pixels <= perf_pixels + 32'd1; + end +end + +always @(posedge sys_clk) begin + if(sys_rst|start) begin + perf_stall1 <= 32'd0; + perf_complete1 <= 32'd0; + end else begin + if(stb1) begin + if(ack1) + perf_complete1 <= perf_complete1 + 32'd1; + else + perf_stall1 <= perf_stall1 + 32'd1; + end + end +end + +always @(posedge sys_clk) begin + if(sys_rst|start) begin + perf_stall2 <= 32'd0; + perf_complete2 <= 32'd0; + end else begin + if(stb2) begin + if(ack2) + perf_complete2 <= perf_complete2 + 32'd1; + else + perf_stall2 <= perf_stall2 + 32'd1; + end + end +end + +always @(posedge sys_clk) begin + if(sys_rst|start) + perf_misses <= 32'd0; + else if(inc_misses) + perf_misses <= perf_misses + 32'd1; +end + +endmodule Index: rtl/tmu.v =================================================================== --- rtl/tmu.v (nonexistent) +++ rtl/tmu.v (revision 7) @@ -0,0 +1,906 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu #( + parameter csr_addr = 4'h0, + parameter fml_depth = 26, + parameter pixin_cache_depth = 12 /* 4kb cache */ +) ( + /* Global clock and reset signals */ + input sys_clk, + input sys_rst, + + /* Control interface */ + input [13:0] csr_a, + input csr_we, + input [31:0] csr_di, + output [31:0] csr_do, + + output irq, + + /* WB master - Mesh read. */ + output [31:0] wbm_adr_o, + output [2:0] wbm_cti_o, + output wbm_cyc_o, + output wbm_stb_o, + input wbm_ack_i, + input [31:0] wbm_dat_i, + + /* FML master - Pixel read. fml_we=0 is assumed. */ + output [fml_depth-1:0] fmlr_adr, + output fmlr_stb, + input fmlr_ack, + input [63:0] fmlr_di, + + /* FML master - Pixel write. fml_we=1 is assumed. */ + output [fml_depth-1:0] fmlw_adr, + output fmlw_stb, + input fmlw_ack, + output [7:0] fmlw_sel, + output [63:0] fmlw_do +); + +wire start; +reg busy; +wire [29:0] mesh_base; +wire [6:0] hmesh_count; +wire [6:0] hmesh_size; +wire [6:0] vmesh_count; +wire [6:0] vmesh_size; +wire [fml_depth-1-1:0] src_base; +wire [10:0] src_hres; +wire [10:0] src_vres; +wire [fml_depth-1-1:0] dst_base; +wire [10:0] dst_hres; +wire [10:0] dst_vres; +wire [10:0] hoffset; +wire [10:0] voffset; +wire [5:0] brightness; +wire [31:0] perf_pixels; +wire [31:0] perf_clocks; +wire [31:0] perf_stall1; +wire [31:0] perf_complete1; +wire [31:0] perf_stall2; +wire [31:0] perf_complete2; +wire [31:0] perf_misses; + +tmu_ctlif #( + .csr_addr(csr_addr), + .fml_depth(fml_depth) +) ctlif ( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .csr_a(csr_a), + .csr_we(csr_we), + .csr_di(csr_di), + .csr_do(csr_do), + + .irq(irq), + + .start(start), + .busy(busy), + .mesh_base(mesh_base), + .hmesh_count(hmesh_count), + .hmesh_size(hmesh_size), + .vmesh_count(vmesh_count), + .vmesh_size(vmesh_size), + .src_base(src_base), + .src_hres(src_hres), + .src_vres(src_vres), + .dst_base(dst_base), + .dst_hres(dst_hres), + .dst_vres(dst_vres), + .hoffset(hoffset), + .voffset(voffset), + .brightness(brightness), + + .perf_pixels(perf_pixels), + .perf_clocks(perf_clocks), + .perf_stall1(perf_stall1), + .perf_complete1(perf_complete1), + .perf_stall2(perf_stall2), + .perf_complete2(perf_complete2), + .perf_misses(perf_misses) +); + +/* Stage 1 - Fetch vertexes */ +wire meshgen_busy; +wire meshgen_pipe_stb; +wire meshgen_pipe_ack; +wire [10:0] A0_S_X; +wire [10:0] A0_S_Y; +wire [10:0] B0_S_X; +wire [10:0] B0_S_Y; +wire [10:0] C0_S_X; +wire [10:0] C0_S_Y; +wire [10:0] A0_D_X; +wire [10:0] A0_D_Y; +wire [10:0] B0_D_X; +wire [10:0] B0_D_Y; +wire [10:0] C0_D_X; +wire [10:0] C0_D_Y; + +tmu_meshgen meshgen( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .wbm_adr_o(wbm_adr_o), + .wbm_cti_o(wbm_cti_o), + .wbm_cyc_o(wbm_cyc_o), + .wbm_stb_o(wbm_stb_o), + .wbm_ack_i(wbm_ack_i), + .wbm_dat_i(wbm_dat_i), + + .start(start), + .busy(meshgen_busy), + + .mesh_base(mesh_base), + .hmesh_count(hmesh_count), + .hmesh_size(hmesh_size), + .vmesh_count(vmesh_count), + .vmesh_size(vmesh_size), + + .pipe_stb(meshgen_pipe_stb), + .pipe_ack(meshgen_pipe_ack), + .A_S_X(A0_S_X), + .A_S_Y(A0_S_Y), + .B_S_X(B0_S_X), + .B_S_Y(B0_S_Y), + .C_S_X(C0_S_X), + .C_S_Y(C0_S_Y), + .A_D_X(A0_D_X), + .A_D_Y(A0_D_Y), + .B_D_X(B0_D_X), + .B_D_Y(B0_D_Y), + .C_D_X(C0_D_X), + .C_D_Y(C0_D_Y) +); + +/* Stage 2 - Vertex reordering (A_D_Y <= B_D_Y <= C_D_Y) */ +wire reorder_busy; +wire reorder_pipe_stb; +wire reorder_pipe_ack; +wire [10:0] A_S_X; +wire [10:0] A_S_Y; +wire [10:0] B_S_X; +wire [10:0] B_S_Y; +wire [10:0] C_S_X; +wire [10:0] C_S_Y; +wire [10:0] A_D_X; +wire [10:0] A_D_Y; +wire [10:0] B_D_X; +wire [10:0] B_D_Y; +wire [10:0] C_D_X; +wire [10:0] C_D_Y; + +tmu_reorder reorder( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .busy(reorder_busy), + + .pipe_stb_i(meshgen_pipe_stb), + .pipe_ack_o(meshgen_pipe_ack), + .A0_S_X(A0_S_X), + .A0_S_Y(A0_S_Y), + .B0_S_X(B0_S_X), + .B0_S_Y(B0_S_Y), + .C0_S_X(C0_S_X), + .C0_S_Y(C0_S_Y), + .A0_D_X(A0_D_X), + .A0_D_Y(A0_D_Y), + .B0_D_X(B0_D_X), + .B0_D_Y(B0_D_Y), + .C0_D_X(C0_D_X), + .C0_D_Y(C0_D_Y), + + .pipe_stb_o(reorder_pipe_stb), + .pipe_ack_i(reorder_pipe_ack), + .A_S_X(A_S_X), + .A_S_Y(A_S_Y), + .B_S_X(B_S_X), + .B_S_Y(B_S_Y), + .C_S_X(C_S_X), + .C_S_Y(C_S_Y), + .A_D_X(A_D_X), + .A_D_Y(A_D_Y), + .B_D_X(B_D_X), + .B_D_Y(B_D_Y), + .C_D_X(C_D_X), + .C_D_Y(C_D_Y) +); + +/* Stage 3 - Compute edge division operands */ +wire edgedivops_busy; +wire edgedivops_pipe_stb; +wire edgedivops_pipe_ack; +wire [10:0] A1_S_X; +wire [10:0] A1_S_Y; +wire [10:0] A1_D_X; +wire [10:0] A1_D_Y; +wire [10:0] B1_D_Y; +wire [10:0] C1_D_Y; +wire dx10_positive; +wire [10:0] dx10; +wire dx20_positive; +wire [10:0] dx20; +wire dx30_positive; +wire [10:0] dx30; +wire du10_positive; +wire [10:0] du10; +wire du20_positive; +wire [10:0] du20; +wire du30_positive; +wire [10:0] du30; +wire dv10_positive; +wire [10:0] dv10; +wire dv20_positive; +wire [10:0] dv20; +wire dv30_positive; +wire [10:0] dv30; +wire [10:0] divisor10; +wire [10:0] divisor20; +wire [10:0] divisor30; + +tmu_edgedivops edgedivops( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .busy(edgedivops_busy), + + .pipe_stb_i(reorder_pipe_stb), + .pipe_ack_o(reorder_pipe_ack), + .A0_S_X(A_S_X), + .A0_S_Y(A_S_Y), + .B0_S_X(B_S_X), + .B0_S_Y(B_S_Y), + .C0_S_X(C_S_X), + .C0_S_Y(C_S_Y), + .A0_D_X(A_D_X), + .A0_D_Y(A_D_Y), + .B0_D_X(B_D_X), + .B0_D_Y(B_D_Y), + .C0_D_X(C_D_X), + .C0_D_Y(C_D_Y), + + .pipe_stb_o(edgedivops_pipe_stb), + .pipe_ack_i(edgedivops_pipe_ack), + .A_S_X(A1_S_X), + .A_S_Y(A1_S_Y), + .A_D_X(A1_D_X), + .A_D_Y(A1_D_Y), + .B_D_Y(B1_D_Y), + .C_D_Y(C1_D_Y), + .dx1_positive(dx10_positive), + .dx1(dx10), + .dx2_positive(dx20_positive), + .dx2(dx20), + .dx3_positive(dx30_positive), + .dx3(dx30), + .du1_positive(du10_positive), + .du1(du10), + .du2_positive(du20_positive), + .du2(du20), + .du3_positive(du30_positive), + .du3(du30), + .dv1_positive(dv10_positive), + .dv1(dv10), + .dv2_positive(dv20_positive), + .dv2(dv20), + .dv3_positive(dv30_positive), + .dv3(dv30), + .divisor1(divisor10), + .divisor2(divisor20), + .divisor3(divisor30) +); + +/* Stage 4 - Edge division */ +wire edgediv_busy; +wire edgediv_pipe_stb; +wire edgediv_pipe_ack; +wire [10:0] A2_S_X; +wire [10:0] A2_S_Y; +wire [10:0] A2_D_X; +wire [10:0] A2_D_Y; +wire [10:0] B2_D_Y; +wire [10:0] C2_D_Y; +wire dx1_positive; +wire [10:0] dx1_q; +wire [10:0] dx1_r; +wire dx2_positive; +wire [10:0] dx2_q; +wire [10:0] dx2_r; +wire dx3_positive; +wire [10:0] dx3_q; +wire [10:0] dx3_r; +wire du1_positive; +wire [10:0] du1_q; +wire [10:0] du1_r; +wire du2_positive; +wire [10:0] du2_q; +wire [10:0] du2_r; +wire du3_positive; +wire [10:0] du3_q; +wire [10:0] du3_r; +wire dv1_positive; +wire [10:0] dv1_q; +wire [10:0] dv1_r; +wire dv2_positive; +wire [10:0] dv2_q; +wire [10:0] dv2_r; +wire dv3_positive; +wire [10:0] dv3_q; +wire [10:0] dv3_r; +wire [10:0] divisor1; +wire [10:0] divisor2; +wire [10:0] divisor3; + +tmu_edgediv edgediv( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .busy(edgediv_busy), + + .pipe_stb_i(edgedivops_pipe_stb), + .pipe_ack_o(edgedivops_pipe_ack), + .A0_S_X(A1_S_X), + .A0_S_Y(A1_S_Y), + .A0_D_X(A1_D_X), + .A0_D_Y(A1_D_Y), + .B0_D_Y(B1_D_Y), + .C0_D_Y(C1_D_Y), + .dx10_positive(dx10_positive), + .dx10(dx10), + .dx20_positive(dx20_positive), + .dx20(dx20), + .dx30_positive(dx30_positive), + .dx30(dx30), + .du10_positive(du10_positive), + .du10(du10), + .du20_positive(du20_positive), + .du20(du20), + .du30_positive(du30_positive), + .du30(du30), + .dv10_positive(dv10_positive), + .dv10(dv10), + .dv20_positive(dv20_positive), + .dv20(dv20), + .dv30_positive(dv30_positive), + .dv30(dv30), + .divisor10(divisor10), + .divisor20(divisor20), + .divisor30(divisor30), + + .pipe_stb_o(edgediv_pipe_stb), + .pipe_ack_i(edgediv_pipe_ack), + .A_S_X(A2_S_X), + .A_S_Y(A2_S_Y), + .A_D_X(A2_D_X), + .A_D_Y(A2_D_Y), + .B_D_Y(B2_D_Y), + .C_D_Y(C2_D_Y), + .dx1_positive(dx1_positive), + .dx1_q(dx1_q), + .dx1_r(dx1_r), + .dx2_positive(dx2_positive), + .dx2_q(dx2_q), + .dx2_r(dx2_r), + .dx3_positive(dx3_positive), + .dx3_q(dx3_q), + .dx3_r(dx3_r), + .du1_positive(du1_positive), + .du1_q(du1_q), + .du1_r(du1_r), + .du2_positive(du2_positive), + .du2_q(du2_q), + .du2_r(du2_r), + .du3_positive(du3_positive), + .du3_q(du3_q), + .du3_r(du3_r), + .dv1_positive(dv1_positive), + .dv1_q(dv1_q), + .dv1_r(dv1_r), + .dv2_positive(dv2_positive), + .dv2_q(dv2_q), + .dv2_r(dv2_r), + .dv3_positive(dv3_positive), + .dv3_q(dv3_q), + .dv3_r(dv3_r), + .divisor1(divisor1), + .divisor2(divisor2), + .divisor3(divisor3) +); + +/* Stage 5 - Edge trace */ +wire edgetrace_busy; +wire edgetrace_pipe_stb; +wire edgetrace_pipe_ack; +wire [10:0] Y0; +wire [10:0] S_X0; +wire [10:0] S_U0; +wire [10:0] S_V0; +wire [10:0] E_X0; +wire [10:0] E_U0; +wire [10:0] E_V0; + +tmu_edgetrace edgetrace( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .busy(edgetrace_busy), + + .pipe_stb_i(edgediv_pipe_stb), + .pipe_ack_o(edgediv_pipe_ack), + .A_S_X(A2_S_X), + .A_S_Y(A2_S_Y), + .A_D_X(A2_D_X), + .A_D_Y(A2_D_Y), + .B_D_Y(B2_D_Y), + .C_D_Y(C2_D_Y), + .dx1_positive(dx1_positive), + .dx1_q(dx1_q), + .dx1_r(dx1_r), + .dx2_positive(dx2_positive), + .dx2_q(dx2_q), + .dx2_r(dx2_r), + .dx3_positive(dx3_positive), + .dx3_q(dx3_q), + .dx3_r(dx3_r), + .du1_positive(du1_positive), + .du1_q(du1_q), + .du1_r(du1_r), + .du2_positive(du2_positive), + .du2_q(du2_q), + .du2_r(du2_r), + .du3_positive(du3_positive), + .du3_q(du3_q), + .du3_r(du3_r), + .dv1_positive(dv1_positive), + .dv1_q(dv1_q), + .dv1_r(dv1_r), + .dv2_positive(dv2_positive), + .dv2_q(dv2_q), + .dv2_r(dv2_r), + .dv3_positive(dv3_positive), + .dv3_q(dv3_q), + .dv3_r(dv3_r), + .divisor1(divisor1), + .divisor2(divisor2), + .divisor3(divisor3), + + .pipe_stb_o(edgetrace_pipe_stb), + .pipe_ack_i(edgetrace_pipe_ack), + .Y(Y0), + .S_X(S_X0), + .S_U(S_U0), + .S_V(S_V0), + .E_X(E_X0), + .E_U(E_U0), + .E_V(E_V0) +); + +/* Stage 6 - Compute scanline division operands */ +wire scandivops_busy; +wire scandivops_pipe_stb; +wire scandivops_pipe_ack; +wire [10:0] Y; +wire [10:0] S_X; +wire [10:0] S_U; +wire [10:0] S_V; +wire [10:0] E_X; +wire du0_positive; +wire [10:0] du0; +wire dv0_positive; +wire [10:0] dv0; +wire [10:0] divisor0; + +tmu_scandivops scandivops( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .busy(scandivops_busy), + + .pipe_stb_i(edgetrace_pipe_stb), + .pipe_ack_o(edgetrace_pipe_ack), + .Y0(Y0), + .S_X0(S_X0), + .S_U0(S_U0), + .S_V0(S_V0), + .E_X0(E_X0), + .E_U0(E_U0), + .E_V0(E_V0), + + .pipe_stb_o(scandivops_pipe_stb), + .pipe_ack_i(scandivops_pipe_ack), + .Y(Y), + .S_X(S_X), + .S_U(S_U), + .S_V(S_V), + .E_X(E_X), + .du_positive(du0_positive), + .du(du0), + .dv_positive(dv0_positive), + .dv(dv0), + .divisor(divisor0) +); + +/* Stage 7 - Scanline division */ +wire scandiv_busy; +wire scandiv_pipe_stb; +wire scandiv_pipe_ack; +wire [10:0] Y1; +wire [10:0] S_X1; +wire [10:0] S_U1; +wire [10:0] S_V1; +wire [10:0] E_X1; +wire du_positive; +wire [10:0] du_q; +wire [10:0] du_r; +wire dv_positive; +wire [10:0] dv_q; +wire [10:0] dv_r; +wire [10:0] divisor; + +tmu_scandiv scandiv( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .busy(scandiv_busy), + + .pipe_stb_i(scandivops_pipe_stb), + .pipe_ack_o(scandivops_pipe_ack), + .Y0(Y), + .S_X0(S_X), + .S_U0(S_U), + .S_V0(S_V), + .E_X0(E_X), + .du0_positive(du0_positive), + .du0(du0), + .dv0_positive(dv0_positive), + .dv0(dv0), + .divisor0(divisor0), + + .pipe_stb_o(scandiv_pipe_stb), + .pipe_ack_i(scandiv_pipe_ack), + .Y(Y1), + .S_X(S_X1), + .S_U(S_U1), + .S_V(S_V1), + .E_X(E_X1), + .du_positive(du_positive), + .du_q(du_q), + .du_r(du_r), + .dv_positive(dv_positive), + .dv_q(dv_q), + .dv_r(dv_r), + .divisor(divisor) +); + +/* Stage 8 - Scanline trace */ +wire scantrace_busy; +wire scantrace_pipe_stb; +wire scantrace_pipe_ack; +wire [10:0] P_X; +wire [10:0] P_Y; +wire [10:0] P_U; +wire [10:0] P_V; + +tmu_scantrace scantrace( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .busy(scantrace_busy), + + .pipe_stb_i(scandiv_pipe_stb), + .pipe_ack_o(scandiv_pipe_ack), + .Y(Y1), + .S_X(S_X1), + .S_U(S_U1), + .S_V(S_V1), + .E_X(E_X1), + .du_positive(du_positive), + .du_q(du_q), + .du_r(du_r), + .dv_positive(dv_positive), + .dv_q(dv_q), + .dv_r(dv_r), + .divisor(divisor), + + .pipe_stb_o(scantrace_pipe_stb), + .pipe_ack_i(scantrace_pipe_ack), + .P_X(P_X), + .P_Y(P_Y), + .P_U(P_U), + .P_V(P_V) +); + +/* Stage 9 - Filter out off-screen points */ +wire filter_busy; +wire filter_pipe_stb; +wire filter_pipe_ack; +wire [10:0] P_Xf; +wire [10:0] P_Yf; +wire [10:0] P_Uf; +wire [10:0] P_Vf; + +tmu_filter filter( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .busy(filter_busy), + + .src_hres(src_hres), + .src_vres(src_vres), + .dst_hres(dst_hres), + .dst_vres(dst_vres), + .hoffset(hoffset), + .voffset(voffset), + + .pipe_stb_i(scantrace_pipe_stb), + .pipe_ack_o(scantrace_pipe_ack), + .P_X(P_X), + .P_Y(P_Y), + .P_U(P_U), + .P_V(P_V), + + .pipe_stb_o(filter_pipe_stb), + .pipe_ack_i(filter_pipe_ack), + .P_Xf(P_Xf), + .P_Yf(P_Yf), + .P_Uf(P_Uf), + .P_Vf(P_Vf) +); + +/* Stage 10 - Compute memory addresses */ +wire addresses_busy; +wire addresses_pipe_stb; +wire addresses_pipe_ack; +wire [fml_depth-1-1:0] src_addr; +wire [fml_depth-1-1:0] dst_addr; + +tmu_addresses #( + .fml_depth(fml_depth) +) addresses ( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .busy(addresses_busy), + + .src_base(src_base), + .src_hres(src_hres), + .dst_base(dst_base), + .dst_hres(dst_hres), + + .pipe_stb_i(filter_pipe_stb), + .pipe_ack_o(filter_pipe_ack), + .P_X(P_Xf), + .P_Y(P_Yf), + .P_U(P_Uf), + .P_V(P_Vf), + + .pipe_stb_o(addresses_pipe_stb), + .pipe_ack_i(addresses_pipe_ack), + .src_addr(src_addr), + .dst_addr(dst_addr) +); + +/* Stage 11 - Pixel input */ +wire pixin_busy; +wire pixin_pipe_stb; +wire pixin_pipe_ack; +wire [15:0] src_pixel; +wire [fml_depth-1-1:0] dst_addr1; +wire inc_misses; + +tmu_pixin #( + .fml_depth(fml_depth), + .cache_depth(pixin_cache_depth) +) pixin ( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .fml_adr(fmlr_adr), + .fml_stb(fmlr_stb), + .fml_ack(fmlr_ack), + .fml_di(fmlr_di), + + .flush(start), + .busy(pixin_busy), + + .pipe_stb_i(addresses_pipe_stb), + .pipe_ack_o(addresses_pipe_ack), + .src_addr(src_addr), + .dst_addr(dst_addr), + + .pipe_stb_o(pixin_pipe_stb), + .pipe_ack_i(pixin_pipe_ack), + .src_pixel(src_pixel), + .dst_addr1(dst_addr1), + + .inc_misses(inc_misses) +); + +/* Stage 12 - Apply decay effect */ +wire decay_busy; +wire decay_pipe_stb; +wire decay_pipe_ack; +wire [15:0] src_pixel_d; +wire [fml_depth-1-1:0] dst_addr2; + +tmu_decay #( + .fml_depth(fml_depth) +) decay ( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .busy(decay_busy), + + .brightness(brightness), + + .pipe_stb_i(pixin_pipe_stb), + .pipe_ack_o(pixin_pipe_ack), + .src_pixel(src_pixel), + .dst_addr(dst_addr1), + + .pipe_stb_o(decay_pipe_stb), + .pipe_ack_i(decay_pipe_ack), + .src_pixel_d(src_pixel_d), + .dst_addr1(dst_addr2) +); + +/* Stage 13 - Burst assembler */ +reg burst_flush; +wire burst_busy; +wire burst_pipe_stb; +wire burst_pipe_ack; +wire [fml_depth-5-1:0] burst_addr; +wire [15:0] burst_sel; +wire [255:0] burst_do; + +tmu_burst #( + .fml_depth(fml_depth) +) burst ( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .flush(burst_flush), + .busy(burst_busy), + + .pipe_stb_i(decay_pipe_stb), + .pipe_ack_o(decay_pipe_ack), + .src_pixel_d(src_pixel_d), + .dst_addr(dst_addr2), + + .pipe_stb_o(burst_pipe_stb), + .pipe_ack_i(burst_pipe_ack), + .burst_addr(burst_addr), + .burst_sel(burst_sel), + .burst_do(burst_do) +); + +/* Stage 14 - Pixel output */ +wire pixout_busy; + +tmu_pixout #( + .fml_depth(fml_depth) +) pixout ( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .busy(pixout_busy), + + .pipe_stb_i(burst_pipe_stb), + .pipe_ack_o(burst_pipe_ack), + .burst_addr(burst_addr), + .burst_sel(burst_sel), + .burst_do(burst_do), + + .fml_adr(fmlw_adr), + .fml_stb(fmlw_stb), + .fml_ack(fmlw_ack), + .fml_sel(fmlw_sel), + .fml_do(fmlw_do) +); + +/* FSM to flush the burst assembler at the end */ + +wire pipeline_busy = meshgen_busy|reorder_busy + |edgedivops_busy|edgediv_busy|edgetrace_busy + |scandivops_busy|scandiv_busy|scantrace_busy + |filter_busy|addresses_busy|pixin_busy + |decay_busy|burst_busy|pixout_busy; + +parameter IDLE = 2'd0; +parameter WAIT_PROCESS = 2'd1; +parameter FLUSH = 2'd2; +parameter WAIT_FLUSH = 2'd3; + +reg [1:0] state; +reg [1:0] next_state; + +always @(posedge sys_clk) begin + if(sys_rst) + state <= IDLE; + else + state <= next_state; +end + +always @(*) begin + next_state = state; + + busy = 1'b1; + burst_flush = 1'b0; + + case(state) + IDLE: begin + busy = 1'b0; + if(start) + next_state = WAIT_PROCESS; + end + WAIT_PROCESS: begin + if(~pipeline_busy) + next_state = FLUSH; + end + FLUSH: begin + burst_flush = 1'b1; + next_state = WAIT_FLUSH; + end + WAIT_FLUSH: begin + if(~pipeline_busy) + next_state = IDLE; + end + endcase +end + +/* Performance counters */ + +tmu_perfcounters perfcounters( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .start(start), + .busy(busy), + + /* When the filter puts out a pixel that is acked, + * this pixel will be drawn sooner or later. + * So counting the cycles with both these signals + * asserted gives the total number of traced pixels. + */ + .inc_pixels(filter_pipe_stb & filter_pipe_ack), + + /* Measure read efficiency */ + .stb1(filter_pipe_stb), + .ack1(filter_pipe_ack), + + /* Measure write efficiency */ + .stb2(decay_pipe_stb), + .ack2(decay_pipe_ack), + + .inc_misses(inc_misses), + + .perf_pixels(perf_pixels), + .perf_clocks(perf_clocks), + .perf_stall1(perf_stall1), + .perf_complete1(perf_complete1), + .perf_stall2(perf_stall2), + .perf_complete2(perf_complete2), + .perf_misses(perf_misses) +); + +endmodule Index: rtl/tmu_edgetrace.v =================================================================== --- rtl/tmu_edgetrace.v (nonexistent) +++ rtl/tmu_edgetrace.v (revision 7) @@ -0,0 +1,491 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_edgetrace( + input sys_clk, + input sys_rst, + + output reg busy, + + input pipe_stb_i, + output reg pipe_ack_o, + input [10:0] A_S_X, + input [10:0] A_S_Y, + input [10:0] A_D_X, + input [10:0] A_D_Y, + input [10:0] B_D_Y, + input [10:0] C_D_Y, + + input dx1_positive, + input [10:0] dx1_q, + input [10:0] dx1_r, + input dx2_positive, + input [10:0] dx2_q, + input [10:0] dx2_r, + input dx3_positive, + input [10:0] dx3_q, + input [10:0] dx3_r, + + input du1_positive, + input [10:0] du1_q, + input [10:0] du1_r, + input du2_positive, + input [10:0] du2_q, + input [10:0] du2_r, + input du3_positive, + input [10:0] du3_q, + input [10:0] du3_r, + + input dv1_positive, + input [10:0] dv1_q, + input [10:0] dv1_r, + input dv2_positive, + input [10:0] dv2_q, + input [10:0] dv2_r, + input dv3_positive, + input [10:0] dv3_q, + input [10:0] dv3_r, + + input [10:0] divisor1, + input [10:0] divisor2, + input [10:0] divisor3, + + output reg pipe_stb_o, + input pipe_ack_i, + output reg [10:0] Y, /* common Y coordinate */ + output reg [10:0] S_X, /* start point */ + output reg [10:0] S_U, + output reg [10:0] S_V, + output reg [10:0] E_X, /* end point */ + output reg [10:0] E_U, + output reg [10:0] E_V +); + +reg load; + +/* Register some inputs */ +reg [10:0] B_D_Y_r; +reg [10:0] C_D_Y_r; + +reg dx1_positive_r; +reg [10:0] dx1_q_r; +reg [10:0] dx1_r_r; +reg dx2_positive_r; +reg [10:0] dx2_q_r; +reg [10:0] dx2_r_r; +reg dx3_positive_r; +reg [10:0] dx3_q_r; +reg [10:0] dx3_r_r; +reg du1_positive_r; +reg [10:0] du1_q_r; +reg [10:0] du1_r_r; +reg du2_positive_r; +reg [10:0] du2_q_r; +reg [10:0] du2_r_r; +reg du3_positive_r; +reg [10:0] du3_q_r; +reg [10:0] du3_r_r; +reg dv1_positive_r; +reg [10:0] dv1_q_r; +reg [10:0] dv1_r_r; +reg dv2_positive_r; +reg [10:0] dv2_q_r; +reg [10:0] dv2_r_r; +reg dv3_positive_r; +reg [10:0] dv3_q_r; +reg [10:0] dv3_r_r; +reg [10:0] divisor1_r; +reg [10:0] divisor2_r; +reg [10:0] divisor3_r; +always @(posedge sys_clk) begin + if(load) begin + B_D_Y_r <= B_D_Y; + C_D_Y_r <= C_D_Y; + dx1_positive_r <= dx1_positive; + dx1_q_r <= dx1_q; + dx1_r_r <= dx1_r; + dx2_positive_r <= dx2_positive; + dx2_q_r <= dx2_q; + dx2_r_r <= dx2_r; + dx3_positive_r <= dx3_positive; + dx3_q_r <= dx3_q; + dx3_r_r <= dx3_r; + du1_positive_r <= du1_positive; + du1_q_r <= du1_q; + du1_r_r <= du1_r; + du2_positive_r <= du2_positive; + du2_q_r <= du2_q; + du2_r_r <= du2_r; + du3_positive_r <= du3_positive; + du3_q_r <= du3_q; + du3_r_r <= du3_r; + dv1_positive_r <= dv1_positive; + dv1_q_r <= dv1_q; + dv1_r_r <= dv1_r; + dv2_positive_r <= dv2_positive; + dv2_q_r <= dv2_q; + dv2_r_r <= dv2_r; + dv3_positive_r <= dv3_positive; + dv3_q_r <= dv3_q; + dv3_r_r <= dv3_r; + divisor1_r <= divisor1; + divisor2_r <= divisor2; + divisor3_r <= divisor3; + end +end + +/* Current points, with X's unordered */ +reg [10:0] I_X; +reg [10:0] I_U; +reg [10:0] I_V; +reg [10:0] J_X; +reg [10:0] J_U; +reg [10:0] J_V; + +/* Sort the points according to X's */ +always @(posedge sys_clk) begin + if(I_X < J_X) begin + S_X <= I_X; + S_U <= I_U; + S_V <= I_V; + E_X <= J_X; + E_U <= J_U; + E_V <= J_V; + end else begin + S_X <= J_X; + S_U <= J_U; + S_V <= J_V; + E_X <= I_X; + E_U <= I_U; + E_V <= I_V; + end +end + +/* See scantrace.v for a simpler version of the interpolation algorithm. + * Here, we only repeat it. + */ + +/* Current point datapath */ +/* control signals: */ +reg addDX1; /* add DX1 to J */ +reg addDX2; /* add DX2 to I */ +reg addDX3; /* add DX3 to J */ + +/* error accumulators: */ +reg [11:0] errIX2; +reg [11:0] errIU2; +reg [11:0] errIV2; +reg [11:0] errJX1; +reg [11:0] errJU1; +reg [11:0] errJV1; +reg [11:0] errJX3; +reg [11:0] errJU3; +reg [11:0] errJV3; + +/* intermediate variables: */ +reg correctJX1; +reg correctJU1; +reg correctJV1; +reg correctJX3; +reg correctJU3; +reg correctJV3; + +reg correctIX2; +reg correctIU2; +reg correctIV2; + +always @(posedge sys_clk) begin + if(load) begin + I_X = A_D_X; + I_U = A_S_X; + I_V = A_S_Y; + J_X = A_D_X; + J_U = A_S_X; + J_V = A_S_Y; + + errIX2 = 12'd0; + errIU2 = 12'd0; + errIV2 = 12'd0; + errJX1 = 12'd0; + errJU1 = 12'd0; + errJV1 = 12'd0; + errJX3 = 12'd0; + errJU3 = 12'd0; + errJV3 = 12'd0; + end else begin + /* J */ + if(addDX1) begin + errJX1 = errJX1 + dx1_r_r; + correctJX1 = (errJX1[10:0] > {1'b0, divisor1_r[10:1]}) & ~errJX1[11]; + if(dx1_positive_r) begin + J_X = J_X + dx1_q_r; + if(correctJX1) + J_X = J_X + 11'd1; + end else begin + J_X = J_X - dx1_q_r; + if(correctJX1) + J_X = J_X - 11'd1; + end + if(correctJX1) + errJX1 = errJX1 - {1'b0, divisor1_r}; + + errJU1 = errJU1 + du1_r_r; + correctJU1 = (errJU1[10:0] > {1'b0, divisor1_r[10:1]}) & ~errJU1[11]; + if(du1_positive_r) begin + J_U = J_U + du1_q_r; + if(correctJU1) + J_U = J_U + 11'd1; + end else begin + J_U = J_U - du1_q_r; + if(correctJU1) + J_U = J_U - 11'd1; + end + if(correctJU1) + errJU1 = errJU1 - {1'b0, divisor1_r}; + + errJV1 = errJV1 + dv1_r_r; + correctJV1 = (errJV1[10:0] > {1'b0, divisor1_r[10:1]}) & ~errJV1[11]; + if(dv1_positive_r) begin + J_V = J_V + dv1_q_r; + if(correctJV1) + J_V = J_V + 11'd1; + end else begin + J_V = J_V - dv1_q_r; + if(correctJV1) + J_V = J_V - 11'd1; + end + if(correctJV1) + errJV1 = errJV1 - {1'b0, divisor1_r}; + end else if(addDX3) begin + errJX3 = errJX3 + dx3_r_r; + correctJX3 = (errJX3[10:0] > {1'b0, divisor3_r[10:1]}) & ~errJX3[11]; + if(dx3_positive_r) begin + J_X = J_X + dx3_q_r; + if(correctJX3) + J_X = J_X + 11'd1; + end else begin + J_X = J_X - dx3_q_r; + if(correctJX3) + J_X = J_X - 11'd1; + end + if(correctJX3) + errJX3 = errJX3 - {1'b0, divisor3_r}; + + errJU3 = errJU3 + du3_r_r; + correctJU3 = (errJU3[10:0] > {1'b0, divisor3_r[10:1]}) & ~errJU3[11]; + if(du3_positive_r) begin + J_U = J_U + du3_q_r; + if(correctJU3) + J_U = J_U + 11'd1; + end else begin + J_U = J_U - du3_q_r; + if(correctJU3) + J_U = J_U - 11'd1; + end + if(correctJU3) + errJU3 = errJU3 - {1'b0, divisor3_r}; + + errJV3 = errJV3 + dv3_r_r; + correctJV3 = (errJV3[10:0] > {1'b0, divisor3_r[10:1]}) & ~errJV3[11]; + if(dv3_positive_r) begin + J_V = J_V + dv3_q_r; + if(correctJV3) + J_V = J_V + 11'd1; + end else begin + J_V = J_V - dv3_q_r; + if(correctJV3) + J_V = J_V - 11'd1; + end + if(correctJV3) + errJV3 = errJV3 - {1'b0, divisor3_r}; + end + /* I */ + if(addDX2) begin + errIX2 = errIX2 + dx2_r_r; + correctIX2 = (errIX2[10:0] > {1'b0, divisor2_r[10:1]}) & ~errIX2[11]; + if(dx2_positive_r) begin + I_X = I_X + dx2_q_r; + if(correctIX2) + I_X = I_X + 11'd1; + end else begin + I_X = I_X - dx2_q_r; + if(correctIX2) + I_X = I_X - 11'd1; + end + if(correctIX2) + errIX2 = errIX2 - {1'b0, divisor2_r}; + + errIU2 = errIU2 + du2_r_r; + correctIU2 = (errIU2[10:0] > {1'b0, divisor2_r[10:1]}) & ~errIU2[11]; + if(du2_positive_r) begin + I_U = I_U + du2_q_r; + if(correctIU2) + I_U = I_U + 11'd1; + end else begin + I_U = I_U - du2_q_r; + if(correctIU2) + I_U = I_U - 11'd1; + end + if(correctIU2) + errIU2 = errIU2 - {1'b0, divisor2_r}; + + errIV2 = errIV2 + dv2_r_r; + correctIV2 = (errIV2[10:0] > {1'b0, divisor2_r[10:1]}) & ~errIV2[11]; + if(dv2_positive_r) begin + I_V = I_V + dv2_q_r; + if(correctIV2) + I_V = I_V + 11'd1; + end else begin + I_V = I_V - dv2_q_r; + if(correctIV2) + I_V = I_V - 11'd1; + end + if(correctIV2) + errIV2 = errIV2 - {1'b0, divisor2_r}; + end + end +end + +/* Y datapath */ +reg incY; +always @(posedge sys_clk) begin + if(load) + Y <= A_D_Y; + else if(incY) + Y <= Y + 11'd1; +end + +wire reachedB = (Y == B_D_Y_r); +wire reachedC = (Y == C_D_Y_r); + +/* FSM-based controller */ + +reg [2:0] state; +reg [2:0] next_state; + +parameter IDLE = 3'd0; +parameter A_NEXT = 3'd1; +parameter A_PIPEOUT_WAIT = 3'd2; +parameter A_PIPEOUT = 3'd3; +parameter B_START = 3'd4; +parameter B_NEXT = 3'd5; +parameter B_PIPEOUT_WAIT = 3'd6; +parameter B_PIPEOUT = 3'd7; + +/* Register to handle the "AB horizontal" corner case properly */ +reg ABh; +reg next_ABh; + +always @(posedge sys_clk) + ABh <= next_ABh; + +always @(posedge sys_clk) begin + if(sys_rst) + state <= IDLE; + else + state <= next_state; +end + +always @(*) begin + next_state = state; + + busy = 1'b1; + + pipe_ack_o = 1'b0; + pipe_stb_o = 1'b0; + + load = 1'b0; + + addDX1 = 1'b0; + addDX2 = 1'b0; + addDX3 = 1'b0; + + incY = 1'b0; + + next_ABh = ABh; + + case(state) + IDLE: begin + busy = 1'b0; + pipe_ack_o = 1'b1; + next_ABh = 1'b1; + if(pipe_stb_i) begin + load = 1'b1; + next_state = A_PIPEOUT_WAIT; + end + end + /* We start the triangle by using factors 2 and 1 */ + A_NEXT: begin + addDX1 = 1'b1; + addDX2 = 1'b1; + next_ABh = 1'b0; + next_state = A_PIPEOUT_WAIT; + end + /* There is one cycle latency because the point must be sorted by X's + * (see the beginning of this file). + */ + A_PIPEOUT_WAIT: next_state = A_PIPEOUT; + A_PIPEOUT: begin + if(reachedB & ABh) begin + /* We reach B right from the beginning: AB is horizontal. + * In this case, the D1 factors have been set so that J becomes B + * in one step (we must enter state B_START with J=B). + */ + addDX1 = 1'b1; + next_state = B_START; + end else begin + pipe_stb_o = 1'b1; + if(pipe_ack_i) begin + if(reachedB) + next_state = B_START; + else begin + incY = 1'b1; + next_state = A_NEXT; + end + end + end + end + + /* Once we reach B, we use factors 2 and 3 */ + B_START: begin + if(reachedC) + next_state = IDLE; + else + next_state = B_PIPEOUT_WAIT; + end + B_NEXT: begin + addDX3 = 1'b1; + addDX2 = 1'b1; + next_state = B_PIPEOUT_WAIT; + end + B_PIPEOUT_WAIT: next_state = B_PIPEOUT; + B_PIPEOUT: begin + pipe_stb_o = 1'b1; + if(pipe_ack_i) begin + if(reachedC) + next_state = IDLE; + else begin + incY = 1'b1; + next_state = B_NEXT; + end + end + end + endcase +end + +endmodule Index: rtl/tmu_filter.v =================================================================== --- rtl/tmu_filter.v (nonexistent) +++ rtl/tmu_filter.v (revision 7) @@ -0,0 +1,79 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_filter( + input sys_clk, + input sys_rst, + + output busy, + + input [10:0] src_hres, + input [10:0] src_vres, + input [10:0] dst_hres, + input [10:0] dst_vres, + input [10:0] hoffset, + input [10:0] voffset, + + input pipe_stb_i, + output pipe_ack_o, + input [10:0] P_X, + input [10:0] P_Y, + input [10:0] P_U, + input [10:0] P_V, + + output pipe_stb_o, + input pipe_ack_i, + output reg [10:0] P_Xf, + output reg [10:0] P_Yf, + output reg [10:0] P_Uf, + output reg [10:0] P_Vf +); + +wire en; +wire s0_valid; +wire s1_valid; +reg s1_valid_r; + +always @(posedge sys_clk) begin + if(sys_rst) + s1_valid_r <= 1'b0; + else if(en) begin + if((P_X >= hoffset) & (P_Y >= voffset) & (P_U < src_hres) & (P_V < src_vres)) + s1_valid_r <= s0_valid; + else + s1_valid_r <= 1'b0; + P_Xf <= P_X - hoffset; + P_Yf <= P_Y - voffset; + P_Uf <= P_U; + P_Vf <= P_V; + end +end + +assign s1_valid = s1_valid_r & (P_Xf < dst_hres) & (P_Yf < dst_vres); + +/* Pipeline management */ + +assign busy = s1_valid; + +assign s0_valid = pipe_stb_i; +assign pipe_ack_o = pipe_ack_i; + +assign en = pipe_ack_i; +assign pipe_stb_o = s1_valid; + +endmodule Index: rtl/tmu_decay.v =================================================================== --- rtl/tmu_decay.v (nonexistent) +++ rtl/tmu_decay.v (revision 7) @@ -0,0 +1,132 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free and excepted software; you can use it, redistribute it + * and/or modify it under the terms of the Exception General Public License as + * published by the Exception License Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more + * details. + * + * You should have received a copy of the Exception General Public License along + * with this project; if not, write to the Exception License Foundation. + */ + +module tmu_decay #( + parameter fml_depth = 26 +) ( + input sys_clk, + input sys_rst, + + output busy, + + input [5:0] brightness, + + input pipe_stb_i, + output pipe_ack_o, + input [15:0] src_pixel, + input [fml_depth-1-1:0] dst_addr, + + output pipe_stb_o, + input pipe_ack_i, + output [15:0] src_pixel_d, + output reg [fml_depth-1-1:0] dst_addr1 +); + +wire en; +wire s0_valid; +reg s1_valid; +reg s2_valid; +reg s3_valid; + +always @(posedge sys_clk) begin + if(sys_rst) begin + s1_valid <= 1'b0; + s2_valid <= 1'b0; + s3_valid <= 1'b0; + end else if(en) begin + s1_valid <= s0_valid; + s2_valid <= s1_valid; + s3_valid <= s2_valid; + end +end + +/* Pipeline operation on three stages. */ + +reg [fml_depth-1-1:0] s1_dst_addr; +reg [fml_depth-1-1:0] s2_dst_addr; +/* third stage register is output */ + +reg s1_full_brightness; +reg s2_full_brightness; +reg s3_full_brightness; + +reg [15:0] s1_pixel_full; +reg [15:0] s2_pixel_full; +reg [15:0] s3_pixel_full; + +wire [5:0] brightness1 = brightness + 6'd1; +reg [5:0] s1_brightness1; + +wire [4:0] r = src_pixel[15:11]; +wire [5:0] g = src_pixel[10:5]; +wire [4:0] b = src_pixel[4:0]; + +reg [4:0] s1_r; +reg [5:0] s1_g; +reg [4:0] s1_b; + +reg [10:0] s2_r; +reg [11:0] s2_g; +reg [10:0] s2_b; + +reg [10:0] s3_r; +reg [11:0] s3_g; +reg [10:0] s3_b; + +always @(posedge sys_clk) begin + if(en) begin + s1_dst_addr <= dst_addr; + s2_dst_addr <= s1_dst_addr; + dst_addr1 <= s2_dst_addr; + + s1_full_brightness <= brightness == 6'b111111; + s2_full_brightness <= s1_full_brightness; + s3_full_brightness <= s2_full_brightness; + + s1_pixel_full <= src_pixel; + s2_pixel_full <= s1_pixel_full; + s3_pixel_full <= s2_pixel_full; + + s1_r <= r; + s1_g <= g; + s1_b <= b; + s1_brightness1 <= brightness1; + + s2_r <= s1_brightness1*s1_r; + s2_g <= s1_brightness1*s1_g; + s2_b <= s1_brightness1*s1_b; + + s3_r <= s2_r; + s3_g <= s2_g; + s3_b <= s2_b; + end +end + +assign src_pixel_d = s3_full_brightness ? s3_pixel_full : {s3_r[10:6], s3_g[11:6], s3_b[10:6]}; + +/* Pipeline management */ + +assign busy = s1_valid|s2_valid|s3_valid; + +assign s0_valid = pipe_stb_i; +assign pipe_ack_o = pipe_ack_i; + +assign en = pipe_ack_i; +assign pipe_stb_o = s3_valid; + +endmodule Index: doc/comm.eps =================================================================== --- doc/comm.eps (nonexistent) +++ doc/comm.eps (revision 7) @@ -0,0 +1,1171 @@ +%!PS-Adobe-2.0 EPSF-2.0 +%%Title: /home/lekernel/Milkymist/milkymist/milkymist-core/cores/warper/doc/comm.dia +%%Creator: Dia v0.96.1 +%%CreationDate: Tue Mar 3 16:20:17 2009 +%%For: lekernel +%%Orientation: Portrait +%%Magnification: 1.0000 +%%BoundingBox: 0 0 343 230 +%%BeginSetup +%%EndSetup +%%EndComments +%%BeginProlog +[ /.notdef /.notdef /.notdef /.notdef /.notdef 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+768 1383 lineto +1933 2432 lineto +2432 2432 lineto +1171 1294 lineto +2496 0 lineto +1983 0 lineto +768 1188 lineto +768 0 lineto +384 0 lineto +384 3328 lineto +end_ol grestore +showpage Index: doc/tmu.tex =================================================================== --- doc/tmu.tex (nonexistent) +++ doc/tmu.tex (revision 7) @@ -0,0 +1,154 @@ +\documentclass[a4paper,11pt]{article} +\usepackage{fullpage} +\usepackage[latin1]{inputenc} +\usepackage[T1]{fontenc} +\usepackage[normalem]{ulem} +\usepackage[english]{babel} +\usepackage{listings,babel} +\lstset{breaklines=true,basicstyle=\ttfamily} +\usepackage{graphicx} +\usepackage{moreverb} +\usepackage{url} +\usepackage{amsmath} +\usepackage{float} + +\title{Texture Mapping Unit} +\author{S\'ebastien Bourdeauducq} +\date{\today} +\begin{document} +\maketitle{} + +\section{Presentation} +Milkymist has hardware acceleration for texture mapping on triangle strips. This process is used to implement the image warping effect in MilkDrop. + +The texture mapping unit also supports blending, which can for instance be used to implement the fade-to-black feature (the \verb!decay! variable in presets) of MilkDrop. + +The core deals with 16-bit RGB565 progressive-scan framebuffers, accessed via FML links with a width of 64 bits and a burst length of 4. + +The vertex data is fetched using a 32-bit WISHBONE master. Connecting this bus to the WISHBONE-to-FML caching bridge allows the mesh data to be stored in cost-effective DRAM. + +For controlling the core, a CSR bus slave is also implemented. + +\section{Configuration and Status Registers} +Registers can be read at any time, and written when the core is not busy. Write operations when the busy bit is set in register 0, including those to the control register, are illegal and can cause unpredictable behaviour. + +Addresses are in bytes to match the addresses seen by the CPU when the CSR bus is bridged to Wishbone. + +\subsection{Parameters and control} +\begin{tabular}{|l|l|l|p{10.5cm}|} +\hline +\bf{Offset} & \bf{Access} & \bf{Default} & \bf{Description} \\ +\hline +0x00 & RW & 0 & Control register. Bit 0 = busy/start. Bit 1 = IRQ status (cleared whenever the register is written). \\ +\hline +0x04 & RW & 0 & Address of the mesh data. Must be aligned on a 32-bit boundary. \\ +\hline +0x08 & RW & 32 & Number of mesh areas in the X direction (which is the number of mesh points minus one). \\ +\hline +0x0C & RW & 20 & Size of the mesh in the X direction. This is typically the horizontal resolution divided by the number of mesh points. \\ +\hline +0x10 & RW & 24 & Number of mesh areas in the Y direction. \\ +\hline +0x14 & RW & 20 & Size of the mesh in the Y direction. This is typically the vertical resolution divided by the number of mesh points. \\ +\hline +0x18 & RW & 0 & Source framebuffer address. Must be aligned on a 16-bit boundary. \\ +\hline +0x1C & RW & 640 & Source horizontal resolution. \\ +\hline +0x20 & RW & 480 & Source vertical resolution. \\ +\hline +0x24 & RW & 0 & Destination framebuffer address. Must be aligned on a 16-bit boundary. \\ +\hline +0x28 & RW & 640 & Destination horizontal resolution. \\ +\hline +0x2C & RW & 480 & Destination vertical resolution. \\ +\hline +0x30 & RW & 0 & Horizontal offset (a number substracted to each destination X coordinate). \\ +\hline +0x34 & RW & 0 & Vertical offset (a number substracted to each destination Y coordinate). \\ +\hline +0x38 & RW & 63 & Brightness, between 0 and 63. The components of each pixel are multiplied by $ (n+1) \over 64 $ and rounded to the lowest integer. That means that a value of 0 in this register makes the destination picture completely black (because of the limited resolution of RGB565). \\ +\hline +\end{tabular} + +\subsection{Performance counters} +In order to help tracking down the ``low FPS'' symptom, the core is equipped with integrated performance counters. + +Those counters are automatically reset when a new frame is submitted for processing, and must be read after the frame processing is finished. + +These registers are read-only. Attempting to write them results in undefined behaviour. + +\begin{tabular}{|l|l|l|p{10.5cm}|} +\hline +\bf{Offset} & \bf{Access} & \bf{Default} & \bf{Description} \\ +\hline +0x40 & R & 0 & Total number of drawn pixels. Off-screen pixels are not counted. \\ +\hline +0x44 & R & 0 & Total number of used clock cycles. \\ +\hline +0x48 & R & 0 & Total number of stalled transactions detected at pipeline monitor 1. \\ +\hline +0x4C & R & 0 & Total number of completed transactions detected at pipeline monitor 1. \\ +\hline +0x50 & R & 0 & Total number of stalled transactions detected at pipeline monitor 2. \\ +\hline +0x54 & R & 0 & Total number of completed transactions detected at pipeline monitor 2. \\ +\hline +0x58 & R & 0 & Total number of misses in the input image cache. \\ +\hline +\end{tabular} + +\section{Encoding the vertex data} +The core supports a maximum mesh of 128x128 points. The address of the point at indices $ (x, y) $ in the mesh is, regardless of the actual the number of mesh points : + +\begin{equation*} +base + 4 \cdot (128 \cdot y + x) +\end{equation*} + +This means that the mesh always has the same size in memory. + +Each point is made up of 32 bits, with the 16 upper bits being the destination Y coordinates and the 16 lower bits the X coordinate. + +Exactly 64KB are used by the mesh. + +\section{Architecture} + +\begin{figure}[H] +\centering +\includegraphics[height=180mm]{architecture.eps} +\caption{Texture mapping unit architecture.}\label{fig:architecture} +\end{figure} + +\subsection{Handshake protocol between pipeline stages} +Because pipeline stages are not always ready to accept and/or to produce data (because, for example, of memory latencies), a flow control protocol must be implemented. + +The situation is the same between all stages : an upstream stage is registering data into a downstream stage. During some cycles, the upstream stage cannot produce valid data and/or the downstream stage is processing the previous data and has no memory left to store the incoming data. + +\begin{figure}[H] +\centering +\includegraphics[height=30mm]{comm.eps} +\caption{Communication between two pipeline stages.}\label{fig:comm} +\end{figure} + +Appropriate handling of these cases is done using standardized \verb!stb! and \verb!ack! signals. The meaning of these is summarized in this table :\\ + +\begin{tabular}{|l|l|p{12cm}|} +\hline +\verb!stb! & \bf \verb!ack! & \bf Situation \\ +\hline +0 & 0 & The upstream stage does not have data to send, and the downstream stage is not ready to accept data. \\ +\hline +0 & 1 & The downstream stage is ready to accept data, but the upstream stage has currently no data to send. The downstream stage is not required to keep its \verb!ack! signal asserted. \\ +\hline +1 & 0 & The upstream stage is trying to send data to the downstream stage, which is currently not ready to accept it. The transaction is \textit{stalled}. The upstream stage must keep \verb!stb! asserted and continue to present valid data until the transaction is completed. \\ +\hline +1 & 1 & The upstream stage is sending data to the downstream stage which is ready to accept it. The transaction is \textit{completed}. The downstream stage must register the incoming data, as the upstream stage is not required to hold it valid at the next cycle. \\ +\hline +\end{tabular}\\ + +It is not allowed to generate \verb!ack! combinatorially from \verb!stb!. The \verb!ack! signal must always represent the current state of the downstream stage, ie. whether or not it will accept whatever data we present to it. + +\subsection{Triangle filling} +The triangle filling algorithm is inspired by \url{http://www.geocities.com/wronski12/3d_tutor/tri_fillers.html}. To make the linear interpolations, a variant of the Bresenham algorithm is used. + +\end{document} Index: doc/comm.dia =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/comm.dia =================================================================== --- doc/comm.dia (nonexistent) +++ doc/comm.dia (revision 7)
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=================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/texel_cache.ods =================================================================== --- doc/texel_cache.ods (nonexistent) +++ doc/texel_cache.ods (revision 7)
doc/texel_cache.ods Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/Makefile =================================================================== --- doc/Makefile (nonexistent) +++ doc/Makefile (revision 7) @@ -0,0 +1,23 @@ +TEX=tmu.tex + +DVI=$(TEX:.tex=.dvi) +PS=$(TEX:.tex=.ps) +PDF=$(TEX:.tex=.pdf) +AUX=$(TEX:.tex=.aux) +LOG=$(TEX:.tex=.log) + +all: $(PDF) + +%.dvi: %.tex + latex $< + +%.ps: %.dvi + dvips $< + +%.pdf: %.ps + ps2pdf $< + +clean: + rm -f $(DVI) $(PS) $(PDF) $(AUX) $(LOG) + +.PHONY: clean Index: doc/architecture.dia =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/architecture.dia =================================================================== --- doc/architecture.dia (nonexistent) +++ doc/architecture.dia (revision 7)
doc/architecture.dia Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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