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URL https://opencores.org/ocsvn/wb2axi4/wb2axi4/trunk

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/wb2axi4/trunk/verif/src.vlist File deleted
/wb2axi4/trunk/verif/tb.v File deleted
/wb2axi4/trunk/verif/wb2axi_parameters.vh File deleted
/wb2axi4/trunk/verif/Makefile File deleted
/wb2axi4/trunk/verif/env.csh File deleted
/wb2axi4/trunk/model/sram_model.sv File deleted
/wb2axi4/trunk/model/axi_master_model.sv File deleted
/wb2axi4/trunk/rtl/gray2bin.sv File deleted
/wb2axi4/trunk/rtl/axi_ingress.sv
2,7 → 2,6
//Date : 03-11-2015
//Basic : How to storage the AXI info and data into sram or fifo.
`include "wb2axi_parameters.vh"
 
module axi_ingress (
axi_clk,
reset_n,
13,27 → 12,14
fifo_addr_wr,
fifo_data_wr
);
parameter AXI_ID_W = `WB2AXI_AXI_ID_W ;
parameter AXI_ADDR_W = `WB2AXI_AXI_ADDR_W ;
parameter AXI_DATA_W = `WB2AXI_AXI_DATA_W ;
parameter AXI_PROT_W = `WB2AXI_AXI_PROT_W ;
parameter AXI_STB_W = `WB2AXI_AXI_STB_W ;
parameter AXI_LEN_W = `WB2AXI_AXI_LEN_W ;
parameter AXI_SIZE_W = `WB2AXI_AXI_SIZE_W ;
parameter AXI_BURST_W = `WB2AXI_AXI_BURST_W;
parameter AXI_LOCK_W = `WB2AXI_AXI_LOCK_W ;
parameter AXI_CACHE_W = `WB2AXI_AXI_CACHE_W;
parameter AXI_RESP_W = `WB2AXI_AXI_RESP_W ;
parameter AXI_MAX_RESP_W = 3;
parameter FIFO_ADR_W = 10;
parameter FIFO_DAT_W = 10;
 
parameter AXI_WID_W = 5;
parameter AXI_MAX_RESP_W = 3;
input axi_clk;
input reset_n;
axi_if.target AXI_IF;
output fifo_full;
output [FIFO_ADR_W-1:0] fifo_addr_info;
output [FIFO_DAT_W-1:0] fifo_data_info;
output [FIFO_AW-1:0] fifo_addr_info;
output [FIFO_DW-1:0] fifo_data_info;
output reg fifo_addr_wr;
output reg fifo_data_wr;
localparam ST_W = 2;
52,12 → 38,12
reg [ST_W-1:0] state;
reg [ST_W-1:0] next_state;
reg [AXI_MAX_RESP_W-1:0] bresp_pending_cnt; //responses pending to generate
reg [AXI_ID_W-1:0] last_wid;
reg [FIFO_ADR_W-1:0] fifo_addr_in;
reg [FIFO_DAT_W-1:0] fifo_data_in;
reg [AXI_WID_W-1:0] last_wid;
reg [FIFO_AW-1:0] fifo_addr_in;
reg [FIFO_DW-1:0] fifo_data_in;
 
assign input_addr_event = AXI_IF.AWVALID & AXI_IF.AWREADY;
assign input_data_event = AXI_IF.WVALID & AXI_IF.WREADY;
assign input_data_event = AXI_FI.WVALID & AXI_IF.WREADY;
assign inc_bresp = AXI_IF.WLAST & input_data_event;
assign dec_bresp = AXI_IF.BREADY & AXI_IF.BVALID;
assign bresp_cnt_max = (bresp_pending_cnt == AXI_MAX_RESP_VAL);
117,7 → 103,7
assign AXI_IF.RRESP = 0;
assign AXI_IF.RLAST = 0;
assign AXI_IF.RVALID = 0;
assign AXI_IF.AWREADY = (state ==ST_IDLE || state==ST_WDATA) & ~fifo_full & ~bresp_cnt_max;
assign AIX_IF.AWREADY = (state ==ST_IDLE || state==ST_WDATA) & ~fifo_full & ~bresp_cnt_max;
assign AXI_IF.WREADY = ~fifo_full & ~bresp_cnt_max;
 
assign fifo_addr_info = fifo_addr_in;
/wb2axi4/trunk/rtl/axi2wb.sv
1,6 → 1,5
//Author : Alex Zhang (cgzhangwei@gmail.com)
//Date : 03-11-2015
`include "wb2axi_parameters.vh"
module axi2wb (
axi_clk,
wb_clk,
10,22 → 9,20
AXI_IF,
WB_TX_IF
);
parameter AXI_ID_W = `WB2AXI_AXI_ID_W ;
parameter AXI_ADDR_W = `WB2AXI_AXI_ADDR_W ;
parameter AXI_DATA_W = `WB2AXI_AXI_DATA_W ;
parameter AXI_PROT_W = `WB2AXI_AXI_PROT_W ;
parameter AXI_STB_W = `WB2AXI_AXI_STB_W ;
parameter AXI_LEN_W = `WB2AXI_AXI_LEN_W ;
parameter AXI_SIZE_W = `WB2AXI_AXI_SIZE_W ;
parameter AXI_BURST_W = `WB2AXI_AXI_BURST_W;
parameter AXI_LOCK_W = `WB2AXI_AXI_LOCK_W ;
parameter AXI_CACHE_W = `WB2AXI_AXI_CACHE_W;
parameter AXI_RESP_W = `WB2AXI_AXI_RESP_W ;
parameter AXI_WID_W = 4;
parameter AXI_ADDR_W = 32;
parameter AXI_DATA_W = 32;
parameter AXI_PROT_W = 3;
parameter AXI_STB_W = 4;
parameter AXI_LEN_W = 4;
parameter AXI_ASIZE_W = 3;
parameter AXI_ABURST_W = 2;
parameter AXI_ALOCK_W = 2;
parameter AXI_ACACHE_W = 4;
parameter AXI_RESP_W = 2;
 
parameter FIFO_ADDR_DEPTH_W = 10;
parameter FIFO_ADDR_W = AXI_ID_W+AXI_ADDR_W+AXI_PROT_W+AXI_LEN_W+AXI_SIZE_W+AXI_BURST_W+AXI_LOCK_W+AXI_CACHE_W+1;
parameter FIFO_DATA_DEPTH_W = 11;
parameter FIFO_DATA_W = AXI_ID_W+AXI_DATA_W+AXI_STB_W+2;
parameter FIFO_DEPTH_W = 10;
parameter FIFO_W = 64;
 
parameter WB_ADR_W = 32;
parameter WB_DAT_W = 32;
36,62 → 33,46
parameter WB_CTI_W = 3;
parameter WB_BTE_W = 2;
 
localparam SRAM_UNUSED_ADDR_W= 4;
localparam AXI_MAX_RESP_W = 4;
localparam FA_SRAM_UNUSED_ADDR_W = 1;
localparam FD_SRAM_UNUSED_ADDR_W = 1;
parameter AXI_MAX_RESP_W = 3;
parameter SRAM_UNUSED_ADDR_W= 4;
 
input wire axi_clk;
input wire wb_clk;
input wire axi_resetn;
input wire wb_resetn;
input wire ENABLE;
axi_if.target AXI_IF;
wishbone_if.master WB_TX_IF;
wb_if.master WB_TX_IF;
sram_if.initiator SRAM_ADR_IF;
sram_if.initiator SRAM_DAT_IF;
 
sram_if #(.DATA_W(32), .ADDR_W(11)) dat_sram_tx();
sram_if #(.DATA_W(64), .ADDR_W(10)) adr_sram_tx();
 
wire sync_ENABLE_axi;
wire sync_ENABLE_wb ;
wire fifo_adr_full ;
wire fifo_dat_full ;
wire [FIFO_DATA_W-1:0] fifo_dat_rdata ;
wire [FIFO_ADDR_W-1:0] fifo_adr_rdata ;
 
wire sync_ENABLE_axi;
wire sync_ENABLE_wb;
sync_doble_ff #(.DATA_W(1)) I_SYNC_ENABLE_AXI (
.CLK ( axi_clk ),
.RESET_N ( axi_resetn ),
.CLK ( AXI_CLK ),
.RESET_N ( AXI_RESET_N ),
.DIN ( ENABLE ),
.DOUT ( sync_ENABLE_axi )
);
sync_doble_ff #(.DATA_W(1)) I_SYNC_ENABLE_WB (
.CLK ( wb_clk ),
.RESET_N ( wb_resetn ),
.CLK ( MAC_CLK ),
.RESET_N ( MAC_RESET_N ),
.DIN ( ENABLE ),
.DOUT ( sync_ENABLE_wb )
);
wire [FIFO_ADDR_W-1:0] fifo_addr_info;
wire [FIFO_DATA_W-1:0] fifo_data_info;
wire fifo_addr_wr ;
wire fifo_data_wr ;
wire [FIFO_ADDR_W-1:0] fifo_adr_wdata;
wire [FIFO_DATA_W-1:0] fifo_dat_wdata;
 
axi_ingress #(
.AXI_ID_W ( AXI_ID_W ),
.AXI_WID_W ( AXI_WID_W ),
.AXI_ADDR_W ( AXI_ADDR_W ),
.AXI_DATA_W ( AXI_DATA_W ),
.AXI_PROT_W ( AXI_PROT_W ),
.AXI_STB_W ( AXI_STB_W ),
.AXI_LEN_W ( AXI_LEN_W ),
.AXI_SIZE_W ( AXI_SIZE_W ),
.AXI_BURST_W ( AXI_BURST_W ),
.AXI_LOCK_W ( AXI_LOCK_W ),
.AXI_CACHE_W ( AXI_CACHE_W ),
.AXI_RESP_W ( AXI_RESP_W ),
.AXI_MAX_RESP_W ( AXI_MAX_RESP_W ),
.FIFO_DAT_W ( FIFO_DATA_W ),
.FIFO_ADR_W ( FIFO_ADDR_W )
.AXI_ASIZE_W ( AXI_ASIZE_W ),
.AXI_ABURST_W ( AXI_ABURST_W ),
.AXI_ALOCK_W ( AXI_ALOCK_W ),
.AXI_ACACHE_W ( AXI_ACACHE_W ),
.AXI_RESP_W ( AXI_RESP_W ),
.AXI_MAX_RESP_W ( AXI_MAX_RESP_W )
) I_AXI_INGRESS (
.axi_clk ( axi_clk ),
.reset_n ( axi_resetn ),
122,32 → 103,7
.fifo_rdata ( fifo_adr_rdata ),
.fifo_empty ( fifo_adr_empty ),
.fifo_full ( fifo_adr_full ),
.fifo_level ( ),
.SRAM_IF ( adr_sram_tx )
);
wire adr_sram_enable;
wire adr_sram_wr;
wire [FIFO_ADDR_W-1:0] adr_sram_din;
wire [FIFO_ADDR_W-1:0] adr_sram_dout;
wire [FIFO_ADDR_DEPTH_W-1:0] adr_sram_addr;
sram_model #(
.MEM_ADDR_W (FIFO_ADDR_DEPTH_W),
.MEM_DATA_W (FIFO_ADDR_W)
) SRAM_ADR_1phc1024x32mx4tn(
.CLK(axi_clk ),
.NCE(adr_sram_enable),
.NWRT(adr_sram_wr ),
.NOE(1'b0 ),
.DIN(adr_sram_din ),
.ADDR(adr_sram_addr ),
.DOUT(adr_sram_dout )
);
assign adr_sram_enable = adr_sram_tx.rd_l | adr_sram_tx.wr_l;
assign adr_sram_wr = adr_sram_tx.wr_l;
assign adr_sram_din = adr_sram_tx.wdata;
assign adr_sram_addr = ~adr_sram_tx.wr_l ? adr_sram_tx.wr_address : adr_sram_tx.rd_address;
assign adr_sram_tx.rdata = adr_sram_dout;
 
assign fifo_adr_wr = fifo_addr_wr;
assign fifo_adr_wdata = fifo_addr_info;
async_fifo #(
167,54 → 123,28
.fifo_rdata ( fifo_dat_rdata ),
.fifo_empty ( fifo_dat_empty ),
.fifo_full ( fifo_dat_full ),
.fifo_level ( ),
.SRAM_IF ( dat_sram_tx )
);
wire dat_sram_enable;
wire dat_sram_wr;
wire [FIFO_DATA_W-1:0] dat_sram_din;
wire [FIFO_DATA_W-1:0] dat_sram_dout;
wire [FIFO_DATA_DEPTH_W-1:0] dat_sram_addr;
sram_model #(
.MEM_ADDR_W (FIFO_DATA_DEPTH_W),
.MEM_DATA_W (FIFO_DATA_W)
) SRAM_DAT_1phc1024x32mx4tn(
.CLK(axi_clk ),
.NCE(dat_sram_enable),
.NWRT(dat_sram_wr ),
.NOE(1'b0 ),
.DIN(dat_sram_din ),
.ADDR(dat_sram_addr),
.DOUT(dat_sram_dout)
);
assign dat_sram_enable = dat_sram_tx.rd_l | dat_sram_tx.wr_l;
assign dat_sram_wr = dat_sram_tx.wr_l;
assign dat_sram_din = dat_sram_tx.wdata;
assign dat_sram_addr = ~dat_sram_tx.wr_l ? dat_sram_tx.wr_address : dat_sram_tx.rd_address;
assign dat_sram_tx.rdata = dat_sram_dout;
 
 
assign fifo_dat_wr = fifo_data_wr;
assign fifo_dat_wdata = fifo_data_info;
wb_egress #(
.WB_ADR_W (WB_ADR_W ),
.WB_DAT_W (WB_DAT_W ),
.WB_TGA_W (WB_TGA_W ),
.WB_TGD_W (WB_TGD_W ),
.WB_TGC_W (WB_TGC_W ),
.WB_SEL_W (WB_SEL_W ),
.WB_CTI_W (WB_CTI_W ),
.WB_BTE_W (WB_BTE_W ),
.AXI_ID_W (AXI_ID_W ),
.AXI_ADDR_W (AXI_ADDR_W ),
.AXI_LEN_W (AXI_LEN_W ),
.AXI_SIZE_W (AXI_SIZE_W ),
.AXI_BURST_W(AXI_BURST_W),
.AXI_LOCK_W (AXI_LOCK_W ),
.AXI_CACHE_W(AXI_CACHE_W),
.AXI_PROT_W (AXI_PROT_W ),
.AXI_DATA_W (AXI_DATA_W ),
.AXI_STB_W (AXI_STB_W )
.WB_ADR_W (WB_ADR_W )
.WB_DAT_W (WB_DAT_W )
.WB_TGA_W (WB_TGA_W )
.WB_TGD_W (WB_TGD_W )
.WB_TGC_W (WB_TGC_W )
.WB_SEL_W (WB_SEL_W )
.WB_CTI_W (WB_CTI_W )
.WB_BTE_W (WB_BTE_W )
.AXI_ID_W (AXI_ID_W )
.AXI_ADDR_W (AXI_ADDR_W )
.AXI_LEN_W (AXI_LEN_W )
.AXI_SIZE_W (AXI_SIZE_W )
.AXI_BURST_W(AXI_BURST_W)
.AXI_LOCK_W (AXI_LOCK_W )
.AXI_CACHE_W(AXI_CACHE_W)
.AXI_PROT_W (AXI_PROT_W )
.AXI_DATA_W (AXI_DATA_W )
.AXI_STRB_W (AXI_STRB_W )
) I_WB_EGRESS(
.wb_clk ( wb_clk ),
.wb_resetn ( wb_resetn ),
225,7 → 155,7
.fifo_adr_empty ( fifo_adr_empty ),
.fifo_dat_rdata ( fifo_dat_rdata ),
.fifo_dat_rd ( fifo_dat_rd ),
.fifo_dat_empty ( fifo_dat_empty )
.fifo_dat_empty ( fifo_dat_empty ),
);
 
endmodule
/wb2axi4/trunk/rtl/wb_egress.sv
14,7 → 14,7
fifo_adr_empty,
fifo_dat_rdata,
fifo_dat_rd,
fifo_dat_empty
fifo_dat_empty,
);
 
parameter WB_ADR_W = 32;
34,9 → 34,9
parameter AXI_CACHE_W = 4;
parameter AXI_PROT_W = 3;
parameter AXI_DATA_W = 32;
parameter AXI_STB_W = 4;
parameter AXI_STRB_W = 4;
parameter FIFO_ADR_W = AXI_ID_W + AXI_ADDR_W + AXI_LEN_W + AXI_SIZE_W + AXI_BURST_W + AXI_LOCK_W + AXI_CACHE_W + AXI_PROT_W +1 ;
parameter FIFO_DAT_W = AXI_ID_W + AXI_DATA_W + AXI_STB_W + 2;
parameter FIFO_DAT_W = AXI_ID_W + AXI_DATA_W + AXI_STRB_W + 2;
parameter ST_W = 2 ;
parameter ST_IDLE = 2'b00,
ST_READ_ADDR = 2'b01,
47,11 → 47,10
WB_FIRST_DATA = 2'b01,
WB_NEXT_DATA = 2'b10;
 
 
input wire wb_clk;
input wire wb_resetn;
input wire ENABLE;
wishbone_if.master WB_TX_IF;
wb_if.master WB_TX_IF;
input wire [FIFO_ADR_W-1:0] fifo_adr_rdata;
output wire fifo_adr_rd;
input wire fifo_adr_empty;
65,7 → 64,9
reg inc_dat_ptr;
reg [4:0] data_count;
wire allow_adr_rd;
wire fifo_adr_rd;
wire fifo_adr_rd_q;
wire fifo_dat_rd;
reg [AXI_ID_W -1:0] axi_id ;
reg [AXI_ADDR_W -1:0] axi_addr ;
reg [AXI_LEN_W -1:0] axi_len ;
77,7 → 78,7
reg wr_req ;
reg [AXI_ID_W -1:0] axi_wid ;
reg [AXI_DATA_W -1:0] axi_wdata ;
reg [AXI_STB_W -1:0] axi_wstrb ;
reg [AXI_STRB_W -1:0] axi_wstrb ;
reg axi_wlast ;
reg axi_wvalid;
reg wb_we_o ;
84,21 → 85,16
reg [WB_ADR_W-1:0] wb_adr_o;
reg [WB_TGA_W-1:0] wb_tga_o;
reg [WB_ADR_W-1:0] wb_adr_tmp;
reg [AXI_LEN_W-1:0] wb_len_tmp;
reg [WB_BTE_W-1:0] wb_bte_o;
reg wb_cyc_o;
reg [WB_TGC_W-1:0] wb_tgc_o;
reg [WB_CTI_W-1:0] wb_cti_o;
reg wb_stb_o;
reg [WB_STB_W-1:0] wb_stb_o;
reg [WB_DAT_W-1:0] wb_dat_o;
reg [WB_TGD_W-1:0] wb_tgd_o;
reg [WB_SEL_W-1:0] wb_sel_o;
 
reg [WB_W-1:0] wb_cs;
reg [WB_W-1:0] wb_ns;
 
 
 
assign allow_adr_rd = wb_cs == WB_IDLE;
always_comb begin
next_state = state;
115,7 → 111,7
next_state = ST_WAIT_DATA;
end
ST_WAIT_DATA : begin
if (WB_TX_IF.ACK & !fifo_dat_empty) begin
if (WB_TX_IF.ACK_I & !fifo_dat_empty) begin
next_state = ST_READ_DATA;
end else begin
next_state = ST_WAIT_DATA;
122,13 → 118,13
end
end
ST_READ_DATA : begin
if (data_count>0 & WB_TX_IF.ACK) begin
if (data_count>0 & WB_TX_IF.ACK_I) begin
next_state = ST_READ_DATA;
inc_dat_ptr = 1;
end else if (data_count>0) begin
next_state = ST_WAIT_DATA;
inc_dat_ptr = 0;
end else begin
end
next_state = ST_IDLE;
inc_dat_ptr = 0;
end
144,8 → 140,7
.DOUT ( fifo_adr_rd_q ),
.CLK ( wb_clk ),
.RESET_N( wb_resetn )
);
 
)
always @(posedge wb_clk or negedge wb_resetn)
if (~wb_resetn) begin
state <= ST_IDLE;
194,7 → 189,7
wb_ns = wb_cs;
case (wb_cs)
WB_IDLE : begin
if (fifo_dat_rd) begin
if (fifo_data_rd) begin
wb_ns = WB_FIRST_DATA;
end else begin
wb_ns = WB_IDLE;
201,9 → 196,9
end
end
WB_FIRST_DATA : begin
if (axi_wlast & WB_TX_IF.ACK)
if (axi_wlast & WB_TX_IF.ACK_I)
wb_ns = WB_IDLE;
else if (~axi_wlast & WB_TX_IF.ACK)
else if (~axi_wlast & WB_TX_IF.ACK_I)
wb_ns = WB_NEXT_DATA;
else
wb_ns = WB_FIRST_DATA;
210,7 → 205,7
end
WB_NEXT_DATA : begin
if (axi_wlast & WB_TX_IF.ACK)
if (axi_wlast & WB_TX_IF.ACK_I)
wb_ns = WB_IDLE;
else
wb_ns = WB_NEXT_DATA;
290,16 → 285,16
end
end
 
assign WB_TX_IF.ADR = wb_adr_o;
assign WB_TX_IF.WE = wb_we_o;
assign WB_TX_IF.TGA = wb_tga_o;
assign WB_TX_IF.BTE = wb_bte_o;
assign WB_TX_IF.CYC = wb_cyc_o;
assign WB_TX_IF.TGC = wb_tgc_o;
assign WB_TX_IF.CTI = wb_cti_o;
assign WB_TX_IF.STB = wb_stb_o;
assign WB_TX_IF.ADR_O = wb_adr_o;
assign WB_TX_IF.WE_O = wb_we_o;
assign WB_TX_IF.TGA_O = wb_tga_o;
assign WB_TX_IF.BTE_O = wb_bte_o;
assign WB_TX_IF.CYC_O = wb_cyc_o;
assign WB_TX_IF.TGC_O = wb_tgc_o;
assign WB_TX_IF.CTI_O = wb_cti_o;
assign WB_TX_IF.STB_O = wb_stb_o;
assign WB_TX_IF.DAT_O = wb_dat_o;
assign WB_TX_IF.TGD_O = wb_tgd_o;
assign WB_TX_IF.SEL = wb_sel_o;
assign WB_TX_IF.SEL_O = wb_sel_o;
 
endmodule
/wb2axi4/trunk/rtl/ifaces/wishbone_if.sv
7,7 → 7,7
interface wishbone_if #(
WB_ADR_WIDTH = 32,
WB_BTE_WIDTH = 2 ,
WB_CTI_WIDTH = 3 ,
WB_CIT_WIDTH = 3 ,
WB_DAT_WIDTH = 32,
WB_TGA_WIDTH = 8,
WB_TGD_WIDTH = 8,
15,63 → 15,74
WB_SEL_WIDTH = 4
 
);
logic [WB_ADR_WIDTH -1 : 0] ADR;
logic [WB_TGA_WIDTH -1 :0 ] TGA;
logic [WB_DAT_WIDTH -1 : 0] DAT_I;
logic [WB_DAT_WIDTH -1 : 0] DAT_O;
logic [WB_TGD_WIDTH -1 : 0] TGD_I;
logic [WB_DAT_WIDTH -1 : 0] DAT_O;
logic [WB_TGD_WIDTH -1 : 0] TGD_O;
logic WE;
logic [WB_SEL_WIDTH -1 : 0] SEL;
logic STB;
logic ACK;
logic CYC;
logic ERR;
logic LOCK;
logic [WB_BTE_WIDTH -1 :0 ] BTE;
logic RTY;
logic [WB_CTI_WIDTH -1 :0 ] CTI;
logic [WB_TGA_WIDTH -1 :0 ] TGC;
logic ACK_I;
logic [WB_ADR_WIDTH -1 : 0] ADR_O;
logic CYC_O;
logic ERR_I;
logic LOCK_O;
logic RTY_I;
logic [WB_SEL_WIDTH -1 : 0] SEL_O;
logic STB_O;
logic [WB_TGA_WIDTH -1 :0 ] TGA_O;
logic [WB_TGA_WIDTH -1 :0 ] TGC_O;
logic WE_O;
logic [WB_BTE_WIDTH -1 :0 ] BTE_O;
logic [WB_BTE_WIDTH -1 :0 ] BTE_I;
logic [WB_CTI_WIDTH -1 :0 ] CTI_O;
logic [WB_CTI_WIDTH -1 :0 ] CTI_I;
 
 
logic ACK_O;
logic [WB_ADR_WIDTH -1 : 0] ADR_I;
logic CYC_I;
logic ERR_O;
logic LOCK_I;
logic RTY_O;
logic [WB_SEL_WIDTH -1 : 0] SEL_I;
logic [WB_TGA_WIDTH -1 :0 ] TGA_I;
logic [WB_TGA_WIDTH -1 :0 ] TGC_I;
logic WE_I;
 
modport master(
output ADR ,
output TGA ,
output ADR_O,
output TGA_O,
input DAT_I,
input TGD_I,
output DAT_O,
output TGD_O,
output WE ,
output SEL ,
output STB ,
input ACK ,
output CYC ,
input ERR ,
output LOCK ,
output BTE ,
input RTY ,
output CTI ,
output TGC
output WE_O,
output SEL_O,
output STB_O,
input ACK_I,
output CYC_O,
input ERR_I,
output LOCK_O,
output BTE_O,
input RTY_I,
output TGC_O
);
 
modport slave(
input ADR ,
input TGA ,
output ADR_I,
output TGA_I,
input DAT_I,
input TGD_I,
output DAT_O,
output TGD_O,
input DAT_I,
input TGD_I,
input WE ,
input SEL ,
input STB ,
output ACK ,
input CYC ,
output ERR ,
input LOCK ,
input BTE ,
output RTY ,
input CTI ,
input TGC
output WE_I,
output SEL_I,
output STB_I,
input ACK_O,
output CYC_I,
input ERR_O,
output LOCK_I,
input BTE_I,
input RTY_O,
output TGC_I
);
 
 
/wb2axi4/trunk/rtl/ifaces/axi_if.sv
1,59 → 1,59
interface axi_if
#(AXI_ID_W = 8,
AXI_ADDR_W = 32,
AXI_DATA_W = 32,
AXI_PROT_W = 3,
AXI_STB_W = 4,
AXI_LEN_W = 4,
AXI_SIZE_W = 3,
AXI_BURST_W = 2,
AXI_LOCK_W = 2,
AXI_CACHE_W = 4,
AXI_RESP_W = 2
#(AXI_WID_WIDTH = 8,
AXI_ADDR_WIDTH = 32,
AXI_DATA_WIDTH = 32,
AXI_PROT_WIDTH = 3,
AXI_STB_WIDTH = 4,
AXI_LEN_W = 4,
AXI_ASIZE_W = 3,
AXI_ABURST_W = 2,
AXI_ALOCK_W = 2,
AXI_ACACHE_W = 4,
AXI_RESP_W = 2
)
();
 
//Write control channel signals
logic [AXI_ID_W - 1:0] AWID ;
logic [AXI_ADDR_W - 1:0] AWADDR ;
logic [AXI_LEN_W - 1:0] AWLEN ;
logic [AXI_SIZE_W - 1:0] AWSIZE ;
logic [AXI_BURST_W - 1:0] AWBURST ;
logic [AXI_LOCK_W - 1:0] AWLOCK ;
logic [AXI_CACHE_W - 1:0] AWCACHE ;
logic [AXI_PROT_W - 1:0] AWPROT ;
logic AWVALID ;
logic AWREADY ;
logic [AXI_WID_WIDTH - 1:0] AWID ;
logic [AXI_ADDR_WIDTH - 1:0] AWADDR ;
logic [AXI_LEN_W - 1:0] AWLEN ;
logic [AXI_ASIZE_W - 1:0] AWSIZE ;
logic [AXI_ABURST_W - 1:0] AWBURST ;
logic [AXI_ALOCK_W - 1:0] AWLOCK ;
logic [AXI_ACACHE_W - 1:0] AWCACHE ;
logic [AXI_PROT_WIDTH - 1:0] AWPROT ;
logic AWVALID ;
logic AWREADY ;
//write data channel signals
logic [AXI_ID_W - 1:0 ] WID ;
logic [AXI_DATA_W - 1:0] WDATA ;
logic [AXI_STB_W - 1:0] WSTRB ;
logic WLAST ;
logic WVALID ;
logic WREADY ;
logic [AXI_WID_WIDTH - 1:0] WID ;
logic [AXI_DATA_WIDTH - 1:0] WDATA ;
logic [AXI_STB_WIDTH - 1:0] WSTRB ;
logic WLAST ;
logic WVALID ;
logic WREADY ;
//write response channel
logic [AXI_ID_W - 1:0] BID ;
logic [AXI_RESP_W - 1:0] BRESP ;
logic BVALID ;
logic BREADY ;
logic [AXI_WID_WIDTH - 1:0] BID ;
logic [AXI_RESP_W - 1:0] BRESP ;
logic BVALID ;
logic BREADY ;
//Read control channel signals
logic [AXI_ID_W - 1:0] ARID ;
logic [AXI_ADDR_W - 1:0] ARADDR ;
logic [AXI_WID_WIDTH - 1:0] ARID ;
logic [AXI_ADDR_WIDTH - 1:0] ARADDR ;
logic [AXI_LEN_W - 1:0] ARLEN ;
logic [AXI_SIZE_W - 1:0] ARSIZE ;
logic [AXI_BURST_W - 1:0] ARBURST ;
logic [AXI_LOCK_W - 1:0] ARLOCK ;
logic [AXI_CACHE_W - 1:0] ARCACHE ;
logic [AXI_PROT_W - 1:0] ARPROT ;
logic [AXI_ASIZE_W - 1:0] ARSIZE ;
logic [AXI_ABURST_W - 1:0] ARBURST ;
logic [AXI_ALOCK_W - 1:0] ARLOCK ;
logic [AXI_ACACHE_W - 1:0] ARCACHE ;
logic [AXI_PROT_WIDTH - 1:0] ARPROT ;
logic ARVALID ;
logic ARREADY ;
//Read data channel signals
logic [AXI_ID_W - 1:0] RID ;
logic [AXI_DATA_W - 1:0] RDATA ;
logic [AXI_RESP_W - 1:0] RRESP ;
logic RLAST ;
logic RVALID ;
logic RREADY ;
logic [AXI_WID_WIDTH - 1:0] RID ;
logic [AXI_DATA_WIDTH - 1:0] RDATA ;
logic [AXI_RESP_W - 1:0] RRESP ;
logic RLAST ;
logic RVALID ;
logic RREADY ;
 
modport initiator (
//Write control channel signals

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