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URL https://opencores.org/ocsvn/wb2axi4/wb2axi4/trunk

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/wb2axi4/trunk/model/axi_master_model.sv
0,0 → 1,281
module axi_master_model (
axi_clk,
axi_resetn,
AWID ,
AWADDR ,
AWLEN ,
AWSIZE ,
AWBURST ,
AWLOCK ,
AWCACHE ,
AWPROT ,
AWVALID ,
AWREADY ,
//write data channel signals
WID ,
WDATA ,
WSTRB ,
WLAST ,
WVALID ,
WREADY ,
//write response channel
BID ,
BRESP ,
BVALID ,
BREADY ,
//Read control channel signals
ARID ,
ARADDR ,
ARLEN ,
ARSIZE ,
ARBURST ,
ARLOCK ,
ARCACHE ,
ARPROT ,
ARVALID ,
ARREADY ,
//Read data channel signals
RID ,
RDATA ,
RRESP ,
RLAST ,
RVALID ,
RREADY
);
parameter AXI_ID_W = 4;
parameter AXI_ADDR_W = 32;
parameter AXI_DATA_W = 32;
parameter AXI_PROT_W = 3;
parameter AXI_STB_W = 4;
parameter AXI_LEN_W = 4;
parameter AXI_SIZE_W = 3;
parameter AXI_BURST_W = 2;
parameter AXI_LOCK_W = 2;
parameter AXI_CACHE_W = 4;
parameter AXI_RESP_W = 2;
 
input axi_clk;
input axi_resetn;
output [AXI_ID_W - 1:0] AWID ;
output [AXI_ADDR_W - 1:0] AWADDR ;
output [AXI_LEN_W - 1:0] AWLEN ;
output [AXI_SIZE_W - 1:0] AWSIZE ;
output [AXI_BURST_W - 1:0] AWBURST ;
output [AXI_LOCK_W - 1:0] AWLOCK ;
output [AXI_CACHE_W - 1:0] AWCACHE ;
output [AXI_PROT_W - 1:0] AWPROT ;
output AWVALID ;
input AWREADY ;
//write data channel signals
output [AXI_ID_W - 1:0] WID ;
output [AXI_DATA_W - 1:0] WDATA ;
output [AXI_STB_W - 1:0] WSTRB ;
output WLAST ;
output WVALID ;
input WREADY ;
//write response channel
input [AXI_ID_W - 1:0] BID ;
input [AXI_RESP_W - 1:0] BRESP ;
input BVALID ;
output BREADY ;
//Read control channel signals
output [AXI_ID_W - 1:0] ARID ;
output [AXI_ADDR_W - 1:0] ARADDR ;
output [AXI_LEN_W - 1:0] ARLEN ;
output [AXI_SIZE_W - 1:0] ARSIZE ;
output [AXI_BURST_W - 1:0] ARBURST ;
output [AXI_LOCK_W - 1:0] ARLOCK ;
output [AXI_CACHE_W - 1:0] ARCACHE ;
output [AXI_PROT_W - 1:0] ARPROT ;
output ARVALID ;
input ARREADY ;
//Read data channel signals
input [AXI_ID_W - 1:0] RID ;
input [AXI_DATA_W - 1:0] RDATA ;
input [AXI_RESP_W - 1:0] RRESP ;
input RLAST ;
input RVALID ;
output RREADY ;
 
 
reg [AXI_ID_W -1:0] axi_id ;
reg [AXI_ADDR_W -1:0] axi_addr ;
reg [AXI_LEN_W -1:0] axi_len ;
reg [AXI_SIZE_W -1:0] axi_size ;
reg [AXI_BURST_W-1:0] axi_burst ;
reg [AXI_LOCK_W -1:0] axi_lock ;
reg [AXI_CACHE_W-1:0] axi_cache ;
reg [AXI_PROT_W -1:0] axi_prot ;
reg axi_valid ;
reg wr_req ;
reg [AXI_ID_W -1:0] axi_wid ;
reg [AXI_DATA_W -1:0] axi_wdata ;
reg [AXI_STB_W -1:0] axi_wstrb ;
reg axi_wlast ;
reg axi_wvalid;
 
reg [AXI_ADDR_W-1:0] start_addr;
reg [AXI_ADDR_W-1:0] end_addr;
reg [7:0] num_pkt;
 
initial begin
if ($value$plusargs("start_addr=%d", start_addr ))
$display("****** start_addr=0x%0x", start_addr);
else
start_addr = 32'h10_0000;
if ($value$plusargs("end_addr=%d", end_addr ))
$display("****** end_addr=0x%0x", end_addr);
else
end_addr = 32'h1F_0000;
if ($value$plusargs("num_pkt=%d", num_pkt))
$display("****** num_pkt=%0d", num_pkt);
else
num_pkt = 3;
end
parameter AXI_IDLE = 3'b000;
parameter AXI_ADDR = 3'b001;
parameter AXI_DATA = 3'b010;
parameter AXI_WAIT_DATA = 3'b111;
parameter AXI_CFG = 3'b011;
parameter AXI_UPD = 3'b100;
reg [7:0] pkt_count;
reg [4:0] txn_count;
reg [1:0] axi_cs;
reg [1:0] axi_ns;
 
always @(posedge axi_clk or negedge axi_resetn)
if (~axi_resetn) begin
axi_cs <= AXI_IDLE;
end else begin
axi_cs <= axi_ns;
end
 
always @(posedge axi_clk or negedge axi_resetn)
if (~axi_resetn) begin
pkt_count <= 0;
txn_count <= 0;
end else begin
case (axi_cs)
AXI_IDLE : begin
axi_id <= 0;
axi_addr <= 0;
axi_len <= 0;
axi_size <= 0;
axi_burst <= 0;
axi_lock <= 0;
axi_cache <= 0;
axi_prot <= 0;
axi_valid <= 0;
wr_req <= 0;
axi_wid <= 0;
axi_wdata <= 0;
axi_wstrb <= 0;
axi_wlast <= 0;
axi_wvalid <= 0;
end
AXI_CFG : begin
pkt_count <= num_pkt;
end
AXI_ADDR : begin
axi_id <= 1;
axi_addr <= start_addr + 32'h20;
axi_len <= 4'hF;
axi_size <= 3'b010;
axi_burst <= 0;
axi_lock <= 0;
axi_cache <= 0;
axi_prot <= 0;
axi_valid <= 1;
wr_req <= 1;
txn_count <= 5'b10000;
end
AXI_DATA: begin
txn_count <= txn_count >0 ? txn_count - 1 : txn_count;
axi_valid <= 0;
axi_wid <= 2;
axi_wdata <= $random;
axi_wstrb <= 4'hF;
axi_wlast <= txn_count==0 ? 1 : 0;
axi_wvalid<= 1'b1;
end
AXI_WAIT_DATA : begin
axi_wvalid<= 1'b0;
end
AXI_UPD : begin
pkt_count <= pkt_count >0 ? pkt_count -1 : pkt_count;
axi_wvalid<= 1'b0;
end
endcase
end
 
always @(*) begin
axi_ns = axi_cs;
 
case (axi_cs)
AXI_IDLE : begin
axi_ns = AXI_CFG;
end
AXI_CFG : begin
if (pkt_count >0 & AWREADY)
axi_ns = AXI_ADDR;
else
axi_ns = AXI_CFG;
end
AXI_ADDR : begin
axi_ns = AXI_DATA;
end
AXI_DATA: begin
if (WREADY & txn_count>0)
axi_ns = AXI_DATA;
else if (txn_count==0)
axi_ns = AXI_UPD;
else
axi_ns = AXI_WAIT_DATA;
end
AXI_WAIT_DATA: begin
if (WREADY)
axi_ns = AXI_DATA;
else
axi_ns = AXI_WAIT_DATA;
end
AXI_UPD: begin
if (pkt_count >0)
axi_ns = AXI_ADDR;
else
axi_ns = AXI_UPD;
end
endcase
end
 
assign AWID = wr_req ?axi_id : 'hx;
assign AWADDR = wr_req ?axi_addr : 'hx;
assign AWLEN = wr_req ?axi_len : 'hx;
assign AWSIZE = wr_req ?axi_size : 'hx;
assign AWBURST = wr_req ?axi_burst : 'hx;
assign AWLOCK = wr_req ?axi_lock : 'hx;
assign AWCACHE = wr_req ?axi_cache : 'hx;
assign AWPROT = wr_req ?axi_prot : 'hx;
assign AWVALID = wr_req ?axi_valid : 1'b0;
assign WID = wr_req ?axi_wid : 'hx;
assign WDATA = wr_req ?axi_wdata : 'hx;
assign WSTRB = wr_req ?axi_wstrb : 'hx;
assign WLAST = wr_req ?axi_wlast : 'hx;
assign WVALID = wr_req ?axi_valid : 1'b0;
 
assign BREADY = 1'b1;
//Read control channel signals
assign ARID = wr_req ? 'hx : axi_id ;
assign ARADDR = wr_req ? 'hx : axi_addr ;
assign ARLEN = wr_req ? 'hx : axi_len ;
assign ARSIZE = wr_req ? 'hx : axi_size ;
assign ARBURST = wr_req ? 'hx : axi_burst;
assign ARLOCK = wr_req ? 'hx : axi_lock ;
assign ARCACHE = wr_req ? 'hx : axi_cache;
assign ARPROT = wr_req ? 'hx : axi_prot ;
assign ARVALID = wr_req ? 1'b0: axi_valid;
//Read data channel signals
assign RREADY = 1'b1;
 
 
endmodule
/wb2axi4/trunk/model/sram_model.sv
0,0 → 1,61
module sram_model (
CLK,
NCE, //Wr and Rd Select signal
NWRT,
NOE,
DIN,
ADDR,
DOUT
);
parameter MEM_ADDR_W = 10;
parameter MEM_DATA_W = 32;
localparam MEM_DEPTH = 1<<MEM_ADDR_W;
input CLK;
input NCE;
input NWRT;
input NOE;
input [MEM_ADDR_W-1:0] ADDR;
input [MEM_DATA_W-1:0] DIN;
output [MEM_DATA_W-1:0] DOUT;
 
reg [MEM_DATA_W-1:0] r_din;
reg [MEM_DATA_W-1:0] write_data;
reg [MEM_DATA_W-1:0] do_reg;
reg [MEM_ADDR_W-1:0] r_addr;
reg r_nwrt;
reg r_nce;
 
 
reg [MEM_DATA_W-1:0] array[MEM_DEPTH-1:0];
 
event write, read;
 
always @(posedge CLK) begin
r_din = DIN;
r_addr = ADDR;
r_nce = NCE;
r_nwrt = NWRT;
if (!r_nce && !r_nwrt)
->write;
if (!r_nce && r_nwrt)
->read;
end
always @(write) begin
write_data = r_din;
array[r_addr] = write_data;
end
always @(read) begin
do_reg = array[r_addr];
end
 
wire [MEM_DATA_W-1:0] BDO;
genvar i;
generate for (i=0; i<MEM_DATA_W; i=i+1) begin
buf (BDO[i], do_reg[i]);
bufif0 (DOUT[i], BDO[i], NOE);
end
endgenerate
 
 
endmodule
/wb2axi4/trunk/model/wb_slave_model.sv --- wb2axi4/trunk/rtl/axi_ingress.sv (revision 2) +++ wb2axi4/trunk/rtl/axi_ingress.sv (revision 3) @@ -2,6 +2,7 @@ //Date : 03-11-2015 //Basic : How to storage the AXI info and data into sram or fifo. `include "wb2axi_parameters.vh" + module axi_ingress ( axi_clk, reset_n, @@ -12,14 +13,27 @@ fifo_addr_wr, fifo_data_wr ); -parameter AXI_WID_W = 5; -parameter AXI_MAX_RESP_W = 3; +parameter AXI_ID_W = `WB2AXI_AXI_ID_W ; +parameter AXI_ADDR_W = `WB2AXI_AXI_ADDR_W ; +parameter AXI_DATA_W = `WB2AXI_AXI_DATA_W ; +parameter AXI_PROT_W = `WB2AXI_AXI_PROT_W ; +parameter AXI_STB_W = `WB2AXI_AXI_STB_W ; +parameter AXI_LEN_W = `WB2AXI_AXI_LEN_W ; +parameter AXI_SIZE_W = `WB2AXI_AXI_SIZE_W ; +parameter AXI_BURST_W = `WB2AXI_AXI_BURST_W; +parameter AXI_LOCK_W = `WB2AXI_AXI_LOCK_W ; +parameter AXI_CACHE_W = `WB2AXI_AXI_CACHE_W; +parameter AXI_RESP_W = `WB2AXI_AXI_RESP_W ; +parameter AXI_MAX_RESP_W = 3; +parameter FIFO_ADR_W = 10; +parameter FIFO_DAT_W = 10; + input axi_clk; input reset_n; axi_if.target AXI_IF; output fifo_full; -output [FIFO_AW-1:0] fifo_addr_info; -output [FIFO_DW-1:0] fifo_data_info; +output [FIFO_ADR_W-1:0] fifo_addr_info; +output [FIFO_DAT_W-1:0] fifo_data_info; output reg fifo_addr_wr; output reg fifo_data_wr; localparam ST_W = 2; @@ -38,12 +52,12 @@ reg [ST_W-1:0] state; reg [ST_W-1:0] next_state; reg [AXI_MAX_RESP_W-1:0] bresp_pending_cnt; //responses pending to generate -reg [AXI_WID_W-1:0] last_wid; -reg [FIFO_AW-1:0] fifo_addr_in; -reg [FIFO_DW-1:0] fifo_data_in; +reg [AXI_ID_W-1:0] last_wid; +reg [FIFO_ADR_W-1:0] fifo_addr_in; +reg [FIFO_DAT_W-1:0] fifo_data_in; assign input_addr_event = AXI_IF.AWVALID & AXI_IF.AWREADY; -assign input_data_event = AXI_FI.WVALID & AXI_IF.WREADY; +assign input_data_event = AXI_IF.WVALID & AXI_IF.WREADY; assign inc_bresp = AXI_IF.WLAST & input_data_event; assign dec_bresp = AXI_IF.BREADY & AXI_IF.BVALID; assign bresp_cnt_max = (bresp_pending_cnt == AXI_MAX_RESP_VAL); @@ -103,7 +117,7 @@ assign AXI_IF.RRESP = 0; assign AXI_IF.RLAST = 0; assign AXI_IF.RVALID = 0; -assign AIX_IF.AWREADY = (state ==ST_IDLE || state==ST_WDATA) & ~fifo_full & ~bresp_cnt_max; +assign AXI_IF.AWREADY = (state ==ST_IDLE || state==ST_WDATA) & ~fifo_full & ~bresp_cnt_max; assign AXI_IF.WREADY = ~fifo_full & ~bresp_cnt_max; assign fifo_addr_info = fifo_addr_in;
/wb2axi4/trunk/rtl/axi2wb.sv
1,5 → 1,6
//Author : Alex Zhang (cgzhangwei@gmail.com)
//Date : 03-11-2015
`include "wb2axi_parameters.vh"
module axi2wb (
axi_clk,
wb_clk,
9,20 → 10,22
AXI_IF,
WB_TX_IF
);
parameter AXI_WID_W = 4;
parameter AXI_ADDR_W = 32;
parameter AXI_DATA_W = 32;
parameter AXI_PROT_W = 3;
parameter AXI_STB_W = 4;
parameter AXI_LEN_W = 4;
parameter AXI_ASIZE_W = 3;
parameter AXI_ABURST_W = 2;
parameter AXI_ALOCK_W = 2;
parameter AXI_ACACHE_W = 4;
parameter AXI_RESP_W = 2;
parameter AXI_ID_W = `WB2AXI_AXI_ID_W ;
parameter AXI_ADDR_W = `WB2AXI_AXI_ADDR_W ;
parameter AXI_DATA_W = `WB2AXI_AXI_DATA_W ;
parameter AXI_PROT_W = `WB2AXI_AXI_PROT_W ;
parameter AXI_STB_W = `WB2AXI_AXI_STB_W ;
parameter AXI_LEN_W = `WB2AXI_AXI_LEN_W ;
parameter AXI_SIZE_W = `WB2AXI_AXI_SIZE_W ;
parameter AXI_BURST_W = `WB2AXI_AXI_BURST_W;
parameter AXI_LOCK_W = `WB2AXI_AXI_LOCK_W ;
parameter AXI_CACHE_W = `WB2AXI_AXI_CACHE_W;
parameter AXI_RESP_W = `WB2AXI_AXI_RESP_W ;
 
parameter FIFO_DEPTH_W = 10;
parameter FIFO_W = 64;
parameter FIFO_ADDR_DEPTH_W = 10;
parameter FIFO_ADDR_W = AXI_ID_W+AXI_ADDR_W+AXI_PROT_W+AXI_LEN_W+AXI_SIZE_W+AXI_BURST_W+AXI_LOCK_W+AXI_CACHE_W+1;
parameter FIFO_DATA_DEPTH_W = 11;
parameter FIFO_DATA_W = AXI_ID_W+AXI_DATA_W+AXI_STB_W+2;
 
parameter WB_ADR_W = 32;
parameter WB_DAT_W = 32;
33,46 → 36,62
parameter WB_CTI_W = 3;
parameter WB_BTE_W = 2;
 
parameter AXI_MAX_RESP_W = 3;
parameter SRAM_UNUSED_ADDR_W= 4;
 
localparam SRAM_UNUSED_ADDR_W= 4;
localparam AXI_MAX_RESP_W = 4;
localparam FA_SRAM_UNUSED_ADDR_W = 1;
localparam FD_SRAM_UNUSED_ADDR_W = 1;
input wire axi_clk;
input wire wb_clk;
input wire axi_resetn;
input wire wb_resetn;
input wire ENABLE;
axi_if.target AXI_IF;
wb_if.master WB_TX_IF;
sram_if.initiator SRAM_ADR_IF;
sram_if.initiator SRAM_DAT_IF;
wishbone_if.master WB_TX_IF;
 
wire sync_ENABLE_axi;
wire sync_ENABLE_wb;
sram_if #(.DATA_W(32), .ADDR_W(11)) dat_sram_tx();
sram_if #(.DATA_W(64), .ADDR_W(10)) adr_sram_tx();
 
wire sync_ENABLE_axi;
wire sync_ENABLE_wb ;
wire fifo_adr_full ;
wire fifo_dat_full ;
wire [FIFO_DATA_W-1:0] fifo_dat_rdata ;
wire [FIFO_ADDR_W-1:0] fifo_adr_rdata ;
 
sync_doble_ff #(.DATA_W(1)) I_SYNC_ENABLE_AXI (
.CLK ( AXI_CLK ),
.RESET_N ( AXI_RESET_N ),
.CLK ( axi_clk ),
.RESET_N ( axi_resetn ),
.DIN ( ENABLE ),
.DOUT ( sync_ENABLE_axi )
);
sync_doble_ff #(.DATA_W(1)) I_SYNC_ENABLE_WB (
.CLK ( MAC_CLK ),
.RESET_N ( MAC_RESET_N ),
.CLK ( wb_clk ),
.RESET_N ( wb_resetn ),
.DIN ( ENABLE ),
.DOUT ( sync_ENABLE_wb )
);
wire [FIFO_ADDR_W-1:0] fifo_addr_info;
wire [FIFO_DATA_W-1:0] fifo_data_info;
wire fifo_addr_wr ;
wire fifo_data_wr ;
wire [FIFO_ADDR_W-1:0] fifo_adr_wdata;
wire [FIFO_DATA_W-1:0] fifo_dat_wdata;
 
axi_ingress #(
.AXI_WID_W ( AXI_WID_W ),
.AXI_ID_W ( AXI_ID_W ),
.AXI_ADDR_W ( AXI_ADDR_W ),
.AXI_DATA_W ( AXI_DATA_W ),
.AXI_PROT_W ( AXI_PROT_W ),
.AXI_STB_W ( AXI_STB_W ),
.AXI_LEN_W ( AXI_LEN_W ),
.AXI_ASIZE_W ( AXI_ASIZE_W ),
.AXI_ABURST_W ( AXI_ABURST_W ),
.AXI_ALOCK_W ( AXI_ALOCK_W ),
.AXI_ACACHE_W ( AXI_ACACHE_W ),
.AXI_RESP_W ( AXI_RESP_W ),
.AXI_MAX_RESP_W ( AXI_MAX_RESP_W )
.AXI_SIZE_W ( AXI_SIZE_W ),
.AXI_BURST_W ( AXI_BURST_W ),
.AXI_LOCK_W ( AXI_LOCK_W ),
.AXI_CACHE_W ( AXI_CACHE_W ),
.AXI_RESP_W ( AXI_RESP_W ),
.AXI_MAX_RESP_W ( AXI_MAX_RESP_W ),
.FIFO_DAT_W ( FIFO_DATA_W ),
.FIFO_ADR_W ( FIFO_ADDR_W )
) I_AXI_INGRESS (
.axi_clk ( axi_clk ),
.reset_n ( axi_resetn ),
103,7 → 122,32
.fifo_rdata ( fifo_adr_rdata ),
.fifo_empty ( fifo_adr_empty ),
.fifo_full ( fifo_adr_full ),
.fifo_level ( ),
.SRAM_IF ( adr_sram_tx )
);
wire adr_sram_enable;
wire adr_sram_wr;
wire [FIFO_ADDR_W-1:0] adr_sram_din;
wire [FIFO_ADDR_W-1:0] adr_sram_dout;
wire [FIFO_ADDR_DEPTH_W-1:0] adr_sram_addr;
sram_model #(
.MEM_ADDR_W (FIFO_ADDR_DEPTH_W),
.MEM_DATA_W (FIFO_ADDR_W)
) SRAM_ADR_1phc1024x32mx4tn(
.CLK(axi_clk ),
.NCE(adr_sram_enable),
.NWRT(adr_sram_wr ),
.NOE(1'b0 ),
.DIN(adr_sram_din ),
.ADDR(adr_sram_addr ),
.DOUT(adr_sram_dout )
);
assign adr_sram_enable = adr_sram_tx.rd_l | adr_sram_tx.wr_l;
assign adr_sram_wr = adr_sram_tx.wr_l;
assign adr_sram_din = adr_sram_tx.wdata;
assign adr_sram_addr = ~adr_sram_tx.wr_l ? adr_sram_tx.wr_address : adr_sram_tx.rd_address;
assign adr_sram_tx.rdata = adr_sram_dout;
 
assign fifo_adr_wr = fifo_addr_wr;
assign fifo_adr_wdata = fifo_addr_info;
async_fifo #(
123,28 → 167,54
.fifo_rdata ( fifo_dat_rdata ),
.fifo_empty ( fifo_dat_empty ),
.fifo_full ( fifo_dat_full ),
.fifo_level ( ),
.SRAM_IF ( dat_sram_tx )
);
wire dat_sram_enable;
wire dat_sram_wr;
wire [FIFO_DATA_W-1:0] dat_sram_din;
wire [FIFO_DATA_W-1:0] dat_sram_dout;
wire [FIFO_DATA_DEPTH_W-1:0] dat_sram_addr;
sram_model #(
.MEM_ADDR_W (FIFO_DATA_DEPTH_W),
.MEM_DATA_W (FIFO_DATA_W)
) SRAM_DAT_1phc1024x32mx4tn(
.CLK(axi_clk ),
.NCE(dat_sram_enable),
.NWRT(dat_sram_wr ),
.NOE(1'b0 ),
.DIN(dat_sram_din ),
.ADDR(dat_sram_addr),
.DOUT(dat_sram_dout)
);
assign dat_sram_enable = dat_sram_tx.rd_l | dat_sram_tx.wr_l;
assign dat_sram_wr = dat_sram_tx.wr_l;
assign dat_sram_din = dat_sram_tx.wdata;
assign dat_sram_addr = ~dat_sram_tx.wr_l ? dat_sram_tx.wr_address : dat_sram_tx.rd_address;
assign dat_sram_tx.rdata = dat_sram_dout;
 
 
assign fifo_dat_wr = fifo_data_wr;
assign fifo_dat_wdata = fifo_data_info;
wb_egress #(
.WB_ADR_W (WB_ADR_W )
.WB_DAT_W (WB_DAT_W )
.WB_TGA_W (WB_TGA_W )
.WB_TGD_W (WB_TGD_W )
.WB_TGC_W (WB_TGC_W )
.WB_SEL_W (WB_SEL_W )
.WB_CTI_W (WB_CTI_W )
.WB_BTE_W (WB_BTE_W )
.AXI_ID_W (AXI_ID_W )
.AXI_ADDR_W (AXI_ADDR_W )
.AXI_LEN_W (AXI_LEN_W )
.AXI_SIZE_W (AXI_SIZE_W )
.AXI_BURST_W(AXI_BURST_W)
.AXI_LOCK_W (AXI_LOCK_W )
.AXI_CACHE_W(AXI_CACHE_W)
.AXI_PROT_W (AXI_PROT_W )
.AXI_DATA_W (AXI_DATA_W )
.AXI_STRB_W (AXI_STRB_W )
.WB_ADR_W (WB_ADR_W ),
.WB_DAT_W (WB_DAT_W ),
.WB_TGA_W (WB_TGA_W ),
.WB_TGD_W (WB_TGD_W ),
.WB_TGC_W (WB_TGC_W ),
.WB_SEL_W (WB_SEL_W ),
.WB_CTI_W (WB_CTI_W ),
.WB_BTE_W (WB_BTE_W ),
.AXI_ID_W (AXI_ID_W ),
.AXI_ADDR_W (AXI_ADDR_W ),
.AXI_LEN_W (AXI_LEN_W ),
.AXI_SIZE_W (AXI_SIZE_W ),
.AXI_BURST_W(AXI_BURST_W),
.AXI_LOCK_W (AXI_LOCK_W ),
.AXI_CACHE_W(AXI_CACHE_W),
.AXI_PROT_W (AXI_PROT_W ),
.AXI_DATA_W (AXI_DATA_W ),
.AXI_STB_W (AXI_STB_W )
) I_WB_EGRESS(
.wb_clk ( wb_clk ),
.wb_resetn ( wb_resetn ),
155,7 → 225,7
.fifo_adr_empty ( fifo_adr_empty ),
.fifo_dat_rdata ( fifo_dat_rdata ),
.fifo_dat_rd ( fifo_dat_rd ),
.fifo_dat_empty ( fifo_dat_empty ),
.fifo_dat_empty ( fifo_dat_empty )
);
 
endmodule
/wb2axi4/trunk/rtl/gray2bin.sv
0,0 → 1,21
module gray2bin (
// *************************** Ports ********************************
gray ,
bin
);
// ************************ Parameters ******************************
parameter DATA_W = 32 ;
 
// ********************** Inputs/Outputs ****************************
input wire [DATA_W-1:0] gray ;
output wire [DATA_W-1:0] bin ;
 
genvar i ;
generate
for (i=0; i<DATA_W; i++) begin
assign bin[i] = ^(gray >> i);
end
endgenerate
endmodule // gray2bin
/wb2axi4/trunk/rtl/wb_egress.sv
14,7 → 14,7
fifo_adr_empty,
fifo_dat_rdata,
fifo_dat_rd,
fifo_dat_empty,
fifo_dat_empty
);
 
parameter WB_ADR_W = 32;
34,9 → 34,9
parameter AXI_CACHE_W = 4;
parameter AXI_PROT_W = 3;
parameter AXI_DATA_W = 32;
parameter AXI_STRB_W = 4;
parameter AXI_STB_W = 4;
parameter FIFO_ADR_W = AXI_ID_W + AXI_ADDR_W + AXI_LEN_W + AXI_SIZE_W + AXI_BURST_W + AXI_LOCK_W + AXI_CACHE_W + AXI_PROT_W +1 ;
parameter FIFO_DAT_W = AXI_ID_W + AXI_DATA_W + AXI_STRB_W + 2;
parameter FIFO_DAT_W = AXI_ID_W + AXI_DATA_W + AXI_STB_W + 2;
parameter ST_W = 2 ;
parameter ST_IDLE = 2'b00,
ST_READ_ADDR = 2'b01,
47,10 → 47,11
WB_FIRST_DATA = 2'b01,
WB_NEXT_DATA = 2'b10;
 
 
input wire wb_clk;
input wire wb_resetn;
input wire ENABLE;
wb_if.master WB_TX_IF;
wishbone_if.master WB_TX_IF;
input wire [FIFO_ADR_W-1:0] fifo_adr_rdata;
output wire fifo_adr_rd;
input wire fifo_adr_empty;
64,9 → 65,7
reg inc_dat_ptr;
reg [4:0] data_count;
wire allow_adr_rd;
wire fifo_adr_rd;
wire fifo_adr_rd_q;
wire fifo_dat_rd;
reg [AXI_ID_W -1:0] axi_id ;
reg [AXI_ADDR_W -1:0] axi_addr ;
reg [AXI_LEN_W -1:0] axi_len ;
78,7 → 77,7
reg wr_req ;
reg [AXI_ID_W -1:0] axi_wid ;
reg [AXI_DATA_W -1:0] axi_wdata ;
reg [AXI_STRB_W -1:0] axi_wstrb ;
reg [AXI_STB_W -1:0] axi_wstrb ;
reg axi_wlast ;
reg axi_wvalid;
reg wb_we_o ;
85,16 → 84,21
reg [WB_ADR_W-1:0] wb_adr_o;
reg [WB_TGA_W-1:0] wb_tga_o;
reg [WB_ADR_W-1:0] wb_adr_tmp;
reg [AXI_LEN_W-1:0] wb_len_tmp;
reg [WB_BTE_W-1:0] wb_bte_o;
reg wb_cyc_o;
reg [WB_TGC_W-1:0] wb_tgc_o;
reg [WB_CTI_W-1:0] wb_cti_o;
reg [WB_STB_W-1:0] wb_stb_o;
reg wb_stb_o;
reg [WB_DAT_W-1:0] wb_dat_o;
reg [WB_TGD_W-1:0] wb_tgd_o;
reg [WB_SEL_W-1:0] wb_sel_o;
 
reg [WB_W-1:0] wb_cs;
reg [WB_W-1:0] wb_ns;
 
 
 
assign allow_adr_rd = wb_cs == WB_IDLE;
always_comb begin
next_state = state;
111,7 → 115,7
next_state = ST_WAIT_DATA;
end
ST_WAIT_DATA : begin
if (WB_TX_IF.ACK_I & !fifo_dat_empty) begin
if (WB_TX_IF.ACK & !fifo_dat_empty) begin
next_state = ST_READ_DATA;
end else begin
next_state = ST_WAIT_DATA;
118,13 → 122,13
end
end
ST_READ_DATA : begin
if (data_count>0 & WB_TX_IF.ACK_I) begin
if (data_count>0 & WB_TX_IF.ACK) begin
next_state = ST_READ_DATA;
inc_dat_ptr = 1;
end else if (data_count>0) begin
next_state = ST_WAIT_DATA;
inc_dat_ptr = 0;
end
end else begin
next_state = ST_IDLE;
inc_dat_ptr = 0;
end
140,7 → 144,8
.DOUT ( fifo_adr_rd_q ),
.CLK ( wb_clk ),
.RESET_N( wb_resetn )
)
);
 
always @(posedge wb_clk or negedge wb_resetn)
if (~wb_resetn) begin
state <= ST_IDLE;
189,7 → 194,7
wb_ns = wb_cs;
case (wb_cs)
WB_IDLE : begin
if (fifo_data_rd) begin
if (fifo_dat_rd) begin
wb_ns = WB_FIRST_DATA;
end else begin
wb_ns = WB_IDLE;
196,9 → 201,9
end
end
WB_FIRST_DATA : begin
if (axi_wlast & WB_TX_IF.ACK_I)
if (axi_wlast & WB_TX_IF.ACK)
wb_ns = WB_IDLE;
else if (~axi_wlast & WB_TX_IF.ACK_I)
else if (~axi_wlast & WB_TX_IF.ACK)
wb_ns = WB_NEXT_DATA;
else
wb_ns = WB_FIRST_DATA;
205,7 → 210,7
end
WB_NEXT_DATA : begin
if (axi_wlast & WB_TX_IF.ACK_I)
if (axi_wlast & WB_TX_IF.ACK)
wb_ns = WB_IDLE;
else
wb_ns = WB_NEXT_DATA;
285,16 → 290,16
end
end
 
assign WB_TX_IF.ADR_O = wb_adr_o;
assign WB_TX_IF.WE_O = wb_we_o;
assign WB_TX_IF.TGA_O = wb_tga_o;
assign WB_TX_IF.BTE_O = wb_bte_o;
assign WB_TX_IF.CYC_O = wb_cyc_o;
assign WB_TX_IF.TGC_O = wb_tgc_o;
assign WB_TX_IF.CTI_O = wb_cti_o;
assign WB_TX_IF.STB_O = wb_stb_o;
assign WB_TX_IF.ADR = wb_adr_o;
assign WB_TX_IF.WE = wb_we_o;
assign WB_TX_IF.TGA = wb_tga_o;
assign WB_TX_IF.BTE = wb_bte_o;
assign WB_TX_IF.CYC = wb_cyc_o;
assign WB_TX_IF.TGC = wb_tgc_o;
assign WB_TX_IF.CTI = wb_cti_o;
assign WB_TX_IF.STB = wb_stb_o;
assign WB_TX_IF.DAT_O = wb_dat_o;
assign WB_TX_IF.TGD_O = wb_tgd_o;
assign WB_TX_IF.SEL_O = wb_sel_o;
assign WB_TX_IF.SEL = wb_sel_o;
 
endmodule
/wb2axi4/trunk/rtl/ifaces/wishbone_if.sv
7,7 → 7,7
interface wishbone_if #(
WB_ADR_WIDTH = 32,
WB_BTE_WIDTH = 2 ,
WB_CIT_WIDTH = 3 ,
WB_CTI_WIDTH = 3 ,
WB_DAT_WIDTH = 32,
WB_TGA_WIDTH = 8,
WB_TGD_WIDTH = 8,
15,74 → 15,63
WB_SEL_WIDTH = 4
 
);
logic [WB_ADR_WIDTH -1 : 0] ADR;
logic [WB_TGA_WIDTH -1 :0 ] TGA;
logic [WB_DAT_WIDTH -1 : 0] DAT_I;
logic [WB_TGD_WIDTH -1 : 0] TGD_I;
logic [WB_DAT_WIDTH -1 : 0] DAT_O;
logic [WB_TGD_WIDTH -1 : 0] TGD_I;
logic [WB_TGD_WIDTH -1 : 0] TGD_O;
logic ACK_I;
logic [WB_ADR_WIDTH -1 : 0] ADR_O;
logic CYC_O;
logic ERR_I;
logic LOCK_O;
logic RTY_I;
logic [WB_SEL_WIDTH -1 : 0] SEL_O;
logic STB_O;
logic [WB_TGA_WIDTH -1 :0 ] TGA_O;
logic [WB_TGA_WIDTH -1 :0 ] TGC_O;
logic WE_O;
logic [WB_BTE_WIDTH -1 :0 ] BTE_O;
logic [WB_BTE_WIDTH -1 :0 ] BTE_I;
logic [WB_CTI_WIDTH -1 :0 ] CTI_O;
logic [WB_CTI_WIDTH -1 :0 ] CTI_I;
logic WE;
logic [WB_SEL_WIDTH -1 : 0] SEL;
logic STB;
logic ACK;
logic CYC;
logic ERR;
logic LOCK;
logic [WB_BTE_WIDTH -1 :0 ] BTE;
logic RTY;
logic [WB_CTI_WIDTH -1 :0 ] CTI;
logic [WB_TGA_WIDTH -1 :0 ] TGC;
 
 
logic ACK_O;
logic [WB_ADR_WIDTH -1 : 0] ADR_I;
logic CYC_I;
logic ERR_O;
logic LOCK_I;
logic RTY_O;
logic [WB_SEL_WIDTH -1 : 0] SEL_I;
logic [WB_TGA_WIDTH -1 :0 ] TGA_I;
logic [WB_TGA_WIDTH -1 :0 ] TGC_I;
logic WE_I;
 
modport master(
output ADR_O,
output TGA_O,
output ADR ,
output TGA ,
input DAT_I,
input TGD_I,
output DAT_O,
output TGD_O,
output WE_O,
output SEL_O,
output STB_O,
input ACK_I,
output CYC_O,
input ERR_I,
output LOCK_O,
output BTE_O,
input RTY_I,
output TGC_O
output WE ,
output SEL ,
output STB ,
input ACK ,
output CYC ,
input ERR ,
output LOCK ,
output BTE ,
input RTY ,
output CTI ,
output TGC
);
 
modport slave(
output ADR_I,
output TGA_I,
input ADR ,
input TGA ,
output DAT_O,
output TGD_O,
input DAT_I,
input TGD_I,
output DAT_O,
output TGD_O,
output WE_I,
output SEL_I,
output STB_I,
input ACK_O,
output CYC_I,
input ERR_O,
output LOCK_I,
input BTE_I,
input RTY_O,
output TGC_I
input WE ,
input SEL ,
input STB ,
output ACK ,
input CYC ,
output ERR ,
input LOCK ,
input BTE ,
output RTY ,
input CTI ,
input TGC
);
 
 
/wb2axi4/trunk/rtl/ifaces/axi_if.sv
1,59 → 1,59
interface axi_if
#(AXI_WID_WIDTH = 8,
AXI_ADDR_WIDTH = 32,
AXI_DATA_WIDTH = 32,
AXI_PROT_WIDTH = 3,
AXI_STB_WIDTH = 4,
AXI_LEN_W = 4,
AXI_ASIZE_W = 3,
AXI_ABURST_W = 2,
AXI_ALOCK_W = 2,
AXI_ACACHE_W = 4,
AXI_RESP_W = 2
#(AXI_ID_W = 8,
AXI_ADDR_W = 32,
AXI_DATA_W = 32,
AXI_PROT_W = 3,
AXI_STB_W = 4,
AXI_LEN_W = 4,
AXI_SIZE_W = 3,
AXI_BURST_W = 2,
AXI_LOCK_W = 2,
AXI_CACHE_W = 4,
AXI_RESP_W = 2
)
();
 
//Write control channel signals
logic [AXI_WID_WIDTH - 1:0] AWID ;
logic [AXI_ADDR_WIDTH - 1:0] AWADDR ;
logic [AXI_LEN_W - 1:0] AWLEN ;
logic [AXI_ASIZE_W - 1:0] AWSIZE ;
logic [AXI_ABURST_W - 1:0] AWBURST ;
logic [AXI_ALOCK_W - 1:0] AWLOCK ;
logic [AXI_ACACHE_W - 1:0] AWCACHE ;
logic [AXI_PROT_WIDTH - 1:0] AWPROT ;
logic AWVALID ;
logic AWREADY ;
logic [AXI_ID_W - 1:0] AWID ;
logic [AXI_ADDR_W - 1:0] AWADDR ;
logic [AXI_LEN_W - 1:0] AWLEN ;
logic [AXI_SIZE_W - 1:0] AWSIZE ;
logic [AXI_BURST_W - 1:0] AWBURST ;
logic [AXI_LOCK_W - 1:0] AWLOCK ;
logic [AXI_CACHE_W - 1:0] AWCACHE ;
logic [AXI_PROT_W - 1:0] AWPROT ;
logic AWVALID ;
logic AWREADY ;
//write data channel signals
logic [AXI_WID_WIDTH - 1:0] WID ;
logic [AXI_DATA_WIDTH - 1:0] WDATA ;
logic [AXI_STB_WIDTH - 1:0] WSTRB ;
logic WLAST ;
logic WVALID ;
logic WREADY ;
logic [AXI_ID_W - 1:0 ] WID ;
logic [AXI_DATA_W - 1:0] WDATA ;
logic [AXI_STB_W - 1:0] WSTRB ;
logic WLAST ;
logic WVALID ;
logic WREADY ;
//write response channel
logic [AXI_WID_WIDTH - 1:0] BID ;
logic [AXI_RESP_W - 1:0] BRESP ;
logic BVALID ;
logic BREADY ;
logic [AXI_ID_W - 1:0] BID ;
logic [AXI_RESP_W - 1:0] BRESP ;
logic BVALID ;
logic BREADY ;
//Read control channel signals
logic [AXI_WID_WIDTH - 1:0] ARID ;
logic [AXI_ADDR_WIDTH - 1:0] ARADDR ;
logic [AXI_ID_W - 1:0] ARID ;
logic [AXI_ADDR_W - 1:0] ARADDR ;
logic [AXI_LEN_W - 1:0] ARLEN ;
logic [AXI_ASIZE_W - 1:0] ARSIZE ;
logic [AXI_ABURST_W - 1:0] ARBURST ;
logic [AXI_ALOCK_W - 1:0] ARLOCK ;
logic [AXI_ACACHE_W - 1:0] ARCACHE ;
logic [AXI_PROT_WIDTH - 1:0] ARPROT ;
logic [AXI_SIZE_W - 1:0] ARSIZE ;
logic [AXI_BURST_W - 1:0] ARBURST ;
logic [AXI_LOCK_W - 1:0] ARLOCK ;
logic [AXI_CACHE_W - 1:0] ARCACHE ;
logic [AXI_PROT_W - 1:0] ARPROT ;
logic ARVALID ;
logic ARREADY ;
//Read data channel signals
logic [AXI_WID_WIDTH - 1:0] RID ;
logic [AXI_DATA_WIDTH - 1:0] RDATA ;
logic [AXI_RESP_W - 1:0] RRESP ;
logic RLAST ;
logic RVALID ;
logic RREADY ;
logic [AXI_ID_W - 1:0] RID ;
logic [AXI_DATA_W - 1:0] RDATA ;
logic [AXI_RESP_W - 1:0] RRESP ;
logic RLAST ;
logic RVALID ;
logic RREADY ;
 
modport initiator (
//Write control channel signals
/wb2axi4/trunk/verif/env.csh
0,0 → 1,59
setenv PROJ_TOP /proj/msbgbe0/wa/alzhang/proj/wb2axi
/wb2axi4/trunk/verif/src.vlist
0,0 → 1,15
$PROJ_TOP/rtl/async_fifo.sv
$PROJ_TOP/rtl/ifaces/axi_if.sv
$PROJ_TOP/rtl/ifaces/wishbone_if.sv
$PROJ_TOP/rtl/ifaces/sram_if.sv
$PROJ_TOP/rtl/axi2wb.sv
$PROJ_TOP/rtl/axi_ingress.sv
$PROJ_TOP/rtl/bin2gray.sv
$PROJ_TOP/rtl/gray2bin.sv
$PROJ_TOP/rtl/sync_double_ff.sv
$PROJ_TOP/rtl/sync_single_ff.sv
$PROJ_TOP/rtl/wb_egress.sv
$PROJ_TOP/model/axi_master_model.sv
$PROJ_TOP/model/sram_model.sv
$PROJ_TOP/verif/tb.v
+incdir+$PROJ_TOP/verif
/wb2axi4/trunk/verif/tb.v
0,0 → 1,148
`include "wb2axi_parameters.vh"
module tb;
 
reg axi_clk;
reg wb_clk;
reg resetn;
 
axi_if #(
.AXI_ID_W (`WB2AXI_AXI_ID_W ),
.AXI_ADDR_W (`WB2AXI_AXI_ADDR_W ),
.AXI_DATA_W (`WB2AXI_AXI_DATA_W ),
.AXI_PROT_W (`WB2AXI_AXI_PROT_W ),
.AXI_STB_W (`WB2AXI_AXI_STB_W ),
.AXI_LEN_W (`WB2AXI_AXI_LEN_W ),
.AXI_SIZE_W (`WB2AXI_AXI_SIZE_W ),
.AXI_BURST_W (`WB2AXI_AXI_BURST_W ),
.AXI_LOCK_W (`WB2AXI_AXI_LOCK_W ),
.AXI_CACHE_W (`WB2AXI_AXI_CACHE_W ),
.AXI_RESP_W (`WB2AXI_AXI_RESP_W )
) axi_if_m();
 
wishbone_if #(
.WB_ADR_WIDTH(`WB2AXI_WB_ADR_W) ,
.WB_BTE_WIDTH(`WB2AXI_WB_BTE_W) ,
.WB_CTI_WIDTH(`WB2AXI_WB_CTI_W) ,
.WB_DAT_WIDTH(`WB2AXI_WB_DAT_W) ,
.WB_TGA_WIDTH(`WB2AXI_WB_TGA_W) ,
.WB_TGD_WIDTH(`WB2AXI_WB_TGD_W) ,
.WB_TGC_WIDTH(`WB2AXI_WB_TGC_W) ,
.WB_SEL_WIDTH(`WB2AXI_WB_SEL_W)
) wb_if_s();
 
assign wb_if_s.ACK = 1'b1;
 
axi_master_model# (
.AXI_ID_W (`WB2AXI_AXI_ID_W ),
.AXI_ADDR_W (`WB2AXI_AXI_ADDR_W ),
.AXI_DATA_W (`WB2AXI_AXI_DATA_W ),
.AXI_PROT_W (`WB2AXI_AXI_PROT_W ),
.AXI_STB_W (`WB2AXI_AXI_STB_W ),
.AXI_LEN_W (`WB2AXI_AXI_LEN_W ),
.AXI_SIZE_W (`WB2AXI_AXI_SIZE_W ),
.AXI_BURST_W (`WB2AXI_AXI_BURST_W ),
.AXI_LOCK_W (`WB2AXI_AXI_LOCK_W ),
.AXI_CACHE_W (`WB2AXI_AXI_CACHE_W ),
.AXI_RESP_W (`WB2AXI_AXI_RESP_W )
)I_AXIM (
.axi_clk (axi_clk ),
.axi_resetn (resetn ),
.AWID (axi_if_m.AWID ),
.AWADDR (axi_if_m.AWADDR ),
.AWLEN (axi_if_m.AWLEN ),
.AWSIZE (axi_if_m.AWSIZE ),
.AWBURST (axi_if_m.AWBURST),
.AWLOCK (axi_if_m.AWLOCK ),
.AWCACHE (axi_if_m.AWCACHE),
.AWPROT (axi_if_m.AWPROT ),
.AWVALID (axi_if_m.AWVALID),
.AWREADY (axi_if_m.AWREADY),
.WID (axi_if_m.WID ),
.WDATA (axi_if_m.WDATA ),
.WSTRB (axi_if_m.WSTRB ),
.WLAST (axi_if_m.WLAST ),
.WVALID (axi_if_m.WVALID ),
.WREADY (axi_if_m.WREADY ),
.BID (axi_if_m.BID ),
.BRESP (axi_if_m.BRESP ),
.BVALID (axi_if_m.BVALID ),
.BREADY (axi_if_m.BREADY ),
.ARID (axi_if_m.ARID ),
.ARADDR (axi_if_m.ARADDR ),
.ARLEN (axi_if_m.ARLEN ),
.ARSIZE (axi_if_m.ARSIZE ),
.ARBURST (axi_if_m.ARBURST),
.ARLOCK (axi_if_m.ARLOCK ),
.ARCACHE (axi_if_m.ARCACHE),
.ARPROT (axi_if_m.ARPROT ),
.ARVALID (axi_if_m.ARVALID),
.ARREADY (axi_if_m.ARREADY),
.RID (axi_if_m.RID ),
.RDATA (axi_if_m.RDATA ),
.RRESP (axi_if_m.RRESP ),
.RLAST (axi_if_m.RLAST ),
.RVALID (axi_if_m.RVALID ),
.RREADY (axi_if_m.RREADY )
);
 
 
axi2wb #(
.AXI_ID_W (`WB2AXI_AXI_ID_W ),
.AXI_ADDR_W (`WB2AXI_AXI_ADDR_W ),
.AXI_DATA_W (`WB2AXI_AXI_DATA_W ),
.AXI_PROT_W (`WB2AXI_AXI_PROT_W ),
.AXI_STB_W (`WB2AXI_AXI_STB_W ),
.AXI_LEN_W (`WB2AXI_AXI_LEN_W ),
.AXI_SIZE_W (`WB2AXI_AXI_SIZE_W ),
.AXI_BURST_W (`WB2AXI_AXI_BURST_W ),
.AXI_LOCK_W (`WB2AXI_AXI_LOCK_W ),
.AXI_CACHE_W (`WB2AXI_AXI_CACHE_W ),
.AXI_RESP_W (`WB2AXI_AXI_RESP_W ),
.FIFO_ADDR_DEPTH_W(`WB2AXI_FIFO_ADDR_DEPTH_W),
.FIFO_DATA_DEPTH_W(`WB2AXI_FIFO_DATA_DEPTH_W),
.WB_ADR_W (`WB2AXI_WB_ADR_W ),
.WB_DAT_W (`WB2AXI_WB_DAT_W ),
.WB_TGA_W (`WB2AXI_WB_TGA_W ),
.WB_TGD_W (`WB2AXI_WB_TGD_W ),
.WB_TGC_W (`WB2AXI_WB_TGC_W ),
.WB_SEL_W (`WB2AXI_WB_SEL_W ),
.WB_CTI_W (`WB2AXI_WB_CTI_W ),
.WB_BTE_W (`WB2AXI_WB_BTE_W )
) I_AXI2WB (
.axi_clk (axi_clk ),
.wb_clk (wb_clk ),
.axi_resetn(resetn ),
.wb_resetn (resetn ),
.ENABLE (1'b1 ),
.AXI_IF (axi_if_m),
.WB_TX_IF (wb_if_s )
);
 
initial begin
wb_clk = 1'b1;
axi_clk= 1'b1;
resetn = 1'b1;
#10;
resetn = 1'b0;
#100;
$display ("Resetn is done");
resetn = 1'b1;
#20000;
$display ("Simulation is done");
$finish;
end
always begin
#2;
axi_clk = ~axi_clk;
end
 
always begin
#5 wb_clk = ~wb_clk;
end
 
initial begin
$fsdbDumpfile("./test_wb2axi.fsdb");
$fsdbDumpvars(0, tb);
end
 
endmodule
/wb2axi4/trunk/verif/wb2axi_parameters.vh
0,0 → 1,25
`define WB2AXI_AXI_ID_W 4
`define WB2AXI_AXI_ADDR_W 32
`define WB2AXI_AXI_DATA_W 32
`define WB2AXI_AXI_PROT_W 3
`define WB2AXI_AXI_STB_W 4
`define WB2AXI_AXI_LEN_W 4
`define WB2AXI_AXI_SIZE_W 3
`define WB2AXI_AXI_BURST_W 2
`define WB2AXI_AXI_LOCK_W 2
`define WB2AXI_AXI_CACHE_W 4
`define WB2AXI_AXI_RESP_W 2
 
`define WB2AXI_FIFO_ADDR_DEPTH_W 10
`define WB2AXI_FIFO_ADDR_W 64
`define WB2AXI_FIFO_DATA_DEPTH_W 11
`define WB2AXI_FIFO_DATA_W 64
`define WB2AXI_WB_ADR_W 32
`define WB2AXI_WB_DAT_W 32
`define WB2AXI_WB_TGA_W 8
`define WB2AXI_WB_TGD_W 8
`define WB2AXI_WB_TGC_W 4
`define WB2AXI_WB_SEL_W 4
`define WB2AXI_WB_CTI_W 3
`define WB2AXI_WB_BTE_W 2
 
/wb2axi4/trunk/verif/Makefile
0,0 → 1,32
VCS=/proj/cadtools/bin/vcs
TGT=simv
VERICOM=/proj/cadtools/bin/vericom
VERDI=/proj/cadtools/bin/verdi
TAB_FILE=/proj/cadsim/simtools/simtools2.linux/pli64_rh4/dummytbv.tab
PLI_FILE=/proj/cadsim/simtools/simtools2.linux/pli64_rh4/dummytbv_vcs.a
VERDI_TAB=/proj/caeeda/NOVAS/VERDI/201403-3/share/PLI/VCS/LINUX/verdi.tab
VERDI_PLI=/proj/caeeda/NOVAS/VERDI/201403-3/share/PLI/VCS/LINUX/pli.a
SIM_DIR= $(PROJ_TOP)/output/
SRCFILE = src.vlist
 
FLAGS= +lint=TFIPC-L -P $(VERDI_TAB) $(VERDI_PLI) -unit_timescale=1ps/1ps
all:simv
 
setup:
mkdir -p $(SIM_DIR)
cd $(SIM_DIR); ln -fs $(PROJ_TOP)/verif/* .
 
$(TGT):$(SRCFILE)
rm out -rf
mkdir out
$(VCS) -sverilog $(FLAGS) +define+DUMPFSDB -f $(SRCFILE) -sgq short
 
run: $(TGT)
/proj/caeeda/SYNOPSYS/bin/simv -sgq normal
 
run_verdi:
$(VERDI) -f src.vlist -top tb -ssf $(SIM_DIR)/test_wb2axi.fsdb -sgq normal
 
clean:
rm simv; rm csrc -rf; rm *.daidir -rf; rm out -rf; rm verdiLog -rf; rm vcs.log; rm novas.*; rm ucli.key
 

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