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/trunk/rtl/verilog/serirq_slave.v
0,0 → 1,200
//////////////////////////////////////////////////////////////////////
//// ////
//// $Id: serirq_slave.v,v 1.1 2008-03-10 14:08:13 hharte Exp $ ////
//// serirq_slave.v - Wishbone Slave to SERIRQ Host Bridge ////
//// ////
//// This file is part of the Wishbone LPC Bridge project ////
//// http://www.opencores.org/projects/lpc/ ////
//// ////
//// Author: ////
//// - Howard M. Harte (hharte@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Howard M. Harte ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1 ns / 1 ns
 
`include "../../rtl/verilog/serirq_defines.v"
 
module serirq_slave(clk_i, nrst_i,
irq_i,
serirq_o, serirq_i, serirq_oe
);
// Wishbone Slave Interface
input clk_i;
input nrst_i; // Active low reset.
// SERIRQ Master Interface
output reg serirq_o; // SERIRQ output
input serirq_i; // SERIRQ Input
output reg serirq_oe; // SERIRQ Output Enable
 
input [31:0] irq_i; // IRQ Input Bus
reg [31:0] current_irq;
 
reg [12:0] state; // Current state
reg [4:0] irq_cnt; // IRQ Frame counter
 
reg found_stop;
reg found_start;
reg serirq_mode;
 
wire irq_changed = (serirq_mode & (current_irq != irq_i));
always @(posedge clk_i or negedge nrst_i)
if(~nrst_i)
begin
state <= `SERIRQ_ST_IDLE;
serirq_oe <= 1'b0;
serirq_o <= 4'b1;
irq_cnt <= 5'h00;
current_irq <= irq_i;
end
else begin
case(state)
`SERIRQ_ST_IDLE:
begin
serirq_oe <= 1'b0;
irq_cnt <= 5'h00;
serirq_o <= 1'b1;
 
if(found_start == 1'b1) // Wait for Start cycle
begin
current_irq <= irq_i;
if(irq_i[irq_cnt] == 1'b0) begin
serirq_oe <= 1'b1;
serirq_o <= 1'b0;
end
state <= `SERIRQ_ST_IRQ_R;
end
else if(irq_changed) begin
current_irq <= irq_i;
serirq_o <= 1'b0;
serirq_oe <= 1'b1;
state <= `SERIRQ_ST_IDLE;
end else
state <= `SERIRQ_ST_IDLE;
end
`SERIRQ_ST_IRQ:
begin
if(irq_i[irq_cnt] == 1'b0) begin
serirq_oe <= 1'b1;
serirq_o <= 1'b0;
end
if(found_stop == 1'b0)
state <= `SERIRQ_ST_IRQ_R;
else
state <= `SERIRQ_ST_IDLE;
end
`SERIRQ_ST_IRQ_R:
begin
serirq_o <= 1'b1;
if(found_stop == 1'b0)
state <= `SERIRQ_ST_IRQ_T;
else
state <= `SERIRQ_ST_IDLE;
end
`SERIRQ_ST_IRQ_T:
begin
serirq_oe <= 1'b0;
if(irq_cnt == 5'h1f)
begin
state <= `SERIRQ_ST_WAIT_STOP;
end
else begin
irq_cnt <= irq_cnt + 1;
if(found_stop == 1'b0)
state <= `SERIRQ_ST_IRQ;
else
state <= `SERIRQ_ST_IDLE;
end
end
`SERIRQ_ST_WAIT_STOP:
begin
if(found_stop == 1'b0)
state <= `SERIRQ_ST_WAIT_STOP;
else
state <= `SERIRQ_ST_IDLE;
end
endcase
end
 
reg [3:0] stop_clk_cnt;
 
// Look for STOP cycles
always @(posedge clk_i or negedge nrst_i)
if(~nrst_i)
begin
found_stop <= 1'b0;
found_start <= 1'b0;
serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
stop_clk_cnt <= 4'h0;
end
else begin
if(serirq_i == 1'b0) begin
stop_clk_cnt <= stop_clk_cnt + 1;
end
else begin
case (stop_clk_cnt)
4'h2:
begin
found_stop <= 1'b1;
found_start <= 1'b0;
serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
end
4'h3:
begin
found_stop <= 1'b1;
found_start <= 1'b0;
serirq_mode <= `SERIRQ_MODE_QUIET;
end
4'h4:
begin
found_stop <= 1'b0;
found_start <= 1'b1;
end
4'h6:
begin
found_stop <= 1'b0;
found_start <= 1'b1;
end
4'h8:
begin
found_stop <= 1'b0;
found_start <= 1'b1;
end
default:
begin
found_stop <= 1'b0;
found_start <= 1'b0;
end
endcase
stop_clk_cnt <= 4'h0;
end
end
endmodule
 
trunk/rtl/verilog/serirq_slave.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/verilog/serirq_defines.v =================================================================== --- trunk/rtl/verilog/serirq_defines.v (nonexistent) +++ trunk/rtl/verilog/serirq_defines.v (revision 11) @@ -0,0 +1,53 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// $Id: serirq_defines.v,v 1.1 2008-03-10 14:08:13 hharte Exp $ +//// wb_lpc_defines.v //// +//// //// +//// This file is part of the Wishbone LPC Bridge project //// +//// http://www.opencores.org/projects/wb_lpc/ //// +//// //// +//// Author: //// +//// - Howard M. Harte (hharte@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Howard M. Harte //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// Wishbone SERIRQ Host/Slave Interface Definitions +`define SERIRQ_ST_IDLE 13'h000 // SERIRQ Idle state +`define SERIRQ_ST_START 13'h001 // SERIRQ Start state +`define SERIRQ_ST_START_R 13'h002 // SERIRQ Start state +`define SERIRQ_ST_START_T 13'h004 // SERIRQ Start state +`define SERIRQ_ST_IRQ 13'h008 // SERIRQ IRQ Frame State +`define SERIRQ_ST_IRQ_R 13'h010 // SERIRQ IRQ Frame State +`define SERIRQ_ST_IRQ_T 13'h020 // SERIRQ IRQ Frame State +`define SERIRQ_ST_STOP 13'h040 // SERIRQ Stop State +`define SERIRQ_ST_STOP_R 13'h080 // SERIRQ Stop State +`define SERIRQ_ST_STOP_T 13'h100 // SERIRQ Stop State +`define SERIRQ_ST_WAIT_STOP 13'h200 + +`define SERIRQ_MODE_CONTINUOUS 1'b0 // Serirq "Continuous Mode" +`define SERIRQ_MODE_QUIET 1'b1 // Serirq "Quiet Mode"
trunk/rtl/verilog/serirq_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/verilog/serirq_host.v =================================================================== --- trunk/rtl/verilog/serirq_host.v (nonexistent) +++ trunk/rtl/verilog/serirq_host.v (revision 11) @@ -0,0 +1,172 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// $Id: serirq_host.v,v 1.1 2008-03-10 14:08:13 hharte Exp $ //// +//// serirq_host.v - SERIRQ Host Controller //// +//// //// +//// This file is part of the Wishbone LPC Bridge project //// +//// http://www.opencores.org/projects/wb_lpc/ //// +//// //// +//// Author: //// +//// - Howard M. Harte (hharte@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Howard M. Harte //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`timescale 1 ns / 1 ns + +`include "../../rtl/verilog/serirq_defines.v" + +module serirq_host(clk_i, nrst_i, + serirq_mode_i, irq_o, + serirq_o, serirq_i, serirq_oe +); + // Wishbone Slave Interface + input clk_i; + input nrst_i; // Active low reset. + input serirq_mode_i; + + // SERIRQ Master Interface + output reg serirq_o; // SERIRQ output + input serirq_i; // SERIRQ Input + output reg serirq_oe; // SERIRQ Output Enable + + output reg [31:0] irq_o; // IRQ Output Bus + + reg [12:0] state; // Current state + reg [4:0] irq_cnt; // IRQ Frame counter + reg [2:0] start_cnt; // START counter + reg [2:0] stop_cnt; // STOP counter + reg current_mode; + + always @(posedge clk_i or negedge nrst_i) + if(~nrst_i) + begin + state <= `SERIRQ_ST_IDLE; + serirq_oe <= 1'b0; + serirq_o <= 4'b1; + irq_cnt <= 5'h00; + start_cnt <= 3'b000; + stop_cnt <= 2'b00; + irq_o <= 32'hFFFFFFFF; + current_mode <= `SERIRQ_MODE_CONTINUOUS; + end + else begin + case(state) + `SERIRQ_ST_IDLE: + begin + serirq_oe <= 1'b0; + start_cnt <= 3'b000; + stop_cnt <= 2'b00; + serirq_o <= 1'b1; + if((current_mode == `SERIRQ_MODE_QUIET) && (serirq_i == 1'b0)) begin + start_cnt <= 3'b010; + serirq_o <= 1'b0; + serirq_oe <= 1'b1; + state <= `SERIRQ_ST_START; + end + else if(current_mode == `SERIRQ_MODE_CONTINUOUS) + begin + start_cnt <= 3'b000; + state <= `SERIRQ_ST_START; + end + else if((current_mode == `SERIRQ_MODE_QUIET) && (serirq_mode_i == `SERIRQ_MODE_CONTINUOUS)) + begin // Switch to Continuous mode if by starting a new cycle to inform the slaves. + start_cnt <= 3'b000; + state <= `SERIRQ_ST_START; + end + else + state <= `SERIRQ_ST_IDLE; + end + `SERIRQ_ST_START: + begin + serirq_o <= 1'b0; + serirq_oe <= 1'b1; + irq_cnt <= 5'h00; + start_cnt <= start_cnt + 1; + if(start_cnt == 3'b111) begin + state <= `SERIRQ_ST_START_R; + end + else begin + state <= `SERIRQ_ST_START; + end + end + `SERIRQ_ST_START_R: + begin + serirq_o <= 1'b1; + state <= `SERIRQ_ST_START_T; + end + `SERIRQ_ST_START_T: + begin + serirq_oe <= 1'b0; + state <= `SERIRQ_ST_IRQ; + end + `SERIRQ_ST_IRQ: + begin + state <= `SERIRQ_ST_IRQ_R; + end + `SERIRQ_ST_IRQ_R: + begin + irq_o[irq_cnt] <= (serirq_i == 1'b0 ? 1'b0 : 1'b1); + state <= `SERIRQ_ST_IRQ_T; + end + `SERIRQ_ST_IRQ_T: + begin + if(irq_cnt == 5'h1f) begin + state <= `SERIRQ_ST_STOP; + end else begin + state <= `SERIRQ_ST_IRQ; + irq_cnt <= irq_cnt + 1; + end + end + `SERIRQ_ST_STOP: + begin + serirq_o <= 1'b0; + serirq_oe <= 1'b1; + stop_cnt <= stop_cnt + 1; + if(stop_cnt == (serirq_mode_i ? 2'b10 : 2'b01)) begin + state <= `SERIRQ_ST_STOP_R; + end + else begin + state <= `SERIRQ_ST_STOP; + end + end + `SERIRQ_ST_STOP_R: + begin + serirq_o <= 1'b1; + state <= `SERIRQ_ST_STOP_T; + end + `SERIRQ_ST_STOP_T: + begin + serirq_oe <= 1'b0; + state <= `SERIRQ_ST_IDLE; + current_mode <= serirq_mode_i; + end + endcase + end +endmodule + +
trunk/rtl/verilog/serirq_host.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/verilog/wb_lpc_defines.v =================================================================== --- trunk/rtl/verilog/wb_lpc_defines.v (revision 10) +++ trunk/rtl/verilog/wb_lpc_defines.v (revision 11) @@ -43,8 +43,8 @@ `define LPC_FW_WRITE 4'b1110 `define LPC_SYNC_READY 4'b0000 // LPC Sync Ready -`define LPC_SYNC_SWAIT 4'b0101 // LPC Sync Short Wait -`define LPC_SYNC_LWAIT 4'b0110 // LPC Sync Long Wait +`define LPC_SYNC_SWAIT 4'b0101 // LPC Sync Short Wait (up to 8 cycles) +`define LPC_SYNC_LWAIT 4'b0110 // LPC Sync Long Wait (no limit) `define LPC_SYNC_MORE 4'b1001 // LPC Sync Ready More (DMA only) `define LPC_SYNC_ERROR 4'b1010 // LPC Sync Error

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