URL
https://opencores.org/ocsvn/wb_lpc/wb_lpc/trunk
Subversion Repositories wb_lpc
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- This comparison shows the changes necessary to convert path
/
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/trunk/examples/lpc_7seg/lpc_7seg.ucf
0,0 → 1,28
#PACE: Start of Constraints generated by PACE |
|
#PACE: Start of PACE I/O Pin Assignments |
NET "DISP_LED<0>" LOC = "AB20" | IOSTANDARD = LVCMOS33 ; |
NET "DISP_LED<1>" LOC = "AA20" | IOSTANDARD = LVCMOS33 ; |
NET "DISP_LED<2>" LOC = "V18" | IOSTANDARD = LVCMOS33 ; |
NET "DISP_LED<3>" LOC = "Y17" | IOSTANDARD = LVCMOS33 ; |
NET "DISP_LED<4>" LOC = "AB18" | IOSTANDARD = LVCMOS33 ; |
NET "DISP_LED<5>" LOC = "AA18" | IOSTANDARD = LVCMOS33 ; |
NET "DISP_LED<6>" LOC = "W18" | IOSTANDARD = LVCMOS33 ; |
NET "DISP_SEL<0>" LOC = "AA17" | IOSTANDARD = LVCMOS33 ; |
NET "DISP_SEL<1>" LOC = "U17" | IOSTANDARD = LVCMOS33 ; |
NET "DISP_SEL<2>" LOC = "U16" | IOSTANDARD = LVCMOS33 ; |
NET "DISP_SEL<3>" LOC = "U14" | IOSTANDARD = LVCMOS33 ; |
NET "LAD<0>" LOC = "V5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | IOBDELAY = BOTH | KEEPER ; |
NET "LAD<1>" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | IOBDELAY = BOTH | KEEPER ; |
NET "LAD<2>" LOC = "V2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | IOBDELAY = BOTH | KEEPER ; |
NET "LAD<3>" LOC = "V1" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | IOBDELAY = BOTH | KEEPER ; |
NET "LAD_OE" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ; |
NET "LFRAME" LOC = "W2" | IOSTANDARD = LVCMOS33 ; |
NET "LPC_CLK" LOC = "W1" | IOSTANDARD = LVCMOS33 ; |
NET "RST" LOC = "A19" | IOSTANDARD = PCI33_3 ; |
|
#PACE: Start of PACE Area Constraints |
|
#PACE: Start of PACE Prohibit Constraints |
|
#PACE: End of Constraints generated by PACE |
trunk/examples/lpc_7seg/lpc_7seg.ucf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/examples/lpc_7seg/lpc_7seg.bit
===================================================================
--- trunk/examples/lpc_7seg/lpc_7seg.bit (nonexistent)
+++ trunk/examples/lpc_7seg/lpc_7seg.bit (revision 7)
@@ -0,0 +1,82 @@
+ a
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+
+ @ ! @ H @ @
+
+
+
+ @ P0P 0 p P
+ 0 0 x $p H $H $@ ̈
+ H A P @ !
+ p @ A @ PJ 0 QT0 @ @@ @ 0@
+ p p t p p0 X @ @ H_̻Ȁ
+N 0 x x 0 x 0 x H H H 3 N
+ "T 3 @ @ H p # Db FD "AD @ ! @ (D.H .0 h @@ 0A
+(" I@ @ p @ 0 P ņ + ! ! @" @ 0 n M
+
+
+P
+
+
+ 00p 0 4 0 0 0 PA_̀?̌ x 0 0 0 0 $x x x H H H ̊ @ "QQ 3 @ @ 0p @ b C @ "`D P@A
+ ( H 0
+ iHb ' AR@q&@ t
+ @ 8@ @ @4 # @ AW $ p @ EB ` 8 cC 9A b0F 0 U A KHD$G
+@
+ B@"" $4$"(,( "P @
+ ` 0`
+
+ 0 T < p 00 0 P 00 0 p 0 @ @ $p $p $p 0 8 $p 0 0 $x 0 $@ $@ ظ_Ĩ H H 5 $ " " A H A"@ @(Pa
+ * P @0 @!. ' ! A %@ ( A A ` 0C@ Ъ 0 -h aF L@ h`C s . ! @!2A!Q (@"@ D@@ P P 0 p n0P Z 0 0T
+ ,( 4p 00 | < @ D @ ! A D $p p $p 0 0 $p $p 8 $@ $@ $@ $@ $@ D* 0@ @@ H @@ $I @ ! @ ! 4@ @ @ H @
+ @ C P 4 t x ( @ &
+I B "
+ "I !@ ( !@ @ 0p >0 000
+ q
+P
+
+ 0p 80<< 00 00 @
+ 0 ϯ " 0 8 $p 0 $p 0$p 0 0 $@ $@ P
+"O @ @
+
+ @ $ P # D@ # A V ` 9 ` ( @ 8 N` 8 &
+ 1@ @ `@` 4 ( (
+ 0B ) 4 x@ 4
+@
+" " 0! @ ` 0 h@
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+
+j P \ 0 0 0 0 @ @ @
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+H & H H $ " P @ 0 ^: r ,8 , 0 8 < 5
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+ ` @
+^ 0 P X 0 0 0 @ @
+ $p $p "
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+ 0 0 0 B
+ 0 0 p 0 p $@ $@ @ D @ $ P
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+
+ @ 0 0
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\ No newline at end of file
trunk/examples/lpc_7seg/lpc_7seg.bit
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/examples/lpc_7seg/lpc_7seg.ise
===================================================================
--- trunk/examples/lpc_7seg/lpc_7seg.ise (nonexistent)
+++ trunk/examples/lpc_7seg/lpc_7seg.ise (revision 7)
@@ -0,0 +1,3332 @@
+PK
+
+ __OBJSTORE__/PK
+ __OBJSTORE__/common/PK
+ ' __OBJSTORE__/common/HierarchicalDesign/PK
+ T ~ ~ 0 __OBJSTORE__/common/HierarchicalDesign/HDProject PK
+ ^ ^ 7 __OBJSTORE__/common/HierarchicalDesign/HDProject_StrTbl
+ 1 4 /lpc_7seg TS_EXPANDED TS_FRAGCOVERED TS_PACKED TS_ROUTED TS_SYNTHESIS lpc_7seg PK
+ ";< < + __OBJSTORE__/common/__stored_object_table__ ( : PK
+ __OBJSTORE__/HierarchicalDesign/PK
+ __OBJSTORE__/PnAutoRun/PK
+ __OBJSTORE__/PnAutoRun/Scripts/PK
+ > * __OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl PK
+ 髭 1 __OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl namespace eval xilinx {
+namespace eval Dpm {
+proc GetIseVersion {} {
+ set fsetName "fileset.txt"
+ set fsetPath ""
+ # Find the file in the Xilinx environment.
+ # First, construct the environment path.
+ set sep ":"; # Default to UNIX style seperator.
+ if {[string compare -length 7 $::tcl_platform(platform) "windows"] == 0} {
+ set sep ";"; # Platform is a Windows variant, so use semi-colon.
+ }
+ set xilinxPath $::env(XILINX)
+ if [info exists ::env(MYXILINX)] then {
+ set xilinxPath [join [list $::env(MYXILINX) $xilinxPath] $sep]
+ }
+ # Now look in each path of the path until we find a match.
+ foreach xilElem [split $xilinxPath $sep] {
+ set checkPath ${xilElem}/$fsetName
+ set checkPath [ string map { \\ / } $checkPath ]
+ if { [file exists $checkPath] } {
+ set fsetPath $checkPath
+ break
+ }
+ }
+ if { [string equal $fsetPath ""] } {
+ puts "ERROR: Can not determine the ISE software version."
+ return ""
+ }
+ if { [catch { open $fsetPath r } fset] } {
+ puts "ERROR: Could not open $fsetPath: $fset"
+ return ""
+ }
+ # have the file open, scan for the version entry.
+ set sVersion ""
+ while { ![eof $fset] } {
+ set line [gets $fset]
+ regexp {version=(.*)} $line match sVersion
+ # The above doesn't stop looking in the file. This assumes that if
+ # there are multiple version entries, the last one is the one we want.
+ }
+ close $fset
+ return $sVersion
+}
+proc CheckForIron {project_name} {
+
+ # Determine if the currently running version of ProjNav is earlier than Jade.
+ set version [GetIseVersion]
+ set dotLocation [string first "." $version]
+ set versionBase [string range $version 0 [expr {$dotLocation - 1}]]
+ if {$versionBase < 9} {
+
+ # The project file is newer than Iron, so take action to prevent the
+ # file from being corrupted.
+ # Make the file read-only.
+ if {[string compare -length 7 $::tcl_platform(platform) "windows"]} {
+ # The above will return 0 for a match to "windows" or "windows64".
+ # This is the non-zero part of the if, for lin and sol.
+ # Change the permissions to turn off writability.
+ file attributes $project_name -permissions a-w
+ } else {
+ # On Windows, set file to read-only.
+ file attributes $project_name -readonly 1
+ }
+
+ # And tell the user about it.
+ set messageText "WARNING: This project was last saved with a newer version of Project Navigator.\nThe project file will be made read-only so that it will not be invalidated by this version."
+ # In the console window
+ puts $messageText
+ # And with a GUI message box if possible.
+ ::xilinx::Dpm::TOE::loadGuiLibraries
+ set iInterface 0
+ set messageDisplay 0
+ if {[catch {
+ set iInterface [Xilinx::CitP::GetInstance $::xilinx::GuiI::IMessageDlgID]
+ set messageDisplay [$iInterface GetInterface $::xilinx::GuiI::IMessageDlgID]
+ if {$messageDisplay != 0} {
+ # Managed to get a component to display a dialog, so use it
+ set messageTitle "Incompatible Project Version (Newer)"
+ set messageType 2
+ # 2 corresponds to a warning dialog. TclWrapGuiI_Init.cpp doesn't put the enum into Tcl.
+ set messageTimeout 300000
+ # in milliseconds, 5 minutes
+ set messageReturn [$messageDisplay MessageDlg $messageTitle $messageText $messageType 1 1 $messageTimeout "OK" "" ""]
+ }
+ } catchResult]} {
+ # There was an error, probably because we aren't in a GUI enviroment.
+ } else {
+ # All is well.
+ }
+ set messageDisplay 0
+ set iInterface 0
+ }
+
+ return 1
+}
+}
+}
+::xilinx::Dpm::CheckForIron PK
+ __OBJSTORE__/ProjectNavigator/PK
+ / __OBJSTORE__/ProjectNavigator/dpm_project_main/PK
+ dV V ? __OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main EB PK
+ Ե]8 8 F __OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl lpc_7seg acr2 spartan3 virtex2p xbr xc9500xl PK
+ ۙ 0 __OBJSTORE__/ProjectNavigator/__stored_objects__
+
+ p ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ +
+ + ` _ ^ e d X V Y W c b z y x w [ \ Z ] v u t f a 7
+ 6 n r q p o m s l H i g h k j q # / - $ 0 _ ^ . 2 1 3 4 H G F E D C B A @ j i > h g < ; : 9 8 7 6 5 ] \ [ Z X V U T S R Q P O M K J I v u t s r q p o n m l k f e + d c ) b a ` & %
+ ~ } |
+ { z y x w {
+
+ ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
+
+ ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
+
+ ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
+
+ ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
+
+ ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
+
+ ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
+
+ ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
+
+ ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
+
+ ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
+
+ ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
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+ &wS 7 __OBJSTORE__/ProjectNavigator/__stored_objects___StrTbl work verilog onalib lpc_7seg simprim vcomponents unisim AND2B1|unisim|vcomponents AND2B2|unisim|vcomponents AND2|unisim|vcomponents AND3B1|unisim|vcomponents AND3B2|unisim|vcomponents AND3B3|unisim|vcomponents AND3|unisim|vcomponents AND4B1|unisim|vcomponents AND4B2|unisim|vcomponents AND4B3|unisim|vcomponents AND4B4|unisim|vcomponents AND4|unisim|vcomponents AND5B1|unisim|vcomponents AND5B2|unisim|vcomponents AND5B3|unisim|vcomponents AND5B4|unisim|vcomponents AND5B5|unisim|vcomponents AND5|unisim|vcomponents AND6|unisim|vcomponents AND7|unisim|vcomponents AND8|unisim|vcomponents BSCAN_FPGACORE|unisim|vcomponents BSCAN_SPARTAN2|unisim|vcomponents BSCAN_SPARTAN3A|unisim|vcomponents BSCAN_SPARTAN3|unisim|vcomponents BSCAN_VIRTEX2|unisim|vcomponents BSCAN_VIRTEX4|unisim|vcomponents BSCAN_VIRTEX5|unisim|vcomponents BSCAN_VIRTEX|unisim|vcomponents BUFCF|unisim|vcomponents BUFE|unisim|vcomponents BUFFOE|unisim|vcomponents BUFGCE_1|unisim|vcomponents BUFGCE|unisim|vcomponents BUFGCTRL|unisim|vcomponents BUFGDLL|unisim|vcomponents BUFGMUX_1|unisim|vcomponents BUFGMUX_CTRL|unisim|vcomponents BUFGMUX_VIRTEX4|unisim|vcomponents BUFGMUX|unisim|vcomponents BUFGP|unisim|vcomponents BUFGSR|unisim|vcomponents BUFGTS|unisim|vcomponents BUFG|unisim|vcomponents BUFIO|unisim|vcomponents BUFR|unisim|vcomponents BUFT|unisim|vcomponents BUF|unisim|vcomponents CAPTURE_FPGACORE|unisim|vcomponents CAPTURE_SPARTAN2|unisim|vcomponents CAPTURE_SPARTAN3A|unisim|vcomponents CAPTURE_SPARTAN3|unisim|vcomponents CAPTURE_VIRTEX2|unisim|vcomponents CAPTURE_VIRTEX4|unisim|vcomponents CAPTURE_VIRTEX5|unisim|vcomponents CAPTURE_VIRTEX|unisim|vcomponents CARRY4|unisim|vcomponents CFGLUT5|unisim|vcomponents CLKDLLE|unisim|vcomponents CLKDLLHF|unisim|vcomponents CLKDLL|unisim|vcomponents CLK_DIV10RSD|unisim|vcomponents CLK_DIV10R|unisim|vcomponents CLK_DIV10SD|unisim|vcomponents CLK_DIV10|unisim|vcomponents CLK_DIV12RSD|unisim|vcomponents CLK_DIV12R|unisim|vcomponents CLK_DIV12SD|unisim|vcomponents CLK_DIV12|unisim|vcomponents CLK_DIV14RSD|unisim|vcomponents CLK_DIV14R|unisim|vcomponents CLK_DIV14SD|unisim|vcomponents CLK_DIV14|unisim|vcomponents CLK_DIV16RSD|unisim|vcomponents CLK_DIV16R|unisim|vcomponents CLK_DIV16SD|unisim|vcomponents CLK_DIV16|unisim|vcomponents CLK_DIV2RSD|unisim|vcomponents CLK_DIV2R|unisim|vcomponents CLK_DIV2SD|unisim|vcomponents CLK_DIV2|unisim|vcomponents CLK_DIV4RSD|unisim|vcomponents CLK_DIV4R|unisim|vcomponents CLK_DIV4SD|unisim|vcomponents CLK_DIV4|unisim|vcomponents CLK_DIV6RSD|unisim|vcomponents CLK_DIV6R|unisim|vcomponents CLK_DIV6SD|unisim|vcomponents CLK_DIV6|unisim|vcomponents CLK_DIV8RSD|unisim|vcomponents CLK_DIV8R|unisim|vcomponents CLK_DIV8SD|unisim|vcomponents CLK_DIV8|unisim|vcomponents CONFIG|unisim|vcomponents CRC32|unisim|vcomponents CRC64|unisim|vcomponents DCC_FPGACORE|unisim|vcomponents DCIRESET|unisim|vcomponents DCM_ADV|unisim|vcomponents DCM_BASE|unisim|vcomponents DCM_PS|unisim|vcomponents DCM_SP|unisim|vcomponents DCM|unisim|vcomponents DNA_PORT|unisim|vcomponents DSP48A|unisim|vcomponents DSP48E|unisim|vcomponents DSP48|unisim|vcomponents EMAC|unisim|vcomponents FDCE_1|unisim|vcomponents FDCE|unisim|vcomponents FDCPE_1|unisim|vcomponents FDCPE|unisim|vcomponents FDCPX1|unisim|vcomponents FDCP_1|unisim|vcomponents FDCP|unisim|vcomponents FDC_1|unisim|vcomponents FDC|unisim|vcomponents FDDCE|unisim|vcomponents FDDCPE|unisim|vcomponents FDDCP|unisim|vcomponents FDDC|unisim|vcomponents FDDPE|unisim|vcomponents FDDP|unisim|vcomponents FDDRCPE|unisim|vcomponents FDDRRSE|unisim|vcomponents FDD|unisim|vcomponents FDE_1|unisim|vcomponents FDE|unisim|vcomponents FDPE_1|unisim|vcomponents FDPE|unisim|vcomponents FDP_1|unisim|vcomponents FDP|unisim|vcomponents FDRE_1|unisim|vcomponents FDRE|unisim|vcomponents FDRSE_1|unisim|vcomponents FDRSE|unisim|vcomponents FDRS_1|unisim|vcomponents FDRS|unisim|vcomponents FDR_1|unisim|vcomponents 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GT10_OC192_4|unisim|vcomponents GT10_OC192_8|unisim|vcomponents GT10_OC48_1|unisim|vcomponents GT10_OC48_2|unisim|vcomponents GT10_OC48_4|unisim|vcomponents GT10_PCI_EXPRESS_1|unisim|vcomponents GT10_PCI_EXPRESS_2|unisim|vcomponents GT10_PCI_EXPRESS_4|unisim|vcomponents GT10_XAUI_1|unisim|vcomponents GT10_XAUI_2|unisim|vcomponents GT10_XAUI_4|unisim|vcomponents GT10|unisim|vcomponents GT11CLK_MGT|unisim|vcomponents GT11CLK|unisim|vcomponents GT11_CUSTOM|unisim|vcomponents GT11_DUAL|unisim|vcomponents GT11|unisim|vcomponents GTP_DUAL|unisim|vcomponents GT_AURORA_1|unisim|vcomponents GT_AURORA_2|unisim|vcomponents GT_AURORA_4|unisim|vcomponents GT_CUSTOM|unisim|vcomponents GT_ETHERNET_1|unisim|vcomponents GT_ETHERNET_2|unisim|vcomponents GT_ETHERNET_4|unisim|vcomponents GT_FIBRE_CHAN_1|unisim|vcomponents GT_FIBRE_CHAN_2|unisim|vcomponents GT_FIBRE_CHAN_4|unisim|vcomponents GT_INFINIBAND_1|unisim|vcomponents GT_INFINIBAND_2|unisim|vcomponents GT_INFINIBAND_4|unisim|vcomponents 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OBUFT_LVCMOS18_F_2|unisim|vcomponents OBUFT_LVCMOS18_F_4|unisim|vcomponents OBUFT_LVCMOS18_F_6|unisim|vcomponents OBUFT_LVCMOS18_F_8|unisim|vcomponents OBUFT_LVCMOS18_S_12|unisim|vcomponents OBUFT_LVCMOS18_S_16|unisim|vcomponents OBUFT_LVCMOS18_S_2|unisim|vcomponents OBUFT_LVCMOS18_S_4|unisim|vcomponents OBUFT_LVCMOS18_S_6|unisim|vcomponents OBUFT_LVCMOS18_S_8|unisim|vcomponents OBUFT_LVCMOS18|unisim|vcomponents OBUFT_LVCMOS25_F_12|unisim|vcomponents OBUFT_LVCMOS25_F_16|unisim|vcomponents OBUFT_LVCMOS25_F_24|unisim|vcomponents OBUFT_LVCMOS25_F_2|unisim|vcomponents OBUFT_LVCMOS25_F_4|unisim|vcomponents OBUFT_LVCMOS25_F_6|unisim|vcomponents OBUFT_LVCMOS25_F_8|unisim|vcomponents OBUFT_LVCMOS25_S_12|unisim|vcomponents OBUFT_LVCMOS25_S_16|unisim|vcomponents OBUFT_LVCMOS25_S_24|unisim|vcomponents OBUFT_LVCMOS25_S_2|unisim|vcomponents OBUFT_LVCMOS25_S_4|unisim|vcomponents OBUFT_LVCMOS25_S_6|unisim|vcomponents OBUFT_LVCMOS25_S_8|unisim|vcomponents OBUFT_LVCMOS25|unisim|vcomponents OBUFT_LVCMOS2|unisim|vcomponents OBUFT_LVCMOS33_F_12|unisim|vcomponents OBUFT_LVCMOS33_F_16|unisim|vcomponents OBUFT_LVCMOS33_F_24|unisim|vcomponents OBUFT_LVCMOS33_F_2|unisim|vcomponents OBUFT_LVCMOS33_F_4|unisim|vcomponents OBUFT_LVCMOS33_F_6|unisim|vcomponents OBUFT_LVCMOS33_F_8|unisim|vcomponents OBUFT_LVCMOS33_S_12|unisim|vcomponents OBUFT_LVCMOS33_S_16|unisim|vcomponents OBUFT_LVCMOS33_S_24|unisim|vcomponents OBUFT_LVCMOS33_S_2|unisim|vcomponents OBUFT_LVCMOS33_S_4|unisim|vcomponents OBUFT_LVCMOS33_S_6|unisim|vcomponents OBUFT_LVCMOS33_S_8|unisim|vcomponents OBUFT_LVCMOS33|unisim|vcomponents OBUFT_LVDCI_15|unisim|vcomponents OBUFT_LVDCI_18|unisim|vcomponents OBUFT_LVDCI_25|unisim|vcomponents OBUFT_LVDCI_33|unisim|vcomponents OBUFT_LVDCI_DV2_15|unisim|vcomponents OBUFT_LVDCI_DV2_18|unisim|vcomponents OBUFT_LVDCI_DV2_25|unisim|vcomponents OBUFT_LVDCI_DV2_33|unisim|vcomponents OBUFT_LVDS|unisim|vcomponents OBUFT_LVPECL|unisim|vcomponents OBUFT_LVTTL_F_12|unisim|vcomponents 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|Generic||lpc_7seg.twr lpc_7seg.twr DESUT_TIMING_TXT_REPORT |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/_xmsgs/par.xmsgs|PLUGIN_General|1204672756| |Generic||par.xmsgs par.xmsgs |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_pad.csv|PLUGIN_General|1204672755| FILE_PAD_EXCEL_REPORT |Generic||lpc_7seg_pad.csv lpc_7seg_pad.csv DESUT_PAD_EXCEL_REPORT |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_pad.txt|PLUGIN_General|1204672756| FILE_PAD_TXT_REPORT |Generic||lpc_7seg_pad.txt lpc_7seg_pad.txt DESUT_PAD_TXT_REPORT TBIND_viewPadRpts TRAN_viewPadRpts |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.xpi|PLUGIN_General|1204672756| FILE_XPI |Generic||lpc_7seg.xpi lpc_7seg.xpi DESUT_XPI |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.unroutes|PLUGIN_General|1204672756| FILE_UNROUTES |Generic||lpc_7seg.unroutes lpc_7seg.unroutes DESUT_UNROUTES |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.par|PLUGIN_General|1204672756| FILE_PAR_REPORT |Generic||lpc_7seg.par lpc_7seg.par DESUT_PAR_REPORT TBIND_viewParRpts TRAN_viewParRpts |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.pad|PLUGIN_General|1204672755| FILE_PAD_MISC |Generic||lpc_7seg.pad lpc_7seg.pad DESUT_PAD_MISC |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ncd|PLUGIN_NCD|1204672756| PLUGIN_NCD FILE_NCD |Module||lpc_7seg DESUT_NCD |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_usage.xml|PLUGIN_General|1204672765| FILE_WEBTALK |Generic||lpc_7seg_usage.xml lpc_7seg_usage.xml DESUT_GENERIC |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/_xmsgs/map.xmsgs|PLUGIN_General|1204672746| |Generic||map.xmsgs map.xmsgs |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_map.ngm|PLUGIN_NGM|1204672745| PLUGIN_NGM FILE_NGM DESUT_NGM 3s400fg456-4 |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.pcf|PLUGIN_General|1204672746| FILE_PCF |Generic||lpc_7seg.pcf lpc_7seg.pcf DESUT_PCF |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_map.mrp|PLUGIN_General|1204672746| FILE_MAP_REPORT |Generic||lpc_7seg_map.mrp lpc_7seg_map.mrp DESUT_MAP_REPORT |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_map.ncd|PLUGIN_NCD|1204672746| |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/_xmsgs/ngdbuild.xmsgs|PLUGIN_General|1204672742| |Generic||ngdbuild.xmsgs ngdbuild.xmsgs |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/_ngo|PLUGIN_General|1204672739| FILE_DIRECTORY |Generic||_ngo _ngo DESUT_DIRECTORY |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/_ngo/netlist.lst|PLUGIN_General|1204672742| FILE_LST |Generic||netlist.lst netlist.lst DESUT_LST |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.bld|PLUGIN_General|1204672742| FILE_NGDBUILD_LOG |Generic||lpc_7seg.bld lpc_7seg.bld DESUT_NGDBUILD_LOG |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ngd|PLUGIN_NGD|1204672741| PLUGIN_NGD FILE_NGD DESUT_NGD |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/_xmsgs/xst.xmsgs|PLUGIN_General|1204672736| |Generic||xst.xmsgs xst.xmsgs |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.cmd_log|PLUGIN_General|1204672761| FILE_CMD_LOG |Generic||lpc_7seg.cmd_log lpc_7seg.cmd_log DESUT_CMD_LOG |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/xst|PLUGIN_General|1204672726| |Generic||xst xst |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ngr|PLUGIN_NGR|1204672730| PLUGIN_NGR FILE_NGR DESUT_NGR |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ngc|PLUGIN_NGC|1204672736| PLUGIN_NGC FILE_NGC DESUT_NGC xc3s400-4-fg456 |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_vhdl.prj|PLUGIN_General|1204672726| FILE_XST_PROJECT |Generic||lpc_7seg_vhdl.prj lpc_7seg_vhdl.prj DESUT_XST_PROJECT |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.prj|PLUGIN_General|1204672725| |Generic||lpc_7seg.prj lpc_7seg.prj |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.syr|PLUGIN_General|1204672736| FILE_XST_REPORT |Generic||lpc_7seg.syr lpc_7seg.syr DESUT_XST_REPORT |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.lso|PLUGIN_General|1204672726| FILE_LSO |Generic||lpc_7seg.lso lpc_7seg.lso DESUT_LSO |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.xst|PLUGIN_General|1204672725| FILE_XST |Generic||lpc_7seg.xst lpc_7seg.xst DESUT_XST |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.stx|PLUGIN_General|1204672736| FILE_XST_STX |Generic||lpc_7seg.stx lpc_7seg.stx DESUT_XST_STX |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_guide.ncd|PLUGIN_NCD|1204672756| |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/wb_7seg.vhd|PLUGIN_Vhdl|1204597328| FILE_VHDL |Architecture||wb_7seg_behav|wb_7seg|| |ComponentInstantiation||wb_7seg|wb_7seg_behav|u1|disp_dec| |Entity||wb_7seg |Library||| |Use||IEEE|STD_LOGIC_1164|all| |Use||IEEE|STD_LOGIC_ARITH|all| |Use||IEEE|STD_LOGIC_UNSIGNED|all| wb_7seg_behav wb_7seg DESUT_VHDL_ARCHITECTURE u1 disp_dec DESUT_VHDL_ENTITY IEEE.STD_LOGIC_UNSIGNED.all IEEE STD_LOGIC_UNSIGNED all IEEE.STD_LOGIC_ARITH.all STD_LOGIC_ARITH IEEE.STD_LOGIC_1164.all STD_LOGIC_1164 |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/disp_dec.vhd|PLUGIN_Vhdl|1141325921| |Architecture||disp_dec_behave|disp_dec|| |Entity||disp_dec disp_dec_behave |File||C:/hharte/work/HarteTec/cores/wb_lpc/rtl/verilog/wb_lpc_periph.v|PLUGIN_Verilog|1204671613| FILE_VERILOG |Module||wb_lpc_periph wb_lpc_periph DESUT_VERILOG |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ucf|PLUGIN_AssocModule|1204662943| PLUGIN_AssocModule FILE_UCF |Module||lpc_7seg.ucf lpc_7seg.ucf DESUT_UCF |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/top_lpc_7seg.v|PLUGIN_Verilog|1204671374| |ComponentInstantiation||lpc_7seg|lpc_7seg|lpc_periph|wb_lpc_periph| |ComponentInstantiation||lpc_7seg|lpc_7seg|seven_seg0|wb_7seg| seven_seg0 lpc_periph AutoGeneratedView VIEW_AssignPackagePins TBIND_XSTAssignPackagePins TRAN_assignPackagePins VIEW_XSTPreSynthesis TBIND_EditConstraintsTextApp TRAN_editConstraints VIEW_PreSynthEditConstraints TBINDEXT_XSTPreSynthesisToStructural_spartan3 TRAN_copyPreSynthesisToStructuralForBitgen TRANEXT_xstsynthesize_spartan3 TRAN_copyPreSynthesisToStructuralForTranslate VIEW_Structural TBIND_StructuralToPost-SynthesisAbstractSimulation TRAN_postSynthesisSimModel Module|lpc7seg VIEW_Post-SynthesisAbstractSimulation TBINDEXT_StructuralToTranslation_FPGA TRAN_copyStructuralToTranslationForBitgen TRAN_copyStructuralToTranslationForConstraints TRANEXT_ngdbuild_FPGA VIEW_Translation TBIND_xlateFloorPlanner TRAN_xlateFloorPlanner VIEW_Post-TranslateFloorPlanner TBIND_xlateAssignPackagePins TRAN_xlateAssignPackagePins VIEW_Post-TranslateAssignPins TBIND_TranslationToPost-TranslateFormalityNetlist TRAN_postXlateFormalityNetlist VIEW_Post-TranslateFormalityNetlist TBIND_TranslationToPost-TranslateAbstractSimulation TRAN_postXlateSimModel VIEW_Post-TranslateAbstractSimulation TBIND_Post-TranslateAbstractToTBWPreSimulation TRAN_createPostXlateTestBench TRAN_copyPost-TranslateAbstractToPreSimulation VIEW_TBWPost-TranslatePreSimulation TBIND_Post-TranslateAbstractToPreSimulation VIEW_Post-TranslatePreSimulation TBIND_NGCAssignPackagePins TRAN_ngcAssignPackagePins VIEW_ngcAssignPackagePins TBIND_CreateTimingConstraints TRAN_createTimingConstraints VIEW_Post-TranslateTimingConstraints TBIND_CreateAreaConstraints TRAN_createAreaConstraints VIEW_Post-TranslateAreaConstraints TBINDEXT_TranslationToMap_spartan3 TRAN_copyTranslationToMapForBitgen TRANEXT_map_spartan3 VIEW_Map TBIND_preRouteTrce TRAN_preRouteTrce VIEW_Post-MapStaticTiming TBIND_mapFpgaEditor TRAN_mapFpgaEditor VIEW_Post-MapFpgaEditor TBIND_mapFloorPlanner TRAN_mapFloorPlanner VIEW_Post-MapFloorPlanner TBIND_MapToPost-MapAbstractSimulation TRAN_postMapSimModel VIEW_Post-MapAbstractSimulation TBIND_Post-MapAbstractToTBWPreSimulation TRAN_createPostMapTestBench TRAN_copyPost-MapAbstractToPreSimulation VIEW_TBWPost-MapPreSimulation TBIND_Post-MapAbstractToPreSimulation VIEW_Post-MapPreSimulation TBINDEXT_MapToPar_spartan3 TRAN_copyMapToParForBitgen TRANEXT_par_spartan3 VIEW_Par TBIND_postRouteTrce TRAN_postRouteTrce VIEW_Post-ParStaticTiming TBIND_postParPrimetimeNetlist TRAN_postParPrimetimeNetlist VIEW_PrimetimeNetlist TBIND_parFpgaEditor TRAN_parFpgaEditor VIEW_Post-ParFpgaEditor TBIND_parFloorPlanner TRAN_parFloorPlanner VIEW_Post-ParFloorPlanner TBIND_genPowerData TRAN_genPowerData VIEW_FPGAGeneratePowerData TBIND_createIBISModel TRAN_createIBISModel VIEW_IBISModel TBIND_Xpower TRAN_XPower VIEW_FPGAAnalyzePower TBIND_ParToPost-ParFormalityNetlist TRAN_postParFormalityNetlist VIEW_Post-ParFormalityNetlist TBIND_ParToPost-ParClockRegion TRAN_clkRegionRpt VIEW_Post-ParClockRegionReport TBIND_ParToPost-ParAsyncDelay TRAN_asynDlyRpt VIEW_Post-ParAsyncDelayReport TBIND_ParToPost-ParAbstractSimulation TRAN_postParSimModel VIEW_Post-ParAbstractSimulation TBIND_Post-ParAbstractToTBWPreSimulation TRAN_createPostParTestBench TRAN_copyPost-ParAbstractToPreSimulation VIEW_TBWPost-ParPreSimulation TBIND_TBWPost-ParPreToFuse TRAN_ISimulatePostPlace&RouteModelRunFuse(bencher) VIEW_TBWPost-ParFuse TBIND_TBWPost-ParFuseToSimulationISim TRAN_ISimulatePostPlace&RouteModel(bencher) VIEW_TBWPost-ParSimulationISim TBIND_Post-ParAbstractToPreSimulation VIEW_Post-ParPreSimulation TBIND_Post-ParPreToFuse TRAN_ISimulatePostPlace&RouteModelRunFuse VIEW_Post-ParFuse TBIND_Post-ParFuseToSimulationISim TRAN_ISimulatePostPlace&RouteModel VIEW_Post-ParSimulationISim TBIND_ParToMpprResult TRAN_copyMpprRslt VIEW_MpprResult TBIND_ParToLockedPinConstraints TRAN_genLockedPinConstraints VIEW_LockedPinConstraints TBIND_ParToBackAnnoPinLocations TRAN_backAnnoPinLocations VIEW_BackAnnoPinLocations TBINDEXT_ParToFPGAConfiguration_spartan3 TRANEXT_bitFile_spartan3 VIEW_FPGAConfiguration TBIND_analyzeDesignUsingChipscope TRAN_analyzeDesignUsingChipscope VIEW_AnalyzedDesign TBIND_UpdateBitstreamXPS TRAN_xpsUpdBitstream VIEW_UpdatedBitstream TBIND_FPGAConfigurationToFPGAGeneratePROM TRAN_genImpactFile VIEW_FPGAGeneratePROM TBIND_FPGAConfigurationToFPGAConfigureDevice TRAN_impactProgrammingTool VIEW_FPGAConfigureDevice TBIND_XSTAbstractToPreSynthesis TRAN_copyAbstractToPreSynthesisForBitgen TRAN_copyAbstractToPreSynthesisForTranslate TRAN_convertToHdl TRAN_copyAbstractToPreSynthesisForSynthesis VIEW_XSTAbstractSynthesis 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\ No newline at end of file
trunk/examples/lpc_7seg/lpc_7seg.ise
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/examples/lpc_7seg/top_lpc_7seg.v
===================================================================
--- trunk/examples/lpc_7seg/top_lpc_7seg.v (nonexistent)
+++ trunk/examples/lpc_7seg/top_lpc_7seg.v (revision 7)
@@ -0,0 +1,122 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// $Id: top_lpc_7seg.v,v 1.1 2008-03-05 05:58:39 hharte Exp $ ////
+//// top_lpc_7seg.v - LPC Peripheral to 7-Segment Display for ////
+//// Enterpoint Raggedstone1 card. ////
+//// ////
+//// This file is part of the Wishbone LPC Bridge project ////
+//// http://www.opencores.org/projects/wb_lpc/ ////
+//// ////
+//// Author: ////
+//// - Howard M. Harte (hharte@opencores.org) ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2008 Howard M. Harte ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module lpc_7seg
+(
+ RST, // Active Low (From PCI bus)
+ DISP_SEL,
+ DISP_LED,
+
+ LPC_CLK,
+ LFRAME,
+ LAD,
+ LAD_OE
+);
+
+input RST ;
+
+output [3:0] DISP_SEL ;
+output [6:0] DISP_LED ;
+
+input LPC_CLK;
+input LFRAME;
+inout [3:0] LAD;
+output LAD_OE;
+
+wire [2:0] dma_chan_i = 3'b000;
+wire dma_tc_i = 1'b0;
+wire [3:0] lad_i;
+wire [3:0] lad_o;
+wire periph_lad_oe;
+
+assign LAD = (periph_lad_oe ? lad_o : 4'bzzzz);
+assign LAD_OE = periph_lad_oe;
+
+wire [24:0] wb_adr_o;
+wire [31:0] wb_dat_i;
+wire [31:0] wb_dat_o;
+wire [3:0] wb_sel_o;
+wire wb_we_o;
+wire wb_stb_o;
+wire wb_cyc_o;
+wire wb_ack_i;
+wire wb_rty_i;
+wire wb_err_i;
+wire wb_int_i;
+
+// Instantiate the module
+wb_lpc_periph lpc_periph (
+ .clk_i(LPC_CLK),
+ .nrst_i(RST),
+ .wbm_adr_o(wb_adr_o),
+ .wbm_dat_o(wb_dat_o),
+ .wbm_dat_i(wb_dat_i),
+ .wbm_sel_o(wb_sel_o),
+ .wbm_tga_o(wb_tga_o),
+ .wbm_we_o(wb_we_o),
+ .wbm_stb_o(wb_stb_o),
+ .wbm_cyc_o(wb_cyc_o),
+ .wbm_ack_i(wb_ack_i),
+ .dma_chan_o(dma_chan_i),
+ .dma_tc_o(dma_tc_i),
+ .lframe_i(~LFRAME),
+ .lad_i(LAD),
+ .lad_o(lad_o),
+ .lad_oe(periph_lad_oe)
+ );
+
+// Instantiate the 7-Segment module
+wb_7seg seven_seg0 (
+ .clk_i(LPC_CLK),
+ .nrst_i(RST),
+ .wb_adr_i(wb_adr_o),
+ .wb_dat_o(wb_dat_i),
+ .wb_dat_i(wb_dat_o),
+ .wb_sel_i(wb_sel_o),
+ .wb_we_i(wb_we_o),
+ .wb_stb_i(wb_stb_o),
+ .wb_cyc_i(wb_cyc_o),
+ .wb_ack_o(wb_ack_i),
+ .wb_err_o(wb_err_i),
+ .wb_int_o(wb_int_i),
+ .DISP_SEL(DISP_SEL),
+ .DISP_LED(DISP_LED)
+ );
+
+endmodule
trunk/examples/lpc_7seg/top_lpc_7seg.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/examples/lpc_7seg/disp_dec.vhd
===================================================================
--- trunk/examples/lpc_7seg/disp_dec.vhd (nonexistent)
+++ trunk/examples/lpc_7seg/disp_dec.vhd (revision 7)
@@ -0,0 +1,83 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:07:18 01/02/06
+-- Design Name:
+-- Module Name: dip_dec - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity disp_dec is
+port (
+ disp_dec_in : in std_logic_vector(3 downto 0);
+ disp_dec_out : out std_logic_vector(6 downto 0)
+ );
+end disp_dec;
+
+
+architecture disp_dec_behave of disp_dec is
+
+begin
+
+
+process (disp_dec_in)
+begin
+ case disp_dec_in is
+ when "0000" =>
+ disp_dec_out <= "1000000";
+ when "0001" =>
+ disp_dec_out <= "1111001";
+ when "0010" =>
+ disp_dec_out <= "0100100";
+ when "0011" =>
+ disp_dec_out <= "0110000";
+ when "0100" =>
+ disp_dec_out <= "0011001";
+ when "0101" =>
+ disp_dec_out <= "0010010";
+ when "0110" =>
+ disp_dec_out <= "0000010";
+ when "0111" =>
+ disp_dec_out <= "1111000";
+ when "1000" =>
+ disp_dec_out <= "0000000";
+ when "1001" =>
+ disp_dec_out <= "0010000";
+ when "1010" =>
+ disp_dec_out <= "0001000";
+ when "1011" =>
+ disp_dec_out <= "0000011";
+ when "1100" =>
+ disp_dec_out <= "1000110";
+ when "1101" =>
+ disp_dec_out <= "0100001";
+ when "1110" =>
+ disp_dec_out <= "0000110";
+ when "1111" =>
+ disp_dec_out <= "0001110";
+ when others =>
+ disp_dec_out <= "1111111";
+ end case;
+end process;
+
+end disp_dec_behave;
\ No newline at end of file
trunk/examples/lpc_7seg/disp_dec.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/examples/lpc_7seg/wb_7seg.vhd
===================================================================
--- trunk/examples/lpc_7seg/wb_7seg.vhd (nonexistent)
+++ trunk/examples/lpc_7seg/wb_7seg.vhd (revision 7)
@@ -0,0 +1,155 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 10:22:14 12/29/05
+-- Design Name:
+-- Module Name: wb_7seg - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity wb_7seg is
+ port(
+
+ clk_i : in std_logic;
+ nrst_i : in std_logic;
+ wb_adr_i : in std_logic_vector(24 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_we_i : in std_logic;
+ wb_stb_i : in std_logic;
+ wb_cyc_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_err_o : out std_logic;
+ wb_int_o : out std_logic;
+ DISP_SEL : inout std_logic_vector(3 downto 0);
+ DISP_LED : out std_logic_vector(6 downto 0)
+
+ );
+
+end wb_7seg;
+
+architecture wb_7seg_behav of wb_7seg is
+
+component disp_dec
+port (
+ disp_dec_in : in std_logic_vector(3 downto 0);
+ disp_dec_out : out std_logic_vector(6 downto 0)
+ );
+end component;
+
+
+ signal data_reg : std_logic_vector(31 downto 0);
+ signal disp_cnt : std_logic_vector(6 downto 0);
+ signal disp_data : std_logic_vector(3 downto 0);
+ signal disp_data_led : std_logic_vector(6 downto 0);
+ signal disp_pos : std_logic_vector(3 downto 0);
+ constant DISP_CNT_MAX : std_logic_vector(6 downto 0) := "1111111";
+
+
+
+begin
+
+process (clk_i,nrst_i)
+begin
+ if nrst_i = '0' then
+ data_reg <= x"10eef00d";
+ elsif ( clk_i'event and clk_i = '1' ) then
+ if ( wb_stb_i = '1' and wb_we_i = '1' ) then
+ data_reg <= wb_dat_i;
+ end if;
+ end if;
+end process;
+
+wb_ack_o <= wb_stb_i;
+wb_err_o <= '0';
+wb_int_o <= '0';
+wb_dat_o <= data_reg;
+
+
+
+process (clk_i,nrst_i)
+begin
+ if nrst_i = '0' then
+ disp_cnt <= ( others => '0' );
+ elsif clk_i'event and clk_i = '1' then
+ disp_cnt <= disp_cnt + 1;
+ end if;
+end process;
+
+process (clk_i,nrst_i)
+begin
+ if nrst_i = '0' then
+ disp_pos <= "0001";
+ elsif clk_i'event and clk_i = '1' then
+ if disp_cnt = DISP_CNT_MAX then
+ disp_pos <= (
+ 3 => DISP_SEL(2), 2 => DISP_SEL(1),
+ 1 => DISP_SEL(0), 0 => DISP_SEL(3)
+ );
+ end if;
+ end if;
+end process;
+
+process (clk_i,nrst_i)
+begin
+ if nrst_i = '0' then
+ disp_data <= "0000";
+ elsif clk_i'event and clk_i = '1' then
+ case DISP_SEL is
+ when "1000" =>
+ disp_data <= data_reg(3 downto 0);
+ when "0100" =>
+ disp_data <= data_reg(7 downto 4);
+ when "0010" =>
+ disp_data <= data_reg(11 downto 8);
+ when "0001" =>
+ disp_data <= data_reg(15 downto 12);
+ when others =>
+ disp_data <= (others => '0');
+ end case;
+ end if;
+end process;
+
+
+u1: component disp_dec
+port map (
+ disp_dec_in => disp_data,
+ disp_dec_out => disp_data_led
+ );
+
+process (clk_i,nrst_i)
+begin
+ if nrst_i = '0' then
+ DISP_LED <= (others => '0');
+ elsif clk_i'event and clk_i = '1' then
+ DISP_LED <= disp_data_led;
+ end if;
+end process;
+
+process (clk_i,nrst_i)
+begin
+ if nrst_i = '0' then
+ DISP_SEL <= (others => '0');
+ elsif clk_i'event and clk_i = '1' then
+ DISP_SEL <= disp_pos;
+ end if;
+end process;
+
+end wb_7seg_behav;
trunk/examples/lpc_7seg/wb_7seg.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/examples/lpc_7seg
===================================================================
--- trunk/examples/lpc_7seg (nonexistent)
+++ trunk/examples/lpc_7seg (revision 7)
trunk/examples/lpc_7seg
Property changes :
Added: svn:ignore
## -0,0 +1,44 ##
+lpc_7seg.stx
+lpc_7seg.par
+lpc_7seg.restore
+lpc_7seg.unroutes
+lpc_7seg.ngr
+lpc_7seg_map.mrp
+lpc_7seg.lso
+timing.twr
+lpc_7seg.bld
+lpc_7seg_map.ncd
+lpc_7seg_pad.txt
+lpc_7seg.cmd_log
+lpc_7seg.ise_ISE_Backup
+lpc_7seg.drc
+lpc_7seg_map.map
+lpc_7seg.twr
+lpc_7seg.syr
+lpc_7seg_summary.xml
+lpc_7seg.xst
+lpc_7seg_map.ngm
+lpc_7seg_pad.csv
+_ngo
+lpc_7seg_guide.ncd
+lpc_7seg.lfp
+lpc_7seg_summary.html
+_pace.ucf
+lpc_7seg.twx
+lpc_7seg_usage.xml
+lpc_7seg.ut
+lpc_7seg.prj
+_xmsgs
+lpc_7seg.xpi
+lpc_7seg_prev_built.ngd
+__ISE_repository_lpc_7seg.ise_.lock
+lpc_7seg.pad
+lpc_7seg.ncd
+lpc_7seg.bgn
+lpc_7seg.ngc
+lpc_7seg.ntrc_log
+lpc_7seg.pcf
+lpc_7seg.ngd
+lpc_7seg_vhdl.prj
+xst
+.svn
Index: trunk/examples/pci_lpc/pci_lpc_host.bit
===================================================================
--- trunk/examples/pci_lpc/pci_lpc_host.bit (nonexistent)
+++ trunk/examples/pci_lpc/pci_lpc_host.bit (revision 7)
@@ -0,0 +1,109 @@
+ a pci_lpc_host.ncd b 3s400fg456 c 2008/03/04 d 15:14:59 e =Uf0 0` D0 @ ?0A0 0 0 0 0 @ P @ @ @ c 0 W 0aH 0aH0 W @& d @& d @ @ @ @ @ @ @
+
+ p 0 0 @ P P 0 p P
+ 0 A P P 0 Q ` @
+ 0 @ @ i 0 Q ` ?̯ @ D A 3
+ @ 0 0
+
+ P
+ ` @ 0 @ 0 Q ` ` A @ @ $ @ 0 p 0 @ @ @ @ @ 3 0 Q ` 0 @ . ( @ p
+ P
+ Ѐ ` @ @ 0 Q ` @ ( " @0 @ 8 y P 0 0 0 ` 0 @ 0 0 @ ` ? @ B @@ DP ( F $P C 0 @ @ @ @ @ 0 0
+ 0P 0 1 @ @ 0 0 0 ~ 0 $p $p 0 Q ʿ 0 I $ ( " 1 Ye@p @ @ @ @2 ) @ T@ H 4@ @ -X A 0! @0 @ @ P `* 0 @
+ 0 0 0 0 0 0 0 0 @ @ 0 0 @ @ 3 if 0 0 0 0 0 0 $p 0 0 0 0 0 $@ $@ $@ Q `_lcA5i _ 0
+ (!D(3 $ $ C# @ ( @ @ ` PR ň(
+8 : @ @ @ @ ( @ @ B 0P @ ` @ @ 0 6 @1 @F d 6 6 P @0$X@ @D
+$ @@ @ @ @ @ @ 9 p p00 r P
+ P
+ *00|*j0 < 00p0
+
+ @ @ @ 0 0 @ #?7 0 0 0 0 $p 0 $p 0 0 @ `? i w & " @ @ @D EF p h @ @ @ 8 ( $0H@ (H ! @ H@@ ` 0 M' & p fJ A* @ ! 2$)!! @@ P ( D P @ @
+0 1 @0@P
+0 z P u P 2 8, |< 00 P0 0 B
+ PP 0
+ 0 0 @ @ @
+ A ̀ 0 0 0 0 0 $p 0 $p 0 $p 0 $x 0 x x 0 0 $@ $@ $@ H Q ů i 0 `@ 0 &( I Q @ " " " D @ "D# @ @ A @ @
+ 9X V \ h H 0 Pp& G ! L 0 8 8 @ " B! " ( 0 B !L Q
+ ! E `
+ 0 0 p @ C` X ( X ! @"@P @! @ @ " " @ @ @ @ 0 ` p `
+ 2P
+ N@
+ `
+ < zp << 08 p p 0 , 0 < 0 0 00 @ @ @ ! 0
+ Ȉ "wĨ!?_?{ު ' $p 0 x x 0 0 x 0 $x 0 0 $p 0 0 0 x 0 0 0 0 x x $@ @ $H H i * 0 k
+ $ ($ ( " D D " GF b c b " @ @@ @ ! p G E `E
+ X 0 @ @
+
+
+p& @ ( 0 @L c& @ @@ ( A @@ g @
+ @ @ $Q@
+! ` ` qG c U @ ( @ G ` @ ( K( ` p@ 0 g $ "01 )
+ $ DH) @T @ " D ! m0< P }
+ p
+ u `v ` Pp`
+ 6 0 0 :x 0P<> x0 < , 8 X 0P 0
+
+x < P @ 0 @ ` @
+ 0 @ Z@ p <Ó9U 0 0 0 0 x 0 $x $p $p $p $p H _o d (0
+& $ P 0 @%
+ B `H p(% @ H 0 @G rA O. 0 <@ ``-P H @@ c b <@ ` 0 '( @ h 0 "0$* @! "I @ B B $ @ 0
+` 0 0 }:` - |\` 0 pR 8
+>
+ pP ` <68
+< 80a X P < 8 0 0 @ @ 0
+ 0 @ U|p* ##3 0 0 0 0 0 0 0 8 0 $p $@ @ 0 d P @ D @ H 0 D3 t h q @ / ( @ @@ p@ j"^ @ @ @ @ % H @ hA 1 'N @ ! Y 0 h . A* I 8 B8:\ @ ( 0 @ `` @p 0
+ p : <
+
+M `
+
+
+ p
+p0 0 P
+
+ , 0 `
+ 0 0
+ @ ! a i 0 0 x 0 0 / 0 ` P "
+@D D ( B Q @ @ G ' ' ( 0 ( < P p ( ` pA q"
+@ QA "@0 P 4
+ P `<@ =H y z
+
+P P l 0 8 00*0 P 0 10 @ 0 0
+ A 0 @ K 322 0 0 0 0 0 0 xx HH ` }@@ ݯ " E @ ( " GF @ D @ @ ! 0 2`@r1 /@ Pe ' t
+ ` @ @ @ " T | ` 0 c
+
+A @ @ p + @ p P% @, B Q @ $ @"( B " P@} p } P
+
+
+
+\ l 4
+0
+ 0 p @ @ @ @ 0 << 0 0 0 ` i} @ @ " h P r @ 0 ` W @ X 0 "@ !4B 0 @1 $ }0 @ 0P <
+
+ \p p p 0< 01 @ 0 o Ϫ0 0 0 $p 0 $x $p p $p H $H H $@ `Q ` ( ( s 4 @ D@ # @ G c @@ @ @ ! : 8 @ # A ( AP
+ 0 6 @4 "" : 0 0 q0 p p
+ 0 P p 0 ` ` b8 0 ` 0 @ p ! @ 0 0 @ @ @ R@ 0 ` ! 0 `p
+
+
+ 00 < 0 @ 0 @ 0 `Q ` @@ 0 @ 0 ! @ P$ P
+ q
+ 0
+ 0 p 0 @ 00 ek| 0 0 0 Q ` > Ee A ! @ @ ͖@ 5F @ 0 E ``
+
+ 0 ` 0 0 @ @0 0 1 0 @ Q ` @ 0 @ P 0 0 0 @ 0 Q `
+ @ @ @
+ h
+ @ @ } p 0
+
+
+ `Q ` " @ @ @ @ p
+ 0 0 00 0
+ @ @
+ 0 0
+
+ 0 @ ` " @ `
+ $ @ 0 A
+ @
+
+ 00 p 60
+0 0 0 0 _W0
+
\ No newline at end of file
trunk/examples/pci_lpc/pci_lpc_host.bit
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/examples/pci_lpc/pci_lpc.ucf
===================================================================
--- trunk/examples/pci_lpc/pci_lpc.ucf (nonexistent)
+++ trunk/examples/pci_lpc/pci_lpc.ucf (revision 7)
@@ -0,0 +1,80 @@
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "CBE0" LOC = "F9" | IOSTANDARD = PCI33_3 ;
+NET "CBE1" LOC = "C10" | IOSTANDARD = PCI33_3 ;
+NET "CBE2" LOC = "D13" | IOSTANDARD = PCI33_3 ;
+NET "CBE3" LOC = "E13" | IOSTANDARD = PCI33_3 ;
+NET "CLK" LOC = "A11" | IOSTANDARD = PCI33_3 ;
+NET "DEVSEL" LOC = "E12" | IOSTANDARD = PCI33_3 ;
+NET "DISP_LED<0>" LOC = "AB20" | IOSTANDARD = LVCMOS33 ;
+NET "DISP_LED<1>" LOC = "AA20" | IOSTANDARD = LVCMOS33 ;
+NET "DISP_LED<2>" LOC = "V18" | IOSTANDARD = LVCMOS33 ;
+NET "DISP_LED<3>" LOC = "Y17" | IOSTANDARD = LVCMOS33 ;
+NET "DISP_LED<4>" LOC = "AB18" | IOSTANDARD = LVCMOS33 ;
+NET "DISP_LED<5>" LOC = "AA18" | IOSTANDARD = LVCMOS33 ;
+NET "DISP_LED<6>" LOC = "W18" | IOSTANDARD = LVCMOS33 ;
+NET "DISP_SEL<0>" LOC = "AA17" | IOSTANDARD = LVCMOS33 ;
+NET "DISP_SEL<1>" LOC = "U17" | IOSTANDARD = LVCMOS33 ;
+NET "DISP_SEL<2>" LOC = "U16" | IOSTANDARD = LVCMOS33 ;
+NET "DISP_SEL<3>" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
+NET "FRAME" LOC = "C13" | IOSTANDARD = PCI33_3 ;
+NET "GNT" LOC = "D18" | IOSTANDARD = PCI33_3 ;
+NET "IDSEL" LOC = "D14" | IOSTANDARD = PCI33_3 ;
+NET "INTA" LOC = "B19" | IOSTANDARD = PCI33_3 ;
+NET "IRDY" LOC = "A13" | IOSTANDARD = PCI33_3 ;
+NET "LAD<0>" LOC = "V5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | IOBDELAY = BOTH | KEEPER ;
+NET "LAD<1>" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | IOBDELAY = BOTH | KEEPER ;
+NET "LAD<2>" LOC = "V2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | IOBDELAY = BOTH | KEEPER ;
+NET "LAD<3>" LOC = "V1" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | IOBDELAY = BOTH | KEEPER ;
+
+NET "LAD_OE" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
+NET "LFRAME" LOC = "W2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
+NET "LPC_CLK" LOC = "W1" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
+NET "LPC_INT" LOC = "T4" | IOSTANDARD = LVCMOS33 | PULLUP ;
+NET "PAR" LOC = "A9" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<0>" LOC = "A5" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<10>" LOC = "E9" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<11>" LOC = "F11" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<12>" LOC = "E10" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<13>" LOC = "A8" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<14>" LOC = "B9" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<15>" LOC = "B10" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<16>" LOC = "F17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<17>" LOC = "F16" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<18>" LOC = "A14" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<19>" LOC = "B14" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<1>" LOC = "B5" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<20>" LOC = "B15" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<21>" LOC = "A15" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<22>" LOC = "F12" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<23>" LOC = "F13" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<24>" LOC = "D15" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<25>" LOC = "E15" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<26>" LOC = "D17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<27>" LOC = "C17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<28>" LOC = "B17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<29>" LOC = "E17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<2>" LOC = "E6" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<30>" LOC = "A18" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<31>" LOC = "B18" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<3>" LOC = "D6" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<4>" LOC = "C6" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<5>" LOC = "B6" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<6>" LOC = "D7" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<7>" LOC = "E7" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<8>" LOC = "B8" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<9>" LOC = "F10" | IOSTANDARD = PCI33_3 ;
+NET "PERR" LOC = "D12" | IOSTANDARD = PCI33_3 ;
+NET "PREVENT_STRIPPING_OF_UNUSED_INPUTS" LOC = "AA4" | IOSTANDARD = LVCMOS33 ;
+NET "REQ" LOC = "C18" | IOSTANDARD = PCI33_3 ;
+NET "RST" LOC = "A19" | IOSTANDARD = PCI33_3 ;
+NET "SERR" LOC = "B12" | IOSTANDARD = PCI33_3 ;
+NET "STOP" LOC = "A12" | IOSTANDARD = PCI33_3 ;
+NET "TRDY" LOC = "B13" | IOSTANDARD = PCI33_3 ;
+
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
trunk/examples/pci_lpc/pci_lpc.ucf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/examples/pci_lpc/pci_lpc.ise
===================================================================
--- trunk/examples/pci_lpc/pci_lpc.ise (nonexistent)
+++ trunk/examples/pci_lpc/pci_lpc.ise (revision 7)
@@ -0,0 +1,6823 @@
+PK
+
+ __OBJSTORE__/PK
+ __OBJSTORE__/common/PK
+ ' __OBJSTORE__/common/HierarchicalDesign/PK
+ T ~ ~ 0 __OBJSTORE__/common/HierarchicalDesign/HDProject PK
+ Pf f 7 __OBJSTORE__/common/HierarchicalDesign/HDProject_StrTbl
+ 1 4 /pci_lpc_host TS_EXPANDED TS_FRAGCOVERED TS_PACKED TS_ROUTED TS_SYNTHESIS pci_lpc_host PK
+ ";< < + __OBJSTORE__/common/__stored_object_table__ ( : PK
+ __OBJSTORE__/HierarchicalDesign/PK
+ __OBJSTORE__/PnAutoRun/PK
+ __OBJSTORE__/PnAutoRun/Scripts/PK
+ > * __OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl PK
+ 髭 1 __OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl namespace eval xilinx {
+namespace eval Dpm {
+proc GetIseVersion {} {
+ set fsetName "fileset.txt"
+ set fsetPath ""
+ # Find the file in the Xilinx environment.
+ # First, construct the environment path.
+ set sep ":"; # Default to UNIX style seperator.
+ if {[string compare -length 7 $::tcl_platform(platform) "windows"] == 0} {
+ set sep ";"; # Platform is a Windows variant, so use semi-colon.
+ }
+ set xilinxPath $::env(XILINX)
+ if [info exists ::env(MYXILINX)] then {
+ set xilinxPath [join [list $::env(MYXILINX) $xilinxPath] $sep]
+ }
+ # Now look in each path of the path until we find a match.
+ foreach xilElem [split $xilinxPath $sep] {
+ set checkPath ${xilElem}/$fsetName
+ set checkPath [ string map { \\ / } $checkPath ]
+ if { [file exists $checkPath] } {
+ set fsetPath $checkPath
+ break
+ }
+ }
+ if { [string equal $fsetPath ""] } {
+ puts "ERROR: Can not determine the ISE software version."
+ return ""
+ }
+ if { [catch { open $fsetPath r } fset] } {
+ puts "ERROR: Could not open $fsetPath: $fset"
+ return ""
+ }
+ # have the file open, scan for the version entry.
+ set sVersion ""
+ while { ![eof $fset] } {
+ set line [gets $fset]
+ regexp {version=(.*)} $line match sVersion
+ # The above doesn't stop looking in the file. This assumes that if
+ # there are multiple version entries, the last one is the one we want.
+ }
+ close $fset
+ return $sVersion
+}
+proc CheckForIron {project_name} {
+
+ # Determine if the currently running version of ProjNav is earlier than Jade.
+ set version [GetIseVersion]
+ set dotLocation [string first "." $version]
+ set versionBase [string range $version 0 [expr {$dotLocation - 1}]]
+ if {$versionBase < 9} {
+
+ # The project file is newer than Iron, so take action to prevent the
+ # file from being corrupted.
+ # Make the file read-only.
+ if {[string compare -length 7 $::tcl_platform(platform) "windows"]} {
+ # The above will return 0 for a match to "windows" or "windows64".
+ # This is the non-zero part of the if, for lin and sol.
+ # Change the permissions to turn off writability.
+ file attributes $project_name -permissions a-w
+ } else {
+ # On Windows, set file to read-only.
+ file attributes $project_name -readonly 1
+ }
+
+ # And tell the user about it.
+ set messageText "WARNING: This project was last saved with a newer version of Project Navigator.\nThe project file will be made read-only so that it will not be invalidated by this version."
+ # In the console window
+ puts $messageText
+ # And with a GUI message box if possible.
+ ::xilinx::Dpm::TOE::loadGuiLibraries
+ set iInterface 0
+ set messageDisplay 0
+ if {[catch {
+ set iInterface [Xilinx::CitP::GetInstance $::xilinx::GuiI::IMessageDlgID]
+ set messageDisplay [$iInterface GetInterface $::xilinx::GuiI::IMessageDlgID]
+ if {$messageDisplay != 0} {
+ # Managed to get a component to display a dialog, so use it
+ set messageTitle "Incompatible Project Version (Newer)"
+ set messageType 2
+ # 2 corresponds to a warning dialog. TclWrapGuiI_Init.cpp doesn't put the enum into Tcl.
+ set messageTimeout 300000
+ # in milliseconds, 5 minutes
+ set messageReturn [$messageDisplay MessageDlg $messageTitle $messageText $messageType 1 1 $messageTimeout "OK" "" ""]
+ }
+ } catchResult]} {
+ # There was an error, probably because we aren't in a GUI enviroment.
+ } else {
+ # All is well.
+ }
+ set messageDisplay 0
+ set iInterface 0
+ }
+
+ return 1
+}
+}
+}
+::xilinx::Dpm::CheckForIron PK
+ __OBJSTORE__/ProjectNavigator/PK
+ / __OBJSTORE__/ProjectNavigator/dpm_project_main/PK
+ dV V ? __OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main EB PK
+ _S7 7 F __OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl pci_lpc acr2 spartan3 virtex2p xbr xc9500xl PK
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OBUFT_LVCMOS18_F_2|unisim|vcomponents OBUFT_LVCMOS18_F_4|unisim|vcomponents OBUFT_LVCMOS18_F_6|unisim|vcomponents OBUFT_LVCMOS18_F_8|unisim|vcomponents OBUFT_LVCMOS18_S_12|unisim|vcomponents OBUFT_LVCMOS18_S_16|unisim|vcomponents OBUFT_LVCMOS18_S_2|unisim|vcomponents OBUFT_LVCMOS18_S_4|unisim|vcomponents OBUFT_LVCMOS18_S_6|unisim|vcomponents OBUFT_LVCMOS18_S_8|unisim|vcomponents OBUFT_LVCMOS18|unisim|vcomponents OBUFT_LVCMOS25_F_12|unisim|vcomponents OBUFT_LVCMOS25_F_16|unisim|vcomponents OBUFT_LVCMOS25_F_24|unisim|vcomponents OBUFT_LVCMOS25_F_2|unisim|vcomponents OBUFT_LVCMOS25_F_4|unisim|vcomponents OBUFT_LVCMOS25_F_6|unisim|vcomponents OBUFT_LVCMOS25_F_8|unisim|vcomponents OBUFT_LVCMOS25_S_12|unisim|vcomponents OBUFT_LVCMOS25_S_16|unisim|vcomponents OBUFT_LVCMOS25_S_24|unisim|vcomponents OBUFT_LVCMOS25_S_2|unisim|vcomponents OBUFT_LVCMOS25_S_4|unisim|vcomponents OBUFT_LVCMOS25_S_6|unisim|vcomponents OBUFT_LVCMOS25_S_8|unisim|vcomponents OBUFT_LVCMOS25|unisim|vcomponents OBUFT_LVCMOS2|unisim|vcomponents OBUFT_LVCMOS33_F_12|unisim|vcomponents OBUFT_LVCMOS33_F_16|unisim|vcomponents OBUFT_LVCMOS33_F_24|unisim|vcomponents OBUFT_LVCMOS33_F_2|unisim|vcomponents OBUFT_LVCMOS33_F_4|unisim|vcomponents OBUFT_LVCMOS33_F_6|unisim|vcomponents OBUFT_LVCMOS33_F_8|unisim|vcomponents OBUFT_LVCMOS33_S_12|unisim|vcomponents OBUFT_LVCMOS33_S_16|unisim|vcomponents OBUFT_LVCMOS33_S_24|unisim|vcomponents OBUFT_LVCMOS33_S_2|unisim|vcomponents OBUFT_LVCMOS33_S_4|unisim|vcomponents OBUFT_LVCMOS33_S_6|unisim|vcomponents OBUFT_LVCMOS33_S_8|unisim|vcomponents OBUFT_LVCMOS33|unisim|vcomponents OBUFT_LVDCI_15|unisim|vcomponents OBUFT_LVDCI_18|unisim|vcomponents OBUFT_LVDCI_25|unisim|vcomponents OBUFT_LVDCI_33|unisim|vcomponents OBUFT_LVDCI_DV2_15|unisim|vcomponents OBUFT_LVDCI_DV2_18|unisim|vcomponents OBUFT_LVDCI_DV2_25|unisim|vcomponents OBUFT_LVDCI_DV2_33|unisim|vcomponents OBUFT_LVDS|unisim|vcomponents OBUFT_LVPECL|unisim|vcomponents OBUFT_LVTTL_F_12|unisim|vcomponents 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bitgen.xmsgs DESUT_XMSGS |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.bgn|PLUGIN_General|1204672500| FILE_BITGEN_REPORT |Generic||pci_lpc_host.bgn pci_lpc_host.bgn DESUT_BITGEN_REPORT |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.bit|PLUGIN_General|1204672499| FILE_BIT |Generic||pci_lpc_host.bit pci_lpc_host.bit DESUT_BIT |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.drc|PLUGIN_General|1204672496| FILE_BITGEN_DRC |Generic||pci_lpc_host.drc pci_lpc_host.drc DESUT_BITGEN_DRC |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/_xmsgs/trce.xmsgs|PLUGIN_General|1204672492| |Generic||trce.xmsgs trce.xmsgs |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.twx|PLUGIN_General|1204672491| FILE_TIMING_XML_REPORT |Generic||pci_lpc_host.twx pci_lpc_host.twx DESUT_TIMING_XML_REPORT |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.twr|PLUGIN_General|1204672492| FILE_TIMING_TXT_REPORT |Generic||pci_lpc_host.twr pci_lpc_host.twr DESUT_TIMING_TXT_REPORT |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/_xmsgs/par.xmsgs|PLUGIN_General|1204672488| |Generic||par.xmsgs par.xmsgs |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host_pad.csv|PLUGIN_General|1204672488| FILE_PAD_EXCEL_REPORT |Generic||pci_lpc_host_pad.csv pci_lpc_host_pad.csv DESUT_PAD_EXCEL_REPORT |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host_pad.txt|PLUGIN_General|1204672488| FILE_PAD_TXT_REPORT |Generic||pci_lpc_host_pad.txt pci_lpc_host_pad.txt DESUT_PAD_TXT_REPORT TBIND_viewPadRpts TRAN_viewPadRpts |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.xpi|PLUGIN_General|1204672488| FILE_XPI |Generic||pci_lpc_host.xpi pci_lpc_host.xpi DESUT_XPI |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.unroutes|PLUGIN_General|1204672488| FILE_UNROUTES |Generic||pci_lpc_host.unroutes pci_lpc_host.unroutes DESUT_UNROUTES |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.par|PLUGIN_General|1204672488| FILE_PAR_REPORT |Generic||pci_lpc_host.par pci_lpc_host.par DESUT_PAR_REPORT TBIND_viewParRpts TRAN_viewParRpts |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.pad|PLUGIN_General|1204672488| FILE_PAD_MISC |Generic||pci_lpc_host.pad pci_lpc_host.pad DESUT_PAD_MISC |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.ncd|PLUGIN_NCD|1204672488| PLUGIN_NCD FILE_NCD |Module||pci_lpc_host pci_lpc_host DESUT_NCD |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host_usage.xml|PLUGIN_General|1204672499| FILE_WEBTALK |Generic||pci_lpc_host_usage.xml pci_lpc_host_usage.xml DESUT_GENERIC |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/_xmsgs/map.xmsgs|PLUGIN_General|1204672476| |Generic||map.xmsgs map.xmsgs |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host_map.ngm|PLUGIN_NGM|1204672475| PLUGIN_NGM FILE_NGM DESUT_NGM 3s400fg456-4 |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.pcf|PLUGIN_General|1204672475| FILE_PCF |Generic||pci_lpc_host.pcf pci_lpc_host.pcf DESUT_PCF |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host_map.mrp|PLUGIN_General|1204672476| FILE_MAP_REPORT |Generic||pci_lpc_host_map.mrp pci_lpc_host_map.mrp DESUT_MAP_REPORT |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host_map.ncd|PLUGIN_NCD|1204672476| |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/_xmsgs/ngdbuild.xmsgs|PLUGIN_General|1204672471| |Generic||ngdbuild.xmsgs ngdbuild.xmsgs |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/_ngo|PLUGIN_General|1204672468| FILE_DIRECTORY |Generic||_ngo _ngo DESUT_DIRECTORY |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/_ngo/netlist.lst|PLUGIN_General|1204672471| FILE_LST |Generic||netlist.lst netlist.lst DESUT_LST |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.bld|PLUGIN_General|1204672471| FILE_NGDBUILD_LOG |Generic||pci_lpc_host.bld pci_lpc_host.bld DESUT_NGDBUILD_LOG |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.ngd|PLUGIN_NGD|1204672471| PLUGIN_NGD FILE_NGD DESUT_NGD |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/_xmsgs/xst.xmsgs|PLUGIN_General|1204672464| |Generic||xst.xmsgs xst.xmsgs |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.cmd_log|PLUGIN_General|1204672494| FILE_CMD_LOG |Generic||pci_lpc_host.cmd_log pci_lpc_host.cmd_log DESUT_CMD_LOG |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/xst|PLUGIN_General|1204672450| |Generic||xst xst |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.ngr|PLUGIN_NGR|1204672455| PLUGIN_NGR FILE_NGR DESUT_NGR |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.ngc|PLUGIN_NGC|1204672464| PLUGIN_NGC FILE_NGC DESUT_NGC xc3s400-4-fg456 |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host_vhdl.prj|PLUGIN_General|1204672450| FILE_XST_PROJECT |Generic||pci_lpc_host_vhdl.prj pci_lpc_host_vhdl.prj DESUT_XST_PROJECT |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.prj|PLUGIN_General|1204672449| |Generic||pci_lpc_host.prj pci_lpc_host.prj |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.syr|PLUGIN_General|1204672464| FILE_XST_REPORT |Generic||pci_lpc_host.syr pci_lpc_host.syr DESUT_XST_REPORT |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.lso|PLUGIN_General|1204672450| FILE_LSO |Generic||pci_lpc_host.lso pci_lpc_host.lso DESUT_LSO |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.xst|PLUGIN_General|1204672449| FILE_XST |Generic||pci_lpc_host.xst pci_lpc_host.xst DESUT_XST |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host.stx|PLUGIN_General|1204672465| FILE_XST_STX |Generic||pci_lpc_host.stx pci_lpc_host.stx DESUT_XST_STX |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/wb_7seg.vhd|PLUGIN_Vhdl|1204597328| FILE_VHDL |Architecture||wb_7seg_behav|wb_7seg|| |ComponentInstantiation||wb_7seg|wb_7seg_behav|u1|disp_dec| |Entity||wb_7seg |Library||| |Use||IEEE|STD_LOGIC_1164|all| |Use||IEEE|STD_LOGIC_ARITH|all| |Use||IEEE|STD_LOGIC_UNSIGNED|all| wb_7seg_behav wb_7seg DESUT_VHDL_ARCHITECTURE u1 disp_dec DESUT_VHDL_ENTITY IEEE.STD_LOGIC_UNSIGNED.all IEEE STD_LOGIC_UNSIGNED all IEEE.STD_LOGIC_ARITH.all STD_LOGIC_ARITH IEEE.STD_LOGIC_1164.all STD_LOGIC_1164 |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/disp_dec.vhd|PLUGIN_Vhdl|1141325921| |Architecture||disp_dec_behave|disp_dec|| |Entity||disp_dec disp_dec_behave |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc_host_guide.ncd|PLUGIN_NCD|1204672488| |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/top_pci_lpc_host.v|PLUGIN_Verilog|1204671407| FILE_VERILOG |ComponentInstantiation||pci_lpc_host|pci_lpc_host|lpc_host|wb_lpc_host| |ComponentInstantiation||pci_lpc_host|pci_lpc_host|pci_target|pci32tLite| |ComponentInstantiation||pci_lpc_host|pci_lpc_host|seven_seg0|wb_7seg| DESUT_VERILOG seven_seg0 lpc_host wb_lpc_host pci_target pci32tLite |File||C:/hharte/work/HarteTec/cores/wb_lpc/rtl/verilog/wb_lpc_host.v|PLUGIN_Verilog|1204671559| |Module||wb_lpc_host |File||C:/hharte/work/HarteTec/cores/pci32tlite/rtl/sync.vhd|PLUGIN_Vhdl|1141325922| |Architecture||rtl|sync|| |Entity||sync |Use||ieee|std_logic_1164|all| rtl sync ieee.std_logic_1164.all ieee std_logic_1164 |File||C:/hharte/work/HarteTec/cores/pci32tlite/rtl/pfs.vhd|PLUGIN_Vhdl|1141325915| |Architecture||rtl|pfs|| |Entity||pfs pfs |File||C:/hharte/work/HarteTec/cores/pci32tlite/rtl/pciwbsequ.vhd|PLUGIN_Vhdl|1190247720| |Architecture||rtl|pciwbsequ|| |ComponentInstantiation||pciwbsequ|rtl|uu1|syncl| |Entity||pciwbsequ |Use||onalib|onapackage|all| pciwbsequ uu1 syncl onalib.onapackage.all onapackage |File||C:/hharte/work/HarteTec/cores/pci32tlite/rtl/pciregs.vhd|PLUGIN_Vhdl|1190247540| |Architecture||rtl|pciregs|| |ComponentInstantiation||pciregs|rtl|u1|pfs| |ComponentInstantiation||pciregs|rtl|u2|pfs| |ComponentInstantiation||pciregs|rtl|u3|pfs| |Entity||pciregs pciregs u3 u2 |File||C:/hharte/work/HarteTec/cores/pci32tlite/rtl/pcipargen.vhd|PLUGIN_Vhdl|1190247540| |Architecture||rtl|pcipargen|| |ComponentInstantiation||pcipargen|rtl|u1|sync| |Entity||pcipargen pcipargen |File||C:/hharte/work/HarteTec/cores/pci32tlite/rtl/pcidmux.vhd|PLUGIN_Vhdl|1190247780| |Architecture||rtl|pcidmux|| |Entity||pcidmux pcidmux |File||C:/hharte/work/HarteTec/cores/pci32tlite/rtl/pcidec.vhd|PLUGIN_Vhdl|1190247600| |Architecture||rtl|pcidec|| |Entity||pcidec pcidec |File||C:/hharte/work/HarteTec/cores/pci32tlite/rtl/pci32tlite.vhd|PLUGIN_Vhdl|1203982953| |Architecture||rtl|pci32tLite|| |ComponentInstantiation||pci32tLite|rtl|u1|pcidec| |ComponentInstantiation||pci32tLite|rtl|u2|pciwbsequ| |ComponentInstantiation||pci32tLite|rtl|u3|pcidmux| |ComponentInstantiation||pci32tLite|rtl|u4|pciregs| |ComponentInstantiation||pci32tLite|rtl|u5|pcipargen| |Entity||pci32tLite u5 u4 |File||C:/hharte/work/HarteTec/cores/pci32tlite/rtl/onalib.vhd|PLUGIN_Vhdl|1190247780| |Architecture||rtl|decoder3to8|| |Architecture||rtl|pfb|| |Architecture||rtl|sync2h|| |Architecture||rtl|sync2l|| |Architecture||rtl|sync2|| |Architecture||rtl|synch|| |Architecture||rtl|syncl|| |Architecture||rtl|syncv2h|| |Architecture||rtl|syncv|| |Entity||decoder3to8 |Entity||pfb |Entity||sync2 |Entity||sync2h |Entity||sync2l |Entity||synch |Entity||syncl |Entity||syncv |Entity||syncv2h |PackageDecl||onapackage| pfb decoder3to8 success_TRAN_chkSynVhdl_OPER syncv2h syncv sync2l sync2h sync2 synch DESUT_VHDL_PACKAGE_DECL |File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/pci_lpc/pci_lpc.ucf|PLUGIN_AssocModule|1204656398| PLUGIN_AssocModule FILE_UCF |Module||pci_lpc.ucf pci_lpc.ucf DESUT_UCF AutoGeneratedView VIEW_AssignPackagePins TBIND_XSTAssignPackagePins TRAN_assignPackagePins VIEW_XSTPreSynthesis TBIND_EditConstraintsTextApp TRAN_editConstraints VIEW_PreSynthEditConstraints TBINDEXT_XSTPreSynthesisToStructural_spartan3 TRAN_copyPreSynthesisToStructuralForBitgen TRANEXT_xstsynthesize_spartan3 TRAN_copyPreSynthesisToStructuralForTranslate VIEW_Structural TBIND_StructuralToPost-SynthesisAbstractSimulation TRAN_postSynthesisSimModel Module|pci_lpc VIEW_Post-SynthesisAbstractSimulation TBINDEXT_StructuralToTranslation_FPGA TRAN_copyStructuralToTranslationForBitgen TRAN_copyStructuralToTranslationForConstraints TRANEXT_ngdbuild_FPGA VIEW_Translation TBIND_xlateFloorPlanner TRAN_xlateFloorPlanner VIEW_Post-TranslateFloorPlanner TBIND_xlateAssignPackagePins TRAN_xlateAssignPackagePins VIEW_Post-TranslateAssignPins TBIND_TranslationToPost-TranslateFormalityNetlist TRAN_postXlateFormalityNetlist VIEW_Post-TranslateFormalityNetlist TBIND_TranslationToPost-TranslateAbstractSimulation TRAN_postXlateSimModel VIEW_Post-TranslateAbstractSimulation TBIND_Post-TranslateAbstractToTBWPreSimulation TRAN_createPostXlateTestBench TRAN_copyPost-TranslateAbstractToPreSimulation VIEW_TBWPost-TranslatePreSimulation TBIND_Post-TranslateAbstractToPreSimulation VIEW_Post-TranslatePreSimulation TBIND_NGCAssignPackagePins TRAN_ngcAssignPackagePins VIEW_ngcAssignPackagePins TBIND_CreateTimingConstraints TRAN_createTimingConstraints VIEW_Post-TranslateTimingConstraints TBIND_CreateAreaConstraints TRAN_createAreaConstraints VIEW_Post-TranslateAreaConstraints TBINDEXT_TranslationToMap_spartan3 TRAN_copyTranslationToMapForBitgen TRANEXT_map_spartan3 VIEW_Map TBIND_preRouteTrce TRAN_preRouteTrce VIEW_Post-MapStaticTiming TBIND_mapFpgaEditor TRAN_mapFpgaEditor VIEW_Post-MapFpgaEditor TBIND_mapFloorPlanner TRAN_mapFloorPlanner VIEW_Post-MapFloorPlanner TBIND_MapToPost-MapAbstractSimulation TRAN_postMapSimModel VIEW_Post-MapAbstractSimulation TBIND_Post-MapAbstractToTBWPreSimulation TRAN_createPostMapTestBench TRAN_copyPost-MapAbstractToPreSimulation VIEW_TBWPost-MapPreSimulation TBIND_Post-MapAbstractToPreSimulation VIEW_Post-MapPreSimulation TBINDEXT_MapToPar_spartan3 TRAN_copyMapToParForBitgen TRANEXT_par_spartan3 VIEW_Par TBIND_postRouteTrce TRAN_postRouteTrce VIEW_Post-ParStaticTiming TBIND_postParPrimetimeNetlist TRAN_postParPrimetimeNetlist VIEW_PrimetimeNetlist TBIND_parFpgaEditor TRAN_parFpgaEditor VIEW_Post-ParFpgaEditor TBIND_parFloorPlanner TRAN_parFloorPlanner VIEW_Post-ParFloorPlanner TBIND_genPowerData TRAN_genPowerData VIEW_FPGAGeneratePowerData TBIND_createIBISModel TRAN_createIBISModel VIEW_IBISModel TBIND_Xpower TRAN_XPower VIEW_FPGAAnalyzePower TBIND_ParToPost-ParFormalityNetlist TRAN_postParFormalityNetlist VIEW_Post-ParFormalityNetlist TBIND_ParToPost-ParClockRegion TRAN_clkRegionRpt VIEW_Post-ParClockRegionReport TBIND_ParToPost-ParAsyncDelay TRAN_asynDlyRpt VIEW_Post-ParAsyncDelayReport TBIND_ParToPost-ParAbstractSimulation TRAN_postParSimModel VIEW_Post-ParAbstractSimulation TBIND_Post-ParAbstractToTBWPreSimulation TRAN_createPostParTestBench TRAN_copyPost-ParAbstractToPreSimulation VIEW_TBWPost-ParPreSimulation TBIND_TBWPost-ParPreToFuse TRAN_ISimulatePostPlace&RouteModelRunFuse(bencher) VIEW_TBWPost-ParFuse TBIND_TBWPost-ParFuseToSimulationISim TRAN_ISimulatePostPlace&RouteModel(bencher) VIEW_TBWPost-ParSimulationISim TBIND_Post-ParAbstractToPreSimulation VIEW_Post-ParPreSimulation TBIND_Post-ParPreToFuse TRAN_ISimulatePostPlace&RouteModelRunFuse VIEW_Post-ParFuse TBIND_Post-ParFuseToSimulationISim TRAN_ISimulatePostPlace&RouteModel VIEW_Post-ParSimulationISim TBIND_ParToMpprResult TRAN_copyMpprRslt VIEW_MpprResult TBIND_ParToLockedPinConstraints TRAN_genLockedPinConstraints VIEW_LockedPinConstraints TBIND_ParToBackAnnoPinLocations TRAN_backAnnoPinLocations VIEW_BackAnnoPinLocations TBINDEXT_ParToFPGAConfiguration_spartan3 TRANEXT_bitFile_spartan3 VIEW_FPGAConfiguration TBIND_analyzeDesignUsingChipscope TRAN_analyzeDesignUsingChipscope VIEW_AnalyzedDesign TBIND_UpdateBitstreamXPS TRAN_xpsUpdBitstream VIEW_UpdatedBitstream TBIND_FPGAConfigurationToFPGAGeneratePROM TRAN_genImpactFile VIEW_FPGAGeneratePROM TBIND_FPGAConfigurationToFPGAConfigureDevice TRAN_impactProgrammingTool VIEW_FPGAConfigureDevice TBIND_XSTAbstractToPreSynthesis TRAN_copyAbstractToPreSynthesisForBitgen TRAN_copyAbstractToPreSynthesisForTranslate TRAN_convertToHdl TRAN_copyAbstractToPreSynthesisForSynthesis VIEW_XSTAbstractSynthesis TBIND_InitialToXSTAbstractSynthesis TRAN_copyInitialToXSTAbstractSynthesis VIEW_Initial TBIND_InitialToAbstractSimulation TRAN_copyInitialToAbstractSimulation VIEW_AbstractSimulation TBIND_AbstractToPostAbstractSimulation TRAN_copyAbstractToPostAbstractSimulation VIEW_PostAbstractSimulation TBIND_PostAbstractToTBWPreSimulation TRAN_viewBehavioralTestbench TRAN_copyPostAbstractToPreSimulation VIEW_TBWPreSimulation TBIND_TBWPreToBehavioralFuse TRAN_ISimulateBehavioralModelRunFuse(bencher) VIEW_TBWBehavioralFuse TBIND_TBWBehavioralFuseToSimulationISim TRAN_ISimulateBehavioralModel(bencher) VIEW_TBWBehavioralSimulationISim TBIND_PostAbstractToPreSimulation VIEW_PreSimulation TBIND_PreToBehavioralFuse TRAN_ISimulateBehavioralModelRunFuse VIEW_BehavioralFuse TBIND_BehavioralFuseToSimulationISim TRAN_ISimulateBehavioralModel VIEW_BehavioralSimulationISim TBIND_PostAbstractToAnnotatedPreSimulation TRAN_viewBehavioralTestbenchForAnno TRAN_copyPostAbstractToAnnotatedPreSimulation VIEW_AnnotatedPreSimulation TBIND_PreToGenerateAnnotatedResultsFuse TRAN_ISimGenerateAnnotatedResultsRunFuse TRAN_copyPreToGenerateAnnotatedResultsFuseForTBW VIEW_AnnotatedResultsFuse TBIND_FuseToAnnotatedResultsISim TRAN_ISimGenerateAnnotatedResults TRAN_copyFuseToAnnotatedResultsISimForTBW VIEW_AnnotatedResultsISim TBIND_AnnotatedToGenerateExpectedSimulationResultsISim TRAN_ISimGenerateExpectedSimulationResults VIEW_ExpectedSimulationResultsISim TBINDEXT_InitialToCommon_FPGA TRANEXT_compLibraries_FPGA VIEW_Common DESPF_TRADITIONAL PROP_PreferredLanguage Verilog PROP_Simulator Modelsim-XE VHDL ISE Simulator (VHDL/Verilog) Other Mixed Other Verilog Other VHDL VCS-MXi Mixed VCS-MXi Verilog VCS-MXi VHDL VCS-MX Mixed VCS-MX Verilog VCS-MX VHDL NC-Sim Mixed NC-Sim Verilog NC-Sim VHDL Modelsim-XE Verilog Modelsim-PE Mixed Modelsim-PE Verilog Modelsim-PE VHDL Modelsim-SE Mixed Modelsim-SE Verilog Modelsim-SE VHDL PROP_Synthesis_Tool XST (VHDL/Verilog) PROP_Top_Level_Module_Type HDL VHDL PROP_DevSpeed -5 -4 PROP_DevPackage fg320 fg456 PROP_DevDevice xc3s50 xc3s400 xc3s1500l xc3s1500 xc3s1000l xc3s1000 xc3s200 tq144 pq208 ft256 PROP_ParSmartGuideFileName PROP_SmartGuide PROP_TopDesignUnit Module|pci_lpc_host NCD files (*.ncd)|*.ncd PROP_MapSmartGuideFileName PROP_ISimSpecifyDefMacroAndValue PROP_ISimSpecifySearchDirectory PROP_ISimSpecifySearchDir PROP_ISimValueRangeCheck PROP_ISimCompileForHdlDebug PROP_ISimIncreCompilation PROP_xstVeriIncludeDir PROP_tbwPostParTestbenchName PROP_tbwTestbenchTargetLang PROP_tbwPostMapTestbenchName PROP_tbwPostXlateTestbenchName PROP_PostParSimModelName pci_lpc_host_timesim.v PROP_SimModelTarget _timesim.v PROP_PostMapSimModelName pci_lpc_host_map.v _map.v PROP_PostXlateSimModelName _translate.v pci_lpc_host_translate.v PROP_SimModelRenTopLevEntTo PROP_SimModelGenArchOnly PROPEXT_xilxBitgCfg_DCIUpdateMode_spartan3 As Required PROPEXT_xilxBitgCfg_Rate_spartan3 Default (6) PROPEXT_xilxSynthAddBufg_spartan3 PROPEXT_xilxSynthMaxFanout_virtex2 PROPEXT_SynthMultStyle_virtex2 Auto PROPEXT_xilxMapGenInputK_virtex2 4 PROP_MapRegDuplication PROP_xilxMapTimingDrivenPacking PROP_MapLogicOptimization PROP_MapPlacerCostTable PROP_MapExtraEffort None PROP_MapEffortLevel Medium High Standard Continue on Impossible Normal PROP_xilxBitgStart_Clk_MatchCycle PROP_xilxBitgCfg_DCMShutdown PROP_xilxBitgCfg_GenOpt_EnableCRC PROP_xilxBitgCfg_GenOpt_IEEE1532File PROP_xilxBitgCfg_GenOpt_Compress PROP_xilxBitgCfg_GenOpt_ASCIIFile PROP_xilxBitgCfg_GenOpt_BinaryFile PROP_xilxBitgCfg_GenOpt_BitFile PROP_xilxBitgCfg_GenOpt_DRC PROP_parMpprNodelistFile PROP_xilxPARstrat Normal Place and Route All files (*)|* PROP_parMpprResultsDirectory PROP_parMpprResultsToSave PROP_parMpprParIterations PROP_mpprRsltToCopy PROP_mpprViewPadRptForSelRslt PROP_mpprViewPadRptsForAllRslt PROP_mpprViewParRptForSelRslt PROP_mpprViewParRptsForAllRslt PROP_par_otherCmdLineOptions PROP_parPowerReduction PROP_parGenSimModel PROP_parGenTimingRpt PROP_parGenClkRegionRpt PROP_parGenAsyDlyRpt PROP_xilxPARuseBondedIO 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trunk/examples/pci_lpc/pci_lpc.ise
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/examples/pci_lpc/top_pci_lpc_host.v
===================================================================
--- trunk/examples/pci_lpc/top_pci_lpc_host.v (nonexistent)
+++ trunk/examples/pci_lpc/top_pci_lpc_host.v (revision 7)
@@ -0,0 +1,238 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// $Id: top_pci_lpc_host.v,v 1.1 2008-03-05 05:58:41 hharte Exp $ ////
+//// top_pci_lpc_host.v - Top Level for PCI to LPC Host ////
+//// for the Enterpoint Raggedstone1 PCI Card. Based on the ////
+//// OpenCores raggedstone project, and uses the OpenCores ////
+//// pci32tlite core. ////
+//// ////
+//// This file is part of the Wishbone LPC Bridge project ////
+//// http://www.opencores.org/projects/wb_lpc/ ////
+//// ////
+//// Author: ////
+//// - Howard M. Harte (hharte@opencores.org) ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2008 Howard M. Harte ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module pci_lpc_host
+(
+ CLK,
+ RST, // Active Low
+ INTA,
+ REQ,
+ GNT,
+ FRAME,
+ IRDY,
+ IDSEL,
+ DEVSEL,
+ TRDY,
+ STOP,
+ PAR,
+ PERR,
+ SERR,
+ PCI_AD,
+ CBE0,
+ CBE1,
+ CBE2,
+ CBE3,
+
+ DISP_SEL,
+ DISP_LED,
+
+ LPC_CLK,
+ LFRAME,
+ LAD,
+ LAD_OE,
+ LPC_INT,
+
+ PREVENT_STRIPPING_OF_UNUSED_INPUTS
+);
+
+input CLK ;
+input RST ;
+
+inout [31:0] PCI_AD ;
+
+input CBE0,
+ CBE1,
+ CBE2,
+ CBE3 ;
+
+output PAR ;
+input FRAME ;
+input IRDY ;
+output TRDY ;
+output DEVSEL ;
+inout STOP ;
+input IDSEL ;
+inout PERR ;
+inout SERR ;
+output INTA ;
+//attribute s: string; -- SAVE NET FLAG
+input REQ ; // attribute s of PCI_nREQ: signal is "yes";
+input GNT ; // attribute s of PCI_nGNT: signal is "yes";
+output [3:0] DISP_SEL ;
+output [6:0] DISP_LED ;
+
+output LPC_CLK;
+output LFRAME;
+inout [3:0] LAD;
+input LPC_INT;
+output LAD_OE;
+
+output PREVENT_STRIPPING_OF_UNUSED_INPUTS ;
+
+assign PREVENT_STRIPPING_OF_UNUSED_INPUTS = REQ & GNT;
+
+wire [2:0] dma_chan_i = 3'b000;
+wire dma_tc_i = 1'b0;
+wire lframe_o;
+wire [3:0] lad_i;
+wire [3:0] lad_o;
+wire host_lad_oe;
+
+assign LAD = (host_lad_oe ? lad_o : 4'bzzzz);
+assign LAD_OE = host_lad_oe;
+assign LPC_CLK = CLK;
+assign LFRAME = ~lframe_o;
+
+wire [3:0] CBE_in =
+{
+ CBE3,
+ CBE2,
+ CBE1,
+ CBE0
+} ;
+
+wire PCI_CLK = CLK;
+
+wire [24:0] wb_adr_o;
+wire [31:0] wb_dat_i;
+wire [31:0] wb_dat_o;
+wire [3:0] wb_sel_o;
+wire [1:0] wb_tga;
+wire wb_we_o;
+wire wb_stb_o;
+wire wb_cyc_o;
+wire wb_ack_i;
+wire wb_rty_i = 1'b0;
+wire wb_err_i = 1'b0;
+wire wb_int_i;
+
+//assign wb_tga = wb_adr_o[17:16]; // I/O Cycle
+assign wb_tga = 2'b10; // Firmware cycle
+
+assign wb_int_i = ~LPC_INT;
+
+// Instantiate the pci32tlite module
+pci32tLite #(
+// .vendorID(16'h10ee),
+// .deviceID(16'hf00d),
+// .revisionID(8'h01),
+ .vendorID(16'h14e4),
+ .deviceID(16'h43f5),
+ .revisionID(8'h0a),
+ .subsystemID(16'h0),
+ .subsystemvID(16'h0),
+ .BARS("1BARMEM"),
+ .WBSIZE(32),
+ .WBENDIAN("LITTLE"))
+pci_target (
+ .clk33(PCI_CLK),
+ .rst(~RST),
+ .ad(PCI_AD),
+ .cbe(CBE_in),
+ .par(PAR),
+ .frame(FRAME),
+ .irdy(IRDY),
+ .trdy(TRDY),
+ .devsel(DEVSEL),
+ .stop(STOP),
+ .idsel(IDSEL),
+ .perr(PERR),
+ .serr(SERR),
+ .intb(INTA),
+ .wb_adr_o(wb_adr_o),
+ .wb_dat_i(wb_dat_i),
+ .wb_dat_o(wb_dat_o),
+ .wb_sel_o(wb_sel_o),
+ .wb_we_o(wb_we_o),
+ .wb_stb_o(wb_stb_o),
+ .wb_cyc_o(wb_cyc_o),
+ .wb_ack_i(wb_ack_i),
+ .wb_rty_i(wb_rty_i),
+ .wb_err_i(wb_err_i),
+ .wb_int_i(wb_int_i)
+ );
+
+wb_lpc_host lpc_host (
+ .clk_i(CLK),
+ .nrst_i(RST),
+ .wbs_adr_i(wb_adr_o),
+ .wbs_dat_o(wb_dat_i),
+ .wbs_dat_i(wb_dat_o),
+ .wbs_sel_i(wb_sel_o),
+ .wbs_tga_i(wb_tga),
+ .wbs_we_i(wb_we_o),
+ .wbs_stb_i(wb_stb_o),
+ .wbs_cyc_i(wb_cyc_o),
+ .wbs_ack_o(wb_ack_i),
+ .dma_chan_i(dma_chan_i),
+ .dma_tc_i(dma_tc_i),
+ .lframe_o(lframe_o),
+ .lad_i(LAD),
+ .lad_o(lad_o),
+ .lad_oe(host_lad_oe)
+ );
+
+// The 7-segment display is write-only from the PCI interface.
+// Use some dummy nets for inputs that are ignored.
+wire [31:0] wb2_dat_i;
+wire wb2_ack_i;
+wire wb2_err_i;
+wire wb2_int_i;
+
+// Instantiate the 7-Segment module on the host
+wb_7seg seven_seg0 (
+ .clk_i(CLK),
+ .nrst_i(RST),
+ .wb_adr_i(wb_adr_o),
+ .wb_dat_o(wb2_dat_i),
+ .wb_dat_i(wb_dat_o),
+ .wb_sel_i(wb_sel_o),
+ .wb_we_i(wb_we_o),
+ .wb_stb_i(wb_stb_o),
+ .wb_cyc_i(wb_cyc_o),
+ .wb_ack_o(wb2_ack_i),
+ .wb_err_o(wb2_err_i),
+ .wb_int_o(wb2_int_i),
+ .DISP_SEL(DISP_SEL),
+ .DISP_LED(DISP_LED)
+ );
+
+endmodule
trunk/examples/pci_lpc/top_pci_lpc_host.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/examples/pci_lpc
===================================================================
--- trunk/examples/pci_lpc (nonexistent)
+++ trunk/examples/pci_lpc (revision 7)
trunk/examples/pci_lpc
Property changes :
Added: svn:ignore
## -0,0 +1,42 ##
+pci_lpc_host_map.map
+pci_lpc_host.twr
+pci_lpc_host.syr
+pci_lpc_host_summary.xml
+pci_lpc_host.xst
+pci_lpc_host_map.ngm
+pci_lpc_host_pad.csv
+pci_lpc_host_guide.ncd
+pci_lpc_host.twx
+pci_lpc_host.unroutes
+pci_lpc_host_usage.xml
+pci_lpc_host.prj
+pci_lpc_host.xpi
+pci_lpc_host.pad
+pci_lpc_host.ncd
+pci_lpc.cel
+pci_lpc_host.bgn
+pci_lpc_host.ngc
+pci_lpc_host.pcf
+pci_lpc_host.ngd
+pci_lpc.ntrc_log
+_ngo
+pci_lpc_host.stx
+pci_lpc_host_summary.html
+pci_lpc_host.par
+pci_lpc_host.ngr
+pci_lpc.restore
+pci_lpc_host.ut
+pci_lpc_host_map.mrp
+_xmsgs
+pci_lpc_host.lso
+pci_lpc_host.bld
+pci_lpc_host_map.ncd
+pci_lpc_host_pad.txt
+pci_lpc_host_prev_built.ngd
+pci_lpc_host.cmd_log
+__ISE_repository_pci_lpc.ise_.lock
+pci_lpc.ise_ISE_Backup
+pci_lpc_host.drc
+pci_lpc_host_vhdl.prj
+xst
+.svn
Index: trunk/examples/README.TXT
===================================================================
--- trunk/examples/README.TXT (nonexistent)
+++ trunk/examples/README.TXT (revision 7)
@@ -0,0 +1,56 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// $Id: README.TXT,v 1.1 2008-03-05 05:58:38 hharte Exp $
+//// ////
+//// This file is part of the Wishbone LPC Bridge project ////
+//// http://www.opencores.org/projects/wb_lpc/ ////
+//// ////
+//// Author: ////
+//// - Howard M. Harte (hharte@opencores.org) ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2008 Howard M. Harte ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+Wishbone LPC Bridge Samples:
+
+1. pci_lpc/ PCI to LPC Host Controller using the Enterpoint Raggedstone1 FPGA card.
+2. lpc_7seg/ LPC 7-Segment Display Peripheral using the Raggedston1 FPGA card.
+
+To use these example, you will need two Raggedstone1 boards. The first board is the PCI to LPC host, and the second board is the LPC device. The two Raggedstone1 cards are connected together by making a short ribbon cable using 16-pin DIP IDC connectors. The topmost pins of JR1/JR2 is where this cable plugs in.
+
+The LPC bus is pinned out as follows, on JR2:
+
+W1 LPC_CLK
+W2 LFRAME#
+V5 LAD<0>
+U5 LAD<1>
+V2 LAD<2>
+V1 LAD<3>
+U4
+T4 LPC_INT (active low, not used by 7-segment peripheral, pulled up in host)
+
+If you only have one Raggedstone1 PCI card, these designs could be combined and run on a single card.
Index: trunk/examples
===================================================================
--- trunk/examples (nonexistent)
+++ trunk/examples (revision 7)
trunk/examples
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Added: svn:ignore
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+.svn