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URL https://opencores.org/ocsvn/wb_vga/wb_vga/trunk

Subversion Repositories wb_vga

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Rev 4 → Rev 3

/trunk/wb_io_reg.vhd File deleted
/trunk/accel.vhd File deleted
/trunk/Makefile File deleted \ No newline at end of file
/trunk/palette.vhd File deleted
/trunk/compile.sh File deleted
/trunk/TestBench/palette_TB.vhd File deleted
/trunk/TestBench/accel_TB.vhd File deleted
/trunk/TestBench/vga_chip_TB.vhd
0,0 → 1,309
library ieee,exemplar;
use ieee.std_logic_1164.all;
use exemplar.exemplar_1164.all;
 
entity vga_chip_tb is
-- Generic declarations of the tested unit
generic(
v_mem_width : POSITIVE := 16;
fifo_size : POSITIVE := 256;
v_addr_width : POSITIVE := 20 );
end vga_chip_tb;
 
architecture TB of vga_chip_tb is
-- Component declaration of the tested unit
component vga_chip
port (
clk_i: in std_logic;
clk_en: in std_logic := '1';
rst_i: in std_logic := '0';
-- CPU bus interface
dat_i: in std_logic_vector (8-1 downto 0);
dat_oi: in std_logic_vector (8-1 downto 0);
dat_o: out std_logic_vector (8-1 downto 0);
cyc_i: in std_logic;
ack_o: out std_logic;
ack_oi: in std_logic;
we_i: in std_logic;
vmem_stb_i: in std_logic;
reg_stb_i: in std_logic;
adr_i: in std_logic_vector (20 downto 0);
-- video memory SRAM interface
s_data : inout std_logic_vector((16-1) downto 0);
s_addr : out std_logic_vector((20-1) downto 0);
s_oen : out std_logic;
s_wrhn : out std_logic;
s_wrln : out std_logic;
s_cen : out std_logic;
-- sync blank and video signal outputs
h_sync: out std_logic;
h_blank: out std_logic;
v_sync: out std_logic;
v_blank: out std_logic;
h_tc: out std_logic;
v_tc: out std_logic;
blank: out std_logic;
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
);
end component;
 
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal clk_i : std_logic;
signal clk_en : std_logic;
signal rst_i : std_logic;
signal dat_i : std_logic_vector(7 downto 0);
signal dat_oi : std_logic_vector(7 downto 0);
signal cyc_i : std_logic;
signal ack_oi : std_logic;
signal we_i : std_logic;
signal vmem_stb_i : std_logic;
signal reg_stb_i : std_logic;
signal adr_i : std_logic_vector(v_addr_width downto 0);
signal s_data : std_logic_vector((v_mem_width-1) downto 0);
-- Observed signals - signals mapped to the output ports of tested entity
signal dat_o : std_logic_vector(7 downto 0);
signal ack_o : std_logic;
signal s_addr : std_logic_vector((v_addr_width-1) downto 0);
signal s_oen : std_logic;
signal s_wrhn : std_logic;
signal s_wrln : std_logic;
signal s_cen : std_logic;
signal h_sync : std_logic;
signal h_blank : std_logic;
signal v_sync : std_logic;
signal v_blank : std_logic;
signal h_tc : std_logic;
signal v_tc : std_logic;
signal blank : std_logic;
signal video_out : std_logic_vector(7 downto 0);
 
constant reg_total0 : std_logic_vector(v_addr_width downto 0) := "000000000000000000000";
constant reg_total1 : std_logic_vector(v_addr_width downto 0) := "000000000000000000001";
constant reg_total2 : std_logic_vector(v_addr_width downto 0) := "000000000000000000010";
constant reg_fifo_treshold : std_logic_vector(v_addr_width downto 0) := "000000000000000000011";
constant reg_hbs : std_logic_vector(v_addr_width downto 0) := "000000000000000000100";
constant reg_hss : std_logic_vector(v_addr_width downto 0) := "000000000000000000101";
constant reg_hse : std_logic_vector(v_addr_width downto 0) := "000000000000000000110";
constant reg_htotal : std_logic_vector(v_addr_width downto 0) := "000000000000000000111";
constant reg_vbs : std_logic_vector(v_addr_width downto 0) := "000000000000000001000";
constant reg_vss : std_logic_vector(v_addr_width downto 0) := "000000000000000001001";
constant reg_vse : std_logic_vector(v_addr_width downto 0) := "000000000000000001010";
constant reg_vtotal : std_logic_vector(v_addr_width downto 0) := "000000000000000001011";
constant reg_pps : std_logic_vector(v_addr_width downto 0) := "000000000000000001100";
constant reg_ws : std_logic_vector(v_addr_width downto 0) := "000000000000000001101";
constant reg_bpp : std_logic_vector(v_addr_width downto 0) := "000000000000000001110";
constant val_total0 : std_logic_vector(7 downto 0) := "00001111";
constant val_total1 : std_logic_vector(7 downto 0) := "00000000";
constant val_total2 : std_logic_vector(7 downto 0) := "00000000";
constant val_fifo_treshold : std_logic_vector(7 downto 0) := "00000011";
constant val_hbs : std_logic_vector(7 downto 0) := "00000111";
constant val_hss : std_logic_vector(7 downto 0) := "00001000";
constant val_hse : std_logic_vector(7 downto 0) := "00001001";
constant val_htotal : std_logic_vector(7 downto 0) := "00001010";
constant val_vbs : std_logic_vector(7 downto 0) := "00000001";
constant val_vss : std_logic_vector(7 downto 0) := "00000010";
constant val_vse : std_logic_vector(7 downto 0) := "00000011";
constant val_vtotal : std_logic_vector(7 downto 0) := "00000100";
constant val_pps : std_logic_vector(7 downto 0) := "00000001";
constant val_ws : std_logic_vector(7 downto 0) := "00010010";
-- constant val_bpp : std_logic_vector(7 downto 0) := "00000001";
constant val_bpp : std_logic_vector(7 downto 0) := "00000011";
-- Add your code here ...
procedure chk_val(
signal clk_i: in STD_LOGIC;
signal adr_i: out STD_LOGIC_VECTOR(v_addr_width downto 0);
signal dat_o: in STD_LOGIC_VECTOR(7 downto 0);
signal dat_i: out STD_LOGIC_VECTOR(7 downto 0);
signal we_i: out STD_LOGIC;
signal cyc_i: out std_logic;
signal stb_i: out STD_LOGIC;
signal ack_o: in STD_LOGIC;
constant addr: in STD_LOGIC_VECTOR(v_addr_width downto 0);
constant data: in STD_LOGIC_VECTOR(7 downto 0)
) is
begin
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
adr_i <= addr;
dat_i <= (others => '0');
cyc_i <= '1';
stb_i <= '1';
we_i <= '0';
wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
assert dat_o = data report "Value does not match!" severity ERROR;
adr_i <= (others => '0');
stb_i <= '0';
cyc_i <= '0';
end procedure;
procedure write_val(
signal clk_i: in STD_LOGIC;
signal adr_i: out STD_LOGIC_VECTOR(v_addr_width downto 0);
signal dat_o: in STD_LOGIC_VECTOR(7 downto 0);
signal dat_i: out STD_LOGIC_VECTOR(7 downto 0);
signal we_i: out STD_LOGIC;
signal cyc_i: out std_logic;
signal stb_i: out STD_LOGIC;
signal ack_o: in STD_LOGIC;
constant addr: in STD_LOGIC_VECTOR(v_addr_width downto 0);
constant data: in STD_LOGIC_VECTOR(7 downto 0)
) is
begin
adr_i <= (others => '0');
dat_i <= (others => '0');
stb_i <= '0';
we_i <= '0';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
adr_i <= addr;
dat_i <= data;
cyc_i <= '1';
stb_i <= '1';
we_i <= '1';
wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
adr_i <= (others => '0');
dat_i <= (others => '0');
cyc_i <= '0';
stb_i <= '0';
we_i <= '0';
end procedure;
begin
 
-- Unit Under Test port map
UUT : vga_chip
port map (
clk_i => clk_i,
clk_en => clk_en,
rst_i => rst_i,
dat_i => dat_i,
dat_oi => dat_oi,
dat_o => dat_o,
cyc_i => cyc_i,
ack_o => ack_o,
ack_oi => ack_oi,
we_i => we_i,
vmem_stb_i => vmem_stb_i,
reg_stb_i => reg_stb_i,
adr_i => adr_i,
s_data => s_data,
s_addr => s_addr,
s_oen => s_oen,
s_wrhn => s_wrhn,
s_wrln => s_wrln,
s_cen => s_cen,
h_sync => h_sync,
h_blank => h_blank,
v_sync => v_sync,
v_blank => v_blank,
h_tc => h_tc,
v_tc => v_tc,
blank => blank,
video_out => video_out
);
 
-- Add your stimulus here ...
 
clk_en <= '1';
-- Add your stimulus here ...
clock: process is
begin
wait for 25 ns;
clk_i <= '1';
wait for 25 ns;
clk_i <= '0';
end process;
ack_oi <= '0';
dat_oi <= (others => '0');
setup: process is
begin
we_i <= '0';
reg_stb_i <= '0';
vmem_stb_i <= '0';
rst_i <= '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
rst_i <= '0';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0 ,val_total0);
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total1 ,val_total1);
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2 ,val_total2);
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold ,val_fifo_treshold);
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs ,val_hbs);
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hss ,val_hss);
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse ,val_hse);
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_htotal ,val_htotal);
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs ,val_vbs);
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vss ,val_vss);
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse ,val_vse);
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vtotal ,val_vtotal);
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps ,val_pps);
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws ,val_ws);
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_bpp ,val_bpp);
 
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
 
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0 ,val_total0);
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total1 ,val_total1);
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2 ,val_total2);
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold ,val_fifo_treshold);
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs ,val_hbs);
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hss ,val_hss);
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse ,val_hse);
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_htotal ,val_htotal);
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs ,val_vbs);
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vss ,val_vss);
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse ,val_vse);
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vtotal ,val_vtotal);
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps ,val_pps);
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws ,val_ws);
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_bpp ,val_bpp);
wait;
end process;
 
s_ram: process is
begin
wait on s_data,s_addr,s_oen,s_wrhn,s_wrln,s_cen;
if (s_cen = '0') then
if (s_oen = '0') then
s_data <= s_addr(v_mem_width-1 downto 0);
elsif (s_wrhn = '0' or s_wrln = '0') then
if (s_wrhn = '0') then
else
end if;
else
s_data <= (others => 'Z');
end if;
end if;
end process;
end TB;
 
configuration TB_vga_chip of vga_chip_tb is
for TB
for UUT : vga_chip
use entity work.vga_chip(vga_chip);
end for;
end for;
end TB_vga_chip;
 
/trunk/mem_reader.vhd
8,8 → 8,8
library IEEE;
use IEEE.std_logic_1164.all;
 
library wb_tk;
use wb_tk.technology.all;
library work;
use work.technology.all;
 
entity mem_reader is
generic (
190,7 → 190,7
end if;
v_mem_addr <= pixel_cnt;
end process;
v_mem_rd <= (not video_fifo_full) and (not reset);
v_mem_rd <= not video_fifo_full;
 
-- Pixel data output state machine.
pixel_output: process is
/trunk/vga_chip.vhd
8,27 → 8,6
library IEEE;
use IEEE.std_logic_1164.all;
 
package constants is
constant v_dat_width: positive := 16;
constant v_adr_width : positive := 20;
constant cpu_dat_width: positive := 8;
constant cpu_adr_width: positive := 21;
constant fifo_size: positive := 256;
-- constant addr_diff: integer := log2(cpu_dat_width/v_dat_width);
end constants;
 
library IEEE;
use IEEE.std_logic_1164.all;
 
library wb_vga;
use wb_vga.all;
use wb_vga.constants.all;
 
library wb_tk;
use wb_tk.all;
use wb_tk.technology.all;
 
 
-- same as VGA_CORE but without generics. Suited for post-layout simulation.
entity vga_chip is
port (
37,9 → 16,9
rst_i: in std_logic := '0';
 
-- CPU bus interface
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
dat_i: in std_logic_vector (8-1 downto 0);
dat_oi: in std_logic_vector (8-1 downto 0);
dat_o: out std_logic_vector (8-1 downto 0);
cyc_i: in std_logic;
ack_o: out std_logic;
ack_oi: in std_logic;
46,12 → 25,11
we_i: in std_logic;
vmem_stb_i: in std_logic;
reg_stb_i: in std_logic;
adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
adr_i: in std_logic_vector (20 downto 0);
 
-- video memory SRAM interface
s_data : inout std_logic_vector(v_dat_width-1 downto 0);
s_addr : out std_logic_vector(v_adr_width-1 downto 0);
s_data : inout std_logic_vector((16-1) downto 0);
s_addr : out std_logic_vector((20-1) downto 0);
s_oen : out std_logic;
s_wrhn : out std_logic;
s_wrln : out std_logic;
65,84 → 43,53
h_tc: out std_logic;
v_tc: out std_logic;
blank: out std_logic;
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
video_out: out std_logic_vector (7 downto 0); -- video output binary signal (unused bits are forced to 0)
 
-- TEST SIGNALS
T_v_we_o: out std_logic;
T_v_stb_o: out std_logic;
T_v_ack_i: out std_logic;
T_v_adr_o : out std_logic_vector((20-1) downto 0);
T_v_sel_o : out std_logic_vector((16/8)-1 downto 0);
T_v_dat_o : out std_logic_vector((16-1) downto 0);
T_v_dat_i : out std_logic_vector((16-1) downto 0)
);
end vga_chip;
 
architecture vga_chip of vga_chip is
component wb_async_slave
generic (
width: positive := 16;
addr_width: positive := 20
);
port (
clk_i: in std_logic;
rst_i: in std_logic := '0';
 
-- interface for wait-state generator state-machine
wait_state: in std_logic_vector (3 downto 0);
 
-- interface to wishbone master device
adr_i: in std_logic_vector (addr_width-1 downto 0);
sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
dat_i: in std_logic_vector (width-1 downto 0);
dat_o: out std_logic_vector (width-1 downto 0);
dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
we_i: in std_logic;
stb_i: in std_logic;
ack_o: out std_logic := '0';
ack_oi: in std_logic := '-';
 
-- interface to async slave
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
a_rdn: out std_logic := '1';
a_wrn: out std_logic := '1';
a_cen: out std_logic := '1';
-- byte-enable signals
a_byen: out std_logic_vector ((width/8)-1 downto 0)
);
end component;
 
component vga_core
generic (
-- cannot be overwritten at the moment...
v_dat_width: positive := 16;
v_adr_width : positive := 20;
cpu_dat_width: positive := 8;
cpu_adr_width: positive := 21;
fifo_size: positive := 256
v_mem_width: positive := 16;
fifo_size: positive := 256;
v_addr_width : positive := 20;
bus_width: positive := 8
);
port (
clk_i: in std_logic;
clk_en: in std_logic := '1';
rst_i: in std_logic := '0';
 
-- CPU bus interface
dat_i: in std_logic_vector (bus_width-1 downto 0);
dat_oi: in std_logic_vector (bus_width-1 downto 0);
dat_o: out std_logic_vector (bus_width-1 downto 0);
cyc_i: in std_logic;
we_i: in std_logic;
vmem_stb_i: in std_logic; -- selects video memory
total_stb_i: in std_logic; -- selects total register
ofs_stb_i: in std_logic; -- selects offset register
reg_bank_stb_i: in std_logic; -- selects all other registers (in a single bank)
ack_o: out std_logic;
ack_oi: in std_logic;
adr_i: in std_logic_vector (v_adr_width downto 0);
sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
 
-- video memory interface
v_adr_o: out std_logic_vector (v_adr_width-1 downto 0);
v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0);
v_dat_i: in std_logic_vector (v_dat_width-1 downto 0);
v_dat_o: out std_logic_vector (v_dat_width-1 downto 0);
v_cyc_o: out std_logic;
v_ack_i: in std_logic;
v_we_o: out std_logic;
v_stb_o: out std_logic;
 
we_i: in std_logic;
vmem_stb_i: in std_logic;
reg_stb_i: in std_logic;
adr_i: in std_logic_vector (v_addr_width downto 0);
-- video memory SRAM interface
s_data : inout std_logic_vector((v_mem_width-1) downto 0);
s_addr : out std_logic_vector((v_addr_width-1) downto 0);
s_oen : out std_logic;
s_wrhn : out std_logic;
s_wrln : out std_logic;
s_cen : out std_logic;
-- sync blank and video signal outputs
h_sync: out std_logic;
h_blank: out std_logic;
151,106 → 98,40
h_tc: out std_logic;
v_tc: out std_logic;
blank: out std_logic;
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
video_out: out std_logic_vector (7 downto 0); -- video output binary signal (unused bits are forced to 0)
 
-- TEST SIGNALS
T_v_we_o: out std_logic;
T_v_stb_o: out std_logic;
T_v_ack_i: out std_logic;
T_v_adr_o : out std_logic_vector((v_addr_width-1) downto 0);
T_v_sel_o : out std_logic_vector((v_addr_width/8)-1 downto 0);
T_v_dat_o : out std_logic_vector((v_mem_width-1) downto 0);
T_v_dat_i : out std_logic_vector((v_mem_width-1) downto 0)
);
end component;
 
component wb_out_reg
generic (
width : positive := 8;
bus_width: positive := 8;
offset: integer := 0
);
port (
clk_i: in std_logic;
rst_i: in std_logic;
rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
 
cyc_i: in std_logic := '1';
stb_i: in std_logic;
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');
we_i: in std_logic;
ack_o: out std_logic;
ack_oi: in std_logic := '-';
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0');
dat_i: in std_logic_vector (bus_width-1 downto 0);
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
dat_o: out std_logic_vector (bus_width-1 downto 0);
q: out std_logic_vector (width-1 downto 0)
);
end component;
 
signal total_stb: std_logic;
signal ofs_stb: std_logic;
signal reg_bank_stb: std_logic;
signal ws_stb: std_logic;
signal wait_state: std_logic_vector(3 downto 0);
 
signal v_adr_o: std_logic_vector (v_adr_width-1 downto 0);
signal v_sel_o: std_logic_vector ((v_dat_width/8)-1 downto 0);
signal v_dat_i: std_logic_vector (v_dat_width-1 downto 0);
signal v_dat_o: std_logic_vector (v_dat_width-1 downto 0);
signal v_cyc_o: std_logic;
signal v_ack_i: std_logic;
signal v_we_o: std_logic;
signal v_stb_o: std_logic;
 
signal s_byen : std_logic_vector((v_dat_width/8)-1 downto 0);
signal ws_dat_o: std_logic_vector(cpu_dat_width-1 downto 0);
signal ws_ack_o: std_logic;
signal s_wrn: std_logic;
begin
ws_reg: wb_out_reg
generic map( width => 4, bus_width => cpu_dat_width , offset => 0 )
port map(
stb_i => ws_stb,
q => wait_state,
rst_val => "1111",
dat_oi => dat_oi,
dat_o => ws_dat_o,
ack_oi => ack_oi,
ack_o => ws_ack_o,
adr_i => adr_i(0 downto 0), -- range should be calculated !!!
sel_i => sel_i, cyc_i => cyc_i, we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
 
core : vga_core
generic map (
v_dat_width => v_dat_width,
v_adr_width => v_adr_width,
cpu_dat_width => cpu_dat_width,
cpu_adr_width => cpu_adr_width,
fifo_size => fifo_size
)
Core : vga_core
port map (
clk_i => clk_i,
clk_en => clk_en,
rst_i => rst_i,
-- CPU bus interface
dat_i => dat_i,
dat_oi => dat_oi,
dat_o => dat_o,
cyc_i => cyc_i,
ack_o => ack_o,
ack_oi => ack_oi,
we_i => we_i,
vmem_stb_i => vmem_stb_i,
total_stb_i => total_stb,
ofs_stb_i => ofs_stb,
reg_bank_stb_i => reg_bank_stb,
ack_o => ack_o,
ack_oi => ws_ack_o,
reg_stb_i => reg_stb_i,
adr_i => adr_i,
sel_i => sel_i,
dat_i => dat_i,
dat_oi => ws_dat_o,
dat_o => dat_o,
-- video memory interface
v_adr_o => v_adr_o,
v_sel_o => v_sel_o,
v_dat_i => v_dat_i,
v_dat_o => v_dat_o,
v_cyc_o => v_cyc_o,
v_ack_i => v_ack_i,
v_we_o => v_we_o,
v_stb_o => v_stb_o,
 
s_data => s_data,
s_addr => s_addr,
s_oen => s_oen,
s_wrhn => s_wrhn,
s_wrln => s_wrln,
s_cen => s_cen,
h_sync => h_sync,
h_blank => h_blank,
v_sync => v_sync,
258,61 → 139,14
h_tc => h_tc,
v_tc => v_tc,
blank => blank,
video_out => video_out
video_out => video_out,
 
T_v_we_o => T_v_we_o,
T_v_stb_o => T_v_stb_o,
T_v_ack_i => T_v_ack_i,
T_v_adr_o => T_v_adr_o,
T_v_sel_o => T_v_sel_o,
T_v_dat_o => T_v_dat_o,
T_v_dat_i => T_v_dat_i
);
 
mem_driver: wb_async_slave
generic map (width => v_dat_width, addr_width => v_adr_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
 
wait_state => wait_state,
 
adr_i => v_adr_o,
sel_i => v_sel_o,
dat_o => v_dat_i,
dat_i => v_dat_o,
-- dat_oi => (others => '0'),
we_i => v_we_o,
stb_i => v_stb_o,
ack_o => v_ack_i,
ack_oi => '0',
 
a_data => s_data,
a_addr => s_addr,
a_rdn => s_oen,
a_wrn => s_wrn,
a_cen => s_cen,
a_byen => s_byen
);
 
s_wrln <= s_wrn or s_byen(0);
s_wrhn <= s_wrn or s_byen(1);
 
 
addr_decoder: process is
begin
wait on reg_stb_i, adr_i;
 
total_stb <= '0';
ofs_stb <= '0';
reg_bank_stb <= '0';
ws_stb <= '0';
 
if (reg_stb_i = '1') then
case (adr_i(4)) is
when '0' =>
case (adr_i(3 downto 2)) is
when "00" => total_stb <= '1';
when "01" => ofs_stb <= '1';
when "10" => ws_stb <= '1';
when others =>
end case;
when '1' => reg_bank_stb <= '1';
when others =>
end case;
end if;
end process;
 
end vga_chip;
/trunk/sync_gen.vhd
10,8 → 10,8
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
library wb_tk;
use wb_tk.technology.all;
library work;
use work.technology.all;
 
entity sync_gen is
port (
/trunk/vga_core.vhd
8,21 → 8,17
library IEEE;
use IEEE.std_logic_1164.all;
 
library wb_tk;
use wb_tk.all;
use wb_tk.technology.all;
library work;
--use wb_tk.all;
use work.wb_tk.all;
 
library wb_vga;
use wb_vga.all;
 
entity vga_core is
generic (
-- cannot be overwritten at the moment...
v_dat_width: positive := 16;
v_adr_width : positive := 20;
cpu_dat_width: positive := 8;
cpu_adr_width: positive := 21;
fifo_size: positive := 256
v_mem_width: positive := 16;
fifo_size: positive := 256;
v_addr_width : positive := 20;
bus_width: positive := 8
);
port (
clk_i: in std_logic;
30,29 → 26,24
rst_i: in std_logic := '0';
 
-- CPU bus interface
dat_i: in std_logic_vector (bus_width-1 downto 0);
dat_oi: in std_logic_vector (bus_width-1 downto 0);
dat_o: out std_logic_vector (bus_width-1 downto 0);
cyc_i: in std_logic;
we_i: in std_logic;
vmem_stb_i: in std_logic; -- selects video memory
total_stb_i: in std_logic; -- selects total register
ofs_stb_i: in std_logic; -- selects offset register
reg_bank_stb_i: in std_logic; -- selects all other registers (in a single bank)
ack_o: out std_logic;
ack_oi: in std_logic;
adr_i: in std_logic_vector (v_adr_width downto 0);
sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
we_i: in std_logic;
vmem_stb_i: in std_logic;
reg_stb_i: in std_logic;
adr_i: in std_logic_vector (v_addr_width downto 0);
 
-- video memory interface
v_adr_o: out std_logic_vector (v_adr_width-1 downto 0);
v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0);
v_dat_i: in std_logic_vector (v_dat_width-1 downto 0);
v_dat_o: out std_logic_vector (v_dat_width-1 downto 0);
v_cyc_o: out std_logic;
v_ack_i: in std_logic;
v_we_o: out std_logic;
v_stb_o: out std_logic;
-- video memory SRAM interface
s_data : inout std_logic_vector((v_mem_width-1) downto 0);
s_addr : out std_logic_vector((v_addr_width-1) downto 0);
s_oen : out std_logic;
s_wrhn : out std_logic;
s_wrln : out std_logic;
s_cen : out std_logic;
 
-- sync blank and video signal outputs
h_sync: out std_logic;
62,7 → 53,16
h_tc: out std_logic;
v_tc: out std_logic;
blank: out std_logic;
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
video_out: out std_logic_vector (7 downto 0); -- video output binary signal (unused bits are forced to 0)
 
-- TEST SIGNALS
T_v_we_o: out std_logic;
T_v_stb_o: out std_logic;
T_v_ack_i: out std_logic;
T_v_adr_o : out std_logic_vector((v_addr_width-1) downto 0);
T_v_sel_o : out std_logic_vector((v_addr_width/8)-1 downto 0);
T_v_dat_o : out std_logic_vector((v_mem_width-1) downto 0);
T_v_dat_i : out std_logic_vector((v_mem_width-1) downto 0)
);
end vga_core;
 
113,6 → 113,40
);
end component video_engine;
 
component wb_async_slave
generic (
width: positive := 16;
addr_width: positive := 20
);
port (
clk_i: in std_logic;
rst_i: in std_logic := '0';
-- interface for wait-state generator state-machine
wait_state: in std_logic_vector (3 downto 0);
 
-- interface to wishbone master device
adr_i: in std_logic_vector (addr_width-1 downto 0);
sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
dat_i: in std_logic_vector (width-1 downto 0);
dat_o: out std_logic_vector (width-1 downto 0);
dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
we_i: in std_logic;
stb_i: in std_logic;
ack_o: out std_logic := '0';
ack_oi: in std_logic := '-';
-- interface to async slave
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
a_rdn: out std_logic := '1';
a_wrn: out std_logic := '1';
a_cen: out std_logic := '1';
-- byte-enable signals
a_byen: out std_logic_vector ((addr_width/8)-1 downto 0)
);
end component;
 
component wb_arbiter
port (
-- clk: in std_logic;
156,36 → 190,32
end component;
 
component wb_out_reg
generic (
width : positive := 8;
bus_width: positive := 8;
offset: integer := 0
);
port (
clk_i: in std_logic;
rst_i: in std_logic;
rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
generic (
width : positive := 8;
bus_width: positive := 8;
offset: integer := 0
);
port (
clk_i: in std_logic;
rst_i: in std_logic;
rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
 
cyc_i: in std_logic := '1';
stb_i: in std_logic;
sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');
we_i: in std_logic;
ack_o: out std_logic;
ack_oi: in std_logic := '-';
adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0');
dat_i: in std_logic_vector (bus_width-1 downto 0);
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
dat_o: out std_logic_vector (bus_width-1 downto 0);
q: out std_logic_vector (width-1 downto 0)
);
dat_i: in std_logic_vector (bus_width-1 downto 0);
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
dat_o: out std_logic_vector (bus_width-1 downto 0);
q: out std_logic_vector (width-1 downto 0);
we_i: in std_logic;
stb_i: in std_logic;
ack_o: out std_logic;
ack_oi: in std_logic := '-'
);
end component;
 
component wb_bus_resize
component wb_bus_upsize
generic (
m_bus_width: positive := 8; -- master bus width
m_addr_width: positive := 21; -- master bus width
s_bus_width: positive := 16; -- slave bus width
s_addr_width: positive := 20; -- master bus width
little_endien: boolean := true -- if set to false, big endien
);
port (
209,7 → 239,7
m_stb_i: in std_logic;
 
-- Slave bus interface
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);
s_adr_o: out std_logic_vector (m_addr_width-2 downto 0);
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
222,54 → 252,108
);
end component;
 
signal total: std_logic_vector(v_adr_width-1 downto 0);
signal offset: std_logic_vector(v_adr_width-1 downto 0);
signal reg_bank: std_logic_vector((8*12)-1 downto 0);
signal reset_core: std_logic_vector(0 downto 0);
signal total: std_logic_vector(v_addr_width-1 downto 0);
signal fifo_treshold: std_logic_vector(7 downto 0);
signal bpp: std_logic_vector(1 downto 0);
signal multi_scan: std_logic_vector(1 downto 0);
signal hbs: std_logic_vector(7 downto 0);
signal hss: std_logic_vector(7 downto 0);
signal hse: std_logic_vector(7 downto 0);
signal htotal: std_logic_vector(7 downto 0);
signal vbs: std_logic_vector(7 downto 0);
signal vss: std_logic_vector(7 downto 0);
signal vse: std_logic_vector(7 downto 0);
signal vtotal: std_logic_vector(7 downto 0);
signal pps: std_logic_vector(7 downto 0);
signal wait_state: std_logic_vector (3 downto 0);
signal sync_pol: std_logic_vector (3 downto 0);
 
alias fifo_treshold: std_logic_vector(7 downto 0) is reg_bank( 7 downto 0);
alias bpp: std_logic_vector(1 downto 0) is reg_bank( 9 downto 8);
alias multi_scan: std_logic_vector(1 downto 0) is reg_bank(13 downto 12);
alias hbs: std_logic_vector(7 downto 0) is reg_bank(23 downto 16);
alias hss: std_logic_vector(7 downto 0) is reg_bank(31 downto 24);
alias hse: std_logic_vector(7 downto 0) is reg_bank(39 downto 32);
alias htotal: std_logic_vector(7 downto 0) is reg_bank(47 downto 40);
alias vbs: std_logic_vector(7 downto 0) is reg_bank(55 downto 48);
alias vss: std_logic_vector(7 downto 0) is reg_bank(63 downto 56);
alias vse: std_logic_vector(7 downto 0) is reg_bank(71 downto 64);
alias vtotal: std_logic_vector(7 downto 0) is reg_bank(79 downto 72);
alias pps: std_logic_vector(7 downto 0) is reg_bank(87 downto 80);
alias sync_pol: std_logic_vector (3 downto 0) is reg_bank(91 downto 88);
alias reset_core: std_logic_vector(0 downto 0) is reg_bank(95 downto 95);
signal reset_core_do: std_logic_vector(bus_width-1 downto 0);
signal total0_do: std_logic_vector(bus_width-1 downto 0);
signal total1_do: std_logic_vector(bus_width-1 downto 0);
signal total2_do: std_logic_vector(bus_width-1 downto 0);
signal fifo_treshold_do: std_logic_vector(bus_width-1 downto 0);
signal bpp_do: std_logic_vector(bus_width-1 downto 0);
signal multi_scan_do: std_logic_vector(bus_width-1 downto 0);
signal hbs_do: std_logic_vector(bus_width-1 downto 0);
signal hss_do: std_logic_vector(bus_width-1 downto 0);
signal hse_do: std_logic_vector(bus_width-1 downto 0);
signal htotal_do: std_logic_vector(bus_width-1 downto 0);
signal vbs_do: std_logic_vector(bus_width-1 downto 0);
signal vss_do: std_logic_vector(bus_width-1 downto 0);
signal vse_do: std_logic_vector(bus_width-1 downto 0);
signal vtotal_do: std_logic_vector(bus_width-1 downto 0);
signal pps_do: std_logic_vector(bus_width-1 downto 0);
signal wait_state_do: std_logic_vector(bus_width-1 downto 0);
signal vm_do: std_logic_vector(bus_width-1 downto 0);
 
signal reg_bank_do: std_logic_vector(cpu_dat_width-1 downto 0);
signal total_do: std_logic_vector(cpu_dat_width-1 downto 0);
signal ofs_do: std_logic_vector(cpu_dat_width-1 downto 0);
signal vm_do: std_logic_vector(cpu_dat_width-1 downto 0);
signal reset_core_sel: std_logic;
signal total0_sel: std_logic;
signal total1_sel: std_logic;
signal total2_sel: std_logic;
signal fifo_treshold_sel: std_logic;
signal bpp_sel: std_logic;
signal multi_scan_sel: std_logic;
signal hbs_sel: std_logic;
signal hss_sel: std_logic;
signal hse_sel: std_logic;
signal htotal_sel: std_logic;
signal vbs_sel: std_logic;
signal vss_sel: std_logic;
signal vse_sel: std_logic;
signal vtotal_sel: std_logic;
signal pps_sel: std_logic;
signal wait_state_sel: std_logic;
signal sync_pol_sel: std_logic;
 
signal reg_bank_ack: std_logic;
signal total_ack: std_logic;
signal ofs_ack: std_logic;
signal reset_core_ack: std_logic;
signal total0_ack: std_logic;
signal total1_ack: std_logic;
signal total2_ack: std_logic;
signal fifo_treshold_ack: std_logic;
signal bpp_ack: std_logic;
signal multi_scan_ack: std_logic;
signal hbs_ack: std_logic;
signal hss_ack: std_logic;
signal hse_ack: std_logic;
signal htotal_ack: std_logic;
signal vbs_ack: std_logic;
signal vss_ack: std_logic;
signal vse_ack: std_logic;
signal vtotal_ack: std_logic;
signal pps_ack: std_logic;
signal wait_state_ack: std_logic;
signal vm_ack: std_logic;
 
signal a_adr_o : std_logic_vector((v_adr_width-1) downto 0);
signal a_sel_o : std_logic_vector((v_adr_width/8)-1 downto 0);
signal a_dat_o : std_logic_vector((v_dat_width-1) downto 0);
signal a_dat_i : std_logic_vector((v_dat_width-1) downto 0);
signal a_adr_o : std_logic_vector((v_addr_width-1) downto 0);
signal a_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
signal a_dat_o : std_logic_vector((v_mem_width-1) downto 0);
signal a_dat_i : std_logic_vector((v_mem_width-1) downto 0);
signal a_we_o : std_logic;
signal a_stb_o : std_logic;
signal a_cyc_o : std_logic;
signal a_ack_i : std_logic;
 
signal b_adr_o : std_logic_vector((v_adr_width-1) downto 0);
signal b_sel_o : std_logic_vector((v_adr_width/8)-1 downto 0);
-- signal b_dat_o : std_logic_vector((v_dat_width-1) downto 0);
signal b_dat_i : std_logic_vector((v_dat_width-1) downto 0);
signal b_adr_o : std_logic_vector((v_addr_width-1) downto 0);
signal b_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
-- signal b_dat_o : std_logic_vector((v_mem_width-1) downto 0);
signal b_dat_i : std_logic_vector((v_mem_width-1) downto 0);
signal b_stb_o : std_logic;
-- signal b_we_o : std_logic;
-- signal b_cyc_o : std_logic;
signal b_ack_i : std_logic;
 
signal v_we_o: std_logic;
signal v_stb_o: std_logic;
signal v_ack_i: std_logic;
signal v_adr_o : std_logic_vector((v_addr_width-1) downto 0);
signal v_sel_o : std_logic_vector((v_addr_width/8)-1 downto 0);
signal v_dat_o : std_logic_vector((v_mem_width-1) downto 0);
signal v_dat_i : std_logic_vector((v_mem_width-1) downto 0);
signal s_byen : std_logic_vector((v_addr_width/8)-1 downto 0);
 
signal mux_signal: std_logic;
 
signal high_prior: std_logic;
282,54 → 366,212
signal i_v_blank: std_logic;
 
signal s_wrn : std_logic;
constant v_adr_zero : std_logic_vector(v_adr_width-1 downto 0) := (others => '0');
constant reg_bank_rst_val: std_logic_vector(reg_bank'Range) := (others => '0');
 
begin
-- map all registers:
-- adr_i: in std_logic_vector (max(log2((width+offset+bus_width-1)/bus_width)-1,0) downto 0) := (others => '0');
 
reg_bank_reg: wb_out_reg
generic map( width => reg_bank'HIGH+1, bus_width => cpu_dat_width , offset => 0 )
reset_core_reg: wb_out_reg
generic map( width => 1, bus_width => bus_width , offset => 4 )
port map(
stb_i => reg_bank_stb_i,
q => reg_bank,
rst_val => reg_bank_rst_val,
stb_i => reset_core_sel,
q => reset_core,
rst_val => "1",
dat_oi => vm_do,
dat_o => reg_bank_do,
dat_o => reset_core_do,
ack_oi => vm_ack,
ack_o => reg_bank_ack,
adr_i => adr_i(3 downto 0), -- range should be calculated !!!
sel_i => sel_i, cyc_i => cyc_i, we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
ofs_reg: wb_out_reg
generic map( width => v_adr_width, bus_width => cpu_dat_width , offset => 0 )
ack_o => reset_core_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
total0_reg: wb_out_reg
generic map( width => 8, bus_width => bus_width , offset => 0 )
port map(
stb_i => ofs_stb_i,
q => offset,
rst_val => v_adr_zero,
dat_oi => reg_bank_do,
dat_o => ofs_do,
ack_oi => reg_bank_ack,
ack_o => ofs_ack,
adr_i => adr_i(1 downto 0), -- range should be calculated !!!
sel_i => sel_i, cyc_i => cyc_i, we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
total_reg: wb_out_reg
generic map( width => v_adr_width, bus_width => cpu_dat_width , offset => 0 )
stb_i => total0_sel,
q => total(7 downto 0),
rst_val => "00000000",
dat_oi => reset_core_do,
dat_o => total0_do,
ack_oi => reset_core_ack,
ack_o => total0_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
total1_reg: wb_out_reg
generic map( width => 8, bus_width => bus_width , offset => 0 )
port map(
stb_i => total_stb_i,
q => total,
rst_val => v_adr_zero,
dat_oi => ofs_do,
stb_i => total1_sel,
q => total(15 downto 8),
rst_val => "00000000",
dat_oi => total0_do,
dat_o => total1_do,
ack_oi => total0_ack,
ack_o => total1_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
total2_reg: wb_out_reg
generic map( width => 4, bus_width => bus_width , offset => 0 )
port map(
stb_i => total2_sel,
q => total(19 downto 16),
rst_val => "0000",
dat_oi => total1_do,
dat_o => total2_do,
ack_oi => total1_ack,
ack_o => total2_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
fifo_treshold_reg: wb_out_reg
generic map( width => 8, bus_width => bus_width , offset => 0 )
port map(
stb_i => fifo_treshold_sel,
q => fifo_treshold,
rst_val => "00000000",
dat_oi => total2_do,
dat_o => fifo_treshold_do,
ack_oi => total2_ack,
ack_o => fifo_treshold_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
bpp_reg: wb_out_reg
generic map( width => 2, bus_width => bus_width , offset => 0 )
port map(
stb_i => bpp_sel,
q => bpp,
rst_val => "00",
dat_oi => fifo_treshold_do,
dat_o => bpp_do,
ack_oi => fifo_treshold_ack,
ack_o => bpp_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
multi_scan_reg: wb_out_reg
generic map( width => 2, bus_width => bus_width , offset => 2 )
port map(
stb_i => multi_scan_sel,
q => multi_scan,
rst_val => "00",
dat_oi => bpp_do,
dat_o => multi_scan_do,
ack_oi => bpp_ack,
ack_o => multi_scan_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
hbs_reg: wb_out_reg
generic map( width => 8, bus_width => bus_width , offset => 0 )
port map(
stb_i => hbs_sel,
q => hbs,
rst_val => "00000000",
dat_oi => multi_scan_do,
dat_o => hbs_do,
ack_oi => multi_scan_ack,
ack_o => hbs_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
hss_reg: wb_out_reg
generic map( width => 8, bus_width => bus_width , offset => 0 )
port map(
stb_i => hss_sel,
q => hss,
rst_val => "00000000",
dat_oi => hbs_do,
dat_o => hss_do,
ack_oi => hbs_ack,
ack_o => hss_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
hse_reg: wb_out_reg
generic map( width => 8, bus_width => bus_width , offset => 0 )
port map(
stb_i => hse_sel,
q => hse,
rst_val => "00000000",
dat_oi => hss_do,
dat_o => hse_do,
ack_oi => hss_ack,
ack_o => hse_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
htotal_reg: wb_out_reg
generic map( width => 8, bus_width => bus_width , offset => 0 )
port map(
stb_i => htotal_sel,
q => htotal,
rst_val => "00000000",
dat_oi => hse_do,
dat_o => htotal_do,
ack_oi => hse_ack,
ack_o => htotal_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
vbs_reg: wb_out_reg
generic map( width => 8, bus_width => bus_width , offset => 0 )
port map(
stb_i => vbs_sel,
q => vbs,
rst_val => "00000000",
dat_oi => htotal_do,
dat_o => vbs_do,
ack_oi => htotal_ack,
ack_o => vbs_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
vss_reg: wb_out_reg
generic map( width => 8, bus_width => bus_width , offset => 0 )
port map(
stb_i => vss_sel,
q => vss,
rst_val => "00000000",
dat_oi => vbs_do,
dat_o => vss_do,
ack_oi => vbs_ack,
ack_o => vss_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
vse_reg: wb_out_reg
generic map( width => 8, bus_width => bus_width , offset => 0 )
port map(
stb_i => vse_sel,
q => vse,
rst_val => "00000000",
dat_oi => vss_do,
dat_o => vse_do,
ack_oi => vss_ack,
ack_o => vse_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
vtotal_reg: wb_out_reg
generic map( width => 8, bus_width => bus_width , offset => 0 )
port map(
stb_i => vtotal_sel,
q => vtotal,
rst_val => "00000000",
dat_oi => vse_do,
dat_o => vtotal_do,
ack_oi => vse_ack,
ack_o => vtotal_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
pps_reg: wb_out_reg
generic map( width => 8, bus_width => bus_width , offset => 0 )
port map(
stb_i => pps_sel,
q => pps,
rst_val => "00000000",
dat_oi => vtotal_do,
dat_o => pps_do,
ack_oi => vtotal_ack,
ack_o => pps_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
wait_state_reg: wb_out_reg
generic map( width => 4, bus_width => bus_width , offset => 0 )
port map(
stb_i => wait_state_sel,
q => wait_state,
rst_val => "0000",
dat_oi => pps_do,
dat_o => wait_state_do,
ack_oi => pps_ack,
ack_o => wait_state_ack,
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
sync_pol_reg: wb_out_reg
generic map( width => 4, bus_width => bus_width , offset => 4 )
port map(
stb_i => sync_pol_sel,
q => sync_pol,
rst_val => "0000",
dat_oi => wait_state_do,
dat_o => dat_o, -- END OF THE CHAIN
ack_oi => ofs_ack,
ack_oi => wait_state_ack,
ack_o => ack_o, -- END OF THE CHAIN
adr_i => adr_i(1 downto 0), -- range should be calculated !!!
sel_i => sel_i, cyc_i => cyc_i, we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
 
reset_engine <= rst_i or not reset_core(0);
reset_engine <= rst_i or reset_core(0);
 
v_e: video_engine
generic map ( v_mem_width => v_dat_width, v_addr_width => v_adr_width, fifo_size => fifo_size, dual_scan_fifo_size => fifo_size )
generic map ( v_mem_width => v_mem_width, v_addr_width => v_addr_width, fifo_size => fifo_size, dual_scan_fifo_size => fifo_size )
port map (
clk => clk_i,
clk_en => clk_en,
370,16 → 612,16
h_blank <= i_h_blank;-- xor sync_pol(2);
v_blank <= i_v_blank;-- xor sync_pol(3);
 
resize: wb_bus_resize
resize: wb_bus_upsize
generic map (
m_bus_width => cpu_dat_width, s_bus_width => v_dat_width, m_addr_width => cpu_adr_width
m_bus_width => bus_width, s_bus_width => v_mem_width, m_addr_width => v_addr_width+1
)
port map (
m_adr_i => adr_i,
m_cyc_i => cyc_i,
m_sel_i => sel_i,
-- m_sel_i => (others => '1'),
m_dat_i => dat_i,
m_dat_oi => dat_oi, -- Beginning of the chain
m_cyc_i => cyc_i,
m_dat_o => vm_do,
m_ack_o => vm_ack,
m_ack_oi => ack_oi, -- Beginning of the chain
411,12 → 653,11
b_cyc_i => b_stb_o,
b_stb_i => b_stb_o,
b_ack_o => b_ack_i,
b_ack_oi => '0',
b_ack_oi => '0', -- maybe not needed at all
 
s_we_o => v_we_o,
s_stb_o => v_stb_o,
s_ack_i => v_ack_i,
s_cyc_o => v_cyc_o,
 
mux_signal => mux_signal,
443,5 → 684,91
end if;
end process;
 
mem_driver: wb_async_slave
generic map (width => v_mem_width, addr_width => v_addr_width)
port map (
clk_i => clk_i,
rst_i => reset_engine,
 
wait_state => wait_state,
adr_i => v_adr_o,
sel_i => v_sel_o,
dat_o => v_dat_i,
dat_i => v_dat_o,
-- dat_oi => (others => '0'), -- may not be needed
we_i => v_we_o,
stb_i => v_stb_o,
ack_o => v_ack_i,
ack_oi => '0', -- may not be needed
 
a_data => s_data,
a_addr => s_addr,
a_rdn => s_oen,
a_wrn => s_wrn,
a_cen => s_cen,
a_byen => s_byen
);
 
s_wrln <= s_wrn or s_byen(0);
s_wrhn <= s_wrn or s_byen(1);
 
addr_decoder: process is
begin
wait on reg_stb_i, adr_i;
 
reset_core_sel <= '0';
total0_sel <= '0';
total1_sel <= '0';
total2_sel <= '0';
fifo_treshold_sel <= '0';
bpp_sel <= '0';
multi_scan_sel <= '0';
hbs_sel <= '0';
hss_sel <= '0';
hse_sel <= '0';
htotal_sel <= '0';
vbs_sel <= '0';
vss_sel <= '0';
vse_sel <= '0';
vtotal_sel <= '0';
pps_sel <= '0';
wait_state_sel <= '0';
sync_pol_sel <= '0';
 
if (reg_stb_i = '1') then
case (adr_i(4 downto 0)) is
when "00000" => total0_sel <= '1';
when "00001" => total1_sel <= '1';
when "00010" => total2_sel <= '1';
when "00011" => fifo_treshold_sel <= '1';
 
when "00100" => hbs_sel <= '1';
when "00101" => hss_sel <= '1';
when "00110" => hse_sel <= '1';
when "00111" => htotal_sel <= '1';
 
when "01000" => vbs_sel <= '1';
when "01001" => vss_sel <= '1';
when "01010" => vse_sel <= '1';
when "01011" => vtotal_sel <= '1';
 
when "01100" => pps_sel <= '1';
when "01101" => wait_state_sel <= '1'; sync_pol_sel <= '1';
when "01110" => bpp_sel <= '1'; multi_scan_sel <= '1'; reset_core_sel <= '1';
when others =>
end case;
end if;
end process;
 
-- TEST SIGNALS
T_v_we_o <= v_we_o;
T_v_stb_o <= v_stb_o;
T_v_ack_i <= v_ack_i;
T_v_adr_o <= v_adr_o;
T_v_sel_o <= v_sel_o;
T_v_dat_o <= v_dat_o;
T_v_dat_i <= v_dat_i;
end vga_core;
 
/trunk/video_engine.vhd
8,8 → 8,8
library IEEE;
use IEEE.std_logic_1164.all;
 
library wb_tk;
use wb_tk.technology.all;
library work;
use work.technology.all;
 
entity video_engine is
generic (

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