OpenCores
URL https://opencores.org/ocsvn/wb_vga/wb_vga/trunk

Subversion Repositories wb_vga

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 5 to Rev 6
    ↔ Reverse comparison
  •

Rev 5 → Rev 6

/trunk/wb_tk.vhd File deleted
/trunk/TestBench/vga_core_v2_TB.vhd
0,0 → 1,459
library ieee,exemplar;
use ieee.std_logic_1164.all;
use exemplar.exemplar_1164.all;
use ieee.std_logic_unsigned.all;
library synopsys;
use synopsys.std_logic_arith.all;
 
library wb_tk;
use wb_tk.wb_test.all;
 
library wb_vga;
use wb_vga.all;
use wb_vga.constants.all;
 
entity vga_core_v2_tb is
generic (
v_dat_width: positive := 16;
v_adr_width : positive := 12;
cpu_dat_width: positive := 8;
cpu_adr_width: positive := 12;
-- cpu_dat_width: positive := 16;
-- cpu_adr_width: positive := 11;
fifo_size: positive := 256;
accel_size: positive := 9;
v_pal_size: positive := 8;
v_pal_width: positive := 16
);
end vga_core_v2_tb;
 
architecture TB of vga_core_v2_tb is
-- Component declaration of the tested unit
component vga_core_v2
generic (
v_dat_width: positive := v_dat_width;
v_adr_width : positive := v_adr_width;
cpu_dat_width: positive := cpu_dat_width;
cpu_adr_width: positive := cpu_adr_width;
fifo_size: positive := fifo_size;
accel_size: positive := accel_size;
v_pal_size: positive := v_pal_size;
v_pal_width: positive := v_pal_width
);
port (
clk_i: in std_logic;
clk_en: in std_logic := '1';
rst_i: in std_logic := '0';
 
-- CPU bus interface
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
cyc_i: in std_logic;
ack_o: out std_logic;
ack_oi: in std_logic;
err_o: out std_logic;
err_oi: in std_logic;
we_i: in std_logic;
accel_stb_i: in std_logic;
pal_stb_i: in std_logic;
reg_stb_i: in std_logic;
adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
 
-- video memory interface
v_adr_o: out std_logic_vector (v_adr_width-1 downto 0);
v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0);
v_dat_i: in std_logic_vector (v_dat_width-1 downto 0);
v_dat_o: out std_logic_vector (v_dat_width-1 downto 0);
v_cyc_o: out std_logic;
v_ack_i: in std_logic;
v_we_o: out std_logic;
v_stb_o: out std_logic;
 
-- sync blank and video signal outputs
h_sync: out std_logic;
h_blank: out std_logic;
v_sync: out std_logic;
v_blank: out std_logic;
h_tc: out std_logic;
v_tc: out std_logic;
blank: out std_logic;
video_out: out std_logic_vector (v_pal_size-1 downto 0); -- video output binary signal (unused bits are forced to 0)
true_color_out: out std_logic_vector (v_pal_width-1 downto 0) -- true-color video output
);
end component;
 
signal clk_i: std_logic;
signal clk_en: std_logic := '1';
signal rst_i: std_logic := '0';
 
-- CPU bus interface
signal dat_i: std_logic_vector (cpu_dat_width-1 downto 0);
signal dat_oi: std_logic_vector (cpu_dat_width-1 downto 0);
signal dat_o: std_logic_vector (cpu_dat_width-1 downto 0);
signal cyc_i: std_logic;
signal ack_o: std_logic;
signal ack_oi: std_logic;
signal err_o: std_logic;
signal err_oi: std_logic;
signal we_i: std_logic;
signal accel_stb_i: std_logic;
signal pal_stb_i: std_logic;
signal reg_stb_i: std_logic;
signal adr_i: std_logic_vector (cpu_adr_width-1 downto 0);
signal sel_i: std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
 
-- video memory interface
signal v_adr_o: std_logic_vector (v_adr_width-1 downto 0);
signal v_sel_o: std_logic_vector ((v_dat_width/8)-1 downto 0);
signal v_dat_i: std_logic_vector (v_dat_width-1 downto 0);
signal v_dat_o: std_logic_vector (v_dat_width-1 downto 0);
signal v_cyc_o: std_logic;
signal v_ack_i: std_logic;
signal v_we_o: std_logic;
signal v_stb_o: std_logic;
 
-- sync blank and video signal outputs
signal h_sync: std_logic;
signal h_blank: std_logic;
signal v_sync: std_logic;
signal v_blank: std_logic;
signal h_tc: std_logic;
signal v_tc: std_logic;
signal blank: std_logic;
signal video_out: std_logic_vector (v_pal_size-1 downto 0); -- video output binary signal (unused bits are forced to 0)
signal true_color_out: std_logic_vector (v_pal_width-1 downto 0); -- true-color video output
 
constant reg_total0 : integer := 0;
constant reg_total1 : integer := 1;
constant reg_total2 : integer := 2;
constant reg_total3 : integer := 3;
constant reg_ofs0 : integer := 4;
constant reg_ofs1 : integer := 5;
constant reg_ofs2 : integer := 6;
constant reg_ofs3 : integer := 7;
 
constant reg_fifo_treshold : integer := 16;
constant reg_bpp : integer := 17;
constant reg_hbs : integer := 18;
constant reg_hss : integer := 19;
constant reg_hse : integer := 20;
constant reg_htotal : integer := 21;
constant reg_vbs : integer := 22;
constant reg_vss : integer := 23;
constant reg_vse : integer := 24;
constant reg_vtotal : integer := 25;
constant reg_pps : integer := 26;
constant reg_sync_pol : integer := 27;
 
constant reg_ws : integer := 32;
constant reg_cur : integer := 40;
constant reg_ext : integer := 44;
 
constant val_total0 : std_logic_vector(7 downto 0) := "11111111";
constant val_total1 : std_logic_vector(7 downto 0) := "00000000";
constant val_total2 : std_logic_vector(7 downto 0) := "00000000";
constant val_total3 : std_logic_vector(7 downto 0) := "00000000";
constant val_ofs0 : std_logic_vector(7 downto 0) := "00000000";
constant val_ofs1 : std_logic_vector(7 downto 0) := "00000000";
constant val_ofs2 : std_logic_vector(7 downto 0) := "00000000";
constant val_ofs3 : std_logic_vector(7 downto 0) := "00000000";
constant val_fifo_treshold : std_logic_vector(7 downto 0) := "00000011";
constant val_bpp : std_logic_vector(7 downto 0) := "00000011";
constant val_hbs : std_logic_vector(7 downto 0) := "00000111";
constant val_hss : std_logic_vector(7 downto 0) := "00001000";
constant val_hse : std_logic_vector(7 downto 0) := "00001001";
constant val_htotal : std_logic_vector(7 downto 0) := "00001010";
constant val_vbs : std_logic_vector(7 downto 0) := "00000001";
constant val_vss : std_logic_vector(7 downto 0) := "00000010";
constant val_vse : std_logic_vector(7 downto 0) := "00000011";
constant val_vtotal : std_logic_vector(7 downto 0) := "00000100";
constant val_pps : std_logic_vector(7 downto 0) := "00000001";
constant val_sync_pol : std_logic_vector(7 downto 0) := "10000000";
constant val_ws : std_logic_vector(7 downto 0) := "00000010";
 
type data_array is array (integer range <>) of std_logic_vector(v_dat_width-1 downto 0);-- Memory Type
signal mem_data : data_array(0 to (2** v_adr_width-1) ); -- Local data
begin
 
UUT : vga_core_v2
port map (
clk_i =>clk_i,
clk_en =>clk_en,
rst_i =>rst_i,
 
-- CPU bus interface
dat_i =>dat_i,
dat_oi =>dat_oi,
dat_o =>dat_o,
cyc_i =>cyc_i,
ack_o =>ack_o,
ack_oi =>ack_oi,
err_o =>err_o,
err_oi =>err_oi,
we_i =>we_i,
accel_stb_i =>accel_stb_i,
pal_stb_i =>pal_stb_i,
reg_stb_i =>reg_stb_i,
adr_i =>adr_i,
sel_i =>sel_i,
 
-- video memory interface
v_adr_o =>v_adr_o,
v_sel_o =>v_sel_o,
v_dat_i =>v_dat_i,
v_dat_o =>v_dat_o,
v_cyc_o =>v_cyc_o,
v_ack_i =>v_ack_i,
v_we_o =>v_we_o,
v_stb_o =>v_stb_o,
 
-- sync blank and video outputs
h_sync =>h_sync,
h_blank =>h_blank,
v_sync =>v_sync,
v_blank =>v_blank,
h_tc =>h_tc,
v_tc =>v_tc,
blank =>blank,
video_out =>video_out,
true_color_out=>true_color_out
);
 
-- Add your stimulus here ...
 
clk_en <= '1';
-- Add your stimulus here ...
clock: process is
begin
wait for 25 ns;
clk_i <= '1';
wait for 25 ns;
clk_i <= '0';
end process;
 
ack_oi <= '1';
err_oi <= '1';
dat_oi <= (others => '0');
 
setup: process is
begin
sel_i <= (others => '1');
we_i <= '0';
reg_stb_i <= '0';
accel_stb_i <= '0';
pal_stb_i <= '0';
cyc_i <= '0';
rst_i <= '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
rst_i <= '0';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
 
if (cpu_dat_width = 8) then
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0 ,val_total0);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total1 ,val_total1);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2 ,val_total2);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total3 ,val_total3);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0 ,val_ofs0);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs1 ,val_ofs1);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs2 ,val_ofs2);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs3 ,val_ofs3);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws ,val_ws);
 
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
 
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold ,val_fifo_treshold);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_bpp ,val_bpp);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs ,val_hbs);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hss ,val_hss);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse ,val_hse);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_htotal ,val_htotal);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs ,val_vbs);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vss ,val_vss);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse ,val_vse);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vtotal ,val_vtotal);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps ,val_pps);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_sync_pol ,val_sync_pol);
 
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,0 ,"00000001");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,1 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,2 ,"00000010");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,3 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,4 ,"00000100");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,5 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,6 ,"00001000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,7 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,8 ,"00010000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,9 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,10 ,"00100000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,11 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,12 ,"01000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,13 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,14 ,"10000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,15 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,16 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,17 ,"00000001");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,18 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,19 ,"00000010");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,20 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,21 ,"00000100");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,22 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,23 ,"00001000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,24 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,25 ,"00010000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,26 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,27 ,"00100000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,28 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,29 ,"01000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,30 ,"00000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,31 ,"10000000");
end if;
if (cpu_dat_width = 16) then
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0/2 ,val_total1 & val_total0);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2/2 ,val_total3 & val_total2);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0/2 ,val_ofs1 & val_ofs0);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs2/2 ,val_ofs3 & val_ofs2);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws/2 ,"00000000" & val_ws );
 
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
 
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold/2 ,val_bpp & val_fifo_treshold);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs/2 ,val_hss & val_hbs);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse/2 ,val_htotal & val_hse);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs/2 ,val_vss & val_vbs);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse/2 ,val_vtotal & val_vse);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps/2 ,val_sync_pol & val_pps);
 
 
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,0 ,"0000000000000001");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,1 ,"0000000000000010");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,2 ,"0000000000000100");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,3 ,"0000000000001000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,4 ,"0000000000010000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,5 ,"0000000000100000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,6 ,"0000000001000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,7 ,"0000000010000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,8 ,"0000000100000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,9 ,"0000001000000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,10 ,"0000010000000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,11 ,"0000100000000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,12 ,"0001000000000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,13 ,"0010000000000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,14 ,"0100000000000000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,pal_stb_i,ack_o,15 ,"1000000000000000");
 
wait for 90us;
wait until clk_i'EVENT and clk_i = '1';
-- Set Cursor to 0
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2 ,"0000000000000000");
-- Accel index 0 is 0
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,0,"0000000000000000");
-- Accel index 1 is 1
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,1,"0000000000000001");
-- Accel index 2 is 3
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2,"0000000000000011");
-- Accel index 3 is -1
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,3,"1111111111111111");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+0,"1111000011110000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000000001");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000001000");
-- Set Cursor to 16
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000010000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+0,"1111000011110000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+1,"1111000011110000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000010001");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+2,"1111000011110000");
wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,accel_stb_i,ack_o,2**accel_size+3,"1111000011110000");
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000011000");
-- Set Cursor to 0
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_cur/2,"0000000000000000");
 
end if;
if (cpu_dat_width = 32) then
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0/4 ,val_total3 & val_total2 & val_total1 & val_total0);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0/4 ,val_ofs3 & val_ofs2 & val_ofs1 & val_ofs0);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws/4 ,"000000000000000000000000" & val_ws );
 
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
 
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold/4 ,val_hss & val_hbs & val_bpp & val_fifo_treshold);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse/4 ,val_vss & val_vbs & val_htotal & val_hse);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse/4 ,val_sync_pol & val_pps & val_vtotal & val_vse);
end if;
 
wait;
end process;
 
 
ram: process is
-- type data_array is array (integer range <>) of std_logic_vector(v_dat_width-1 downto 0);-- Memory Type
-- variable data : data_array(0 to (2** v_adr_width-1) ); -- Local data
variable init: boolean := true;
begin
if (init) then
for i in mem_data'RANGE loop
mem_data(i) <= CONV_STD_LOGIC_VECTOR(i,v_dat_width);
-- data(i) := (others => '0');
end loop;
init := false;
end if;
wait on clk_i, v_cyc_o, v_stb_o, v_we_o, v_dat_o;
if (v_cyc_o = '1' and v_stb_o = '1') then
v_ack_i <= '1';
else
v_ack_i <= '0';
end if;
if (clk_i'EVENT and clk_i = '1' and v_cyc_o = '1' and v_stb_o = '1' and v_we_o = '1') then
mem_data(CONV_INTEGER(v_adr_o)) <= v_dat_o;
v_dat_i <= (others => 'U');
elsif (v_cyc_o = '1' and v_stb_o = '1' and v_we_o = '0') then
v_dat_i <= mem_data(CONV_INTEGER(v_adr_o));
-- v_dat_i <= v_adr_o(v_dat_i'RANGE);
else
v_dat_i <= (others => 'U');
end if;
end process;
 
end TB;
 
/trunk/TestBench/vga_chip_TB.vhd
10,11 → 10,6
use wb_vga.constants.all;
 
entity vga_chip_tb is
-- Generic declarations of the tested unit
generic(
v_mem_width : POSITIVE := 16;
fifo_size : POSITIVE := 256;
v_addr_width : POSITIVE := 20 );
end vga_chip_tb;
 
architecture TB of vga_chip_tb is
89,28 → 84,29
signal blank : std_logic;
signal video_out : std_logic_vector(7 downto 0);
 
constant reg_total0 : std_logic_vector(v_addr_width downto 0) := "000000000000000000000";
constant reg_total1 : std_logic_vector(v_addr_width downto 0) := "000000000000000000001";
constant reg_total2 : std_logic_vector(v_addr_width downto 0) := "000000000000000000010";
constant reg_total3 : std_logic_vector(v_addr_width downto 0) := "000000000000000000011";
constant reg_ofs0 : std_logic_vector(v_addr_width downto 0) := "000000000000000000100";
constant reg_ofs1 : std_logic_vector(v_addr_width downto 0) := "000000000000000000101";
constant reg_ofs2 : std_logic_vector(v_addr_width downto 0) := "000000000000000000110";
constant reg_ofs3 : std_logic_vector(v_addr_width downto 0) := "000000000000000000111";
constant reg_ws : std_logic_vector(v_addr_width downto 0) := "000000000000000001000";
constant reg_total0 : integer := 0;
constant reg_total1 : integer := 1;
constant reg_total2 : integer := 2;
constant reg_total3 : integer := 3;
constant reg_ofs0 : integer := 4;
constant reg_ofs1 : integer := 5;
constant reg_ofs2 : integer := 6;
constant reg_ofs3 : integer := 7;
constant reg_fifo_treshold : std_logic_vector(v_addr_width downto 0) := "000000000000000010000";
constant reg_bpp : std_logic_vector(v_addr_width downto 0) := "000000000000000010001";
constant reg_hbs : std_logic_vector(v_addr_width downto 0) := "000000000000000010010";
constant reg_hss : std_logic_vector(v_addr_width downto 0) := "000000000000000010011";
constant reg_hse : std_logic_vector(v_addr_width downto 0) := "000000000000000010100";
constant reg_htotal : std_logic_vector(v_addr_width downto 0) := "000000000000000010101";
constant reg_vbs : std_logic_vector(v_addr_width downto 0) := "000000000000000010110";
constant reg_vss : std_logic_vector(v_addr_width downto 0) := "000000000000000010111";
constant reg_vse : std_logic_vector(v_addr_width downto 0) := "000000000000000011000";
constant reg_vtotal : std_logic_vector(v_addr_width downto 0) := "000000000000000011001";
constant reg_pps : std_logic_vector(v_addr_width downto 0) := "000000000000000011010";
constant reg_sync_pol : std_logic_vector(v_addr_width downto 0) := "000000000000000011011";
constant reg_fifo_treshold : integer := 16;
constant reg_bpp : integer := 17;
constant reg_hbs : integer := 18;
constant reg_hss : integer := 19;
constant reg_hse : integer := 20;
constant reg_htotal : integer := 21;
constant reg_vbs : integer := 22;
constant reg_vss : integer := 23;
constant reg_vse : integer := 24;
constant reg_vtotal : integer := 25;
constant reg_pps : integer := 26;
constant reg_sync_pol : integer := 27;
 
constant reg_ws : integer := 32;
constant val_total0 : std_logic_vector(7 downto 0) := "00001111";
constant val_total1 : std_logic_vector(7 downto 0) := "00000000";
120,7 → 116,6
constant val_ofs1 : std_logic_vector(7 downto 0) := "00000000";
constant val_ofs2 : std_logic_vector(7 downto 0) := "00000000";
constant val_ofs3 : std_logic_vector(7 downto 0) := "00000000";
constant val_ws : std_logic_vector(7 downto 0) := "00000010";
constant val_fifo_treshold : std_logic_vector(7 downto 0) := "00000011";
constant val_bpp : std_logic_vector(7 downto 0) := "00000011";
constant val_hbs : std_logic_vector(7 downto 0) := "00000111";
133,6 → 128,7
constant val_vtotal : std_logic_vector(7 downto 0) := "00000100";
constant val_pps : std_logic_vector(7 downto 0) := "00000001";
constant val_sync_pol : std_logic_vector(7 downto 0) := "10000000";
constant val_ws : std_logic_vector(7 downto 0) := "00000010";
begin
 
198,34 → 194,69
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0 ,val_total0);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total1 ,val_total1);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2 ,val_total2);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total3 ,val_total3);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0 ,val_ofs0);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs1 ,val_ofs1);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs2 ,val_ofs2);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs3 ,val_ofs3);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws ,val_ws);
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
 
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold ,val_fifo_treshold);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_bpp ,val_bpp);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs ,val_hbs);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hss ,val_hss);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse ,val_hse);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_htotal ,val_htotal);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs ,val_vbs);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vss ,val_vss);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse ,val_vse);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vtotal ,val_vtotal);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps ,val_pps);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_sync_pol ,val_sync_pol);
if (cpu_dat_width = 8) then
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0 ,val_total0);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total1 ,val_total1);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2 ,val_total2);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total3 ,val_total3);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0 ,val_ofs0);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs1 ,val_ofs1);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs2 ,val_ofs2);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs3 ,val_ofs3);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws ,val_ws);
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold ,val_fifo_treshold);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_bpp ,val_bpp);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs ,val_hbs);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hss ,val_hss);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse ,val_hse);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_htotal ,val_htotal);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs ,val_vbs);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vss ,val_vss);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse ,val_vse);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vtotal ,val_vtotal);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps ,val_pps);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_sync_pol ,val_sync_pol);
end if;
if (cpu_dat_width = 16) then
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0/2 ,val_total1 & val_total0);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2/2 ,val_total3 & val_total2);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0/2 ,val_ofs1 & val_ofs0);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs2/2 ,val_ofs3 & val_ofs2);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws/2 ,"00000000" & val_ws );
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold/2 ,val_bpp & val_fifo_treshold);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs/2 ,val_hss & val_hbs);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse/2 ,val_htotal & val_hse);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs/2 ,val_vss & val_vbs);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse/2 ,val_vtotal & val_vse);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps/2 ,val_sync_pol & val_pps);
end if;
if (cpu_dat_width = 32) then
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0/4 ,val_total3 & val_total2 & val_total1 & val_total0);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ofs0/4 ,val_ofs3 & val_ofs2 & val_ofs1 & val_ofs0);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws/4 ,"000000000000000000000000" & val_ws );
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wait until clk_i'EVENT and clk_i = '1';
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold/4 ,val_hss & val_hbs & val_bpp & val_fifo_treshold);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse/4 ,val_vss & val_vbs & val_htotal & val_hse);
wr_chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse/4 ,val_sync_pol & val_pps & val_vtotal & val_vse);
end if;
 
wait;
end process;
235,7 → 266,7
wait on s_data,s_addr,s_oen,s_wrhn,s_wrln,s_cen;
if (s_cen = '0') then
if (s_oen = '0') then
s_data <= s_addr(v_mem_width-1 downto 0);
s_data <= s_addr(v_dat_width-1 downto 0);
elsif (s_wrhn = '0' or s_wrln = '0') then
if (s_wrhn = '0') then
else
/trunk/mem_reader.vhd
24,7 → 24,8
pix_clk_en: in std_logic;
reset: in std_logic := '0';
total: in std_logic_vector(v_addr_width-1 downto 0); -- total video memory size in bytes 7..0
v_mem_end: in std_logic_vector(v_addr_width-1 downto 0); -- video memory end address in words
v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words
fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold
bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8
multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans
175,14 → 176,14
begin
wait until clk'EVENT and clk='1';
if (reset = '1') then
pixel_cnt := (others => '0');
pixel_cnt := v_mem_start;
else
-- A little cheet. It won't work with constant v_mem_rdy.
if (v_mem_rdy = '1') then
-- data is already written to the FIFO, all we need to do is to update the counter,
-- and remove the request
if (pixel_cnt = total) then
pixel_cnt := (others => '0');
if (pixel_cnt = v_mem_end) then
pixel_cnt := v_mem_start;
else
pixel_cnt := add_one(pixel_cnt);
end if;
/trunk/vga_chip.vhd
11,8 → 11,9
package constants is
constant v_dat_width: positive := 16;
constant v_adr_width : positive := 20;
constant cpu_dat_width: positive := 8;
constant cpu_adr_width: positive := 21;
constant cpu_dat_width: positive := 32;
constant cpu_adr_width: positive := 19;
constant reg_adr_width: positive := 5;
constant fifo_size: positive := 256;
-- constant addr_diff: integer := log2(cpu_dat_width/v_dat_width);
end constants;
34,20 → 35,17
port (
clk_i: in std_logic;
clk_en: in std_logic := '1';
rst_i: in std_logic := '0';
rstn: in std_logic := '1';
 
-- CPU bus interface
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
cyc_i: in std_logic;
ack_o: out std_logic;
ack_oi: in std_logic;
we_i: in std_logic;
vmem_stb_i: in std_logic;
reg_stb_i: in std_logic;
adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
data: inout std_logic_vector (cpu_dat_width-1 downto 0) := (others => 'Z');
addr: in std_logic_vector (cpu_adr_width-1 downto 0) := (others => 'U');
rdn: in std_logic := '1';
wrn: in std_logic := '1';
vmem_cen: in std_logic := '1';
reg_cen: in std_logic := '1';
byen: in std_logic_vector ((cpu_dat_width/8)-1 downto 0);
waitn: out std_logic;
 
-- video memory SRAM interface
s_data : inout std_logic_vector(v_dat_width-1 downto 0);
104,13 → 102,45
);
end component;
 
component wb_async_master
generic (
width: positive := 16;
addr_width: positive := 20
);
port (
clk_i: in std_logic;
rst_i: in std_logic := '0';
-- interface to wb slave devices
s_adr_o: out std_logic_vector (addr_width-1 downto 0);
s_sel_o: out std_logic_vector ((width/8)-1 downto 0);
s_dat_i: in std_logic_vector (width-1 downto 0);
s_dat_o: out std_logic_vector (width-1 downto 0);
s_cyc_o: out std_logic;
s_ack_i: in std_logic;
s_err_i: in std_logic := '-';
s_rty_i: in std_logic := '-';
s_we_o: out std_logic;
s_stb_o: out std_logic;
 
-- interface to asyncron master device
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U');
a_rdn: in std_logic := '1';
a_wrn: in std_logic := '1';
a_cen: in std_logic := '1';
a_byen: in std_logic_vector ((width/8)-1 downto 0);
a_waitn: out std_logic
);
end component;
 
component vga_core
generic (
-- cannot be overwritten at the moment...
v_dat_width: positive := 16;
v_adr_width : positive := 20;
cpu_dat_width: positive := 8;
cpu_adr_width: positive := 21;
cpu_dat_width: positive := 16;
cpu_adr_width: positive := 20;
reg_adr_width: positive := 20;
fifo_size: positive := 256
);
port (
117,22 → 147,31
clk_i: in std_logic;
clk_en: in std_logic := '1';
rst_i: in std_logic := '0';
 
-- CPU bus interface
cyc_i: in std_logic;
we_i: in std_logic;
-- CPU memory bus interface
vmem_cyc_i: in std_logic;
vmem_we_i: in std_logic;
vmem_stb_i: in std_logic; -- selects video memory
total_stb_i: in std_logic; -- selects total register
ofs_stb_i: in std_logic; -- selects offset register
reg_bank_stb_i: in std_logic; -- selects all other registers (in a single bank)
ack_o: out std_logic;
ack_oi: in std_logic;
adr_i: in std_logic_vector (v_adr_width downto 0);
sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
 
vmem_ack_o: out std_logic;
vmem_ack_oi: in std_logic;
vmem_adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
vmem_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
vmem_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
vmem_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
vmem_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
-- CPU register bus interface
reg_cyc_i: in std_logic;
reg_we_i: in std_logic;
reg_stb_i: in std_logic; -- selects configuration registers
reg_ack_o: out std_logic;
reg_ack_oi: in std_logic;
reg_adr_i: in std_logic_vector (reg_adr_width-1 downto 0);
reg_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
reg_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
reg_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
reg_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
-- video memory interface
v_adr_o: out std_logic_vector (v_adr_width-1 downto 0);
v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0);
142,7 → 181,7
v_ack_i: in std_logic;
v_we_o: out std_logic;
v_stb_o: out std_logic;
 
-- sync blank and video signal outputs
h_sync: out std_logic;
h_blank: out std_logic;
180,9 → 219,10
);
end component;
 
signal total_stb: std_logic;
signal ofs_stb: std_logic;
signal reg_bank_stb: std_logic;
signal reg_ack_o: std_logic;
signal reg_dat_o: std_logic_vector(cpu_dat_width-1 downto 0);
 
signal reg_stb: std_logic;
signal ws_stb: std_logic;
signal wait_state: std_logic_vector(3 downto 0);
 
201,7 → 241,29
signal ws_ack_o: std_logic;
signal s_wrn: std_logic;
 
 
signal dat_i: std_logic_vector (cpu_dat_width-1 downto 0);
signal dat_oi: std_logic_vector (cpu_dat_width-1 downto 0);
signal dat_o: std_logic_vector (cpu_dat_width-1 downto 0);
signal cyc_i: std_logic;
signal ack_o: std_logic;
signal ack_oi: std_logic;
signal we_i: std_logic;
signal vmem_stb_i: std_logic;
signal reg_stb_i: std_logic;
signal adr_i: std_logic_vector (cpu_adr_width-1 downto 0);
signal sel_i: std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
signal cen: std_logic;
signal stb: std_logic;
 
signal rst_i: std_logic := '0';
 
constant vga_reg_size: integer := size2bits((32*8+cpu_dat_width-1)/cpu_dat_width);
begin
rst_i <= not rstn;
ws_reg: wb_out_reg
generic map( width => 4, bus_width => cpu_dat_width , offset => 0 )
port map(
221,6 → 283,7
v_adr_width => v_adr_width,
cpu_dat_width => cpu_dat_width,
cpu_adr_width => cpu_adr_width,
reg_adr_width => reg_adr_width,
fifo_size => fifo_size
)
port map (
227,20 → 290,32
clk_i => clk_i,
clk_en => clk_en,
rst_i => rst_i,
 
-- CPU bus interface
cyc_i => cyc_i,
we_i => we_i,
vmem_stb_i => vmem_stb_i,
total_stb_i => total_stb,
ofs_stb_i => ofs_stb,
reg_bank_stb_i => reg_bank_stb,
ack_o => ack_o,
ack_oi => ws_ack_o,
adr_i => adr_i,
sel_i => sel_i,
dat_i => dat_i,
dat_oi => ws_dat_o,
dat_o => dat_o,
vmem_cyc_i => cyc_i,
vmem_we_i => we_i,
vmem_stb_i => vmem_stb_i,
vmem_ack_o => ack_o,
vmem_ack_oi => reg_ack_o,
vmem_adr_i => adr_i,
vmem_sel_i => sel_i,
vmem_dat_i => dat_i,
vmem_dat_oi => reg_dat_o,
vmem_dat_o => dat_o,
-- CPU register bus interface
reg_cyc_i => cyc_i,
reg_we_i => we_i,
reg_stb_i => reg_stb_i,
reg_ack_o => reg_ack_o,
reg_ack_oi => ack_oi,
reg_adr_i => adr_i(reg_adr_width-1 downto 0),
reg_sel_i => sel_i,
reg_dat_i => dat_i,
reg_dat_oi => dat_oi,
reg_dat_o => reg_dat_o,
 
-- video memory interface
v_adr_o => v_adr_o,
v_sel_o => v_sel_o,
290,26 → 365,52
s_wrln <= s_wrn or s_byen(0);
s_wrhn <= s_wrn or s_byen(1);
 
master: wb_async_master
generic map (
width => cpu_dat_width,
addr_width => cpu_adr_width
)
port map (
clk_i => clk_i,
rst_i => rst_i,
-- interface to wb slave devices
s_adr_o => adr_i,
s_sel_o => sel_i,
s_dat_i => dat_o,
s_dat_o => dat_i,
s_cyc_o => cyc_i,
s_ack_i => ack_o,
s_err_i => '0',
s_rty_i => '0',
s_we_o => we_i,
s_stb_o => stb,
-- interface to asyncron master device
a_data => data,
a_addr => addr,
a_rdn => rdn,
a_wrn => wrn,
a_cen => cen,
a_byen => byen,
a_waitn => waitn
);
 
cen <= vmem_cen and reg_cen;
vmem_stb_i <= stb and not vmem_cen;
reg_stb_i <= stb and not reg_cen;
addr_decoder: process is
begin
wait on reg_stb_i, adr_i;
 
total_stb <= '0';
ofs_stb <= '0';
reg_bank_stb <= '0';
reg_stb <= '0';
ws_stb <= '0';
 
if (reg_stb_i = '1') then
case (adr_i(4)) is
when '0' =>
case (adr_i(3 downto 2)) is
when "00" => total_stb <= '1';
when "01" => ofs_stb <= '1';
when "10" => ws_stb <= '1';
when others =>
end case;
when '1' => reg_bank_stb <= '1';
case (adr_i(vga_reg_size)) is
when '0' => reg_stb <= '1';
when '1' => ws_stb <= '1';
when others =>
end case;
end if;
/trunk/compile.sh
72,4 → 72,5
compile_file accel.vhd
compile_file palette.vhd
compile_file vga_core.vhd
compile_file vga_core_v2.vhd
compile_file vga_chip.vhd
/trunk/vga_core.vhd
17,11 → 17,11
 
entity vga_core is
generic (
-- cannot be overwritten at the moment...
v_dat_width: positive := 16;
v_adr_width : positive := 20;
cpu_dat_width: positive := 8;
cpu_adr_width: positive := 21;
cpu_dat_width: positive := 16;
cpu_adr_width: positive := 20;
reg_adr_width: positive := 20;
fifo_size: positive := 256
);
port (
29,21 → 29,30
clk_en: in std_logic := '1';
rst_i: in std_logic := '0';
 
-- CPU bus interface
cyc_i: in std_logic;
we_i: in std_logic;
-- CPU memory bus interface
vmem_cyc_i: in std_logic;
vmem_we_i: in std_logic;
vmem_stb_i: in std_logic; -- selects video memory
total_stb_i: in std_logic; -- selects total register
ofs_stb_i: in std_logic; -- selects offset register
reg_bank_stb_i: in std_logic; -- selects all other registers (in a single bank)
ack_o: out std_logic;
ack_oi: in std_logic;
adr_i: in std_logic_vector (v_adr_width downto 0);
sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
vmem_ack_o: out std_logic;
vmem_ack_oi: in std_logic;
vmem_adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
vmem_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
vmem_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
vmem_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
vmem_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
 
-- CPU register bus interface
reg_cyc_i: in std_logic;
reg_we_i: in std_logic;
reg_stb_i: in std_logic; -- selects configuration registers
reg_ack_o: out std_logic;
reg_ack_oi: in std_logic;
reg_adr_i: in std_logic_vector (reg_adr_width-1 downto 0);
reg_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
reg_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
reg_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
reg_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
 
-- video memory interface
v_adr_o: out std_logic_vector (v_adr_width-1 downto 0);
v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0);
79,7 → 88,8
clk_en: in std_logic := '1';
reset: in std_logic := '0';
 
total: in std_logic_vector(v_addr_width-1 downto 0); -- total video memory size in bytes 7..0
v_mem_end: in std_logic_vector(v_addr_width-1 downto 0); -- video memory end address in words
v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words
fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold
bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8
multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans
182,10 → 192,10
 
component wb_bus_resize
generic (
m_bus_width: positive := 8; -- master bus width
m_addr_width: positive := 21; -- master bus width
s_bus_width: positive := 16; -- slave bus width
s_addr_width: positive := 20; -- master bus width
m_bus_width: positive;
m_addr_width: positive;
s_bus_width: positive;
s_addr_width: positive;
little_endien: boolean := true -- if set to false, big endien
);
port (
222,8 → 232,8
);
end component;
 
signal total: std_logic_vector(v_adr_width-1 downto 0);
signal offset: std_logic_vector(v_adr_width-1 downto 0);
signal v_mem_start: std_logic_vector(v_adr_width-1 downto 0);
signal v_mem_end: std_logic_vector(v_adr_width-1 downto 0);
signal reg_bank: std_logic_vector((8*12)-1 downto 0);
 
242,18 → 252,18
alias sync_pol: std_logic_vector (3 downto 0) is reg_bank(91 downto 88);
alias reset_core: std_logic_vector(0 downto 0) is reg_bank(95 downto 95);
 
signal v_mem_start_stb: std_logic; -- selects total register
signal v_mem_end_stb: std_logic; -- selects offset register
signal reg_bank_stb: std_logic; -- selects all other registers (in a single bank)
 
signal reg_bank_do: std_logic_vector(cpu_dat_width-1 downto 0);
signal total_do: std_logic_vector(cpu_dat_width-1 downto 0);
signal ofs_do: std_logic_vector(cpu_dat_width-1 downto 0);
signal vm_do: std_logic_vector(cpu_dat_width-1 downto 0);
signal v_mem_start_do: std_logic_vector(cpu_dat_width-1 downto 0);
 
signal reg_bank_ack: std_logic;
signal total_ack: std_logic;
signal ofs_ack: std_logic;
signal vm_ack: std_logic;
signal v_mem_start_ack: std_logic;
 
signal a_adr_o : std_logic_vector((v_adr_width-1) downto 0);
signal a_sel_o : std_logic_vector((v_adr_width/8)-1 downto 0);
signal a_sel_o : std_logic_vector((v_dat_width/8)-1 downto 0);
signal a_dat_o : std_logic_vector((v_dat_width-1) downto 0);
signal a_dat_i : std_logic_vector((v_dat_width-1) downto 0);
signal a_we_o : std_logic;
262,7 → 272,7
signal a_ack_i : std_logic;
 
signal b_adr_o : std_logic_vector((v_adr_width-1) downto 0);
signal b_sel_o : std_logic_vector((v_adr_width/8)-1 downto 0);
signal b_sel_o : std_logic_vector((v_dat_width/8)-1 downto 0);
-- signal b_dat_o : std_logic_vector((v_dat_width-1) downto 0);
signal b_dat_i : std_logic_vector((v_dat_width-1) downto 0);
signal b_stb_o : std_logic;
285,6 → 295,8
constant v_adr_zero : std_logic_vector(v_adr_width-1 downto 0) := (others => '0');
constant reg_bank_rst_val: std_logic_vector(reg_bank'Range) := (others => '0');
constant reg_bank_size: integer := size2bits((reg_bank'HIGH+cpu_dat_width)/cpu_dat_width);
constant tot_ofs_size: integer := size2bits((v_adr_width+cpu_dat_width-1)/cpu_dat_width);
begin
-- map all registers:
-- adr_i: in std_logic_vector (max(log2((width+offset+bus_width-1)/bus_width)-1,0) downto 0) := (others => '0');
292,39 → 304,39
reg_bank_reg: wb_out_reg
generic map( width => reg_bank'HIGH+1, bus_width => cpu_dat_width , offset => 0 )
port map(
stb_i => reg_bank_stb_i,
stb_i => reg_bank_stb,
q => reg_bank,
rst_val => reg_bank_rst_val,
dat_oi => vm_do,
dat_oi => reg_dat_oi,
dat_o => reg_bank_do,
ack_oi => vm_ack,
ack_oi => reg_ack_oi,
ack_o => reg_bank_ack,
adr_i => adr_i(3 downto 0), -- range should be calculated !!!
sel_i => sel_i, cyc_i => cyc_i, we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
ofs_reg: wb_out_reg
adr_i => reg_adr_i(reg_bank_size-1 downto 0),
sel_i => reg_sel_i, cyc_i => reg_cyc_i, we_i => reg_we_i, clk_i => clk_i, rst_i => rst_i, dat_i => reg_dat_i );
v_mem_start_reg: wb_out_reg
generic map( width => v_adr_width, bus_width => cpu_dat_width , offset => 0 )
port map(
stb_i => ofs_stb_i,
q => offset,
stb_i => v_mem_start_stb,
q => v_mem_start,
rst_val => v_adr_zero,
dat_oi => reg_bank_do,
dat_o => ofs_do,
dat_o => v_mem_start_do,
ack_oi => reg_bank_ack,
ack_o => ofs_ack,
adr_i => adr_i(1 downto 0), -- range should be calculated !!!
sel_i => sel_i, cyc_i => cyc_i, we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
total_reg: wb_out_reg
ack_o => v_mem_start_ack,
adr_i => reg_adr_i(tot_ofs_size-1 downto 0),
sel_i => reg_sel_i, cyc_i => reg_cyc_i, we_i => reg_we_i, clk_i => clk_i, rst_i => rst_i, dat_i => reg_dat_i );
v_mem_end_reg: wb_out_reg
generic map( width => v_adr_width, bus_width => cpu_dat_width , offset => 0 )
port map(
stb_i => total_stb_i,
q => total,
stb_i => v_mem_end_stb,
q => v_mem_end,
rst_val => v_adr_zero,
dat_oi => ofs_do,
dat_o => dat_o, -- END OF THE CHAIN
ack_oi => ofs_ack,
ack_o => ack_o, -- END OF THE CHAIN
adr_i => adr_i(1 downto 0), -- range should be calculated !!!
sel_i => sel_i, cyc_i => cyc_i, we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
dat_oi => v_mem_start_do,
dat_o => reg_dat_o, -- END OF THE CHAIN
ack_oi => v_mem_start_ack,
ack_o => reg_ack_o, -- END OF THE CHAIN
adr_i => reg_adr_i(tot_ofs_size-1 downto 0),
sel_i => reg_sel_i, cyc_i => reg_cyc_i, we_i => reg_we_i, clk_i => clk_i, rst_i => rst_i, dat_i => reg_dat_i );
 
reset_engine <= rst_i or not reset_core(0);
 
334,7 → 346,8
clk => clk_i,
clk_en => clk_en,
reset => reset_engine,
total => total,
v_mem_start => v_mem_start,
v_mem_end => v_mem_end,
fifo_treshold => fifo_treshold,
bpp => bpp,
multi_scan => multi_scan,
372,18 → 385,18
 
resize: wb_bus_resize
generic map (
m_bus_width => cpu_dat_width, s_bus_width => v_dat_width, m_addr_width => cpu_adr_width
m_bus_width => cpu_dat_width, s_bus_width => v_dat_width, m_addr_width => cpu_adr_width, s_addr_width => v_adr_width, little_endien => true
)
port map (
m_adr_i => adr_i,
m_cyc_i => cyc_i,
m_sel_i => sel_i,
m_dat_i => dat_i,
m_dat_oi => dat_oi, -- Beginning of the chain
m_dat_o => vm_do,
m_ack_o => vm_ack,
m_ack_oi => ack_oi, -- Beginning of the chain
m_we_i => we_i,
m_adr_i => vmem_adr_i,
m_cyc_i => vmem_cyc_i,
m_sel_i => vmem_sel_i,
m_dat_i => vmem_dat_i,
m_dat_oi => vmem_dat_oi,
m_dat_o => vmem_dat_o,
m_ack_o => vmem_ack_o,
m_ack_oi => vmem_ack_oi, -- Beginning of the chain
m_we_i => vmem_we_i,
m_stb_i => vmem_stb_i,
s_adr_o => a_adr_o,
443,5 → 456,26
end if;
end process;
 
addr_decoder: process is
begin
wait on reg_stb_i, reg_adr_i;
 
v_mem_start_stb <= '0';
v_mem_end_stb <= '0';
reg_bank_stb <= '0';
 
if (reg_stb_i = '1') then
case (reg_adr_i(reg_bank_size)) is
when '0' =>
case (reg_adr_i(reg_bank_size-2)) is
when '0' => v_mem_end_stb <= '1';
when '1' => v_mem_start_stb <= '1';
when others =>
end case;
when '1' => reg_bank_stb <= '1';
when others =>
end case;
end if;
end process;
end vga_core;
 
/trunk/accel.vhd
22,7 → 22,6
generic (
accel_size: positive := 9;
video_addr_width: positive := 20;
video_data_width: positive := 16;
data_width: positive := 16
);
port (
49,11 → 48,12
-- Master interface to the video memory side.
v_we_o: out std_logic;
v_cyc_o: out std_logic;
v_sel_o: out std_logic;
v_stb_o: out std_logic;
 
v_adr_o: out std_logic_vector (video_addr_width-1 downto 0);
v_dat_o: out std_logic_vector (video_data_width-1 downto 0);
v_dat_i: in std_logic_vector (video_data_width-1 downto 0);
v_sel_o: out std_logic_vector ((data_width/8)-1 downto 0);
v_dat_o: out std_logic_vector (data_width-1 downto 0);
v_dat_i: in std_logic_vector (data_width-1 downto 0);
v_ack_i: in std_logic
);
125,7 → 125,9
accel_ram_stb <= acc_stb_i or mem_stb_i;
accel_ram_we <= we_i and acc_stb_i;
accel_ram_clk <= clk_i;
accel_ram_dat_i(min(video_addr_width,data_width)-1 downto 0) <= dat_i;
accel_ram_dat_i(min2(video_addr_width-1
,data_width-1) downto 0) <=
dat_i(min2(video_addr_width,data_width) - 1 downto 0);
high_accel_dat_gen: if (video_addr_width > data_width) generate
accel_ram_dat_i(video_addr_width-1 downto data_width) <= ext_value;
end generate;
145,7 → 147,7
ack_o => accel_ram_ack
);
 
v_sel_o <= mem_stb_i;
v_stb_o <= mem_stb_i;
v_cyc_o <= mem_stb_i and cyc_i;
v_adr_o <= cursor;
v_we_o <= we_i;
164,7 → 166,7
port map (
clk_i => clk_i,
rst_i => rst_i,
rst_val => (others => '0'),
rst_val => (video_addr_width - data_width-1 downto 0 => '0'),
cyc_i => cyc_i,
stb_i => ext_stb_i,
188,10 → 190,15
end generate;
 
cur_reg: wb_io_reg
generic map (
width => video_addr_width,
bus_width => data_width,
offset => 0
)
port map (
clk_i => clk_i,
rst_i => rst_i,
rst_val => (others => '0'),
rst_val => (video_addr_width-1 downto 0 => '0'),
cyc_i => cyc_i,
stb_i => cur_stb_i,
210,11 → 217,20
 
cur_update <= mem_stb_i and cyc_i and v_ack_i;
 
v_sel_o <= sel_i;
gen_dat_o: for i in dat_o'RANGE generate
mem_dat_o(i) <= (
(cyc_i and ((accel_ram_d_out(i) and acc_stb_i) or (v_dat_i(i) and mem_stb_i))) or
(dat_oi(i) and ((not (acc_stb_i or mem_stb_i or cur_stb_i)) or (not cyc_i)))
);
gen_dat_o1: if (i < video_addr_width) generate
mem_dat_o(i) <= (
(cyc_i and ((accel_ram_d_out(i) and acc_stb_i) or (v_dat_i(i) and mem_stb_i))) or
(dat_oi(i) and ((not (acc_stb_i or mem_stb_i or cur_stb_i)) or (not cyc_i)))
);
end generate;
gen_dat_o2: if (i >= video_addr_width) generate
mem_dat_o(i) <= (
(cyc_i and (('0' and acc_stb_i) or (v_dat_i(i) and mem_stb_i))) or
(dat_oi(i) and ((not (acc_stb_i or mem_stb_i or cur_stb_i)) or (not cyc_i)))
);
end generate;
end generate;
mem_ack_o <= (
(cyc_i and ((accel_ram_ack and acc_stb_i) or (v_ack_i and mem_stb_i))) or
/trunk/video_engine.vhd
23,7 → 23,8
clk_en: in std_logic := '1';
reset: in std_logic := '0';
total: in std_logic_vector(v_addr_width-1 downto 0); -- total video memory size in bytes 7..0
v_mem_end: in std_logic_vector(v_addr_width-1 downto 0); -- video memory end address in words
v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words
fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold
bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8
multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans
96,7 → 97,8
pix_clk_en: in std_logic;
reset: in std_logic := '0';
total: in std_logic_vector(v_addr_width-1 downto 0); -- total video memory size in bytes 7..0
v_mem_end: in std_logic_vector(v_addr_width-1 downto 0); -- video memory end address in words
v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words
fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold
bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8
multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans
159,7 → 161,8
clk_en => clk_en,
pix_clk_en => pix_clk_en,
reset => reset,
total => total,
v_mem_end => v_mem_end,
v_mem_start => v_mem_start,
fifo_treshold => fifo_treshold,
bpp => bpp,
multi_scan => multi_scan,
/trunk/vga_core_v2.vhd
0,0 → 1,386
--
-- File: vga_core_v2.vhd
--
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/04/26
-- This code is distributed under the terms and conditions of the GNU General Public Lince.
--
-- vga_core_v2: A WB compatible monitor controller core with version2 features.
 
library IEEE;
use IEEE.std_logic_1164.all;
 
library wb_vga;
use wb_vga.all;
 
library wb_tk;
use wb_tk.all;
use wb_tk.technology.all;
 
entity vga_core_v2 is
generic (
v_dat_width: positive := 16;
v_adr_width : positive := 20;
cpu_dat_width: positive := 16;
cpu_adr_width: positive := 11;
fifo_size: positive := 256;
accel_size: positive := 9;
v_pal_size: positive := 8;
v_pal_width: positive := 16
);
port (
clk_i: in std_logic;
clk_en: in std_logic := '1';
rst_i: in std_logic := '0';
 
-- CPU bus interface
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
cyc_i: in std_logic;
ack_o: out std_logic;
ack_oi: in std_logic;
err_o: out std_logic;
err_oi: in std_logic;
we_i: in std_logic;
accel_stb_i: in std_logic;
pal_stb_i: in std_logic;
reg_stb_i: in std_logic;
adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
 
-- video memory interface
v_adr_o: out std_logic_vector (v_adr_width-1 downto 0);
v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0);
v_dat_i: in std_logic_vector (v_dat_width-1 downto 0);
v_dat_o: out std_logic_vector (v_dat_width-1 downto 0);
v_cyc_o: out std_logic;
v_ack_i: in std_logic;
v_we_o: out std_logic;
v_stb_o: out std_logic;
 
-- sync blank and video signal outputs
h_sync: out std_logic;
h_blank: out std_logic;
v_sync: out std_logic;
v_blank: out std_logic;
h_tc: out std_logic;
v_tc: out std_logic;
blank: out std_logic;
video_out: out std_logic_vector (v_pal_size-1 downto 0); -- video output binary signal (unused bits are forced to 0)
true_color_out: out std_logic_vector (v_pal_width-1 downto 0) -- true-color video output
);
end vga_core_v2;
 
architecture vga_core_v2 of vga_core_v2 is
component vga_core
generic (
v_dat_width: positive := v_dat_width;
v_adr_width : positive := v_adr_width;
cpu_dat_width: positive := cpu_dat_width;
cpu_adr_width: positive := v_adr_width-bus_resize2adr_bits(cpu_dat_width,v_dat_width);
reg_adr_width: positive := cpu_adr_width;
fifo_size: positive := fifo_size
);
port (
clk_i: in std_logic;
clk_en: in std_logic := '1';
rst_i: in std_logic := '0';
-- CPU memory bus interface
vmem_cyc_i: in std_logic;
vmem_we_i: in std_logic;
vmem_stb_i: in std_logic; -- selects video memory
vmem_ack_o: out std_logic;
vmem_ack_oi: in std_logic;
vmem_adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
vmem_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
vmem_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
vmem_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
vmem_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
-- CPU register bus interface
reg_cyc_i: in std_logic;
reg_we_i: in std_logic;
reg_stb_i: in std_logic; -- selects configuration registers
reg_ack_o: out std_logic;
reg_ack_oi: in std_logic;
reg_adr_i: in std_logic_vector (reg_adr_width-1 downto 0);
reg_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
reg_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
reg_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
reg_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
-- video memory interface
v_adr_o: out std_logic_vector (v_adr_width-1 downto 0);
v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0);
v_dat_i: in std_logic_vector (v_dat_width-1 downto 0);
v_dat_o: out std_logic_vector (v_dat_width-1 downto 0);
v_cyc_o: out std_logic;
v_ack_i: in std_logic;
v_we_o: out std_logic;
v_stb_o: out std_logic;
-- sync blank and video signal outputs
h_sync: out std_logic;
h_blank: out std_logic;
v_sync: out std_logic;
v_blank: out std_logic;
h_tc: out std_logic;
v_tc: out std_logic;
blank: out std_logic;
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
);
end component;
 
component accel is
generic (
accel_size: positive := accel_size;
video_addr_width: positive := v_adr_width-bus_resize2adr_bits(cpu_dat_width,v_dat_width);
data_width: positive := cpu_dat_width
);
port (
clk_i: in std_logic;
rst_i: in std_logic := '0';
-- Slave interface to the CPU side
we_i: in std_logic;
cyc_i: in std_logic;
cur_stb_i: in std_logic;
ext_stb_i: in std_logic;
acc_stb_i: in std_logic;
mem_stb_i: in std_logic;
sel_i: in std_logic_vector ((data_width/8)-1 downto 0) := (others => '1');
adr_i: in std_logic_vector(accel_size-1 downto 0);
dat_i: in std_logic_vector(data_width-1 downto 0);
dat_o: out std_logic_vector(data_width-1 downto 0);
dat_oi: in std_logic_vector(data_width-1 downto 0);
ack_o: out std_logic;
ack_oi: in std_logic;
-- Master interface to the video memory side.
v_we_o: out std_logic;
v_cyc_o: out std_logic;
v_stb_o: out std_logic;
v_adr_o: out std_logic_vector (video_addr_width-1 downto 0);
v_sel_o: out std_logic_vector ((data_width/8)-1 downto 0);
v_dat_o: out std_logic_vector (data_width-1 downto 0);
v_dat_i: in std_logic_vector (data_width-1 downto 0);
v_ack_i: in std_logic
);
end component;
component wb_pal_ram is
generic (
cpu_dat_width: positive := cpu_dat_width;
cpu_adr_width: positive := v_pal_size-bus_resize2adr_bits(cpu_dat_width,v_dat_width);
v_dat_width: positive := v_pal_width;
v_adr_width: positive := v_pal_size
);
port (
-- Wishbone interface to CPU (write-only support)
clk_i: in std_logic;
rst_i: in std_logic := '0';
adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0) := (others => '-');
dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
cyc_i: in std_logic;
ack_o: out std_logic;
ack_oi: in std_logic := '-';
err_o: out std_logic;
err_oi: in std_logic := '-';
we_i: in std_logic;
stb_i: in std_logic;
-- Interface to the video output
blank: in std_logic;
v_dat_i: in std_logic_vector(v_adr_width-1 downto 0);
v_dat_o: out std_logic_vector(v_dat_width-1 downto 0)
);
end component;
 
-- register select signals
signal vga_reg_stb: std_logic;
signal cur_stb: std_logic;
signal ext_stb: std_logic;
-- accelerator select signals
signal acc_stb: std_logic;
signal mem_stb: std_logic;
 
signal vga_dat_o: std_logic_vector(cpu_dat_width-1 downto 0);
signal vga_ack_o: std_logic;
 
signal vreg_dat_o: std_logic_vector(cpu_dat_width-1 downto 0);
signal vreg_ack_o: std_logic;
signal accel_dat_o: std_logic_vector(cpu_dat_width-1 downto 0);
signal accel_ack_o: std_logic;
signal pal_dat_o: std_logic_vector(cpu_dat_width-1 downto 0);
signal pal_ack_o: std_logic;
 
signal i_video_out: std_logic_vector (v_pal_size-1 downto 0);
signal i_blank: std_logic;
signal vmem_stb: std_logic;
 
signal vm_cyc: std_logic;
signal vm_we: std_logic;
signal vm_stb: std_logic;
signal vm_ack: std_logic;
signal vm_adr: std_logic_vector(v_adr_width-bus_resize2adr_bits(cpu_dat_width,v_dat_width)-1 downto 0);
signal vm_sel: std_logic_vector(cpu_dat_width/8-1 downto 0);
signal vm_dat_i: std_logic_vector(cpu_dat_width-1 downto 0);
signal vm_dat_o: std_logic_vector(cpu_dat_width-1 downto 0);
 
constant vga_reg_size: integer := size2bits((32*8)/cpu_dat_width)-1;
begin
core : vga_core
port map (
clk_i => clk_i,
clk_en => clk_en,
rst_i => rst_i,
-- CPU bus interface
vmem_cyc_i => vm_cyc,
vmem_we_i => vm_we,
vmem_stb_i => vm_stb,
vmem_ack_o => vm_ack,
vmem_ack_oi => '1',
vmem_adr_i => vm_adr,
vmem_sel_i => vm_sel,
vmem_dat_i => vm_dat_i,
vmem_dat_oi => (cpu_dat_width-1 downto 0 => '-'),
vmem_dat_o => vm_dat_o,
-- CPU register bus interface
reg_cyc_i => cyc_i,
reg_we_i => we_i,
reg_stb_i => vga_reg_stb,
reg_ack_o => vreg_ack_o,
reg_ack_oi => ack_oi,
reg_adr_i => adr_i,
reg_sel_i => sel_i,
reg_dat_i => dat_i,
reg_dat_oi => dat_oi,
reg_dat_o => vreg_dat_o,
 
-- video memory interface
v_adr_o => v_adr_o,
v_sel_o => v_sel_o,
v_dat_i => v_dat_i,
v_dat_o => v_dat_o,
v_cyc_o => v_cyc_o,
v_ack_i => v_ack_i,
v_we_o => v_we_o,
v_stb_o => v_stb_o,
 
h_sync => h_sync,
h_blank => h_blank,
v_sync => v_sync,
v_blank => v_blank,
h_tc => h_tc,
v_tc => v_tc,
blank => i_blank,
video_out => i_video_out
);
 
acc: accel
port map (
clk_i => clk_i,
rst_i => rst_i,
-- Slave interface to the CPU side
we_i => we_i,
cyc_i => cyc_i,
cur_stb_i => cur_stb,
ext_stb_i => ext_stb,
acc_stb_i => acc_stb,
mem_stb_i => mem_stb,
sel_i => sel_i,
adr_i => adr_i(accel_size-1 downto 0),
dat_i => dat_i,
dat_o => accel_dat_o,
dat_oi => vreg_dat_o,
ack_o => accel_ack_o,
ack_oi => vreg_ack_o,
-- Master interface to the video memory side.
v_we_o => vm_we,
v_cyc_o => vm_cyc,
v_stb_o => vm_stb,
v_adr_o => vm_adr,
v_sel_o => vm_sel,
v_dat_o => vm_dat_i,
v_dat_i => vm_dat_o,
v_ack_i => vm_ack
);
 
palette: wb_pal_ram
port map (
clk_i => clk_i,
rst_i => rst_i,
adr_i => adr_i(v_pal_size-bus_resize2adr_bits(cpu_dat_width,v_dat_width)-1 downto 0),
dat_i => dat_i,
dat_oi => accel_dat_o,
dat_o => dat_o,
cyc_i => cyc_i,
ack_o => ack_o,
ack_oi => accel_ack_o,
err_o => err_o,
err_oi => err_oi,
we_i => we_i,
stb_i => pal_stb_i,
-- Interface to the video output
blank => i_blank,
v_dat_i => i_video_out,
v_dat_o => true_color_out
);
video_out <= i_video_out;
blank <= i_blank;
reg_addr_decoder: process is
begin
wait on reg_stb_i, adr_i;
 
vga_reg_stb <= '0';
cur_stb <= '0';
ext_stb <= '0';
 
if (reg_stb_i = '1') then
case (adr_i(vga_reg_size)) is
when '0' => vga_reg_stb <= '1';
when '1' =>
if (adr_i(vga_reg_size-2) = '1') then
case (adr_i(vga_reg_size-3)) is
when '0' => cur_stb <= '1';
when '1' => ext_stb <= '1';
when others =>
end case;
end if;
when others =>
end case;
end if;
end process;
 
accel_addr_decoder: process is
begin
wait on accel_stb_i, adr_i;
 
acc_stb <= '0';
mem_stb <= '0';
 
if (accel_stb_i = '1') then
case (adr_i(accel_size)) is
when '0' => acc_stb <= '1';
when '1' => mem_stb <= '1';
when others =>
end case;
end if;
end process;
 
end vga_core_v2;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.