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/rtl/Makefile
0,0 → 1,63
################################################################################
##
## Filename: Makefile
##
## Project: A wishbone conrolled DDR3 SDRAM controller.
##
## Purpose: To direct the Verilator build of our one source file. The
## result will be a library, Vwbddrsdram__ALL.a, found and kept
## in the obj_dir/ subdirectory.
##
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2015, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http:##www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
##
all: wbddrsdram
YYMMDD=`date +%Y%m%d`
CXX := g++
FBDIR := .
SOURCES:= wbddrsdram.v
VDIRFB:= $(FBDIR)/obj_dir
 
.PHONY: wbddrsdram
wbddrsdram: $(VDIRFB)/Vwbddrsdram__ALL.a
 
$(VDIRFB)/Vwbddrsdram__ALL.a: $(VDIRFB)/Vwbddrsdram.h $(VDIRFB)/Vwbddrsdram.cpp
$(VDIRFB)/Vfastmaster__ALL.a: $(VDIRFB)/Vwbddrsdram.mk
$(VDIRFB)/Vwbddrsdram.h $(VDIRFB)/wbddrsdram.cpp $(VDIRFB)/wbddrsdram.mk: $(SOURCES)
 
$(VDIRFB)/V%.cpp $(VDIRFB)/V%.h $(VDIRFB)/V%.mk: $(FBDIR)/%.v
verilator -cc $*.v
 
 
$(VDIRFB)/V%__ALL.a: $(VDIRFB)/V%.mk
cd $(VDIRFB); make -f V$*.mk
 
.PHONY: clean
clean:
rm -rf $(VDIRFB)/*.mk
rm -rf $(VDIRFB)/*.cpp
rm -rf $(VDIRFB)/*.h
rm -rf $(VDIRFB)/
 
/rtl/wbddrsdram.v
0,0 → 1,537
////////////////////////////////////////////////////////////////////////////////
//
// Filename: wbddrsdram.v
//
// Project: OpenArty, an entirely open SoC based upon the Arty platform
//
// Purpose:
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
 
// Possible commands to the DDR3 memory. These consist of settings for the
// bits: o_wb_cs_n, o_wb_ras_n, o_wb_cas_n, and o_wb_we_n, respectively.
`define DDR_MRSET 4'b0000
`define DDR_REFRESH 4'b0001
`define DDR_PRECHARGE 4'b0010
`define DDR_ACTIVATE 4'b0011
`define DDR_WRITE 4'b0100
`define DDR_READ 4'b0101
`define DDR_NOOP 4'b0111
//`define DDR_DESELECT 4'b1???
//
// In this controller, 24-bit commands tend to be passed around. These
// 'commands' are bit fields. Here we specify the bits associated with
// the bit fields.
`define DDR_RSTDONE 26
`define DDR_RSTTIMER 25
`define DDR_RSTBIT 24
`define DDR_CKEBIT 23
`define DDR_CSBIT 22
`define DDR_RASBIT 21
`define DDR_CASBIT 20
`define DDR_WEBIT 19
`define DDR_BABITS 3 // BABITS are really from 18:16, they are 3 bits
`define DDR_ADDR_BITS 16
 
module wbddrsdram(i_clk_200mhz,
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
o_wb_ack, o_wb_stb, o_wb_data,
o_ddr_reset_n, o_ddr_cke,
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_dir,
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
parameter CKREFI4 = 13'd6240; // 4 * 7.8us at 200 MHz clock
input i_clk_200mhz;
// Wishbone inputs
input i_wb_cyc, i_wb_stb, i_wb_we;
input [25:0] i_wb_addr;
input [31:0] i_wb_data;
// Wishbone outputs
output reg o_wb_ack;
output reg o_wb_stall;
output reg [31:0] o_wb_data;
// DDR3 RAM Controller
output wire o_ddr_reset_n;
output wire o_ddr_reset_cke;
// Control outputs
output reg o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
output reg [2:0] o_ddr_dqs;
// Address outputs
output reg [13:0] o_ddr_addr;
output reg [2:0] o_ddr_ba;
// And the data inputs and outputs
output reg [31:0] o_ddr_data;
input i_ddr_data;
 
//
// tWTR = 7.5
// tRRD = 7.5
// tREFI= 7.8
// tFAW = 45
// tRTP = 7.5
// tCKE = 5.625
// tRFC = 160
// tRP = 13.5
// tRAS = 36
// tRCD = 13.5
//
// RESET:
// 1. Hold o_reset_n = 1'b0; for 200 us, or 40,000 clocks (65536 perhaps?)
// Hold cke low during this time as well
// The clock should be free running into the chip during this time
// Leave command in NOOP state: {cs,ras,cas,we} = 4'h7;
// ODT must be held low
// 2. Hold cke low for another 500us, or 100,000 clocks
// 3. Raise CKE, continue outputting a NOOP for
// tXPR, tDLLk, and tZQInit
// 4. Load MRS2, wait tMRD
// 4. Load MRS3, wait tMRD
// 4. Load MRS1, wait tMOD
// Before using the SDRAM, we'll need to program at least 3 of the mode
// registers, if not all 4.
// tMOD clocks are required to program the mode registers, during which
// time the RAM must be idle.
//
// NOOP: CS low, RAS, CAS, and WE high
 
//
// Reset logic should be simple, and is given as follows:
// note that it depends upon a ROM memory, reset_mem, and an address into that
// memory: reset_address. Each memory location provides either a "command" to
// the DDR3 SDRAM, or a timer to wait until the next command. Further, the
// timer commands indicate whether or not the command during the timer is to
// be set to idle, or whether the command is instead left as it was.
reg reset_override;
reg [3:0] reset_address;
reg [22:0] reset_cmd;
reg [26:0] reset_instruction;
initial reset_override <= 1'b1;
initial reset_address <= 4'h0;
always @(posedge i_clk)
if (i_reset)
begin
reset_override <= 1'b1;
reset_cmd <= { `DDR_NOOP_CMD, reset_instruction[18:0]};
end else if (!reset_ztimer)
;
else if (reset_instruction[`DDR_RESET_DONE])
reset_override <= 1'b0;
else if (reset_instruction[`DDR_RSTTIMER])
begin
if (reset_instruction[29])
reset_cmd <= { `DDR_NOOP_CMD, reset_instruction[20:0]};
end else begin
reset_cmd[CKE] <= reset_instruction[27];
reset_cmd[~CKE] <= reset_instruction[22:0];
end
always @(posedge i_clk)
if (i_reset)
o_ddr_cke <= 1'b0;
else if (reset_override)&&(reset_ztimer)
o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
 
initial reset_ztimer <= 1'b1; // Is the timer zero?
initial reset_timer <= 17'h00;
always @(posedge i_clk)
if (i_reset)
begin
reset_ztimer <= 1'b0;
reset_timer <= 17'h00;
end else if (!reset_ztimer)
begin
reset_ztimer <= (reset_timer == 17'h01);
reset_timer <= reset_timer - 17'h01;
end else if (reset_instruction[`DDR_RSTTIMER])
begin
reset_ztimer <= 1'b0;
reset_timer <= reset_instruction[16:0];
end
always @(posedge i_clk)
case(reset_address)
4'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 19'd40_000 };
4'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 19'd100_000 };
4'h2: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd40_000 };
4'h3: reset_instruction <= { 4'h3, `DDR_MRS, 3'h0, 3'h0, 1'b0, 3'h1, 1'b0, 1'b0, 3'h1, 1'b0, 1'b0, 2'b00 }; // MRS
// 4'h5: reset_instruction <= { 4'h3, `DDR_MRS, 3'h3, 13'h0, 2'b00 }; // MRS3
4'h5: reset_instruction <= { 4'h3, `DDR_MRS, 3'h2, 5'h0, 2'b00, 1'b0, 1'b0, 1'b1, 3'b0, 3'b0 }; // MRS2
4'h7: reset_instruction <= { 4'h3, `DDR_MRS, 3'h1, 3'h0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 2'b0, 1'b1, 1'b0, 2'b0, 1'b1, 1'b1, 1'b0 }; // MRS1
default:
reset_instruction <={4'hb, `DDR_NOOP, 19'd00_000 };
endcase
// reset_instruction <= reset_mem[reset_address];
 
always @(posedge i_clk)
if (i_reset)
reset_address <= 4'h0;
else if (reset_ztimer)
reset_addres <= reset_address + 4'h1;
//
// initial reset_mem =
// 0. !DONE, TIMER,RESET_N=0, CKE=0, CMD = NOOP, TIMER = 200us ( 40,000)
// 1. !DONE, TIMER,RESET_N=1, CKE=0, CMD = NOOP, TIMER = 500us (100,000)
// 2. !DONE, TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = (Look me up)
// 3. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS
// 4. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
// 5. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS3
// 6. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
// 7. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
// 8. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
// 9. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
// 10. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMOD
// 11. !DONE,!TIMER,RESET_N=1, CKE=1, (Pre-charge all)
// 12. !DONE,!TIMER,RESET_N=1, CKE=1, (wait)
// 13. !DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
// 14. !DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
// 15. !DONE,!TIMER,RESET_N=1, CKE=1, (wait)
 
 
//
//
// Let's keep track of any open banks. There are 8 of them to keep track of.
//
// A precharge requires 3 clocks at 200MHz to complete, 2 clocks at 100MHz.
//
//
//
 
reg [2:0] bank_status[7:0];
always @(posedge i_clk)
begin
bank_status[0] = { bank_status[0][1:0], bank_status[0][0] };
bank_status[1] = { bank_status[1][1:0], bank_status[1][0] };
bank_status[2] = { bank_status[2][1:0], bank_status[2][0] };
bank_status[3] = { bank_status[3][1:0], bank_status[3][0] };
bank_status[4] = { bank_status[4][1:0], bank_status[4][0] };
bank_status[5] = { bank_status[5][1:0], bank_status[5][0] };
bank_status[6] = { bank_status[6][1:0], bank_status[6][0] };
bank_status[7] = { bank_status[7][1:0], bank_status[7][0] };
all_banks_closed <= (bank_status[0][1:0] == 2'b00)
&&(bank_status[1][1:0] == 2'b00)
&&(bank_status[2][1:0] == 2'b00)
&&(bank_status[3][1:0] == 2'b00)
&&(bank_status[4][1:0] == 2'b00)
&&(bank_status[5][1:0] == 2'b00)
&&(bank_status[6][1:0] == 2'b00)
&&(bank_status[7][1:0] == 2'b00);
if ((!reset_override)&&(need_refresh)||(w_precharge_all))
begin
bank_status[0][0] = 1'b0;
bank_status[1][0] = 1'b0;
bank_status[2][0] = 1'b0;
bank_status[3][0] = 1'b0;
bank_status[4][0] = 1'b0;
bank_status[5][0] = 1'b0;
bank_status[6][0] = 1'b0;
bank_status[7][0] = 1'b0;
banks_are_closing <= 1'b1;
end else if (need_close_bank)
begin
bank_status[r_bank][0] = 1'b0;
end else if (need_open_bank)
begin
bank_status[r_bank][0] = 1'b1;
all_banks_closed <= 1'b0;
banks_are_closing <= 1'b0;
end
end
 
always @(posedge i_clk)
if (cmd == OPEN_BANK)
bank_row[cmd_bank] <= cmd_address[14:0];
 
 
 
//
//
// Okay, let's investigate when we need to do a refresh. Our plan will be to
// do 4 refreshes every tREFI*4 seconds. tREFI = 7.8us, but its a parameter
// in the number of clocks so that we can handle both 100MHz and 200MHz clocks.
//
// Note that 160ns are needed between refresh commands (JEDEC, p172), or
// 320 clocks @200MHz, or equivalently 160 clocks @100MHz. Thus to issue 4
// of these refresh cycles will require 4*320=1280 clocks@200 MHz. After this
// time, no more refreshes will be needed for 6240 clocks.
//
// Let's think this through:
// REFRESH_COST = (n*(320)+24)/(n*1560)
//
//
//
reg [12:0] refresh_clk;
always @(posedge i_clk)
if ((endrefresh)&&(refresh_clear))
refresh_clk <= CKREFI4;
else if (|refresh_clk)
refresh_clk <= refresh_clk-1;
always @(posedge i_clk)
need_refresh <= (refresh_clk == 0)||(midrefresh);
always @(posedge i_clk)
if (need_refresh)
refresh_count <= refresh_count - 1;
else
refresh_count <= 0;
always @(posedge i_clk)
if (!need_refresh)
refresh_cmd <= NOOP;
else if (~banks_are_closing)
refresh_cmd <= CLOSE_ALL_BANKS;
else if (~all_banks_closed)
refresh_cmd <= NOOP;
else
refresh_cmd <= REFRESH;
always @(posedge i_clk)
midrefresh <= (need_refresh)&&(all_banks_closed)&&(~endrefresh);
 
always @(posedge i_clk)
if (!mid_refresh)
midrefresh_hctr <= 3'h4;
else if ((midrefresh_lctr == 0)&&(|midrefresh_hctr))
midrefresh_hctr <= midrefresh_hctr - 1;
always @(posedge i_clk)
if (!need_refresh)||(!mid_refresh)
endrefresh <= 1'b0;
else if (midrefresh_hctr == 3'h0)
endrefresh <= 1'b1;
always @(posedge i_clk)
if (!mid_refresh)
midrefresh_lctr <= CKRFC;
else if (midrefresh_lctr == 0)
midrefresh_lctr <= 0;
else
midrefresh_lctr <= CKRFC;
 
always @(posedge i_clk)
refresh_clear <= (needrefresh)&&(endrefresh)&&(midrefresh_lctr == 0);
 
 
//
//
// Let's track: when will our bus be active? When will we be reading or
// writing?
//
//
reg [8:0] bus_active, bus_read, bus_mask, bus_ack;
reg [1:0] bus_subaddr [8:0];
assign pre_cmd = (~reset_override)&&(~need_refresh)&&(valid_bank)
&&(bus_active[2:0]==3'h0)
initial bus_active <= 0;
always @(posedge i_clk)
begin
bus_active[8:0] <= { bus_active[7:0], 1'b0 };
bus_read[8:0] <= { bus_read[7:0], 1'b0 }; // Drive the d-bus?
bus_mask[8:0] <= { bus_mask[7:0], 1'b1 }; // Write this value?
bus_subaddr[8] <= bus_subaddr[7];
bus_subaddr[7] <= bus_subaddr[6];
bus_subaddr[6] <= bus_subaddr[5];
bus_subaddr[5] <= bus_subaddr[4];
bus_subaddr[4] <= bus_subaddr[3];
bus_subaddr[3] <= bus_subaddr[2];
bus_subaddr[2] <= bus_subaddr[1];
bus_subaddr[1] <= bus_subaddr[0];
bus_subaddr[0] <= 2'h3;
if (cmd == READ)
begin
bus_active[3:0]<= 4'hf; // Once per clock
bus_read[3:0] <= 4'hf; // These will be reads
bus_subaddr[3] <= 2'h0;
bus_subaddr[2] <= 2'h1;
bus_subaddr[1] <= 2'h2;
bus_ack[r_sub] <= 1'b1;
end else if (cmd == WRITE)
begin
bus_active[3:0] <= 4'hf;
// bus_read[7:4] = 4'h0;
bus_subaddr[3] <= 2'h0;
bus_subaddr[2] <= 2'h1;
bus_subaddr[1] <= 2'h2;
bus_ack[r_sub] <= 1'b1;
bus_mask[r_sub] <= 1'b0;
bus_data[r_sub] <= r_data;
end
end
 
always @(posedge i_clk)
drive_dqs <= (~bus_read[8])&&(|busactive[8:7]);
 
//
//
// Now, let's see, can we issue a read command?
//
//
always @(posedge i_clk)
begin
if ((i_wb_stb)&&(~o_wb_stall))
begin
pending <= 1'b1;
o_wb_stall <= 1'b1;
end else if ((r_move)||(m_move))
begin
pending <= 1'b0;
o_wb_stall <= 1'b0;
end
 
if (~o_wb_stall)
begin
r_we <= i_wb_we;
r_addr <= i_wb_addr;
r_data <= i_wb_data;
r_row <= i_wb_addr[25:11];
r_bank <= i_wb_addr[10:8];
r_col <= { i_wb_addr[7:2], 2'b00 }; // 9:2
r_sub <= i_wb_addr[1:0];
 
// pre-emptive work
r_nxt_row <= i_wb_addr[25:11]+15'h1;
r_nxt_bank <= i_wb_addr[10:8]+3'h1;
end
end
 
reg need_close_bank, last_close_bank,
need_open_bank, last_open_bank;
always @(posedge i_clk)
begin
need_close_bank <= (r_pending)&&(bank_active[r_bank][0])
&&(r_row != bank_address[r_bank])&&(!last_close_bank);
need_close_this_bank <= (r_pending)&&(bank_active[r_bank][0])
&&(r_row != bank_address[r_bank]);
last_close_bank <= need_close_bank;
 
maybe_close_next_bank <= (r_pending)
&&(bank_active[r_nxt_bank][0])
&&(r_nxt_row != bank_address[r_nxt_bank])
&&(!need_close_this_bank);
 
close_bank_cmd <= (maybe_close_next_bank)
? { `DDR_PRECHARGE, r_nxt_bank, r_nxt_row[15:11], 1'b0, r_nxt_row[9:0] };
: { `DDR_PRECHARGE, r_bank, r_row[15:11], 1'b0, r_row[9:0] };
 
 
need_open_bank <= (r_pending)&&(bank_active[r_bank]==2'b00)
&&(!last_open_bank);
last_open_bank <= need_open_bank;
 
maybe_open_next_bank <= (r_pending)
&&(bank_active[r_nxt_bank] == 2'b00)
&&(!need_open_bank)&&(!need_close_bank);
 
activate_bank_cmd <= (maybe_open_next_bank)
? { `DDR_ACTIVATE,r_nxt_bank,r_nxt_row[15:10] };
: { `DDR_ACTIVATE, r_bank, r_row[15:10] };
 
 
 
valid_bank <= (r_pending)&&(bank_active[r_bank]==2'b11)
&&(bank_address[r_bank]==r_row)
&&(!last_valid_bank);
last_valid_bank <= need_valid_bank;
 
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (~r_pending)?`DDR_NOOP:((r_we)?`DDR_WRITE:`DDR_READ);
rw_cmd[`DDR_WEBIT-1:0] <= { r_bank, 5'h0, 1'b0, r_col }
end
 
 
// Match registers, to see if we can move forward without sending a
// new command
always @(posedge i_clk)
begin
if (r_move)
begin
m_pending <= r_pending;
m_we <= r_we;
m_addr <= r_addr;
m_row <= r_row;
m_bank <= r_bank;
m_col <= r_col;
m_sub <= r_sub;
end else if (m_match)
m_sub <= r_sub;
 
m_match <= (m_pending)&&(pending)&&(r_we == m_we)
&&(r_row == m_row)&&(r_bank == m_bank)
&&(r_col == m_col)
&&(r_sub > m_sub);
m_continue <= (m_pending)&&(pending)&&(r_we == m_we)
&&(r_row == m_row)&&(r_bank == m_bank)
&&(r_col == m_col+8'h1)
m_nextbank <= (m_pending)&&(pending)&&(r_we == m_we)
&&(r_row == m_row)&&(r_bank == m_bank)
end
 
//
//
// Okay, let's look at the last assignment in our chain. It should look
// something like:
always @(posedge i_clk)
o_ddr_reset_n <= (~reset_override)||(reset_cmd[DDR_RSTBIT]);
always @(posedge i_clk)
o_ddr_cke <= (~reset_override)||(reset_cmd[DDR_CKEBIT]);
always @(posedge i_clk)
begin
r_move <= 1'b0;
if (reset_override)
cmd <= reset_command[DDR_CSBIT:0];
else if (need_refresh)
begin
cmd <= refresh_cmd; // The command from the refresh logc
end else if (need_close_bank)
cmd <= close_bank_cmd;
else if (need_open_bank)
cmd <= activate_bank_cmd;
else if ((valid_bank)&&(bus_active[2:0]==3'h0))
begin
cmd <= rw_cmd;
r_move <= 1'b1;
end else
cmd <= noop;
end
 
assign o_ddr_cs_n = cmd[DDR_CSBIT];
assign o_ddr_ras_n = cmd[DDR_RASBIT];
assign o_ddr_cas_n = cmd[DDR_CASBIT];
assign o_ddr_we_n = bus_read[8];
assign o_ddr_dqs = drive_dqs;
assign o_ddr_addr = cmd[(DDR_ADDR_BITS-1):0];
assign o_ddr_ba = cmd[DDR_BABITS+DDR_ADDR_BITS-1:DDR_ADDR_BITS];
assign o_ddr_data = bus_data[8];
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
assign w_precharge_all = (cmd[DDR_CSBIT:DDR_WEBIT]==`DDR_PRECHARGE)
&&(o_ddr_addr[10]); // 5 bits
 
// Need to set o_wb_dqs high one clock prior to any read.
// As per spec, ODT = 0 during reads
assign o_ddr_odt = o_ddr_bus_dir;
 
 
endmodule
/doc/spec.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/spec.pdf
doc/spec.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/src/gpl-3.0.tex =================================================================== --- doc/src/gpl-3.0.tex (nonexistent) +++ doc/src/gpl-3.0.tex (revision 2) @@ -0,0 +1,719 @@ +\documentclass[11pt]{article} + +\title{GNU GENERAL PUBLIC LICENSE} +\date{Version 3, 29 June 2007} + +\begin{document} +\maketitle + +\begin{center} +{\parindent 0in + +Copyright \copyright\ 2007 Free Software Foundation, Inc. \texttt{http://fsf.org/} + +\bigskip +Everyone is permitted to copy and distribute verbatim copies of this + +license document, but changing it is not allowed.} + +\end{center} + +\renewcommand{\abstractname}{Preamble} +\begin{abstract} +The GNU General Public License is a free, copyleft license for +software and other kinds of works. + +The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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If not, see . +\end{verbatim} +} + +Also add information on how to contact you by electronic and paper mail. + +If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + +{\footnotesize +\begin{verbatim} + Copyright (C) + +This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. +This is free software, and you are welcome to redistribute it +under certain conditions; type `show c' for details. +\end{verbatim} +} + +The hypothetical commands {\tt show w} and {\tt show c} should show +the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an ``about box''. + +You should also get your employer (if you work as a programmer) or +school, if any, to sign a ``copyright disclaimer'' for the program, if +necessary. For more information on this, and how to apply and follow +the GNU GPL, see \texttt{http://www.gnu.org/licenses/}. + +The GNU General Public License does not permit incorporating your +program into proprietary programs. If your program is a subroutine +library, you may consider it more useful to permit linking proprietary +applications with the library. If this is what you want to do, use +the GNU Lesser General Public License instead of this License. But +first, please read \texttt{http://www.gnu.org/philosophy/why-not-lgpl.html}. + +\end{enumerate} + +\end{document} Index: doc/src/GT.eps =================================================================== --- doc/src/GT.eps (nonexistent) +++ doc/src/GT.eps (revision 2) @@ -0,0 +1,94 @@ +%!PS-Adobe-3.0 EPSF-3.0 +%%BoundingBox: 0 0 504 288 +%%Creator: Gisselquist Technology LLC +%%Title: Gisselquist Technology Logo +%%CreationDate: 11 Mar 2014 +%%EndComments +%%BeginProlog +/black { 0 setgray } def +/white { 1 setgray } def +/height { 288 } def +/lw { height 8 div } def +%%EndProlog +% %%Page: 1 + +false { % A bounding box + 0 setlinewidth + newpath + 0 0 moveto + 0 height lineto + 1.625 height mul lw add 0 rlineto + 0 height neg rlineto + closepath stroke +} if + +true { % The "G" + newpath + height 2 div 1.25 mul height moveto + height 2 div height 4 div sub height lineto + 0 height 3 4 div mul lineto + 0 height 4 div lineto + height 4 div 0 lineto + height 3 4 div mul 0 lineto + height height 4 div lineto + height height 2 div lineto + % + height lw sub height 2 div lineto + height lw sub height 4 div lw 2 div add lineto + height 3 4 div mul lw 2 div sub lw lineto + height 4 div lw 2 div add lw lineto + lw height 4 div lw 2 div add lineto + lw height 3 4 div mul lw 2 div sub lineto + height 4 div lw 2 div add height lw sub lineto + height 2 div 1.25 mul height lw sub lineto + closepath fill + newpath + height 2 div height 2 div moveto + height 2 div 0 rlineto + 0 height 2 div neg rlineto + lw neg 0 rlineto + 0 height 2 div lw sub rlineto + height 2 div height 2 div lw sub lineto + closepath fill +} if + +height 2 div 1.25 mul lw add 0 translate +false { + newpath + 0 height moveto + height 0 rlineto + 0 lw neg rlineto + height lw sub 2 div neg 0 rlineto + 0 height lw sub neg rlineto + lw neg 0 rlineto + 0 height lw sub rlineto + height lw sub 2 div neg 0 rlineto + 0 lw rlineto + closepath fill +} if + +true { % The "T" of "GT". + newpath + 0 height moveto + height lw add 2 div 0 rlineto + 0 height neg rlineto + lw neg 0 rlineto + 0 height lw sub rlineto + height lw sub 2 div neg 0 rlineto + closepath fill + + % The right half of the top of the "T" + newpath + % (height + lw)/2 + lw + height lw add 2 div lw add height moveto + % height - (above) = height - height/2 - 3/2 lw = height/2-3/2lw + height 3 lw mul sub 2 div 0 rlineto + 0 lw neg rlineto + height 3 lw mul sub 2 div neg 0 rlineto + closepath fill +} if + + +grestore +showpage +%%EOF Index: doc/src/gqtekspec.cls =================================================================== --- doc/src/gqtekspec.cls (nonexistent) +++ doc/src/gqtekspec.cls (revision 2) @@ -0,0 +1,298 @@ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%/ +% +% Copyright (C) 2015, Gisselquist Technology, LLC +% +% This template is free software: you can redistribute it and/or modify it +% under the terms of the GNU General Public License as published by the +% Free Software Foundation, either version 3 of the License, or (at your +% option) any later version. +% +% This template is distributed in the hope that it will be useful, but WITHOUT +% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +% for more details. +% +% You should have received a copy of the GNU General Public License along +% with this program. If not, see for a copy. +% +% License: GPL, v3, as defined and found on www.gnu.org, +% http://www.gnu.org/licenses/gpl.html +% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% \NeedsTeXFormat{LaTeX2e}[1995/12/01] +\ProvidesClass{gqtekspec}[2015/03/03 v0.1 -- Gisselquist Technology Specification] +\typeout{by Dan Gisselquist} +\LoadClassWithOptions{report} +\usepackage{datetime} +\usepackage{graphicx} +\usepackage[dvips]{pstricks} +\usepackage{hhline} +\usepackage{colortbl} +\definecolor{webgreen}{rgb}{0,0.5,0} +\usepackage[dvips,colorlinks=true,linkcolor=webgreen]{hyperref} +\newdateformat{headerdate}{\THEYEAR/\twodigit{\THEMONTH}/\twodigit{\THEDAY}} +\setlength{\hoffset}{0.25in} +\setlength{\voffset}{-0.5in} +\setlength{\marginparwidth}{0in} +\setlength{\marginparsep}{0in} +\setlength{\textwidth}{6in} +\setlength{\oddsidemargin}{0in} + +% ************************************** +% * APPENDIX * +% ************************************** +% +\newcommand\appfl@g{\appendixname} %used to test \@chapapp +% +% \renewcommand\appendix{\par\clearpage + % \setcounter{chapter}{0}% + % \setcounter{section}{0}% + % \renewcommand\@chapapp{\appendixname}% + % \renewcommand\thechapter{\Alph{chapter}} + % \if@nosectnum\else + % \renewcommand\thesection{\Alph{chapter}.\arabic{section}} + % \fi +% } + + +% FIGURE +% redefine the @caption command to put a period after the figure or +% table number in the lof and lot tables +\long\def\@caption#1[#2]#3{\par\addcontentsline{\csname + ext@#1\endcsname}{#1}{\protect\numberline{\csname + the#1\endcsname.}{\ignorespaces #2}}\begingroup + \@parboxrestore + \normalsize + \@makecaption{\csname fnum@#1\endcsname}{\ignorespaces #3}\par + \endgroup} + +% **************************************** +% * TABLE OF CONTENTS, ETC. * +% **************************************** + +\renewcommand\contentsname{Contents} +\renewcommand\listfigurename{Figures} +\renewcommand\listtablename{Tables} + +\newif\if@toc \@tocfalse +\renewcommand\tableofcontents{% + \begingroup% temporarily set if@toc so that \@schapter will not + % put Table of Contents in the table of contents. + \@toctrue + \chapter*{\contentsname} + \endgroup + \thispagestyle{gqtekspecplain} + + \baselineskip=10pt plus .5pt minus .5pt + + {\raggedleft Page \par\vskip-\parskip} + \@starttoc{toc}% + \baselineskip=\normalbaselineskip + } + +\def\l@appendix{\pagebreak[3] + \vskip 1.0em plus 1pt % space above appendix line + \@dottedtocline{0}{0em}{8em}} + +\def\l@chapter{\pagebreak[3] + \vskip 1.0em plus 1pt % space above appendix line + \@dottedtocline{0}{0em}{4em}} + +% \if@nosectnum\else + % \renewcommand\l@section{\@dottedtocline{1}{5.5em}{2.4em}} + % \renewcommand\l@subsection{\@dottedtocline{2}{8.5em}{3.2em}} + % \renewcommand\l@subsubsection{\@dottedtocline{3}{11em}{4.1em}} + % \renewcommand\l@paragraph{\@dottedtocline{4}{13.5em}{5em}} + % \renewcommand\l@subparagraph{\@dottedtocline{5}{16em}{6em}} +% \fi + +% LIST OF FIGURES +% +\def\listoffigures{% + \begingroup + \chapter*{\listfigurename}% + \endgroup + \thispagestyle{gqtekspecplain}% + + \baselineskip=10pt plus .5pt minus .5pt% + + {\hbox to \hsize{Figure\hfil Page} \par\vskip-\parskip}% + + \rule[2mm]{\textwidth}{0.5mm}\par + + \@starttoc{lof}% + \baselineskip=\normalbaselineskip}% + +\def\l@figure{\@dottedtocline{1}{1em}{4.0em}} + +% LIST OF TABLES +% +\def\listoftables{% + \begingroup + \chapter*{\listtablename}% + \endgroup + \thispagestyle{gqtekspecplain}% + \baselineskip=10pt plus .5pt minus .5pt% + {\hbox to \hsize{Table\hfil Page} \par\vskip-\parskip}% + + % Added line underneath headings, 20 Jun 01, Capt Todd Hale. + \rule[2mm]{\textwidth}{0.5mm}\par + + \@starttoc{lot}% + \baselineskip=\normalbaselineskip}% + +\let\l@table\l@figure + +% **************************************** +% * PAGE STYLES * +% **************************************** +% +\def\ps@gqtekspectoc{% + \let\@mkboth\@gobbletwo + \def \@oddhead{} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspectocn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} +\def\ps@gqtekspectocn{\let\@mkboth\@gobbletwo + \def \@oddhead{\rm \hfil\raisebox{10pt}{Page}} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspectocn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +\def\ps@gqtekspeclof{\let\@mkboth\@gobbletwo + \def \@oddhead{} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclofn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} +\def\ps@gqtekspeclofn{\let\@mkboth\@gobbletwo + \def \@oddhead{\rm + \parbox{\textwidth}{\raisebox{0pt}{Figure}\hfil\raisebox{0pt}{Page} % + \raisebox{20pt}{\rule[10pt]{\textwidth}{0.5mm}} }} + + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclofn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +\def\ps@gqtekspeclot{\let\@mkboth\@gobbletwo + \def \@oddhead{} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclotn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} +\def\ps@gqtekspeclotn{\let\@mkboth\@gobbletwo + \def \@oddhead{\rm + \parbox{\textwidth}{\raisebox{0pt}{Table}\hfil\raisebox{0pt}{Page} % + \raisebox{20pt}{\rule[10pt]{\textwidth}{0.5mm}} }} + + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclotn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +\def\ps@gqtekspecplain{\let\@mkboth\@gobbletwo + \def \@oddhead{\rput(0,-2pt){\psline(0,0)(\textwidth,0)}\rm \hbox to 1in{\includegraphics[height=0.8\headheight]{GT.eps} Gisselquist Technology, LLC}\hfil\hbox{\@title}\hfil\hbox to 1in{\hfil\headerdate\@date}} + \def \@oddfoot{\rput(0,9pt){\psline(0,0)(\textwidth,0)}\rm \hbox to 1in{www.opencores.com\hfil}\hfil\hbox{\r@vision}\hfil\hbox to 1in{\hfil{\thepage}}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +% \def\author#1{\def\auth@r{#1}} +% \def\title#1{\def\ti@tle{#1}} + +\def\logo{\begin{pspicture}(0,0)(5.67in,0.75in) + \rput[lb](0.05in,0.10in){\includegraphics[height=0.75in]{GT.eps}} + \rput[lb](1.15in,0.05in){\scalebox{1.8}{\parbox{2.0in}{Gisselquist\\Technology, LLC}}} + \end{pspicture}} +% TITLEPAGE +% +\def\titlepage{\setcounter{page}{1} + \typeout{^^JTitle Page.} + \thispagestyle{empty} + \leftline{\rput(0,0){\psline(0,0)(\textwidth,0)}\hfill} + \vskip 2\baselineskip + \logo\hfil % Original is 3.91 in x 1.26 in, let's match V thus + \vskip 2\baselineskip + \vspace*{10pt}\vfil + \begin{minipage}{\textwidth}\raggedleft + \ifproject{\Huge\bfseries\MakeUppercase\@project} \\\fi + \vspace*{15pt} + {\Huge\bfseries\MakeUppercase\@title} \\ + \vskip 10\baselineskip + \Large \@author \\ + \ifemail{\Large \@email}\\\fi + \vskip 6\baselineskip + \Large \usdate\@date \\ + \end{minipage} + % \baselineskip 22.5pt\large\rm\MakeUppercase\ti@tle + \vspace*{30pt} + \vfil + \newpage\baselineskip=\normalbaselineskip} + +\newenvironment{license}{\clearpage\typeout{^^JLicense Page.}\ \vfill\noindent}% + {\vfill\newpage} +% **************************************** +% * CHAPTER DEFINITIONS * +% **************************************** +% +\renewcommand\chapter{\if@openright\cleardoublepage\else\clearpage\fi + \thispagestyle{gqtekspecplain}% + \global\@topnum\z@ + \@afterindentfalse + \secdef\@chapter\@schapter} +\renewcommand\@makechapterhead[1]{% + \hbox to \textwidth{\hfil{\Huge\bfseries \thechapter.}}\vskip 10\p@ + \hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip \p@ + \hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip 10\p@ + \hbox to \textwidth{\hfill{\Huge\bfseries #1}}% + \par\nobreak\vskip 40\p@} +\renewcommand\@makeschapterhead[1]{% + \hbox to \textwidth{\hfill{\Huge\bfseries #1}}% + \par\nobreak\vskip 40\p@} +% **************************************** +% * INITIALIZATION * +% **************************************** +% +% Default initializations + +\ps@gqtekspecplain % 'gqtekspecplain' page style with lowered page nos. +\onecolumn % Single-column. +\pagenumbering{roman} % the first chapter will change pagenumbering + % to arabic +\setcounter{page}{1} % in case a titlepage is not requested + % otherwise titlepage sets page to 1 since the + % flyleaf is not counted as a page +\widowpenalty 10000 % completely discourage widow lines +\clubpenalty 10000 % completely discourage club (orphan) lines +\raggedbottom % don't force alignment of bottom of pages + +\date{\today} +\newif\ifproject\projectfalse +\def\project#1{\projecttrue\gdef\@project{#1}} +\def\@project{} +\newif\ifemail\emailfalse +\def\email#1{\emailtrue\gdef\@email{#1}} +\def\@email{} +\def\revision#1{\gdef\r@vision{#1}} +\def\r@vision{} +\def\at{\makeatletter @\makeatother} +\newdateformat{theyear}{\THEYEAR} +\newenvironment{revisionhistory}{\clearpage\typeout{^^JRevision History.}% + \hbox to \textwidth{\hfil\scalebox{1.8}{\large\bfseries Revision History}}\vskip 10\p@\noindent% + \begin{tabular}{|p{0.5in}|p{1in}|p{1in}|p{2.875in}|}\hline + \rowcolor[gray]{0.8} Rev. & Date & Author & Description\\\hline\hline} + {\end{tabular}\clearpage} +\newenvironment{clocklist}{\begin{tabular}{|p{0.75in}|p{0.5in}|l|l|p{2.875in}|}\hline + \rowcolor[gray]{0.85} Name & Source & \multicolumn{2}{l|}{Rates (MHz)} & Description \\\hhline{~|~|-|-|~}% + \rowcolor[gray]{0.85} & & Max & Min & \\\hline\hline}% + {\end{tabular}} +\newenvironment{reglist}{\begin{tabular}{|p{0.75in}|p{0.5in}|p{0.5in}|p{0.5in}|p{2.875in}|}\hline + \rowcolor[gray]{0.85} Name & Address & Width & Access & Description \\\hline\hline}% + {\end{tabular}} +\newenvironment{bitlist}{\begin{tabular}{|p{0.5in}|p{0.5in}|p{3.875in}|}\hline + \rowcolor[gray]{0.85} Bit \# & Access & Description \\\hline\hline}% + {\end{tabular}} +\newenvironment{portlist}{\begin{tabular}{|p{0.75in}|p{0.5in}|p{0.75in}|p{3.375in}|}\hline + \rowcolor[gray]{0.85} Port & Width & Direction & Description \\\hline\hline}% + {\end{tabular}} +\newenvironment{wishboneds}{\begin{tabular}{|p{2.5in}|p{2.5in}|}\hline + \rowcolor[gray]{0.85} Description & Specification \\\hline\hline}% + {\end{tabular}} +\newenvironment{preface}{\chapter*{Preface}}{\par\bigskip\bigskip\leftline{\hfill\@author}} +\endinput Index: doc/src/spec.tex =================================================================== --- doc/src/spec.tex (nonexistent) +++ doc/src/spec.tex (revision 2) @@ -0,0 +1,257 @@ +\documentclass{gqtekspec} +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% +%% Filename: spec.tex +%% +%% Project: A wishbone controlled DDR3 SDRAM memory controller. +%% +%% Purpose: This LaTeX file contains all of the documentation, or should I +%% say all of the description necessary to produce the +%% documentation, currently provided with the Wishbone controlled DDR3 +%% SDRAM core. For those interested in this core, this file is not nearly +%% as interesting as the PDF file this file is used to create. Therefore, +%% I recommend building and then reading that pdf file, spec.pdf, before +%% diving into what's going on within this file. You should be able to +%% find the pdf file in this SVN distribution, together with this LaTeX +%% file and a copy of the GPL-3.0 license this file is distributed under. +%% If not, just type 'make' in the doc directory and it (should) build the +%% pdf file without a problem. (This, of course, assumes you have a valid +%% and working LaTeX distribution, together with dvips and Ghostscript.) +%% +%% +%% Creator: Dan Gisselquist, Ph.D. +%% Gisselquist Technology, LLC +%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% +%% Copyright (C) 2015-2016, Gisselquist Technology, LLC +%% +%% This program is free software (firmware): you can redistribute it and/or +%% modify it under the terms of the GNU General Public License as published +%% by the Free Software Foundation, either version 3 of the License, or (at +%% your option) any later version. +%% +%% This program is distributed in the hope that it will be useful, but WITHOUT +%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +%% for more details. +%% +%% You should have received a copy of the GNU General Public License along +%% with this program. (It's in the $(ROOT)/doc directory, run make with no +%% target there if the PDF file isn't present.) If not, see +%% for a copy. +%% +%% License: GPL, v3, as defined and found on www.gnu.org, +%% http://www.gnu.org/licenses/gpl.html +%% +%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% +%% +\usepackage{import} +\project{WB DDR3 SDRAM Controller} +\title{Specification} +\author{Dan Gisselquist, Ph.D.} +\email{dgisselq (at) opencores.org} +\revision{Rev.~0.0} +\begin{document} +\pagestyle{gqtekspecplain} +\titlepage +\begin{license} +Copyright (C) \theyear\today, Owner + +This project is free software (firmware): you can redistribute it and/or +modify it under the terms of the GNU General Public License as published +by the Free Software Foundation, either version 3 of the License, or (at +your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy. +\end{license} +\begin{revisionhistory} +0.0 & 6/20/2016 & D. Gisselquist & Initial Version\\\hline +\end{revisionhistory} +% Revision History +% Table of Contents, named Contents +\tableofcontents +\listoffigures +\listoftables +\begin{preface} +Now, just why am I building this? Because wishbone's been so good to me? +Because I've never used AXI? Because I dislike not being able to see +what goes on within a memory controller, and have no insight into why it's +performance is as fast (or slow) as it is? Because Xilinx allows you to only +open 4 banks at a tim? Or is it because, when I went to purchase my first +high speed FPGA circuit board, the vendor offered me the opportunity to +purchase a DMA controller with it? As a micro businessman, I really can't +afford using someone else's stuff. Time is cheap, money isn't nearly so cheap. + +Hence, I offer my work to you as well. I hope you find it useful. Of course, +the normal caveats are available: I am available for hire, and I would be happy +to modify this core or even the license it is distributed under, for an +appropriate incentive. +\end{preface} + +\chapter{Introduction} +\pagenumbering{arabic} +\setcounter{page}{1} + +% +% Introduction +% +% This section contains the introduction to the core, describing both its +% use and its features. +% +The purpose of this core is to provide a GPL Wishbone Core capable of commanding +a DDR3 memory at full speed. A particular design goal is that consecutive +reads or writes should only take one additional clock per read/write. + +% What is old +Since the DDR3 memory specification is dated as of August, 2009, memory chips +have been built to this specification. However, since DDR3 SDRAM's are rather +complex, and there is a lot of work required to manage them, controllers for +DDR3 SDRAM's remain primarily in the realm of proprietary. + +% What does the old lack? +Currently, there are no DDR3 controllers present on OpenCores. Sure, +there's a project named ``DDR3 SDRAM controller'', yet it has no data files +present with it. This leaves the FPGA engineers with the choice of building +a controller for a very complex interface, or using a proprietary core from +Xilinx's Memory Interface Generator, for which there is no insight into how it +works, and then retooling their bus from wishbone to AXI. + +% What is new +This core is designed to meet that need: it is both open (GPL), as well as +wishbone compliant. +% What does the new have that the old lacks +Further, this core offers 32--bit granularity to an interface that would +otherwise offer only 128--bit granularity. This core also offers complete +pipelind performance. +% What performance gain can be expected? +Because of the pipeline performance, this core is very appropriate for filling +cache lines. Because the core also offers non--pipelined performance, it is +also appropriate for random access from a CPU--whether by a write--through cache +or a CPU working without a cache. + +\chapter{Architecture} + +% This section describes the architecture of the block. A block level diagram +% should be included describing the top level of the design. + +\chapter{Operation} + +% This section describes the operation of the core. Specific sequences, such +% as startup sequences, as well as the modes and states of the block should be +% described. +% + +When accessed from within an FPGA, this core should be simple to access: +Raise the {\tt i\_wb\_cyc} line at the beginning of every transaction. +Set {\tt i\_wb\_stb} (transaction strobe), {\tt i\_wb\_we} (Write enable, +true if writing or false otherwise), {\tt i\_wb\_addr} (address of value), +and {\tt i\_wb\_data} for every transaction. You may move to the next +transaction any time {\tt i\_wb\_stb} is true on the same clock that +{\tt o\_wb\_stall} is false. Transactions will be pipelined internally. When +{\tt o\_wb\_ack} is true, a transaction has completed. If that transaction +was a read transaction, {\tt o\_wb\_data}, will also be filled with the data +read from the memory device. + +\chapter{Clocks} + +% This section specifies all of the clocks. All clocks, clock domain passes +% and the clock relations should be described. + +% Name | Source | Rates (MHz) | Remarks | Description +% | Max|Min|Resolution| + +This design is centered around a DDR-1600 chip. In order to run this chip +at speed, it requires a 200MHz clock. Xilinx recommends a 160~MHz clock for +their design, so it should work at slower rates--I just don't know how much +slower the design will continue to work for. + +If you wish to slow down the design, adjust the parameter {\tt CKREFI4} to be +the number of clocks expected in four timse 7.8~$\mu$s. + +\chapter{Wishbone Datasheet}\label{chap:wishbone} +Tbl.~\ref{tbl:wishbone} +\begin{table}[htbp] +\begin{center} +\begin{wishboneds} +Revision level of wishbone & WB B4 spec \\\hline +Type of interface & Slave, Read/Write, pipeline mode supported \\\hline +Port size & 32--bit \\\hline +Port granularity & 32--bit \\\hline +Maximum Operand Size & 32--bit \\\hline +Data transfer ordering & (Irrelevant) \\\hline +Clock constraints & Designed for 200MHz, DDR1600\\\hline +Signal Names & \begin{tabular}{ll} + Signal Name & Wishbone Equivalent \\\hline + {\tt i\_wb\_clk} & {\tt CLK\_I} \\ + {\tt i\_wb\_cyc} & {\tt CYC\_I} \\ + {\tt i\_wb\_stb} & {\tt STB\_I} \\ + {\tt i\_wb\_we} & {\tt WE\_I} \\ + {\tt i\_wb\_addr} & {\tt ADR\_I} \\ + {\tt i\_wb\_data} & {\tt DAT\_I} \\ + {\tt o\_wb\_ack} & {\tt ACK\_O} \\ + {\tt o\_wb\_stall} & {\tt STALL\_O} \\ + {\tt o\_wb\_data} & {\tt DAT\_O} + \end{tabular}\\\hline +\end{wishboneds} +\caption{Wishbone Datasheet}\label{tbl:wishbone} +\end{center}\end{table} +is required by the wishbone specification, and so +it is included here. The big thing to notice is that all accesses to the +DDR3 SDRAM memory are via 32--bit reads and writes to this interface. You may +also wish to note that the scope supports pipeline reading and writing, to +speed up reading the results out. As a result, the memory interface speed +should approach one transfer per clock once the pipeline is loaded, although +there will be delays loading the pipeline. + +Further, the Wishbone specification this core communicates with has been +simplified in this manner: The {\tt STB\_I} signal has been constrained so that +it will only be true if {\tt CYC\_I} is also true. To interface this core +in an environment without this requirement, simply create the {\tt i\_wb\_stb} +by anding {\tt STB\_I} together with {\tt CYC\_I} before sending the strobe +logic into the core. + +\chapter{I/O Ports} +% This section specifies all of the core IO ports + +The wishbone ports to this core were discussed in the last chapter, and shown +in Tbl.~\ref{tbl:wishbone}. The rest of the I/O ports to this core are listed +in Tbl.~\ref{tbl:ioports}. +\begin{table}[htbp] +\begin{center} +\begin{portlist} +{\tt i\_clk\_200mhz} & 1 & Output & A 200 MHz clock input \\ +{\tt o\_ddr\_reset\_n} & 1 & Output & Active low reset command to the chip\\ +{\tt o\_ddr\_cke} & 1 & Output & Clock Enable \\ +{\tt o\_ddr\_cs\_n} & 1 & Output & Chip select\\ +{\tt o\_ddr\_ras\_n} & 1 & Output & RAS\# Command input \\ +{\tt o\_ddr\_cas\_n} & 1 & Output & RAS\# Command input \\ +{\tt o\_ddr\_we\_n} & 1 & Output & WE\# Command input \\ +{\tt o\_ddr\_dqs} & 1 & Output & True if the FPGA should drive the DQS on this clock, false otherwise. While not a DDR output, this needs to be converted to a DDR 2'b10 (if true) before it leaves the FPGA, or high impedence if false. \\ +{\tt o\_ddr\_dm} & 3 & Output & Data Mask, used to enable only those valid writes. Although a DDR output, we treat it as SDR since all transactions are 32--bits (or more).\\ +{\tt o\_ddr\_odt} & 1 & Output & On--Die--Termination bit. This will be true any time the data lines are being driven\\ +{\tt o\_ddr\_bus\_dir} & 1 & Output & True if the FPGA will be driving the data bus lines during this clock, false otherwise\\ +{\tt o\_ddr\_ba} & 3 & Output & Bank Address, 0-7\\ +{\tt o\_ddr\_addr} & 16 & Output & Command address, either row or column\\ +{\tt o\_ddr\_data} & 32 & Output & The output to be sent to the chip. This will need to be bumped to DDR rates before it actually hits the chip. \\ +{\tt i\_ddr\_data} & 32 & Input & The data input from the chip. This comes in at DDR rates, and needs a Xilinx primitive to bring it from 16'bits to 32'bits.\\ +\end{portlist} +\caption{List of IO ports that are not Wishbone Related}\label{tbl:ioports} +\end{center}\end{table} + +% Appendices +% A. May be added to outline different specifications. (??) + + +% Index +\end{document} + + Index: doc/gpl-3.0.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/gpl-3.0.pdf =================================================================== --- doc/gpl-3.0.pdf (nonexistent) +++ doc/gpl-3.0.pdf (revision 2)
doc/gpl-3.0.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/Makefile =================================================================== --- doc/Makefile (nonexistent) +++ doc/Makefile (revision 2) @@ -0,0 +1,83 @@ +################################################################################ +## +## Filename: Makefile +## +## Project: A wishbone controlled DDR3 SDRAM memory controller. +## +## Purpose: To coordinate the build of documentation PDFs from their +## LaTeX sources. +## +## Targets include: +## all Builds all documents +## +## gpl-3.0.pdf Builds the GPL license these files are released +## under. +## +## spec.pdf Builds the specification for the SDSPI +## controller. +## +## Creator: Dan Gisselquist, Ph.D. +## Gisselquist Technology, LLC +## +################################################################################ +## +## Copyright (C) 2015-2016, Gisselquist Technology, LLC +## +## This program is free software (firmware): you can redistribute it and/or +## modify it under the terms of the GNU General Public License as published +## by the Free Software Foundation, either version 3 of the License, or (at +## your option) any later version. +## +## This program is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with this program. (It's in the $(ROOT)/doc directory, run make with no +## target there if the PDF file isn't present.) If not, see +## for a copy. +## +## License: GPL, v3, as defined and found on www.gnu.org, +## http://www.gnu.org/licenses/gpl.html +## +## +################################################################################ +## +## +all: gpl spec +pdf: gpl spec +DSRC := src + +.PHONY: gpl +gpl: gpl-3.0.pdf + +gpl-3.0.pdf: $(DSRC)/gpl-3.0.tex + latex $(DSRC)/gpl-3.0.tex + latex $(DSRC)/gpl-3.0.tex + dvips -q -z -t letter -P pdf -o gpl-3.0.ps gpl-3.0.dvi + ps2pdf -dAutoRotatePages=/All gpl-3.0.ps gpl-3.0.pdf + rm gpl-3.0.dvi gpl-3.0.log gpl-3.0.aux gpl-3.0.ps + +.PHONY: spec +spec: spec.pdf + +spec.pdf: $(DSRC)/spec.tex $(DSRC)/gqtekspec.cls $(DSRC)/GT.eps + cd $(DSRC)/; latex spec.tex + cd $(DSRC)/; latex spec.tex + cd $(DSRC)/; dvips -q -z -t letter -P pdf -o ../spec.ps spec.dvi + ps2pdf -dAutoRotatePages=/All spec.ps spec.pdf + -grep -i warning $(DSRC)/spec.log + @rm -f $(DSRC)/spec.dvi $(DSRC)/spec.log + @rm -f $(DSRC)/spec.aux $(DSRC)/spec.toc + @rm -f $(DSRC)/spec.lot $(DSRC)/spec.lof + @rm -f $(DSRC)/spec.out spec.ps + +.PHONY: clean +clean: + rm -f $(DSRC)/spec.dvi $(DSRC)/spec.log + rm -f $(DSRC)/spec.aux $(DSRC)/spec.toc + rm -f $(DSRC)/spec.lot $(DSRC)/spec.lof + rm -f $(DSRC)/spec.out spec.ps spec.pdf + rm -f gpl-3.0.pdf + Index: Makefile =================================================================== --- Makefile (nonexistent) +++ Makefile (revision 2) @@ -0,0 +1,56 @@ +################################################################################ +## +## Filename: Makefile +## +## Project: A wishbone controlled DDR3 SDRAM memory controller. +## +## Purpose: To coordinate the master build of the project. This includes +## the Verilator simulation, the test bench, and then the run of +## the testbench itself. +## +## Creator: Dan Gisselquist, Ph.D. +## Gisselquist Technology, LLC +## +################################################################################ +## +## Copyright (C) 2015-2016, Gisselquist Technology, LLC +## +## This program is free software (firmware): you can redistribute it and/or +## modify it under the terms of the GNU General Public License as published +## by the Free Software Foundation, either version 3 of the License, or (at +## your option) any later version. +## +## This program is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with this program. (It's in the $(ROOT)/doc directory, run make with no +## target there if the PDF file isn't present.) If not, see +## for a copy. +## +## License: GPL, v3, as defined and found on www.gnu.org, +## http://www.gnu.org/licenses/gpl.html +## +## +################################################################################ +## +## +all: rtl bench test + +.PHONY: doc +doc: + cd doc; $(MAKE) --no-print-directory + +.PHONY: rtl +rtl: + cd rtl; $(MAKE) --no-print-directory + +.PHONY: bench +bench: + cd bench/cpp; $(MAKE) --no-print-directory wbddr3_tb + +.PHONY: test +test: + cd bench/cpp; $(MAKE) --no-print-directory test

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