URL
https://opencores.org/ocsvn/wbddr3/wbddr3/trunk
Subversion Repositories wbddr3
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- This comparison shows the changes necessary to convert path
/wbddr3/trunk
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/rtl/wbddrsdram.v
93,15 → 93,16
output reg o_wb_stall; |
output reg [31:0] o_wb_data; |
// DDR3 RAM Controller |
output wire o_ddr_reset_n, o_ddr_cke; |
output reg o_ddr_reset_n, o_ddr_cke; |
// Control outputs |
output reg o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n; |
output wire o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n; |
// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow |
output wire o_ddr_dqs; |
output reg o_ddr_dm, o_ddr_odt, o_ddr_bus_oe; |
output reg o_ddr_dm; |
output wire o_ddr_odt, o_ddr_bus_oe; |
// Address outputs |
output reg [13:0] o_ddr_addr; |
output reg [2:0] o_ddr_ba; |
output wire [13:0] o_ddr_addr; |
output wire [2:0] o_ddr_ba; |
// And the data inputs and outputs |
output reg [31:0] o_ddr_data; |
input [31:0] i_ddr_data; |
214,11 → 215,6
reset_override <= 1'b0; |
reset_cmd <= reset_instruction[20:0]; |
end |
always @(posedge i_clk) |
if (i_reset) |
o_ddr_cke <= 1'b0; |
else if ((reset_override)&&(reset_ztimer)) |
o_ddr_cke <= reset_instruction[`DDR_CKEBIT]; |
|
initial reset_ztimer = 1'b0; // Is the timer zero? |
initial reset_timer = 17'h02; |
473,7 → 469,7
|
always @(posedge i_clk) |
if (reset_override) |
refresh_instruction <= { 3'h0, `DDR_NOOP, w_ckREFIn }; |
refresh_cmd <= { 3'h0, `DDR_NOOP, w_ckREFIn }; |
else if (refresh_ztimer) |
refresh_cmd <= refresh_instruction[20:0]; |
always @(posedge i_clk) |
651,7 → 647,6
&&(bank_status[r_bank][0] == 1'b1) |
&&(bank_status[r_nxt_bank][1:0] == 2'b00) |
&&(!w_this_maybe_open)&&(!last_maybe_open); |
last_maybe_open <= (w_this_maybe_open); |
|
activate_bank_cmd<= { `DDR_ACTIVATE, r_bank, r_row[13:0] }; |
maybe_open_cmd <= { `DDR_ACTIVATE,r_nxt_bank, r_nxt_row[13:0] }; |