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URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

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  • This comparison shows the changes necessary to convert path 
    /wbddr3/trunk
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/bench/cpp/ddrsdramsim.h
53,7 → 53,7
class BANKINFO {
public:
int m_state;
unsigned m_row;
unsigned m_row, m_wcounter;
void tick(int cmd, unsigned addr=0);
};
 
/bench/cpp/ddrsdram_tb.cpp
98,7 → 98,7
(m_core->i_wb_stb)?"STB":" ",
(m_core->o_wb_stall)?"STALL":" ",
(m_core->o_wb_ack)?"ACK":" ",
(m_core->o_cmd_accepted)?"BUS":" ",
"", // (m_core->o_cmd_accepted)?"BUS":" ",
(m_core->i_wb_we)?"W":"R",
(m_core->i_wb_addr),
(m_core->i_wb_data),
456,6 → 456,7
printf("Charging my memory with random values\n");
uload(mlen, rdbuf);
 
#define CASE_TESTS
#define SINGULAR_WRITE
#define SINGULAR_READ
#define BIGPIPELINE_WRITE
465,6 → 466,45
#define SKIP_WRITE
#define SKIP_READ
 
#ifdef CASE_TESTS
{
unsigned v;
for(int i=0; i<8; i++) {
tb->wb_write(i, rdbuf[i]);
if ((v=tb->wb_read(i)) != rdbuf[i]) {
printf("CASE-1, %08x -> MEM[%08x] -> %08x FAILED (R/W not equal)\n", rdbuf[i], i, v);
goto test_failure;
}
}
}
 
// Now repeat, hitting a different bank with each command
{
unsigned v, a;
for(int i=0; i<8; i++) {
a = 1087 + i*1031;
tb->wb_write(a, rdbuf[a]);
if ((v=tb->wb_read(a)) != rdbuf[a]) {
printf("CASE-1, %08x -> MEM[%08x] -> %08x FAILED (R/W not equal)\n", rdbuf[a], a, v);
goto test_failure;
}
}
}
 
// And again, hitting the same bank with each command
{
unsigned v, a;
for(int i=0; i<8; i++) {
a = 1109 + i*1024;
tb->wb_write(a, rdbuf[a]);
if ((v=tb->wb_read(a)) != rdbuf[a]) {
printf("CASE-1, %08x -> MEM[%08x] -> %08x FAILED (R/W not equal)\n", rdbuf[a], a, v);
goto test_failure;
}
}
}
#endif
 
#ifdef SINGULAR_WRITE
// First test: singular reads through the memory, followed by
// singular writes
/bench/cpp/ddrsdramsim.cpp
48,6 → 48,8
 
#include "ddrsdramsim.h"
void BANKINFO::tick(int cmd, unsigned addr) {
if (m_wcounter)
m_wcounter--;
switch(cmd) {
case DDR_PRECHARGE:
m_state = 6;
59,10 → 61,15
// refresh logic.
break;
case DDR_ACTIVATE:
assert(m_wcounter == 0);
m_state = 1;
m_row = addr & 0x7fff;
break;
case DDR_READ: case DDR_WRITE:
if (DDR_READ)
assert(m_wcounter == 0);
else
m_wcounter = 3+4+4;
printf("BANK::R/W Request, m_state = %d\n", m_state);
assert((m_state&7) == 7);
break;
/rtl/wbddrsdram.v
82,6 → 82,7
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
parameter CKREFI4 = 13'd6240, // 4 * 7.8us at 200 MHz clock
CKRFC = 320,
CKWR = 3,
CKXPR = CKRFC+5+2; // Clocks per tXPR timeout
input i_clk, i_reset;
// Wishbone inputs
158,6 → 159,8
w_this_maybe_close, w_this_maybe_open,
w_this_rw_move;
reg last_closing_bank, last_opening_bank;
wire w_need_close_this_bank, w_need_open_bank,
w_r_valid, w_s_valid;
//
// tWTR = 7.5
// tRRD = 7.5
340,7 → 343,12
reg banks_are_closing, all_banks_closed;
reg [3:0] bank_status [0:7];
reg [13:0] bank_address [0:7];
reg [3:0] bank_wr_ck [0:7]; // tWTR
reg bank_wr_ckzro [0:7]; // tWTR
 
wire [3:0] write_recycle_clocks;
assign write_recycle_clocks = CKWR+4+4;
 
always @(posedge i_clk)
begin
bank_status[0] <= { bank_status[0][2:0], bank_status[0][0] };
359,6 → 367,29
&&(bank_status[5][2:0] == 3'b00)
&&(bank_status[6][2:0] == 3'b00)
&&(bank_status[7][2:0] == 3'b00);
 
bank_wr_ck[0] <= (|bank_wr_ck[0])?(bank_wr_ck[0]-4'h1):4'h0;
bank_wr_ck[1] <= (|bank_wr_ck[1])?(bank_wr_ck[1]-4'h1):4'h0;
bank_wr_ck[2] <= (|bank_wr_ck[2])?(bank_wr_ck[2]-4'h1):4'h0;
bank_wr_ck[3] <= (|bank_wr_ck[3])?(bank_wr_ck[3]-4'h1):4'h0;
bank_wr_ck[4] <= (|bank_wr_ck[4])?(bank_wr_ck[4]-4'h1):4'h0;
bank_wr_ck[5] <= (|bank_wr_ck[5])?(bank_wr_ck[5]-4'h1):4'h0;
bank_wr_ck[6] <= (|bank_wr_ck[6])?(bank_wr_ck[6]-4'h1):4'h0;
bank_wr_ck[7] <= (|bank_wr_ck[7])?(bank_wr_ck[7]-4'h1):4'h0;
 
bank_wr_ckzro[0] <= (bank_wr_ck[0][3:1]==3'b00);
bank_wr_ckzro[1] <= (bank_wr_ck[1][3:1]==3'b00);
bank_wr_ckzro[2] <= (bank_wr_ck[2][3:1]==3'b00);
bank_wr_ckzro[3] <= (bank_wr_ck[3][3:1]==3'b00);
bank_wr_ckzro[4] <= (bank_wr_ck[4][3:1]==3'b00);
bank_wr_ckzro[5] <= (bank_wr_ck[5][3:1]==3'b00);
bank_wr_ckzro[6] <= (bank_wr_ck[6][3:1]==3'b00);
bank_wr_ckzro[7] <= (bank_wr_ck[7][3:1]==3'b00);
 
if (w_this_rw_move)
bank_wr_ck[rw_cmd[16:14]] <= (rw_cmd[`DDR_WEBIT])? 4'h0
: write_recycle_clocks;
 
if (reset_override)
begin
bank_status[0][0] <= 1'b0;
469,7 → 500,7
 
always @(posedge i_clk)
if (reset_override)
refresh_cmd <= { 3'h0, `DDR_NOOP, w_ckREFIn };
refresh_cmd <= { `DDR_NOOP, w_ckREFIn };
else if (refresh_ztimer)
refresh_cmd <= refresh_instruction[20:0];
always @(posedge i_clk)
606,9 → 637,8
end
end
 
wire w_need_close_this_bank, w_need_open_bank,
w_r_valid, w_s_valid;
assign w_need_close_this_bank = (r_pending)&&(bank_status[r_bank][0])
&&(bank_wr_ckzro[r_bank])
&&(r_row != bank_address[r_bank])
||(pipe_stall)&&(s_pending)&&(bank_status[s_bank][0])
&&(s_row != bank_address[s_bank]);
617,10 → 647,12
assign w_r_valid = (!need_refresh)&&(r_pending)
&&(bank_status[r_bank][3])
&&(bank_address[r_bank]==r_row)
&&((r_we)||(bank_wr_ckzro[r_bank]))
&&(!bus_active[0]);
assign w_s_valid = (!need_refresh)&&(s_pending)
&&(bank_status[s_bank][3])
&&(bank_address[s_bank]==s_row)
&&((r_we)||(bank_wr_ckzro[s_bank]))
&&(!bus_active[0]);
 
always @(posedge i_clk)
632,6 → 664,7
 
maybe_close_next_bank <= (r_pending)
&&(bank_status[r_nxt_bank][0])
&&(bank_wr_ckzro[r_nxt_bank])
&&(r_nxt_row != bank_address[r_nxt_bank])
&&(!w_this_maybe_close)&&(!last_maybe_close);
 

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