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URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

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  • This comparison shows the changes necessary to convert path 
    /wbddr3/trunk
    from Rev 9 to Rev 10
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Rev 9 → Rev 10

/bench/cpp/ddrsdram_tb.cpp
162,7 → 162,7
(m_core->v__DOT__s_col),
(m_core->v__DOT__s_sub),
(m_core->v__DOT__s_data),
(m_core->v__DOT__s_match)?"M":" ",
(m_core->v__DOT__w_s_match)?"M":" ",
(m_core->v__DOT__pipe_stall)?"P":" ",
"-"
//(m_core->v__DOT__s_stall)?"S":" "
/rtl/wbddrsdram.v
6,24 → 6,6
//
// Purpose:
//
/*
Stall logic:
1. First clock sets r_* variables.
2. Second clock sets need_* variables. If need_open, need_close, or
need_refresh are true, that should also set the o_wb_stall
variable. Well also move r_* info to s_* (think s=stall)
3. If stalled, the next command comes from s_*. Otherwise, from r_*.
4. Bus FIFO fills from s_*
//
//
For every transaction, one of 4 possibilities:
1. Wait for refresh to complete
2. Wait for precharge and activate to complete
3. Wait for activate to complete
4. Issue RW cmd
5. Wait for bus transaction to complete
6. ACK
*/
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
97,8 → 79,7
o_ddr_reset_n, o_ddr_cke,
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data,
o_cmd_accepted);
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
parameter CKREFI4 = 13'd6240, // 4 * 7.8us at 200 MHz clock
CKRFC = 320,
CKXPR = CKRFC+5+2; // Clocks per tXPR timeout
124,12 → 105,7
// And the data inputs and outputs
output reg [31:0] o_ddr_data;
input [31:0] i_ddr_data;
// And just for the test bench
output reg o_cmd_accepted;
 
always @(posedge i_clk)
o_cmd_accepted <= (i_wb_stb)&&(~o_wb_stall);
 
reg drive_dqs;
 
// The pending transaction
146,7 → 122,7
// the stage where the read/write command is actually given to the
// interface if we haven't stalled.
reg [31:0] s_data;
reg s_pending, s_we, s_match;
reg s_pending, s_we; // , s_match;
reg [25:0] s_addr;
reg [13:0] s_row, s_nxt_row;
reg [2:0] s_bank, s_nxt_bank;
630,7 → 606,7
s_nxt_row <= r_nxt_row;
s_nxt_bank <= r_nxt_bank;
 
s_match <= w_s_match;
// s_match <= w_s_match;
end
end
 
654,6 → 630,8
always @(posedge i_clk)
begin
need_close_bank <= (w_need_close_this_bank)
&&(!need_open_bank)
&&(!need_close_bank)
&&(!w_this_closing_bank)&&(!last_closing_bank);
 
maybe_close_next_bank <= (r_pending)
807,7 → 785,9
bus_fifo_tail <= 4'h0;
o_ddr_dm <= 1'b0;
end else begin
if ((w_this_rw_move)||((s_pending)&&(s_match)&&(!pipe_stall)))
if
//((w_this_rw_move)||((s_pending)&&(s_match)&&(!pipe_stall)))
((s_pending)&&(!pipe_stall))
bus_fifo_head <= bus_fifo_head + 4'h1;
 
o_ddr_dm <= (bus_active[`BUSREG])&&(!bus_read[`BUSREG]);

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