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///////////////////////////////////////////////////////////////////////////
//
// Filename: wbscope.v
//
// Project: FPGA Library of Routines
//
// Purpose: This is a generic/library routine for providing a bus accessed
// 'scope' or (perhaps more appropriately) a bus accessed logic
// analyzer. The general operation is such that this 'scope' can
// record and report on any 32 bit value transiting through the
// FPGA. Once started and reset, the scope records a copy of the
// input data every time the clock ticks with the circuit enabled.
// That is, it records these values up until the trigger. Once
// the trigger goes high, the scope will record for bw_holdoff
// more counts before stopping. Values may then be read from the
// buffer, oldest to most recent. After reading, the scope may
// then be reset for another run.
//
// In general, therefore, operation happens in this fashion:
// 1. A reset is issued.
// 2. Recording starts, in a circular buffer, and continues until
// 3. The trigger line is asserted.
// The scope registers the asserted trigger by setting
// the 'o_triggered' output flag.
// 4. A counter then ticks until the last value is written
// The scope registers that it has stopped recording by
// setting the 'o_stopped' output flag.
// 5. The scope recording is then paused until the next reset.
// 6. While stopped, the CPU can read the data from the scope
// 7. -- oldest to most recent
// 8. -- one value per i_rd&i_clk
// 9. Writes to the data register reset the address to the
// beginning of the buffer
//
// Although the data width DW is parameterized, it is not very changable,
// since the width is tied to the width of the data bus, as is the
// control word. Therefore changing the data width would require changing
// the interface. It's doable, but it would be a change to the interface.
//
// The SYNCHRONOUS parameter turns on and off meta-stability
// synchronization. Ideally a wishbone scope able to handle one or two
// clocks would have a changing number of ports as this SYNCHRONOUS
// parameter changed. Other than running another script to modify
// this, I don't know how to do that so ... we'll just leave it running
// off of two clocks or not.
//
//
// Internal to this routine, registers and wires are named with one of the
// following prefixes:
//
// i_ An input port to the routine
// o_ An output port of the routine
// br_ A register, controlled by the bus clock
// dr_ A register, controlled by the data clock
// bw_ A wire/net, controlled by the bus clock
// dw_ A wire/net, controlled by the data clock
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
/////////////////////////////////////////////////////////////////////////////
module wbscope(i_clk, i_ce, i_trigger, i_data,
i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
o_wb_ack, o_wb_stall, o_wb_data,
o_interrupt);
parameter LGMEM = 5'd10, BUSW = 32, SYNCHRONOUS=1;
// The input signals that we wish to record
input i_clk, i_ce, i_trigger;
input [(BUSW-1):0] i_data;
// The WISHBONE bus for reading and configuring this scope
input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
input i_wb_addr; // One address line only
input [(BUSW-1):0] i_wb_data;
output wire o_wb_ack, o_wb_stall;
output reg [(BUSW-1):0] o_wb_data;
// And, finally, for a final flair --- offer to interrupt the CPU after
// our trigger has gone off. This line is equivalent to the scope
// being stopped. It is not maskable here.
output wire o_interrupt;
 
reg [(LGMEM-1):0] raddr;
reg [(BUSW-1):0] mem[0:((1<<LGMEM)-1)];
 
// Our status/config register
wire bw_reset_request, bw_manual_trigger,
bw_disable_trigger, bw_reset_complete;
reg [22:0] br_config;
wire [19:0] bw_holdoff;
initial br_config = ((1<<(LGMEM-1))-4);
always @(posedge i_wb_clk)
if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr))
begin
if (i_wb_we)
br_config <= { i_wb_data[31],
(i_wb_data[27]),
i_wb_data[26],
i_wb_data[19:0] };
end else if (bw_reset_complete)
br_config[22] <= 1'b1;
assign bw_reset_request = (~br_config[22]);
assign bw_manual_trigger = (br_config[21]);
assign bw_disable_trigger = (br_config[20]);
assign bw_holdoff = br_config[19:0];
 
wire dw_reset, dw_manual_trigger, dw_disable_trigger;
generate
if (SYNCHRONOUS > 0)
begin
assign dw_reset = bw_reset_request;
assign dw_manual_trigger = bw_manual_trigger;
assign dw_disable_trigger = bw_disable_trigger;
assign bw_reset_complete = bw_reset_request;
end else begin
reg r_reset_complete;
reg [2:0] r_iflags, q_iflags;
 
// Resets are synchronous to the bus clock, not the data clock
// so do a clock transfer here
initial q_iflags = 3'b000;
initial r_reset_complete = 1'b0;
always @(posedge i_clk)
begin
q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger };
r_iflags <= q_iflags;
r_reset_complete <= (dw_reset);
end
 
assign dw_reset = r_iflags[2];
assign dw_manual_trigger = r_iflags[1];
assign dw_disable_trigger = r_iflags[0];
 
reg q_reset_complete, qq_reset_complete;
// Pass an acknowledgement back from the data clock to the bus
// clock that the reset has been accomplished
initial q_reset_complete = 1'b0;
initial qq_reset_complete = 1'b0;
always @(posedge i_wb_clk)
begin
q_reset_complete <= r_reset_complete;
qq_reset_complete <= q_reset_complete;
end
 
assign bw_reset_complete = qq_reset_complete;
end endgenerate
 
//
// Set up the trigger
//
//
// Write with the i-clk, or input clock. All outputs read with the
// WISHBONE-clk, or i_wb_clk clock.
reg dr_triggered, dr_primed;
wire dw_trigger;
assign dw_trigger = (dr_primed)&&(
((i_trigger)&&(~dw_disable_trigger))
||(dr_triggered)
||(dw_manual_trigger));
initial dr_triggered = 1'b0;
always @(posedge i_clk)
if (dw_reset)
dr_triggered <= 1'b0;
else if ((i_ce)&&(dw_trigger))
dr_triggered <= 1'b1;
 
//
// Determine when memory is full and capture is complete
//
// Writes take place on the data clock
reg dr_stopped;
reg [19:0] counter; // This is unsigned
initial dr_stopped = 1'b0;
initial counter = 20'h0000;
always @(posedge i_clk)
if (dw_reset)
begin
counter <= 0;
dr_stopped <= 1'b0;
end else if ((i_ce)&&(dr_triggered))
begin // MUST BE a < and not <=, so that we can keep this w/in
// 20 bits. Else we'd need to add a bit to comparison
// here.
if (counter < bw_holdoff)
counter <= counter + 1;
else
dr_stopped <= 1'b1;
end
 
//
// Actually do our writes to memory. Record, via 'primed' when
// the memory is full.
//
// The 'waddr' address that we are using really crosses two clock
// domains. While writing and changing, it's in the data clock
// domain. Once stopped, it becomes part of the bus clock domain.
// The clock transfer on the stopped line handles the clock
// transfer for these signals.
//
reg [(LGMEM-1):0] waddr;
initial waddr = {(LGMEM){1'b0}};
initial dr_primed = 1'b0;
always @(posedge i_clk)
if (dw_reset) // For simulation purposes, supply a valid value
begin
waddr <= 0; // upon reset.
dr_primed <= 1'b0;
end else if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
begin
mem[waddr] <= i_data;
waddr <= waddr + 1;
dr_primed <= (dr_primed)||(&waddr);
end
 
//
// Clock transfer of the status signals
//
wire bw_stopped, bw_triggered, bw_primed;
generate
if (SYNCHRONOUS > 0)
begin
assign bw_stopped = dr_stopped;
assign bw_triggered = dr_triggered;
assign bw_primed = dr_primed;
end else begin
// These aren't a problem, since none of these are strobe
// signals. They goes from low to high, and then stays high
// for many clocks. Swapping is thus easy--two flip flops to
// protect against meta-stability and we're done.
//
reg [2:0] q_oflags, r_oflags;
initial q_oflags = 3'h0;
initial r_oflags = 3'h0;
always @(posedge i_wb_clk)
if (bw_reset_request)
begin
q_oflags <= 3'h0;
r_oflags <= 3'h0;
end else begin
q_oflags <= { dr_stopped, dr_triggered, dr_primed };
r_oflags <= q_oflags;
end
 
assign bw_stopped = r_oflags[2];
assign bw_triggered = r_oflags[1];
assign bw_primed = r_oflags[0];
end endgenerate
 
// Reads use the bus clock
reg br_wb_ack;
initial br_wb_ack = 1'b0;
wire bw_cyc_stb;
assign bw_cyc_stb = ((i_wb_cyc)&&(i_wb_stb));
always @(posedge i_wb_clk)
begin
if ((bw_reset_request)
||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
raddr <= 0;
else if ((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)&&(bw_stopped))
raddr <= raddr + 1; // Data read, when stopped
 
if ((bw_cyc_stb)&&(~i_wb_we))
begin // Read from the bus
br_wb_ack <= 1'b1;
end else if ((bw_cyc_stb)&&(i_wb_we))
// We did this write above
br_wb_ack <= 1'b1;
else // Do nothing if either i_wb_cyc or i_wb_stb are low
br_wb_ack <= 1'b0;
end
 
wire [4:0] bw_lgmem;
assign bw_lgmem = LGMEM;
always @(posedge i_wb_clk)
if (~i_wb_addr) // Control register read
o_wb_data <= { bw_reset_request,
bw_stopped,
bw_triggered,
bw_primed,
bw_manual_trigger,
bw_disable_trigger,
(raddr == {(LGMEM){1'b0}}),
bw_lgmem,
bw_holdoff };
else if (~bw_stopped) // read, prior to stopping
o_wb_data <= i_data;
else // if (i_wb_addr) // Read from FIFO memory
o_wb_data <= mem[raddr+waddr];
 
assign o_wb_stall = 1'b0;
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
 
reg br_level_interrupt;
initial br_level_interrupt = 1'b0;
assign o_interrupt = (bw_stopped)&&(~bw_disable_trigger)
&&(~br_level_interrupt);
always @(posedge i_wb_clk)
if ((bw_reset_complete)||(bw_reset_request))
br_level_interrupt<= 1'b0;
else
br_level_interrupt<= (bw_stopped)&&(~bw_disable_trigger);
 
endmodule
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/doc/spec.pdf
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You may not convey a covered +work if you are a party to an arrangement with a third party that is +in the business of distributing software, under which you make payment +to the third party based on the extent of your activity of conveying +the work, and under which the third party grants, to any of the +parties who would receive the covered work from you, a discriminatory +patent license (a) in connection with copies of the covered work +conveyed by you (or copies made from those copies), or (b) primarily +for and in connection with specific products or compilations that +contain the covered work, unless you entered into that arrangement, +or that patent license was granted, prior to 28 March 2007. + +Nothing in this License shall be construed as excluding or limiting +any implied license or other defenses to infringement that may +otherwise be available to you under applicable patent law. + +\item No Surrender of Others' Freedom. + +If conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. 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The terms of this +License will continue to apply to the part which is the covered work, +but the special requirements of the GNU Affero General Public License, +section 13, concerning interaction through a network will apply to the +combination as such. + +\item Revised Versions of this License. + +The Free Software Foundation may publish revised and/or new versions of +the GNU General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the +Program specifies that a certain numbered version of the GNU General +Public License ``or any later version'' applies to it, you have the +option of following the terms and conditions either of that numbered +version or of any later version published by the Free Software +Foundation. If the Program does not specify a version number of the +GNU General Public License, you may choose any version ever published +by the Free Software Foundation. + +If the Program specifies that a proxy can decide which future +versions of the GNU General Public License can be used, that proxy's +public statement of acceptance of a version permanently authorizes you +to choose that version for the Program. + +Later license versions may give you additional or different +permissions. However, no additional obligations are imposed on any +author or copyright holder as a result of your choosing to follow a +later version. + +\item Disclaimer of Warranty. + +\begin{sloppypar} + THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY + APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE + COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM ``AS IS'' + WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE + RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. + SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL + NECESSARY SERVICING, REPAIR OR CORRECTION. +\end{sloppypar} + +\item Limitation of Liability. + + IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN + WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES + AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR + DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL + DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM + (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED + INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE + OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH + HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH + DAMAGES. + +\item Interpretation of Sections 15 and 16. + +If the disclaimer of warranty and limitation of liability provided +above cannot be given local legal effect according to their terms, +reviewing courts shall apply local law that most closely approximates +an absolute waiver of all civil liability in connection with the +Program, unless a warranty or assumption of liability accompanies a +copy of the Program in return for a fee. + +\begin{center} +{\Large\sc End of Terms and Conditions} + +\bigskip +How to Apply These Terms to Your New Programs +\end{center} + +If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + +To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the ``copyright'' line and a pointer to where the full notice is found. + +{\footnotesize +\begin{verbatim} + + +Copyright (C) + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . +\end{verbatim} +} + +Also add information on how to contact you by electronic and paper mail. + +If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + +{\footnotesize +\begin{verbatim} + Copyright (C) + +This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. +This is free software, and you are welcome to redistribute it +under certain conditions; type `show c' for details. +\end{verbatim} +} + +The hypothetical commands {\tt show w} and {\tt show c} should show +the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an ``about box''. + +You should also get your employer (if you work as a programmer) or +school, if any, to sign a ``copyright disclaimer'' for the program, if +necessary. For more information on this, and how to apply and follow +the GNU GPL, see \texttt{http://www.gnu.org/licenses/}. + +The GNU General Public License does not permit incorporating your +program into proprietary programs. If your program is a subroutine +library, you may consider it more useful to permit linking proprietary +applications with the library. If this is what you want to do, use +the GNU Lesser General Public License instead of this License. But +first, please read \texttt{http://www.gnu.org/philosophy/why-not-lgpl.html}. + +\end{enumerate} + +\end{document} Index: doc/src/GT.eps =================================================================== --- doc/src/GT.eps (nonexistent) +++ doc/src/GT.eps (revision 2) @@ -0,0 +1,94 @@ +%!PS-Adobe-3.0 EPSF-3.0 +%%BoundingBox: 0 0 504 288 +%%Creator: Gisselquist Technology LLC +%%Title: Gisselquist Technology Logo +%%CreationDate: 11 Mar 2014 +%%EndComments +%%BeginProlog +/black { 0 setgray } def +/white { 1 setgray } def +/height { 288 } def +/lw { height 8 div } def +%%EndProlog +% %%Page: 1 + +false { % A bounding box + 0 setlinewidth + newpath + 0 0 moveto + 0 height lineto + 1.625 height mul lw add 0 rlineto + 0 height neg rlineto + closepath stroke +} if + +true { % The "G" + newpath + height 2 div 1.25 mul height moveto + height 2 div height 4 div sub height lineto + 0 height 3 4 div mul lineto + 0 height 4 div lineto + height 4 div 0 lineto + height 3 4 div mul 0 lineto + height height 4 div lineto + height height 2 div lineto + % + height lw sub height 2 div lineto + height lw sub height 4 div lw 2 div add lineto + height 3 4 div mul lw 2 div sub lw lineto + height 4 div lw 2 div add lw lineto + lw height 4 div lw 2 div add lineto + lw height 3 4 div mul lw 2 div sub lineto + height 4 div lw 2 div add height lw sub lineto + height 2 div 1.25 mul height lw sub lineto + closepath fill + newpath + height 2 div height 2 div moveto + height 2 div 0 rlineto + 0 height 2 div neg rlineto + lw neg 0 rlineto + 0 height 2 div lw sub rlineto + height 2 div height 2 div lw sub lineto + closepath fill +} if + +height 2 div 1.25 mul lw add 0 translate +false { + newpath + 0 height moveto + height 0 rlineto + 0 lw neg rlineto + height lw sub 2 div neg 0 rlineto + 0 height lw sub neg rlineto + lw neg 0 rlineto + 0 height lw sub rlineto + height lw sub 2 div neg 0 rlineto + 0 lw rlineto + closepath fill +} if + +true { % The "T" of "GT". + newpath + 0 height moveto + height lw add 2 div 0 rlineto + 0 height neg rlineto + lw neg 0 rlineto + 0 height lw sub rlineto + height lw sub 2 div neg 0 rlineto + closepath fill + + % The right half of the top of the "T" + newpath + % (height + lw)/2 + lw + height lw add 2 div lw add height moveto + % height - (above) = height - height/2 - 3/2 lw = height/2-3/2lw + height 3 lw mul sub 2 div 0 rlineto + 0 lw neg rlineto + height 3 lw mul sub 2 div neg 0 rlineto + closepath fill +} if + + +grestore +showpage +%%EOF Index: doc/src/gqtekspec.cls =================================================================== --- doc/src/gqtekspec.cls (nonexistent) +++ doc/src/gqtekspec.cls (revision 2) @@ -0,0 +1,296 @@ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%/ +% +% Copyright (C) 2015, Gisselquist Technology, LLC +% +% This template is free software: you can redistribute it and/or modify it +% under the terms of the GNU General Public License as published by the +% Free Software Foundation, either version 3 of the License, or (at your +% option) any later version. +% +% This template is distributed in the hope that it will be useful, but WITHOUT +% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +% for more details. +% +% You should have received a copy of the GNU General Public License along +% with this program. If not, see for a copy. +% +% License: GPL, v3, as defined and found on www.gnu.org, +% http://www.gnu.org/licenses/gpl.html +% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% \NeedsTeXFormat{LaTeX2e}[1995/12/01] +\ProvidesClass{gqtekspec}[2015/03/03 v0.1 -- Gisselquist Technology Specification] +\typeout{by Dan Gisselquist} +\LoadClassWithOptions{report} +\usepackage{datetime} +\usepackage{graphicx} +\usepackage[dvips]{pstricks} +\usepackage{hhline} +\usepackage{colortbl} +\newdateformat{headerdate}{\THEYEAR/\twodigit{\THEMONTH}/\twodigit{\THEDAY}} +\setlength{\hoffset}{0.25in} +\setlength{\voffset}{-0.5in} +\setlength{\marginparwidth}{0in} +\setlength{\marginparsep}{0in} +\setlength{\textwidth}{6in} +\setlength{\oddsidemargin}{0in} + +% ************************************** +% * APPENDIX * +% ************************************** +% +\newcommand\appfl@g{\appendixname} %used to test \@chapapp +% +% \renewcommand\appendix{\par\clearpage + % \setcounter{chapter}{0}% + % \setcounter{section}{0}% + % \renewcommand\@chapapp{\appendixname}% + % \renewcommand\thechapter{\Alph{chapter}} + % \if@nosectnum\else + % \renewcommand\thesection{\Alph{chapter}.\arabic{section}} + % \fi +% } + + +% FIGURE +% redefine the @caption command to put a period after the figure or +% table number in the lof and lot tables +\long\def\@caption#1[#2]#3{\par\addcontentsline{\csname + ext@#1\endcsname}{#1}{\protect\numberline{\csname + the#1\endcsname.}{\ignorespaces #2}}\begingroup + \@parboxrestore + \normalsize + \@makecaption{\csname fnum@#1\endcsname}{\ignorespaces #3}\par + \endgroup} + +% **************************************** +% * TABLE OF CONTENTS, ETC. * +% **************************************** + +\renewcommand\contentsname{Contents} +\renewcommand\listfigurename{Figures} +\renewcommand\listtablename{Tables} + +\newif\if@toc \@tocfalse +\renewcommand\tableofcontents{% + \begingroup% temporarily set if@toc so that \@schapter will not + % put Table of Contents in the table of contents. + \@toctrue + \chapter*{\contentsname} + \endgroup + \thispagestyle{gqtekspecplain} + + \baselineskip=10pt plus .5pt minus .5pt + + {\raggedleft Page \par\vskip-\parskip} + \@starttoc{toc}% + \baselineskip=\normalbaselineskip + } + +\def\l@appendix{\pagebreak[3] + \vskip 1.0em plus 1pt % space above appendix line + \@dottedtocline{0}{0em}{8em}} + +\def\l@chapter{\pagebreak[3] + \vskip 1.0em plus 1pt % space above appendix line + \@dottedtocline{0}{0em}{4em}} + +% \if@nosectnum\else + % \renewcommand\l@section{\@dottedtocline{1}{5.5em}{2.4em}} + % \renewcommand\l@subsection{\@dottedtocline{2}{8.5em}{3.2em}} + % \renewcommand\l@subsubsection{\@dottedtocline{3}{11em}{4.1em}} + % \renewcommand\l@paragraph{\@dottedtocline{4}{13.5em}{5em}} + % \renewcommand\l@subparagraph{\@dottedtocline{5}{16em}{6em}} +% \fi + +% LIST OF FIGURES +% +\def\listoffigures{% + \begingroup + \chapter*{\listfigurename}% + \endgroup + \thispagestyle{gqtekspecplain}% + + \baselineskip=10pt plus .5pt minus .5pt% + + {\hbox to \hsize{Figure\hfil Page} \par\vskip-\parskip}% + + \rule[2mm]{\textwidth}{0.5mm}\par + + \@starttoc{lof}% + \baselineskip=\normalbaselineskip}% + +\def\l@figure{\@dottedtocline{1}{1em}{4.0em}} + +% LIST OF TABLES +% +\def\listoftables{% + \begingroup + \chapter*{\listtablename}% + \endgroup + \thispagestyle{gqtekspecplain}% + \baselineskip=10pt plus .5pt minus .5pt% + {\hbox to \hsize{Table\hfil Page} \par\vskip-\parskip}% + + % Added line underneath headings, 20 Jun 01, Capt Todd Hale. + \rule[2mm]{\textwidth}{0.5mm}\par + + \@starttoc{lot}% + \baselineskip=\normalbaselineskip}% + +\let\l@table\l@figure + +% **************************************** +% * PAGE STYLES * +% **************************************** +% +\def\ps@gqtekspectoc{% + \let\@mkboth\@gobbletwo + \def \@oddhead{} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspectocn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} +\def\ps@gqtekspectocn{\let\@mkboth\@gobbletwo + \def \@oddhead{\rm \hfil\raisebox{10pt}{Page}} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspectocn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +\def\ps@gqtekspeclof{\let\@mkboth\@gobbletwo + \def \@oddhead{} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclofn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} +\def\ps@gqtekspeclofn{\let\@mkboth\@gobbletwo + \def \@oddhead{\rm + \parbox{\textwidth}{\raisebox{0pt}{Figure}\hfil\raisebox{0pt}{Page} % + \raisebox{20pt}{\rule[10pt]{\textwidth}{0.5mm}} }} + + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclofn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +\def\ps@gqtekspeclot{\let\@mkboth\@gobbletwo + \def \@oddhead{} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclotn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} +\def\ps@gqtekspeclotn{\let\@mkboth\@gobbletwo + \def \@oddhead{\rm + \parbox{\textwidth}{\raisebox{0pt}{Table}\hfil\raisebox{0pt}{Page} % + \raisebox{20pt}{\rule[10pt]{\textwidth}{0.5mm}} }} + + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclotn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +\def\ps@gqtekspecplain{\let\@mkboth\@gobbletwo + \def \@oddhead{\rput(0,-2pt){\psline(0,0)(\textwidth,0)}\rm \hbox to 1in{\includegraphics[height=0.8\headheight]{GT.eps} Gisselquist Technology, LLC}\hfil\hbox{\@title}\hfil\hbox to 1in{\hfil\headerdate\@date}} + \def \@oddfoot{\rput(0,9pt){\psline(0,0)(\textwidth,0)}\rm \hbox to 1in{www.opencores.com\hfil}\hfil\hbox{\r@vision}\hfil\hbox to 1in{\hfil{\thepage}}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +% \def\author#1{\def\auth@r{#1}} +% \def\title#1{\def\ti@tle{#1}} + +\def\logo{\begin{pspicture}(0,0)(5.67in,0.75in) + \rput[lb](0.05in,0.10in){\includegraphics[height=0.75in]{GT.eps}} + \rput[lb](1.15in,0.05in){\scalebox{1.8}{\parbox{2.0in}{Gisselquist\\Technology, LLC}}} + \end{pspicture}} +% TITLEPAGE +% +\def\titlepage{\setcounter{page}{1} + \typeout{^^JTitle Page.} + \thispagestyle{empty} + \leftline{\rput(0,0){\psline(0,0)(\textwidth,0)}\hfill} + \vskip 2\baselineskip + \logo\hfil % Original is 3.91 in x 1.26 in, let's match V thus + \vskip 2\baselineskip + \vspace*{10pt}\vfil + \begin{minipage}{\textwidth}\raggedleft + \ifproject{\Huge\bfseries\MakeUppercase\@project} \\\fi + \vspace*{15pt} + {\Huge\bfseries\MakeUppercase\@title} \\ + \vskip 10\baselineskip + \Large \@author \\ + \ifemail{\Large \@email}\\\fi + \vskip 6\baselineskip + \Large \usdate\@date \\ + \end{minipage} + % \baselineskip 22.5pt\large\rm\MakeUppercase\ti@tle + \vspace*{30pt} + \vfil + \newpage\baselineskip=\normalbaselineskip} + +\newenvironment{license}{\clearpage\typeout{^^JLicense Page.}\ \vfill\noindent}% + {\vfill\newpage} +% **************************************** +% * CHAPTER DEFINITIONS * +% **************************************** +% +\renewcommand\chapter{\if@openright\cleardoublepage\else\clearpage\fi + \thispagestyle{gqtekspecplain}% + \global\@topnum\z@ + \@afterindentfalse + \secdef\@chapter\@schapter} +\renewcommand\@makechapterhead[1]{% + \hbox to \textwidth{\hfil{\Huge\bfseries \thechapter.}}\vskip 10\p@ + \hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip \p@ + \hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip 10\p@ + \hbox to \textwidth{\hfill{\Huge\bfseries #1}}% + \par\nobreak\vskip 40\p@} +\renewcommand\@makeschapterhead[1]{% + \hbox to \textwidth{\hfill{\Huge\bfseries #1}}% + \par\nobreak\vskip 40\p@} +% **************************************** +% * INITIALIZATION * +% **************************************** +% +% Default initializations + +\ps@gqtekspecplain % 'gqtekspecplain' page style with lowered page nos. +\onecolumn % Single-column. +\pagenumbering{roman} % the first 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Specification \\\hline\hline}% + {\end{tabular}} +\newenvironment{preface}{\chapter*{Preface}}{\par\bigskip\bigskip\leftline{\hfill\@author}} +\endinput Index: doc/src/spec.tex =================================================================== --- doc/src/spec.tex (nonexistent) +++ doc/src/spec.tex (revision 2) @@ -0,0 +1,271 @@ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% +%% Filename: spec.tex +%% +%% Project: Wishbone scope +%% +%% Purpose: This LaTeX file contains all of the documentation/description +%% currently provided with this Wishbone scope core. It's not +%% nearly as interesting as the PDF file it creates, so I'd +%% recommend reading that before diving into this file. You +%% should be able to find the PDF file in the SVN distribution +%% together with this PDF file and a copy of the GPL-3.0 license +%% this file is distributed under. If not, just type 'make' +%% in the doc directory and it (should) build without a problem. +%% +%% +%% Creator: Dan Gisselquist +%% Gisselquist Technology, LLC +%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% +%% Copyright (C) 2015, Gisselquist Technology, LLC +%% +%% This program is free software (firmware): you can redistribute it and/or +%% modify it under the terms of the GNU General Public License as published +%% by the Free Software Foundation, either version 3 of the License, or (at +%% your option) any later version. +%% +%% This program is distributed in the hope that it will be useful, but WITHOUT +%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +%% for more details. +%% +%% You should have received a copy of the GNU General Public License along +%% with this program. (It's in the $(ROOT)/doc directory, run make with no +%% target there if the PDF file isn't present.) If not, see +%% for a copy. +%% +%% License: GPL, v3, as defined and found on www.gnu.org, +%% http://www.gnu.org/licenses/gpl.html +%% +%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\documentclass{gqtekspec} +\project{Wishbone Scope} +\title{Specification} +\author{Dan Gisselquist, Ph.D.} +\email{dgisselq (at) opencores.org} +\revision{Rev.~0.1} +\begin{document} +\pagestyle{gqtekspecplain} +\titlepage +\begin{license} +Copyright (C) \theyear\today, Gisselquist Technology, LLC + +This project is free software (firmware): you can redistribute it and/or +modify it under the terms of the GNU General Public License as published +by the Free Software Foundation, either version 3 of the License, or (at +your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with this program. If not, see \hbox{} for a +copy. +\end{license} +\begin{revisionhistory} +0.1 & 6/22/2015 & Gisselquist & First Draft \\\hline +\end{revisionhistory} +% Revision History +% Table of Contents, named Contents +\tableofcontents +% \listoffigures +\listoftables +\begin{preface} + +This, then, was and is the genesis of this project. +\end{preface} + +\chapter{Introduction} +\pagenumbering{arabic} +\setcounter{page}{1} + +The wishbone Scope is a debugging tool for reading results from the chip after +events have taken place. In general, the scope records data until some +trigger has taken place, and then continues for some user programmable hold off. +Once the holdoff has been reached, the scope stops recording and asserts an +interrupt. At this time, data may be read from the scope in order from oldest +to most recent. That's the basics, now for two extra details. + +First, the trigger and data that the scope records is implementation dependent. +The scope itself is designed to be easily reconfigurable from one build to the +next so that the actual configuration may even be build dependent. + +Second, the scope is built to be able to run off of a separate clock from the +bus that commands and controls it. This is configurable, set the parameter +``SYNCHRONOUS'' to `1' to run off of a single clock. When running off of two +clocks, it means that actions associated with commands issued to the scope, such +as manual triggering or being disabled or released, will not act synchronously +with the scope itself. + +Third, the data clock associated with the scope has a clock enable line +associated with it. Depending on how often the clock enable line is enabled +may determine how fast the scope is primed, triggered, and eventually completes +its collection. + +% \chapter{Architecture} +\chapter{Operation} + +So how shall one use the scope? First, before using the scope, the holdoff +needs to be set. The scope is designed so that setting the scope control value +to the holdoff alone will reset the scope from whatever condition it was in, +freeing it to run. Once running, then upon every clock enabled clock, one +sample of data is read into the scope and recorded. Once every memory value +is filled, the scope has been {\tt PRIMED}. Once the scope has been +{\tt PRIMED}, it will then be responsive to its trigger. Should the trigger be +active on a clock--enabled input, the scope will then be {\tt TRIGGERED}. It +will then count for the number of clocks in the holdoff before stopping collection, placing it in the {\tt STOPPED} state. If the holdoff is zero, the last +sample in the buffer will be the sample containing the trigger. + +There are two further commands that will affect the operation of the scope. The +first is the {\tt MANUAL} trigger command/bit. This will cause the scope to +trigger immediately if set. If coupled with a {\tt RESET} command, the trigger +will first wait until it is {\tt PRIMED} before the manual trigger takes +effect. + +The last command that can affect the operation of the scope is the {\tt DISABLE} +command/bit. This command will prevent the scope from triggering, or if +triggered, prevent the scope from generating an interrupt. + +\chapter{Registers} + +This scope core supports two registers, as listed in +Tbl.~\ref{tbl:reglist}. The first is the control register, whereas the second +is the data register. +\begin{table}[htbp] +\begin{center} +\begin{reglist} +WBSCOPE & 0 & 32 & R/W & Configuration, control, and status of the + scope.\\\hline +WBSCOPEDATA & 1 & 32 & R & Read out register, to read out the data + from the core.\\\hline +\end{reglist}\caption{List of Registers}\label{tbl:reglist} +\end{center}\end{table} +Each register will be discussed in detail in this chapter. + +\section{Control Register} +The bits in the control register are defined in Tbl.~\ref{tbl:control}. +\begin{table}[htbp] +\begin{center} +\begin{bitlist} +31 & R/W & RESET\_n. Write a `0' to this register to command a reset. + Reading a `1' from this register means the reset has not finished + crossing clock domains and is still pending.\\\hline +30 & R & STOPPED, indicates that all collection has stopped.\\\hline +29 & R & TRIGGERRED, indicates that a trigger has been recognized, and that + the scope is counting for holdoff samples before stopping.\\\hline +28 & R & PRIMED, indicates that the memory has been filled, and that the + scope is now waiting on a trigger.\\\hline +27 & R/W & MANUAL, set to invoke a manual trigger.\\\hline +26 & R/W & DISABLE, set to disable the internal trigger. The scope may still + be triggered manually.\\\hline +25 & R & RZERO, this will be true whenever the scope's internal address + register is pointed at the beginning of the memory.\\\hline +20--24 & R & LGMEMLEN, the base two logarithm of the memory length. Thus, + the memory internal to the scope is given by 1<
doc/gpl-3.0.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/Makefile =================================================================== --- doc/Makefile (nonexistent) +++ doc/Makefile (revision 2) @@ -0,0 +1,20 @@ +all: gpl-3.0.pdf spec.pdf +DSRC := src + +gpl-3.0.pdf: $(DSRC)/gpl-3.0.tex + latex $(DSRC)/gpl-3.0.tex + latex $(DSRC)/gpl-3.0.tex + dvips -q -z -t letter -P pdf -o gpl-3.0.ps gpl-3.0.dvi + ps2pdf -dAutoRotatePages=/All gpl-3.0.ps gpl-3.0.pdf + rm gpl-3.0.dvi gpl-3.0.log gpl-3.0.aux gpl-3.0.ps + +spec.pdf: $(DSRC)/spec.tex $(DSRC)/gqtekspec.cls + cd $(DSRC)/; latex spec.tex + cd $(DSRC)/; latex spec.tex + dvips -q -z -t letter -P pdf -o spec.ps $(DSRC)/spec.dvi + ps2pdf -dAutoRotatePages=/All spec.ps spec.pdf + rm $(DSRC)/spec.dvi $(DSRC)/spec.log + rm $(DSRC)/spec.aux $(DSRC)/spec.toc + rm $(DSRC)/spec.lof $(DSRC)/spec.lot + rm spec.ps + Index: sw/cfgscope.cpp =================================================================== --- sw/cfgscope.cpp (nonexistent) +++ sw/cfgscope.cpp (revision 2) @@ -0,0 +1,156 @@ +/////////////////////////////////////////////////////////////////////////// +// +// Filename: cfgscope.cpp +// +// Project: FPGA library development (Basys-3 development board) +// +// Purpose: To read out, and decompose, the results of the wishbone scope +// as applied to the ICAPE2 interaction. +// +// This is provided together with the wbscope project as an +// example of what might be done with the wishbone scope. +// The intermediate details, though, between this and the +// wishbone scope are not part of the wishbone scope project. +// +// Using this particular scope made it a *lot* easier to get the +// ICAPE2 interface up and running, since I was able to see what +// was going right (or wrong) with the interface as I was +// developing it. Sure, it would've been better to get it to work +// under a simulator instead of with the scope, but not being +// certain of how the interface was supposed to work made building +// a simulator difficult. +// +// Creator: Dan Gisselquist, Ph.D. +// Gisselquist Tecnology, LLC +// +/////////////////////////////////////////////////////////////////////////// +// +// Copyright (C) 2015, Gisselquist Technology, LLC +// +// This program is free software (firmware): you can redistribute it and/or +// modify it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or (at +// your option) any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program. (It's in the $(ROOT)/doc directory, run make with no +// target there if the PDF file isn't present.) If not, see +// for a copy. +// +// License: GPL, v3, as defined and found on www.gnu.org, +// http://www.gnu.org/licenses/gpl.html +// +// +/////////////////////////////////////////////////////////////////////////// +#include +#include +#include +#include +#include +#include +#include +#include + +#include "port.h" +#include "llcomms.h" // This defines how we talk to the device over wishbone +#include "regdefs.h" + +// Here are the two registers needed for accessing our scope: A control register +// and a data register. +#define WBSCOPE R_CFGSCOPE +#define WBSCOPEDATA R_CFGSCOPED + +// +// The DEVBUS structure encapsulates wishbone accesses, so that this code can +// access the wishbone bus on the FPGA. +DEVBUS *m_fpga; +void closeup(int v) { + m_fpga->kill(); + exit(0); +} + +int main(int argc, char **argv) { + // Open up a port to talk to the FPGA ... +#ifndef FORCE_UART + m_fpga = new FPGA(new NETCOMMS("lazarus",PORT)); +#else + m_fpga = new FPGA(new TTYCOMMS("/dev/ttyUSB2")); +#endif + + signal(SIGSTOP, closeup); + signal(SIGHUP, closeup); + + // Check to see whether or not the scope has captured the data we need + // yet or not. If not, exit kindly. + unsigned v, lgln, scoplen; + v = m_fpga->readio(WBSCOPE); + if (0x60000000 != (v & 0x60000000)) { + printf("Scope is not yet ready:\n"); + printf("\tRESET:\t\t%s\n", (v&0x80000000)?"Ongoing":"Complete"); + printf("\tSTOPPED:\t%s\n", (v&0x40000000)?"Yes":"No"); + printf("\tTRIGGERED:\t%s\n", (v&0x20000000)?"Yes":"No"); + printf("\tPRIMED:\t\t%s\n", (v&0x10000000)?"Yes":"No"); + printf("\tMANUAL:\t\t%s\n", (v&0x08000000)?"Yes":"No"); + printf("\tDISABLED:\t%s\n", (v&0x04000000)?"Yes":"No"); + printf("\tZERO:\t\t%s\n", (v&0x02000000)?"Yes":"No"); + exit(0); + } + + // Since the length of the scope memory is a configuration parameter + // internal to the scope, we read it here to find out how it was + // configured. + lgln = (v>>20) & 0x1f; + scoplen = (1<readz(WBSCOPEDATA, scoplen, buf); + + printf("Vector read complete\n"); + } else { + for(int i=0; ireadio(WBSCOPEDATA); + } + + // Now, let's decompose our 32-bit wires into something ... meaningful. + // This section will change from project to project, scope to scope, + // depending on what wires are placed into the scope. + for(int i=0; i0)&&(buf[i] == buf[i-1])&& + (i>24)&0x03f; + switch(cw) { + case 0x20: printf("DUMMY"); break; + case 0x10: printf("NOOP "); break; + case 0x08: printf("SYNC "); break; + case 0x04: printf("CMD "); break; + case 0x02: printf("IPROG"); break; + case 0x01: printf("DSYNC"); break; + default: printf("OTHER"); break; + } + printf(" -> %02x\n", buf[i] & 0x0ffffff); + } + + // Clean up our interface, now, and we're done. + delete m_fpga; +} +

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