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/doc/spec.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/src/spec.tex
101,7 → 101,7
\pagenumbering{arabic}
\setcounter{page}{1}
 
The wishbone Scope is a debugging tool for reading results from the chip after
The Wishbone Scope is a debugging tool for reading results from the chip after
events have taken place. In general, the scope records data until some
some (programmable) holdoff number of data samples after a trigger has taken
place. Once the holdoff has been reached, the scope stops recording and
121,7 → 121,7
 
Third, the data clock associated with the scope has a clock enable line
associated with it. Depending on how often the clock enable line is enabled
may determine how fast the scope is primed, triggered, and eventually completes
may determine how fast the scope is {\tt PRIMED}, {\tt TRIGGERED}, and eventually completes
its collection.
 
Finally, and in conclusion, this scope has been an invaluable tool for
136,25 → 136,26
So how shall one use the scope? The scope itself supports a series of
states:
\begin{enumerate}
\item RESET
\item {\tt RESET}
 
Any write to the control register, without setting the high order bit,
will automatically reset the scope.
\item PRIMED
Any write to the control register, without setting the high order bit,
will automatically reset the scope. Once reset, the scope will
immediately start collecting.
\item {\tt PRIMED}
 
Following a reset, once the scope has filled its memory, it enters the
PRIMED state. Once it reaches this state, it will be sensitive to a
trigger.
\item TRIGGERED
Following a reset, once the scope has filled its memory, it enters the
{\tt PRIMED} state. Once it reaches this state, it will be sensitive
to a trigger.
\item {\tt TRIGGERED}
 
The scope may be triggered either automatically, via an input port to
The scope may be {\tt TRIGGERED} either automatically, via an input port to
the core, or manually, via a wishbone bus command. Once a trigger
has been received, the core will record a user configurable number of
further samples before stopping.
 
\item STOPPED
\item {\tt STOPPED}
 
Once the core has stopped, the data within it may be read back off.
Once the core has {\tt STOPPED}, the data within it may be read back off.
\end{enumerate}
 
Let's go through that list again. First, before using the scope, the holdoff
166,23 → 167,25
{\tt PRIMED}, it will then be responsive to its trigger. Should the trigger be
active on a clock--enabled input, the scope will then be {\tt TRIGGERED}. It
will then count for the number of clocks in the holdoff before stopping
collection, placing it in the {\tt STOPPED} state. If the holdoff is zero,
the last sample in the buffer will be the sample containing the trigger.
Likewise if the holdoff is one less than the size of the memory, the first
sample in the buffer will be the one containing the trigger.
collection, placing it in the {\tt STOPPED} state. (Don't change the holdoff
during between triggered and stopped, or it may stop at some other non--holdoff
value!) If the holdoff is zero, the last sample in the buffer will be the
sample containing the trigger. Likewise if the holdoff is one less than the
size of the memory, the first sample in the buffer will be the one containing
the trigger.
There are two further commands that will affect the operation of the scope. The
first is the {\tt MANUAL} trigger command/bit. This bit may be set by writing
the holdoff to the control register while setting this bit high. This will
cause the scope to trigger immediately. If coupled with a {\tt RESET} command,
that is if the RESET_n bit isn't also set, then the trigger will first wait
until the scope enters its {\tt PRIMED} state before the manual trigger takes
effect.
that is if the {\tt RESET\_n} bit isn't also set, then recording will start
at the beginning and the scope will first wait until its {\tt PRIMED} state
before the manual trigger takes effect.
 
The last command that can affect the operation of the scope is the {\tt DISABLE}
command/bit in the control register. Setting this bit will prevent the scope
from triggering, or if triggered, it will prevent the scope from generating an
interrupt.
from triggering, or if {\tt TRIGGERED}, it will prevent the scope from
generating an interrupt.
 
Finally, be careful how you set the clock enable line. If the clock enable
line leaves the clock too often disabled, the scope might never prime in any
189,7 → 192,7
reasonable amount of time.
 
So, in summary, to use this scope you first set the holdoff value in the
control register. Second, you wait until the scope has been triggered and
control register. Second, you wait until the scope has been {\tt TRIGGERED} and
stopped. Finally, you read from the data register once for every memory value
in the buffer and you can then sit back, relax, and study what took place
within the FPGA.
201,9 → 204,9
\begin{table}[htbp]
\begin{center}
\begin{reglist}
WBSCOPE & 0 & 32 & R/W & Configuration, control, and status of the
CONTROL & 0 & 32 & R/W & Configuration, control, and status of the
scope.\\\hline
WBSCOPEDATA & 1 & 32 & R/W & Read out register, to read out the data
DATA & 1 & 32 & R(/W) & Read out register, to read out the data
from the core. Writes to this register reset the read address
to the beginning of the buffer, but are otherwise ignored.
\\\hline
216,21 → 219,21
\begin{table}[htbp]
\begin{center}
\begin{bitlist}
31 & R/W & RESET\_n. Write a `0' to this register to command a reset.
31 & R/W & {\tt RESET\_n}. Write a `0' to this register to command a reset.
Reading a `1' from this register means the reset has not finished
crossing clock domains and is still pending.\\\hline
30 & R & STOPPED, indicates that all collection has stopped.\\\hline
29 & R & TRIGGERRED, indicates that a trigger has been recognized, and that
30 & R & {\tt STOPPED}, indicates that all collection has stopped.\\\hline
29 & R & {\tt TRIGGERED}, indicates that a trigger has been recognized, and that
the scope is counting for holdoff samples before stopping.\\\hline
28 & R & PRIMED, indicates that the memory has been filled, and that the
28 & R & {\tt PRIMED}, indicates that the memory has been filled, and that the
scope is now waiting on a trigger.\\\hline
27 & R/W & MANUAL, set to invoke a manual trigger.\\\hline
26 & R/W & DISABLE, set to disable the internal trigger. The scope may still
be triggered manually.\\\hline
25 & R & RZERO, this will be true whenever the scope's internal address
27 & R/W & {\tt MANUAL}, set to invoke a manual trigger.\\\hline
26 & R/W & {\tt DISABLE}, set to disable the internal trigger. The scope may still
be {\tt TRIGGERED} manually.\\\hline
25 & R & {\tt RZERO}, this will be true whenever the scope's internal address
register is pointed at the beginning of the memory.\\\hline
20--24 & R & LGMEMLEN, the base two logarithm of the memory length. Thus,
the memory internal to the scope is given by 1<<LGMEMLEN. \\\hline
20--24 & R & {\tt LGMEMLEN}, the base two logarithm of the memory length. Thus,
the memory internal to the scope is given by 1$<<$LGMEMLEN. \\\hline
0--19 & R/W & Unsigned holdoff\\\hline
\end{bitlist}
\caption{Control Register}\label{tbl:control}
239,31 → 242,34
it, while leaving the other bits zero, to get the scope going. On such a write,
the RESET\_n bit will be a zero, causing the scope to internally reset itself.
Further, during normal operation, the high order nibble will go from 4'h8
(a nearly instantaneous reset state) to 4'h0 (running), to 4'h1 (primed),
to 4'h3 (triggered), and then stop at 4'h7 (primed, triggered, and stopped).
(a nearly instantaneous reset state) to 4'h0 (running), to 4'h1 ({\tt PRIMED}),
to 4'h3 ({\tt TRIGGERED}), and then stop at 4'h7 ({\tt PRIMED}, {\tt TRIGGERED},
and {\tt STOPPED}).
Finally, user's are cautioned not to adjust the holdoff between the time the
scope triggers and the time it stops--just to guarantee data coherency.
 
While this approach works, the scope has some other capabilities. For example,
if you set the MANUAL bit, the scope will trigger as soon as it is primed.
If you set the MANUAL bit and the RESET\_n bit, it will trigger immediately
if the scope was already primed. If not, a reset will take place, the scope
will collect enough data to be primed, and then immediately trigger.
if you set the {\tt MANUAL} bit, the scope will trigger as soon as it is {\tt PRIMED}.
If you set the {\tt MANUAL} bit and the {\tt RESET\_n} bit, it will trigger
immediately if the scope was already {\tt PRIMED}. However, if the
{\tt RESET\_n} bit was not also set, a reset will take place and the scope
will start over by first collecting enough data to be {\tt PRIMED}, and only
then will the {\tt MANUAL} trigger take effect.
 
A second optional capability is to disable the scope entirely. This might be
useful if, for example, certain irrelevant things might trigger the scope.
By setting the DISABLE bit, the scope will not automatically trigger. It will
still record into its memory, and it will still prime itself, it will just
not trigger automatically. The scope may still be manually triggered while
the DISABLE bit is set. Likewise, if the DISABLE bit is set after the scope
has been triggered, the scope will continue to its natural stopped state--it
just won't generate an interrupt.
By setting the {\tt DISABLE} bit, the scope will not automatically trigger. It
will still record into its memory, and it will still prime itself, it will just
not trigger automatically. The scope may still be manually {\tt TRIGGERED}
while the {\tt DISABLE} bit is set. Likewise, if the {\tt DISABLE} bit is set
after the scope has been {\tt TRIGGERED}, the scope will continue to its
natural stopped state--it just won't generate an interrupt.
 
There are two other interesting bits in this control register. The RZERO bit
indicates that the next read from the data register will read from the first
value in the memory, while the LGMEMLEN bits indicate how long the memory is.
Thus, if LGMEMLEN is 10, the FIFO will be (1<<10) or 1024 words long, whereas
if LGMEMLEN is 14, the FIFO will be (1<<14) or 16384 words long.
There are two other interesting bits in this control register. The {\tt RZERO}
bit indicates that the next read from the data register will read from the first
value in the memory, while the {\tt LGMEMLEN} bits indicate how long the memory is. Thus, if {\tt LGMEMLEN} is 10, the FIFO will be (1$<<$10) or 1024 words
long, whereas if {\tt LGMEMLEN} is 14, the FIFO will be (1$<<$14) or 16,384 words
long.
 
\section{Data Register}
 
272,9 → 278,11
the core, save only that they have not been protected from any meta-stability
issues. This is useful for reading what's going on when the various lines are
stuck. After the core stops recording, reads from this register return values
from the stored memory. Further, after recording has stopped, every read
increments an internal memory address, so that after $N$ reads (for however
long the internal memory is), the entire memory has been returned over the bus.
from the stored memory, beginning at the oldest and ending with the value
holdoff clocks after the trigger. Further, after recording has stopped, every
read increments an internal memory address, so that after (1$<<$LGMEMLEN)
reads (for however long the internal memory is), the entire memory has been
returned over the bus.
If you would like some assurance that you are reading from the beginning of the
memory, you may either check the control register's {\tt RZERO} flag which will
be `1' for the first value in the buffer, or you may write to the data register.
330,42 → 338,43
\begin{table}[htbp]
\begin{center}
\begin{portlist}
i\_clk & 1 & Input & \\\hline
i\_ce & 1 & Input & Clock Enable. Set this high to clock data in and
{\tt i\_clk} & 1 & Input & The clock the data lines, clock enable, and trigger
are synchronous to. \\\hline
{\tt i\_ce} & 1 & Input & Clock Enable. Set this high to clock data in and
out.\\\hline
i\_trigger & 1 & Input & An active high trigger line. If this trigger is
{\tt i\_trigger} & 1 & Input & An active high trigger line. If this trigger is
set to one on any clock enabled data clock cycle, once
the scope has been primed, it will then enter into its
TRIGGERED state.
the scope has been {\tt PRIMED}, it will then enter into its
{\tt TRIGGERED} state.
\\\hline
i\_data & 32 & Input & 32--wires of ... whatever you are interested in
{\tt i\_data} & 32 & Input & 32--wires of ... whatever you are interested in
recording and later examining. These can be anything, only
they should be synchronous with the data clock.
\\\hline
i\_wb\_clk & 1 & Input & The clock that the wishbone interface runs on.
{\tt i\_wb\_clk} & 1 & Input & The clock that the wishbone interface runs on.
\\\hline
i\_wb\_cyc & 1 & Input & Indicates a wishbone bus cycle is active when high.
\\\hline
i\_wb\_stb & 1 & Input & Indicates a wishbone bus cycle for this peripheral
when high. (See the wishbone spec for more details) \\\hline
i\_wb\_we & 1 & Input & Write enable, allows indicates a write to one of the
two registers when i\_wb\_stb is also high.
{\tt i\_wb\_cyc} & 1 & Input & Indicates a wishbone bus cycle is active when
high. \\\hline
{\tt i\_wb\_stb} & 1 & Input & Indicates a wishbone bus cycle for this
peripheral when high. (See the wishbone spec for more details) \\\hline
{\tt i\_wb\_we} & 1 & Input & Write enable, allows indicates a write to one of
the two registers when {\tt i\_wb\_stb} is also high.
\\\hline
i\_wb\_addr & 1 & Input & A single address line, set to zero to access the
configuration and control regiseter, to one to access the data
{\tt i\_wb\_addr} & 1 & Input & A single address line, set to zero to access the
configuration and control register, to one to access the data
register. \\\hline
i\_wb\_data & 32 & Input & Data used when writing to the control register,
{\tt i\_wb\_data} & 32 & Input & Data used when writing to the control register,
ignored otherwise. \\\hline
o\_wb\_ack & 1 & Output & Wishbone acknowledgement. This line will go high
on the clock after any wishbone access, as long as the wishbone
{\tt i\_wb\_cyc} line remains high (i.e., no ack's if you
terminate the cycle early).
{\tt o\_wb\_ack} & 1 & Output & Wishbone acknowledgement. This line will go
high on the clock after any wishbone access, as long as the
wishbone {\tt i\_wb\_cyc} line remains high (i.e., no ack's if
you terminate the cycle early).
\\\hline
o\_wb\_stall & 1 & Output & Required by the wishbone spec, but always set to
zero in this implementation.
{\tt o\_wb\_stall} & 1 & Output & Required by the wishbone spec, but always
set to zero in this implementation.
\\\hline
o\_wb\_data & 32 & Output & Values read, either control or data, headed back
to the wishbone bus. These values will be valid during any
{\tt o\_wb\_data} & 32 & Output & Values read, either control or data, headed
back to the wishbone bus. These values will be valid during any
read cycle when the {\tt i\_wb\_ack} line is high.
\\\hline
\end{portlist}
/doc/Makefile
15,6 → 15,6
ps2pdf -dAutoRotatePages=/All spec.ps spec.pdf
rm $(DSRC)/spec.dvi $(DSRC)/spec.log
rm $(DSRC)/spec.aux $(DSRC)/spec.toc
rm $(DSRC)/spec.lof $(DSRC)/spec.lot
rm $(DSRC)/spec.lot # $(DSRC)/spec.lof
rm spec.ps
 

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