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URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

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  • This comparison shows the changes necessary to convert path 
    /wbuart32/trunk/rtl
    from Rev 15 to Rev 17
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  •

Rev 15 → Rev 17

/rxuart.v
89,6 → 89,8
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
// States: (@ baud counter == 0)
// 0 First bit arrives
// ..7 Bits arrive
119,9 → 121,9
o_parity_err, o_frame_err, o_ck_uart);
parameter [30:0] INITIAL_SETUP = 31'd868;
// 8 data bits, no parity, (at least 1) stop bit
input i_clk, i_reset;
input [30:0] i_setup;
input i_uart_rx;
input wire i_clk, i_reset;
input wire [30:0] i_setup;
input wire i_uart_rx;
output reg o_wr;
output reg [7:0] o_data;
output reg o_break;
/rxuartlite.v
45,27 → 45,23
////////////////////////////////////////////////////////////////////////////////
//
//
`define RXU_BIT_ZERO 4'h0
`define RXU_BIT_ONE 4'h1
`define RXU_BIT_TWO 4'h2
`define RXU_BIT_THREE 4'h3
`define RXU_BIT_FOUR 4'h4
`define RXU_BIT_FIVE 4'h5
`define RXU_BIT_SIX 4'h6
`define RXU_BIT_SEVEN 4'h7
// `define RXU_PARITY 4'h8 // Unused in RXUARTLITE
`define RXU_STOP 4'h8
// `define RXU_SECOND_STOP 4'ha // Unused in RXUARTLITE
// Unused 4'hb
// Unused 4'hc
// `define RXU_BREAK 4'hd // Unused in RXUARTLITE
// `define RXU_RESET_IDLE 4'he // Unused in RXUARTLITE
`define RXU_IDLE 4'hf
`default_nettype none
//
`define RXUL_BIT_ZERO 4'h0
`define RXUL_BIT_ONE 4'h1
`define RXUL_BIT_TWO 4'h2
`define RXUL_BIT_THREE 4'h3
`define RXUL_BIT_FOUR 4'h4
`define RXUL_BIT_FIVE 4'h5
`define RXUL_BIT_SIX 4'h6
`define RXUL_BIT_SEVEN 4'h7
`define RXUL_STOP 4'h8
`define RXUL_IDLE 4'hf
 
module rxuartlite(i_clk, i_uart_rx, o_wr, o_data);
parameter [23:0] CLOCKS_PER_BAUD = 24'd868;
input i_clk;
input i_uart_rx;
input wire i_clk;
input wire i_uart_rx;
output reg o_wr;
output reg [7:0] o_data;
 
115,26 → 111,26
half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud);
 
 
initial state = `RXU_IDLE;
initial state = `RXUL_IDLE;
always @(posedge i_clk)
begin
if (state == `RXU_IDLE)
if (state == `RXUL_IDLE)
begin // Idle state, independent of baud counter
// By default, just stay in the IDLE state
state <= `RXU_IDLE;
state <= `RXUL_IDLE;
if ((~ck_uart)&&(half_baud_time))
// UNLESS: We are in the center of a valid
// start bit
state <= `RXU_BIT_ZERO;
state <= `RXUL_BIT_ZERO;
end else if (zero_baud_counter)
begin
if (state < `RXU_STOP)
if (state < `RXUL_STOP)
// Data arrives least significant bit first.
// By the time this is clocked in, it's what
// you'll have.
state <= state + 1;
else // Wait for the next character
state <= `RXU_IDLE;
state <= `RXUL_IDLE;
end
end
 
159,7 → 155,7
reg pre_wr;
initial pre_wr = 1'b0;
always @(posedge i_clk)
if ((zero_baud_counter)&&(state == `RXU_STOP))
if ((zero_baud_counter)&&(state == `RXUL_STOP))
begin
o_wr <= 1'b1;
o_data <= data_reg;
173,7 → 169,7
// we set ourselves up for clocks_per_baud counts between baud
// intervals.
always @(posedge i_clk)
if ((zero_baud_counter)|||(state == `RXU_IDLE))
if ((zero_baud_counter)|||(state == `RXUL_IDLE))
baud_counter <= CLOCKS_PER_BAUD-1'b1;
else
baud_counter <= baud_counter-1'b1;
186,7 → 182,7
// before--cleaning up some otherwise difficult timing dependencies.
initial zero_baud_counter = 1'b0;
always @(posedge i_clk)
if (state == `RXU_IDLE)
if (state == `RXUL_IDLE)
zero_baud_counter <= 1'b0;
else
zero_baud_counter <= (baud_counter == 24'h01);
/txuart.v
93,6 → 93,8
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
`define TXU_BIT_ZERO 4'h0
`define TXU_BIT_ONE 4'h1
`define TXU_BIT_TWO 4'h2
114,15 → 116,15
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data,
i_cts_n, o_uart_tx, o_busy);
parameter [30:0] INITIAL_SETUP = 31'd868;
input i_clk, i_reset;
input [30:0] i_setup;
input i_break;
input i_wr;
input [7:0] i_data;
input wire i_clk, i_reset;
input wire [30:0] i_setup;
input wire i_break;
input wire i_wr;
input wire [7:0] i_data;
// Hardware flow control Ready-To-Send bit. Set this to one to use
// the core without flow control. (A more appropriate name would be
// the Ready-To-Receive bit ...)
input i_cts_n;
input wire i_cts_n;
// And the UART input line itself
output reg o_uart_tx;
// A line to tell others when we are ready to accept data. If
/txuartlite.v
49,23 → 49,25
////////////////////////////////////////////////////////////////////////////////
//
//
`define TXU_BIT_ZERO 4'h0
`define TXU_BIT_ONE 4'h1
`define TXU_BIT_TWO 4'h2
`define TXU_BIT_THREE 4'h3
`define TXU_BIT_FOUR 4'h4
`define TXU_BIT_FIVE 4'h5
`define TXU_BIT_SIX 4'h6
`define TXU_BIT_SEVEN 4'h7
`define TXU_STOP 4'h8
`define TXU_IDLE 4'hf
`default_nettype none
//
`define TXUL_BIT_ZERO 4'h0
`define TXUL_BIT_ONE 4'h1
`define TXUL_BIT_TWO 4'h2
`define TXUL_BIT_THREE 4'h3
`define TXUL_BIT_FOUR 4'h4
`define TXUL_BIT_FIVE 4'h5
`define TXUL_BIT_SIX 4'h6
`define TXUL_BIT_SEVEN 4'h7
`define TXUL_STOP 4'h8
`define TXUL_IDLE 4'hf
//
//
module txuartlite(i_clk, i_wr, i_data, o_uart_tx, o_busy);
parameter [23:0] CLOCKS_PER_BAUD = 24'd868;
input i_clk;
input i_wr;
input [7:0] i_data;
input wire i_clk;
input wire i_wr;
input wire [7:0] i_data;
// And the UART input line itself
output reg o_uart_tx;
// A line to tell others when we are ready to accept data. If
79,7 → 81,7
reg r_busy, zero_baud_counter;
 
initial r_busy = 1'b1;
initial state = `TXU_IDLE;
initial state = `TXUL_IDLE;
initial lcl_data= 8'h0;
always @(posedge i_clk)
begin
86,21 → 88,21
if (!zero_baud_counter)
// r_busy needs to be set coming into here
r_busy <= 1'b1;
else if (state == `TXU_IDLE) // STATE_IDLE
else if (state == `TXUL_IDLE) // STATE_IDLE
begin
r_busy <= 1'b0;
if ((i_wr)&&(!r_busy))
begin // Immediately start us off with a start bit
r_busy <= 1'b1;
state <= `TXU_BIT_ZERO;
state <= `TXUL_BIT_ZERO;
end
end else begin
// One clock tick in each of these states ...
r_busy <= 1'b1;
if (state <=`TXU_STOP) // start bit, 8-d bits, stop-b
if (state <=`TXUL_STOP) // start bit, 8-d bits, stop-b
state <= state + 1;
else
state <= `TXU_IDLE;
state <= `TXUL_IDLE;
end
end
 
175,7 → 177,7
// than waiting for the end of the next (fictitious and arbitrary) baud
// interval.
//
// When (i_wr)&&(!r_busy)&&(state == `TXU_IDLE) then we're not only in
// When (i_wr)&&(!r_busy)&&(state == `TXUL_IDLE) then we're not only in
// the idle state, but we also just accepted a command to start writing
// the next word. At this point, the baud counter needs to be reset
// to the number of CLOCKS_PER_BAUD, and zero_baud_counter set to zero.
188,7 → 190,7
always @(posedge i_clk)
begin
zero_baud_counter <= (baud_counter == 24'h01);
if (state == `TXU_IDLE)
if (state == `TXUL_IDLE)
begin
baud_counter <= 24'h0;
zero_baud_counter <= 1'b1;
/ufifo.v
35,15 → 35,17
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module ufifo(i_clk, i_rst, i_wr, i_data, o_empty_n, i_rd, o_data, o_status, o_err);
parameter BW=8; // Byte/data width
parameter [3:0] LGFLEN=4;
parameter RXFIFO=1'b0;
input i_clk, i_rst;
input i_wr;
input [(BW-1):0] i_data;
input wire i_clk, i_rst;
input wire i_wr;
input wire [(BW-1):0] i_data;
output wire o_empty_n; // True if something is in FIFO
input i_rd;
input wire i_rd;
output wire [(BW-1):0] o_data;
output wire [15:0] o_status;
output wire o_err;
67,7 → 69,7
else if (i_rd)
will_overflow <= (will_overflow)&&(i_wr);
else if (i_wr)
will_overflow <= (w_first_plus_two == r_last);
will_overflow <= (will_overflow)||(w_first_plus_two == r_last);
else if (w_first_plus_one == r_last)
will_overflow <= 1'b1;
 
111,7 → 113,7
else if (i_wr)
will_underflow <= (will_underflow)&&(i_rd);
else if (i_rd)
will_underflow <= (w_last_plus_one == r_first);
will_underflow <= (will_underflow)||(w_last_plus_one == r_first);
else
will_underflow <= (r_last == r_first);
 
143,7 → 145,7
// else r_unfl <= 1'b1;
end
 
reg [7:0] fifo_here, fifo_next, r_data;
reg [(BW-1):0] fifo_here, fifo_next, r_data;
always @(posedge i_clk)
fifo_here <= fifo[r_last];
always @(posedge i_clk)
172,11 → 174,13
always @(posedge i_clk)
if (i_rst)
r_empty_n <= 1'b0;
else case({i_wr, i_rd})
2'b00: r_empty_n <= (r_first != r_last);
2'b11: r_empty_n <= (r_first != r_last);
2'b10: r_empty_n <= 1'b1;
2'b01: r_empty_n <= (r_first != w_last_plus_one);
else casez({i_wr, i_rd, will_underflow})
3'b00?: r_empty_n <= (r_first != r_last);
3'b11?: r_empty_n <= (r_first != r_last);
3'b10?: r_empty_n <= 1'b1;
3'b010: r_empty_n <= (r_first != w_last_plus_one);
// 3'b001: r_empty_n <= 1'b0;
default: begin end
endcase
 
wire w_full_n;
190,6 → 194,7
//
// Adjust for these differences here.
reg [(LGFLEN-1):0] r_fill;
initial r_fill = 0;
always @(posedge i_clk)
if (RXFIFO!=0) begin
// Calculate the number of elements in our FIFO
199,7 → 204,7
// another context.
if (i_rst)
r_fill <= 0;
else case({i_wr, i_rd})
else case({(i_wr)&&(!will_overflow), (i_rd)&&(!will_underflow)})
2'b01: r_fill <= r_first - r_next;
2'b10: r_fill <= r_first - r_last + 1'b1;
default: r_fill <= r_first - r_last;
206,7 → 211,8
endcase
end else begin
// Calculate the number of elements that are empty and
// can be filled within our FIFO
// can be filled within our FIFO. Hence, this is really
// not the fill, but (SIZE-1)-fill.
if (i_rst)
r_fill <= { (LGFLEN){1'b1} };
else case({i_wr, i_rd})
/wbuart.v
38,6 → 38,8
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
`define UART_SETUP 2'b00
`define UART_FIFO 2'b01
`define UART_RXREG 2'b10
60,16 → 62,16
localparam [3:0] LCLLGFLEN = (LGFLEN > 4'ha)? 4'ha
: ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN);
//
input i_clk, i_rst;
input wire i_clk, i_rst;
// Wishbone inputs
input i_wb_cyc, i_wb_stb, i_wb_we;
input [1:0] i_wb_addr;
input [31:0] i_wb_data;
input wire i_wb_cyc, i_wb_stb, i_wb_we;
input wire [1:0] i_wb_addr;
input wire [31:0] i_wb_data;
output reg o_wb_ack;
output wire o_wb_stall;
output reg [31:0] o_wb_data;
//
input i_uart_rx;
input wire i_uart_rx;
output wire o_uart_tx;
// RTS is used for hardware flow control. According to Wikipedia, it
// should probably be renamed RTR for "ready to receive". It tell us
78,7 → 80,7
//
// If you don't wish to use hardware flow control, just set i_cts_n to
// 1'b0 and let the optimizer simply remove this logic.
input i_cts_n;
input wire i_cts_n;
// CTS is the "Clear-to-send" signal. We set it anytime our FIFO
// isn't full. Feel free to ignore this output if you do not wish to
// use flow control.
340,7 → 342,7
tx_uart_reset <= 1'b0;
 
`ifdef USE_LITE_UART
txuart #(INITIAL_SETUP[23:0]) tx(i_clk, (tx_empty_n), tx_data,
txuartlite #(INITIAL_SETUP[23:0]) tx(i_clk, (tx_empty_n), tx_data,
o_uart_tx, tx_busy);
`else
wire cts_n;

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