URL
https://opencores.org/ocsvn/wbuart32/wbuart32/trunk
Subversion Repositories wbuart32
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- This comparison shows the changes necessary to convert path
/wbuart32/trunk/rtl
- from Rev 9 to Rev 14
- ↔ Reverse comparison
Rev 9 → Rev 14
/rxuart.v
19,7 → 19,7
// Now for the setup register. The register is 32 bits, so that this |
// UART may be set up over a 32-bit bus. |
// |
// i_setup[30] True if we are using hardware flow control. This bit |
// i_setup[30] True if we are not using hardware flow control. This bit |
// is ignored within this module, as any receive hardware flow |
// control will need to be implemented elsewhere. |
// |
/txuart.v
171,7 → 171,7
always @(posedge i_clk) |
qq_rts <= q_rts; |
always @(posedge i_clk) |
ck_rts <= (qq_rts)&&(hw_flow_control); |
ck_rts <= (qq_rts)||(!hw_flow_control); |
|
initial o_uart_tx = 1'b1; |
initial r_busy = 1'b1; |
255,7 → 255,7
// broken out up top, and indicate what 1) our baud rate is, 2) our |
// number of stop bits, 3) what type of parity we are using, and 4) |
// the size of our data word. |
initial r_setup = INITIAL_SETUP[30:0]; |
initial r_setup = INITIAL_SETUP; |
always @(posedge i_clk) |
if (state == `TXU_IDLE) |
r_setup <= i_setup; |
/ufifo.v
38,7 → 38,7
module ufifo(i_clk, i_rst, i_wr, i_data, o_empty_n, i_rd, o_data, o_status, o_err); |
parameter BW=8; // Byte/data width |
parameter [3:0] LGFLEN=4; |
parameter [0:0] RXFIFO=0; |
parameter RXFIFO=1'b0; |
input i_clk, i_rst; |
input i_wr; |
input [(BW-1):0] i_data; |
190,12 → 190,13
// |
// Adjust for these differences here. |
reg [(LGFLEN-1):0] r_fill; |
generate if (RXFIFO!=0) begin |
// Calculate the number of elements in our FIFO |
// |
// Although used for receive, this is actually the more generic |
// answer--should you wish to use the FIFO in another context. |
always @(posedge i_clk) |
always @(posedge i_clk) |
if (RXFIFO!=0) begin |
// Calculate the number of elements in our FIFO |
// |
// Although used for receive, this is actually the more |
// generic answer--should you wish to use the FIFO in |
// another context. |
if (i_rst) |
r_fill <= 0; |
else case({i_wr, i_rd}) |
203,10 → 204,9
2'b10: r_fill <= r_first - r_last + 1'b1; |
default: r_fill <= r_first - r_last; |
endcase |
end else begin |
// Calculate the number of elements that are empty and can be |
// filled within our FIFO |
always @(posedge i_clk) |
end else begin |
// Calculate the number of elements that are empty and |
// can be filled within our FIFO |
if (i_rst) |
r_fill <= { (LGFLEN){1'b1} }; |
else case({i_wr, i_rd}) |
214,7 → 214,7
2'b10: r_fill <= r_last - w_first_plus_two; |
default: r_fill <= r_last - w_first_plus_one; |
endcase |
end endgenerate |
end |
|
// We don't report underflow errors. These |
assign o_err = (r_ovfl); // || (r_unfl); |
224,8 → 224,8
|
wire [9:0] w_fill; |
assign w_fill[(LGFLEN-1):0] = r_fill; |
generate if (LGFLEN != 10) |
assign w_fill[9:(LGFLEN-1)] = 0; |
generate if (LGFLEN < 10) |
assign w_fill[9:(LGFLEN)] = 0; |
endgenerate |
|
wire w_half_full; |