OpenCores
URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /wbuart32
    from Rev 22 to Rev 23
    ↔ Reverse comparison
  •

Rev 22 → Rev 23

/trunk/bench/cpp/uartsim.cpp
77,7 → 77,7
// any/every one of them.
my_addr.sin_addr.s_addr = htonl(INADDR_ANY);
my_addr.sin_port = htons(port);
 
if (bind(m_skt, (struct sockaddr *)&my_addr, sizeof(my_addr))!=0) {
perror("ERR: BIND FAILED:");
exit(EXIT_FAILURE);
152,10 → 152,11
 
}
 
int UARTSIM::nettick(int i_tx) {
int UARTSIM::rawtick(const int i_tx, const bool network) {
int o_rx = 1, nr = 0;
 
check_for_new_connections();
if (network)
check_for_new_connections();
 
if ((!i_tx)&&(m_last_tx))
m_rx_changectr = 0;
176,10 → 177,14
if (m_conwr >= 0) {
char buf[1];
buf[0] = (m_rx_data >> (32-m_nbits-m_nstop-m_nparity))&0x0ff;
if (1 != send(m_conwr, buf, 1, 0)) {
if ((network)&&(1 != send(m_conwr, buf, 1, 0))) {
close(m_conwr);
m_conrd = m_conwr = -1;
fprintf(stderr, "Failed write, connection closed\n");
} else if ((!network)&&(1 != write(m_conwr, buf, 1))) {
fprintf(stderr, "ERR while attempting to write out--closing output port\n");
perror("UARTSIM::write() ");
m_conrd = m_conwr = -1;
}
}
} else {
200,15 → 205,21
} else
m_rx_baudcounter--;
 
if (m_tx_state == TXIDLE) {
if ((m_tx_state == TXIDLE)&&((network)||(m_conrd >= 0))) {
struct pollfd pb;
pb.fd = m_conrd;
pb.events = POLLIN;
if (poll(&pb, 1, 0) < 0)
perror("Polling error:");
 
if (pb.revents & POLLIN) {
char buf[1];
if (1 == (nr = recv(m_conrd, buf, 1, MSG_DONTWAIT))) {
 
if (network)
nr = recv(m_conrd, buf, 1, MSG_DONTWAIT);
else
nr = read(m_conrd, buf, 1);
if (1 == nr) {
m_tx_data = (-1<<(m_nbits+m_nparity+1))
// << nstart_bits
|((buf[0]<<1)&0x01fe);
233,14 → 244,20
m_tx_state = TXDATA;
o_rx = 0;
m_tx_baudcounter = m_baud_counts-1;
} else if (nr == 0) {
} else if ((network)&&(nr == 0)) {
close(m_conrd);
m_conrd = m_conwr = -1;
// printf("Closing network connection\n");
} else if (nr < 0) {
perror("O/S Read err:");
close(m_conrd);
m_conrd = m_conwr = -1;
if (!network) {
fprintf(stderr, "ERR while attempting to read in--closing input port\n");
perror("UARTSIM::read() ");
m_conrd = -1;
} else {
perror("O/S Read err:");
close(m_conrd);
m_conrd = m_conwr = -1;
}
}
}
} else if (m_tx_baudcounter <= 0) {
259,106 → 276,10
return o_rx;
}
 
int UARTSIM::fdtick(int i_tx) {
int o_rx = 1;
int UARTSIM::nettick(const int i_tx) {
return rawtick(i_tx, true);
}
 
if ((!i_tx)&&(m_last_tx))
m_rx_changectr = 0;
else m_rx_changectr++;
m_last_tx = i_tx;
 
if (m_rx_state == RXIDLE) {
if (!i_tx) {
m_rx_state = RXDATA;
m_rx_baudcounter =m_baud_counts+m_baud_counts/2-1;
m_rx_baudcounter -= m_rx_changectr;
m_rx_busy = 0;
m_rx_data = 0;
}
} else if (m_rx_baudcounter <= 0) {
if (m_rx_busy >= (1<<(m_nbits+m_nparity+m_nstop-1))) {
m_rx_state = RXIDLE;
if (m_conwr >= 0) {
char buf[1];
buf[0] = (m_rx_data >> (32-m_nbits-m_nstop-m_nparity))&0x0ff;
if (1 != write(m_conwr, buf, 1)) {
fprintf(stderr, "ERR while attempting to write out--closing output port\n");
perror("UARTSIM::write() ");
m_conrd = m_conwr = -1;
}
}
} else {
m_rx_busy = (m_rx_busy << 1)|1;
// Low order bit is transmitted first, in this
// order:
// Start bit (1'b1)
// bit 0
// bit 1
// bit 2
// ...
// bit N-1
// (possible parity bit)
// stop bit
// (possible secondary stop bit)
m_rx_data = ((i_tx&1)<<31) | (m_rx_data>>1);
} m_rx_baudcounter = m_baud_counts-1;
} else
m_rx_baudcounter--;
 
if ((m_tx_state == TXIDLE)&&(m_conrd >= 0)) {
struct pollfd pb;
pb.fd = m_conrd;
pb.events = POLLIN;
if (poll(&pb, 1, 0) < 0)
perror("Polling error:");
if (pb.revents & POLLIN) {
char buf[1];
int nr;
if (1==(nr = read(m_conrd, buf, 1))) {
m_tx_data = (-1<<(m_nbits+m_nparity+1))
// << nstart_bits
|((buf[0]<<1)&0x01fe);
if (m_nparity) {
int p;
 
// If m_nparity is set, we need to then
// create the parity bit.
if (m_fixdp)
p = m_evenp;
else {
p = (m_tx_data >> 1)&0x0ff;
p = p ^ (p>>4);
p = p ^ (p>>2);
p = p ^ (p>>1);
p &= 1;
p ^= m_evenp;
}
m_tx_data |= (p<<(m_nbits+m_nparity));
}
m_tx_busy = (1<<(m_nbits+m_nparity+m_nstop+1))-1;
m_tx_state = TXDATA;
o_rx = 0;
m_tx_baudcounter = m_baud_counts-1;
} else if (nr < 0) {
fprintf(stderr, "ERR while attempting to read in--closing input port\n");
perror("UARTSIM::read() ");
m_conrd = -1;
} // and we really don't care if nr == 0 except that
// the poll above is supposed to keep it from happening
}
} else if (m_tx_baudcounter == 0) {
m_tx_data >>= 1;
m_tx_busy >>= 1;
if (!m_tx_busy)
m_tx_state = TXIDLE;
else
m_tx_baudcounter = m_baud_counts-1;
o_rx = m_tx_data&1;
} else {
m_tx_baudcounter--;
o_rx = m_tx_data&1;
}
 
return o_rx;
int UARTSIM::fdtick(const int i_tx) {
return rawtick(i_tx, false);
}
 
/trunk/bench/cpp/uartsim.h
85,8 → 85,8
 
// nettick() gets called if we are connected to a network, and
int nettick(const int i_tx);
// fdtick() if we are not.
int fdtick(const int i_tx);
int rawtick(const int i_tx, const bool network);
 
// We'll use the file descriptor for the listener socket to determine
// whether we are connected to the network or not. If not connected
93,10 → 93,7
// to the network, then we assume m_conrd and m_conwr refer to
// your more traditional file descriptors, and use them as such.
int tick(const int i_tx) {
if (m_skt >= 0)
return nettick(i_tx);
else
return fdtick(i_tx);
return rawtick(i_tx, (m_skt >= 0));
}
 
public:
/trunk/bench/formal/rxuartlite.sby
12,8 → 12,10
smtbmc
 
[script]
one: read_verilog -D RXUARTLITE -formal rxuartlite.v
two: read_verilog -D RXUARTLITE -D PHASE_TWO -formal rxuartlite.v
read -define F_OPT_CLK2FFLOGIC
read -define RXUARTLITE
one: read -sv -formal rxuartlite.v
two: read -sv -D PHASE_TWO -formal rxuartlite.v
chparam -set CLOCKS_PER_BAUD 16 rxuartlite
prep -top rxuartlite
# opt_merge -share_all
/trunk/bench/formal/txuartlite.sby
24,4 → 24,4
--
 
[files]
txuartlite.v
../../rtl/txuartlite.v
/trunk/rtl/rxuartlite.v
204,7 → 204,8
 
`ifdef FORMAL
 
// `define PHASE_TWO // SymbiYosys controls this definition
`define ASSUME assume
 
`define PHASE_ONE_ASSERT assert
`define PHASE_TWO_ASSERT assert
 
239,6 → 240,7
always @(posedge i_clk)
f_past_valid <= 1'b1;
 
`ifdef F_OPT_CLK2FFLOGIC
initial f_rx_clock = 3'h0;
always @($global_clock)
f_rx_clock <= f_rx_clock + 1'b1;
245,6 → 247,7
 
always @(*)
assume(i_clk == f_rx_clock[1]);
`endif
 
 
 
271,6 → 274,7
initial assert(F_MINSTEP <= F_MIDSTEP);
initial assert(F_MIDSTEP <= F_MAXSTEP);
 
`ifdef F_OPT_CLK2FFLOGIC
assign f_tx_step = $anyconst;
// assume((f_tx_step >= F_MINSTEP)&&(f_tx_step <= F_MAXSTEP));
//
284,7 → 288,9
f_tx_clock <= f_tx_clock + f_tx_step;
 
assign f_txclk = f_tx_clock[F_CKRES-1];
 
`else
assign f_tx_clk = i_clk;
`endif
//
initial f_past_valid_tx = 1'b0;
always @(posedge f_txclk)
/trunk/rtl/txuart.v
221,7 → 221,7
if (state == `TXU_BIT_SEVEN)
state <= (use_parity)?`TXU_PARITY:`TXU_STOP;
else
state <= state + 1;
state <= state + 1'b1;
end else if (state == `TXU_PARITY)
begin
state <= `TXU_STOP;
392,5 → 392,191
end else
baud_counter <= clocks_per_baud - 28'h01;
end
 
`ifdef FORMAL
reg fsv_parity;
reg [30:0] fsv_setup;
reg [7:0] fsv_data;
 
always @(posedge i_clk)
if ((i_wr)&&(!o_busy))
fsv_data <= i_data;
 
always @(posedge i_clk)
if ((i_wr)&&(!o_busy))
fsv_setup <= i_setup;
 
always @(posedge i_clk)
assert(zero_baud_counter == (baud_counter == 0));
 
always @(*)
assume(i_setup[21:0] >= 2);
always @(*)
assume(i_setup[21:0] <= 16);
 
// A single baud interval
sequence BAUD_INTERVAL(DAT, SR, ST);
((o_uart_tx == DAT)&&(state == ST)
&&(lcl_data == SR)
&&(baud_counter == fsv_setup[21:0]-1)
&&(!zero_baud_counter))
##1 ((o_uart_tx == DAT)&&(state == ST)
&&(lcl_data == SR)
&&(baud_counter == $past(baud_counter)-1)
&&(baud_counter > 0)
&&(baud_counter < fsv_setup[21:0])
&&(!zero_baud_counter))[*0:$]
##1 (o_uart_tx == DAT)&&(state == ST)
&&(lcl_data == SR)
&&(zero_baud_counter);
endsequence
 
//
// One byte transmitted
//
// DATA = the byte that is sent
// CKS = the number of clocks per bit
//
sequence SEND5(DATA);
BAUD_INTERVAL(1'b0, DATA, 4'h3)
##1 BAUD_INTERVAL(DATA[0], {{(1){1'b1}},DATA[7:1]}, 4'h4)
##1 BAUD_INTERVAL(DATA[1], {{(2){1'b1}},DATA[7:2]}, 4'h5)
##1 BAUD_INTERVAL(DATA[2], {{(3){1'b1}},DATA[7:3]}, 4'h6)
##1 BAUD_INTERVAL(DATA[3], {{(4){1'b1}},DATA[7:4]}, 4'h7)
##1 BAUD_INTERVAL(DATA[4], {{(5){1'b1}},DATA[7:5]}, 4'h8);
endsequence
 
sequence SEND6(DATA);
BAUD_INTERVAL(1'b0, DATA, 4'h2)
##1 BAUD_INTERVAL(DATA[0], {{(1){1'b1}},DATA[7:1]}, 4'h3)
##1 BAUD_INTERVAL(DATA[1], {{(2){1'b1}},DATA[7:2]}, 4'h4)
##1 BAUD_INTERVAL(DATA[2], {{(3){1'b1}},DATA[7:3]}, 4'h5)
##1 BAUD_INTERVAL(DATA[3], {{(4){1'b1}},DATA[7:4]}, 4'h6)
##1 BAUD_INTERVAL(DATA[4], {{(5){1'b1}},DATA[7:5]}, 4'h7)
##1 BAUD_INTERVAL(DATA[5], {{(6){1'b1}},DATA[7:6]}, 4'h8);
endsequence
 
sequence SEND7(DATA);
BAUD_INTERVAL(1'b0, DATA, 4'h1)
##1 BAUD_INTERVAL(DATA[0], {{(1){1'b1}},DATA[7:1]}, 4'h2)
##1 BAUD_INTERVAL(DATA[1], {{(2){1'b1}},DATA[7:2]}, 4'h3)
##1 BAUD_INTERVAL(DATA[2], {{(3){1'b1}},DATA[7:3]}, 4'h4)
##1 BAUD_INTERVAL(DATA[3], {{(4){1'b1}},DATA[7:4]}, 4'h5)
##1 BAUD_INTERVAL(DATA[4], {{(5){1'b1}},DATA[7:5]}, 4'h6)
##1 BAUD_INTERVAL(DATA[5], {{(6){1'b1}},DATA[7:6]}, 4'h7)
##1 BAUD_INTERVAL(DATA[6], {{(7){1'b1}},DATA[7:7]}, 4'h8);
endsequence
 
sequence SEND8(DATA);
BAUD_INTERVAL(1'b0, DATA, 4'h0)
##1 BAUD_INTERVAL(DATA[0], {{(1){1'b1}},DATA[7:1]}, 4'h1)
##1 BAUD_INTERVAL(DATA[1], {{(2){1'b1}},DATA[7:2]}, 4'h2)
##1 BAUD_INTERVAL(DATA[2], {{(3){1'b1}},DATA[7:3]}, 4'h3)
##1 BAUD_INTERVAL(DATA[3], {{(4){1'b1}},DATA[7:4]}, 4'h4)
##1 BAUD_INTERVAL(DATA[4], {{(5){1'b1}},DATA[7:5]}, 4'h5)
##1 BAUD_INTERVAL(DATA[5], {{(6){1'b1}},DATA[7:6]}, 4'h6)
##1 BAUD_INTERVAL(DATA[6], {{(7){1'b1}},DATA[7:7]}, 4'h7)
##1 BAUD_INTERVAL(DATA[7], 8'hff, 4'h8);
endsequence
 
always @(posedge i_clk)
if (fsv_setup[25])
fsv_parity <= fsv_setup[24];
else
case(fsv_setup[29:28])
2'b00: fsv_parity <= (^fsv_data[4:0]) ^ fsv_setup[24];
2'b01: fsv_parity <= (^fsv_data[5:0]) ^ fsv_setup[24];
2'b10: fsv_parity <= (^fsv_data[6:0]) ^ fsv_setup[24];
2'b11: fsv_parity <= (^fsv_data[7:0]) ^ fsv_setup[24];
endcase
 
assert property( @(posedge i_clk)
(o_busy)[*2] |=> $stable(fsv_parity));
 
assert property( @(posedge i_clk)
(o_busy) |=> $stable(fsv_data));
 
assert property( @(posedge i_clk)
(o_busy) |=> $stable(fsv_setup));
 
sequence SENDPARITY(SETUP);
((o_uart_tx == fsv_parity)&&(state == `TXU_PARITY)
&&(SETUP[26])
&&(baud_counter == SETUP[21:0]-1)
&&(!zero_baud_counter))
##1 ((o_uart_tx == fsv_parity)&&(state == `TXU_PARITY)
&&(SETUP[26])
&&(baud_counter < SETUP[21:0])
&&(baud_counter > 0)
&&(baud_counter == $past(baud_counter)-1)
&&(!zero_baud_counter))[*0:$]
##1 (o_uart_tx == fsv_parity)&&(state == `TXU_PARITY)
&&(SETUP[26])
&&(zero_baud_counter);
endsequence
 
sequence SENDSINGLESTOP(CKS,ST);
((o_uart_tx == 1'b1)&&(state == ST)
&&(baud_counter == CKS-1)
&&(!zero_baud_counter))
##1 ((o_uart_tx == 1'b1)&&(state == ST)
&&(baud_counter > 0)
&&(baud_counter == $past(baud_counter)-1)
&&(!zero_baud_counter))[*0:$]
##1 (o_uart_tx == 1'b1)&&(state == ST)
&&(zero_baud_counter);
endsequence
 
sequence SENDFULLSTOP(SETUP);
((!SETUP[27]) throughout SENDSINGLESTOP(SETUP[21:0],`TXU_STOP))
or (SETUP[27]) throughout
SENDSINGLESTOP(SETUP[21:0],`TXU_STOP)
##1 SENDSINGLESTOP(SETUP[21:0],`TXU_SECOND_STOP);
endsequence
 
sequence UART_IDLE;
(!o_busy)&&(o_uart_tx)&&(zero_baud_counter);
endsequence
 
assert property ( @(posedge i_clk) (!o_busy) |-> UART_IDLE);
 
 
assert property ( @(posedge i_clk)
(i_wr)&&(!o_busy)&&(i_setup[29:28]==2'b00) |=>
((o_busy) throughout
SEND5(fsv_data)
##1 SENDPARITY(fsv_setup)
##1 SENDFULLSTOP(fsv_setup)
)
##1 UART_IDLE);
 
assert property ( @(posedge i_clk)
(i_wr)&&(!o_busy)&&(i_setup[29:28]==2'b01) |=>
((o_busy) throughout
SEND6(fsv_data)
##1 SENDPARITY(fsv_setup)
##1 SENDFULLSTOP(fsv_setup)
)
##1 UART_IDLE);
 
assert property ( @(posedge i_clk)
(i_wr)&&(!o_busy)&&(i_setup[29:28]==2'b10) |=>
((o_busy) throughout
SEND7(fsv_data)
##1 SENDPARITY(fsv_setup)
##1 SENDFULLSTOP(fsv_setup)
)
##1 UART_IDLE);
 
assert property ( @(posedge i_clk)
(i_wr)&&(!o_busy)&&(i_setup[29:28]==2'b11) |=>
((o_busy) throughout
SEND8(fsv_data)
##1 SENDPARITY(fsv_setup)
##1 SENDFULLSTOP(fsv_setup)
)
##1 UART_IDLE);
 
`endif // FORMAL
endmodule
 
/trunk/rtl/ufifo.v
374,5 → 374,19
end
end
 
always @(posedge i_clk)
if (RXFIFO)
begin
assert(o_status[0] == (f_fill != 0));
assert(o_status[1] == (f_fill[LGFLEN-1]));
end
 
always @(posedge i_clk)
if (!RXFIFO) // Transmit FIFO interrupt flags
begin
assert(o_status[0] != (!w_full_n));
assert(o_status[1] == (!f_fill[LGFLEN-1]));
end
 
`endif
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.