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URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

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  • This comparison shows the changes necessary to convert path 
    /wbuart32
    from Rev 9 to Rev 10
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Rev 9 → Rev 10

/trunk/bench/verilog/echotest.v
72,7 → 72,7
i_uart_rx, o_uart_tx);
input i_clk;
`ifndef OPT_STANDALONE
input [29:0] i_setup;
input [30:0] i_setup;
`endif
input i_uart_rx;
output wire o_uart_tx;
102,7 → 102,7
// This code only applies if OPT_DUMBECHO is not defined.
`ifdef OPT_STANDALONE
wire [29:0] i_setup;
assign i_setup = 30'd868; // 115200 Baud, if clk @ 100MHz
assign i_setup = 31'd868; // 115200 Baud, if clk @ 100MHz
`endif
 
// Create a reset line that will always be true on a power on reset
128,9 → 128,13
rxuart receiver(i_clk, pwr_reset, i_setup, i_uart_rx, rx_stb, rx_data,
rx_break, rx_perr, rx_ferr, rx_ignored);
 
// Bypass any transmit hardware flow control.
wire rts;
assign rts = 1'b1;
 
wire tx_busy;
txuart transmitter(i_clk, pwr_reset, i_setup, rx_break,
rx_stb, rx_data, o_uart_tx, tx_busy);
rx_stb, rx_data, rts, o_uart_tx, tx_busy);
 
`endif
 
/trunk/bench/verilog/helloworld.v
57,7 → 57,7
input i_clk;
output wire o_uart_tx;
`ifndef OPT_STANDALONE
input [29:0] i_setup;
input [30:0] i_setup;
`endif
 
// If i_setup isnt set up as an input parameter, it needs to be set.
65,8 → 65,8
// comms system from a 100MHz clock. This also sets us to an 8-bit
// data word, 1-stop bit, and no parity.
`ifdef OPT_STANDALONE
wire [29:0] i_setup;
assign i_setup = 30'd868; // 115200 Baud, if clk @ 100MHz
wire [30:0] i_setup;
assign i_setup = 31'd868; // 115200 Baud, if clk @ 100MHz
`endif
 
reg pwr_reset;
121,7 → 121,11
else if ((tx_stb)&&(!tx_busy)&&(tx_index==4'hf))
tx_stb <= 1'b0;
 
// Bypass any hardware flow control
wire rts;
assign rts = 1'b1;
 
txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
tx_stb, tx_data, o_uart_tx, tx_busy);
tx_stb, tx_data, rts, o_uart_tx, tx_busy);
 
endmodule
/trunk/bench/verilog/linetest.v
56,7 → 56,7
i_uart_rx, o_uart_tx);
input i_clk;
`ifndef OPT_STANDALONE
input [29:0] i_setup;
input [30:0] i_setup;
`endif
input i_uart_rx;
output wire o_uart_tx;
67,7 → 67,7
// data word, 1-stop bit, and no parity.
`ifdef OPT_STANDALONE
wire [29:0] i_setup;
assign i_setup = 30'd868; // 115200 Baud, if clk @ 100MHz
assign i_setup = 31'd868; // 115200 Baud, if clk @ 100MHz
`endif
 
reg [7:0] buffer [0:255];
194,8 → 194,12
tail <= 8'h00;
else if ((tx_stb)&&(!tx_busy))
tail <= tail + 8'h01;
 
// Bypass any hardwaare flow control
wire rts;
assign rts = 1'b1;
 
txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
tx_stb, tx_data, o_uart_tx, tx_busy);
tx_stb, tx_data, rts, o_uart_tx, tx_busy);
 
endmodule
/trunk/bench/verilog/speechfifo.v
45,13 → 45,18
////////////////////////////////////////////////////////////////////////////////
//
//
// Uncomment the next line if you want this program to work as a standalone
// (not verilated) RTL "program" to test your UART. You'll also need to set
// your i_setup condition properly, though (below). I recommend setting it to
// the ratio of your onboard clock to your desired baud rate. For more
// information about how to set this, please see the specification.
// One issue with the design is how to set the values of the setup register.
// (*This is a comment, not a verilator attribute ... ) Verilator needs to
// know/set those values in order to work. However, this design can also be
// used as a stand-alone top level configuration file. In this latter case,
// the setup register needs to be set internal to the file. Here, we use
// OPT_STANDALONE to distinguish between the two. If set, the file runs under
// (* Another comment still ...) Verilator and we need to get i_setup from the
// external environment. If not, it must be set internally.
//
//`define OPT_STANDALONE
`ifndef VERILATOR
`define OPT_STANDALONE
`endif
//
module speechfifo(i_clk,
`ifndef OPT_STANDALONE
65,16 → 70,16
// UART system from a 100MHz clock. This also sets us to an 8-bit data
// word, 1-stop bit, and no parity. This will be overwritten by
// i_setup, but at least it gives us something to start with/from.
parameter INITIAL_UART_SETUP = 30'd868;
parameter INITIAL_UART_SETUP = 31'd868;
 
// The i_setup wires are input when run under Verilator, but need to
// be set internally if this is going to run as a standalone top level
// test configuration.
`ifdef OPT_STANDALONE
wire [29:0] i_setup;
wire [30:0] i_setup;
assign i_setup = INITIAL_UART_SETUP;
`else
input [29:0] i_setup;
input [30:0] i_setup;
`endif
 
reg restart;
104,9 → 109,36
integer i;
reg [7:0] message [0:2047];
initial begin
$readmemh("speech.hex",message);
// xx Verilator needs this file to be in the directory the file
// is run from. For that reason, the project builds, makes,
// and keeps speech.hex in bench/cpp.
//
// Vivado, however, wants speech.hex to be in a project file
// directory, such as bench/verilog. For that reason, the
// build function in bench/cpp also copies speech.hex to the
// bench/verilog directory. You may need to make certain the
// file is both built, and copied into a directory where your
// synthesis tool can find it.
//
$readmemh("speech.hex", message);
for(i=1481; i<2048; i=i+1)
message[i] = 8'h20;
//
// The problem with the above approach is Xilinx's ISE program.
// It's broken. It can't handle HEX files well (at all?) and
// has more problems with HEX's defining ROM's. For that
// reason, the mkspeech program can be tuned to create an
// include file, speech.inc. We include that program here.
// It is rather ugly, though, and not a very elegant solution,
// since it walks through every value in our speech, byte by
// byte, with an initial line for each byte declaring what it
// is to be.
//
// If you (need to) use this route, comment out both the
// readmemh, the for loop, and the message[i] = 8'h20 lines
// above and uncomment the include line below.
//
// `include "speech.inc"
end
 
// Let's keep track of time, and send our message over and over again.
160,7 → 192,7
// serial port configuration parameters. Ideally,
// we'd only set this once. But rather than complicate
// the logic, we set it everytime we start over.
wb_data <= { 2'b00, i_setup };
wb_data <= { 1'b0, i_setup };
else if ((wb_stb)&&(!uart_stall))
// Then, if the last thing was received over the bus,
// we move to the next data item.
208,15 → 240,10
// Stop transmitting when we get to the end of our
// message.
wb_stb <= 1'b0;
else if (tx_int)
// If we aren't at the end of the message, and tx_int
// tells us the FIFO is empty, then start writing into
// the FIFO>
else if (txfifo_int)
// If the FIFO is less than half full, then write to
// it.
wb_stb <= 1'b1;
else if (txfifo_int)
// If we are writing into the FIFO, and it's less than
// half full (i.e. txfifo_int is true) then keep going.
wb_stb <= wb_stb;
else
// But once the FIFO gets to half full, stop.
wb_stb <= 1'b0;
225,13 → 252,23
// here as ignored.
wire ignored_rx_int, ignored_rxfifo_int;
 
// The WBUART can handle hardware flow control signals. This test,
// however, cannot. The reason? Simply just to keep things simple.
// If you want to add hardware flow control to your design, simply
// make rts an input to this module.
//
// Since this is an output only module demonstrator, what would be the
// cts output is unused.
wire rts, cts;
assign rts = 1'b1;
 
// Finally--the unit under test--now that we've set up all the wires
// to run/test it.
wbuart #(INITIAL_UART_SETUP)
wbuarti(i_clk, pwr_reset,
wb_stb, wb_stb, 1'b1, wb_addr, wb_data,
uart_stall, uart_ack, uart_data,
1'b1, o_uart_tx,
uart_ack, uart_stall, uart_data,
1'b1, o_uart_tx, rts, cts,
ignored_rx_int, tx_int,
ignored_rxfifo_int, txfifo_int);
 

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