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URL https://opencores.org/ocsvn/wishbone_uart_controller/wishbone_uart_controller/trunk

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/branches/uartcontroller/processor.vhd
0,0 → 1,179
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:50:00 04/16/2013
-- Design Name:
-- Module Name: processor_uart - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity processor is
Port (
ACK_I : IN std_logic;
CLK_I : IN std_logic;
DAT_I : IN std_logic_vector(7 downto 0);
RST_I : IN std_logic;
ADR_O : OUT std_logic_vector(7 downto 0);
CYC_O : OUT std_logic;
DAT_O: OUT std_logic_vector(7 downto 0);
STB_O : OUT std_logic;
WE_O: OUT std_logic;
RX : IN std_logic;
TX : OUT std_logic
 
);
 
end processor;
 
architecture Behavioral of processor is
COMPONENT burst_uart
PORT(
CLOCK : IN std_logic;
DBIN : IN std_logic_vector(7 downto 0);
write_strobe : IN std_logic;
RESET : IN std_logic;
DATA_STREAM_OUT_ACK : IN std_logic;
RX : IN std_logic;
ack : OUT std_logic;
DATA_OUT : OUT std_logic_vector(7 downto 0);
DATA_STREAM_OUT_STB : OUT std_logic;
send_data: in std_logic;
queue_empty:out std_logic;
TX : OUT std_logic
);
END COMPONENT;
 
COMPONENT uart_to_instruction
PORT(
uart_rx_data_out_stb : IN std_logic;
data_in : IN std_logic_vector(7 downto 0);
next_instructie : IN std_logic;
clock : IN std_logic;
queue_empty : IN std_logic;
rd : OUT std_logic;
enable : OUT std_logic;
send_data : OUT std_logic;
opcode : OUT std_logic;
adress : OUT std_logic_vector(7 downto 0);
data : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
 
 
 
-- VHDL Instantiation Created from source file IOALU.vhd -- 10:58:43 05/23/2013
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
 
COMPONENT IOALU
PORT(
ACK_I : IN std_logic;
CLK_I : IN std_logic;
DAT_I : IN std_logic_vector(7 downto 0);
RST_I : IN std_logic;
enable : IN std_logic;
adress : IN std_logic_vector(7 downto 0);
db_in : IN std_logic_vector(7 downto 0);
queue_ack : IN std_logic;
opcode : IN std_logic;
ADR_O : OUT std_logic_vector(7 downto 0);
CYC_O : OUT std_logic;
DAT_O : OUT std_logic_vector(7 downto 0);
STB_O : OUT std_logic;
WE_O : OUT std_logic;
db_out : OUT std_logic_vector(7 downto 0);
rs232_we : OUT std_logic;
error : OUT std_logic;
next_instructie : OUT std_logic
);
END COMPONENT;
 
 
 
signal db_out,DATA_OUT :std_logic_vector(7 downto 0);
signal uart_rx_data_out_stb,next_instructie: std_logic;
signal rd,enable,send_data,queue_empty,write_strobe: std_logic;
signal opcode,error,queue_ack: std_logic;
signal adress :std_logic_vector(7 downto 0);
signal data : std_logic_vector(7 downto 0);
begin
 
Inst_uart_to_instruction: uart_to_instruction PORT MAP(
CLOCK => CLK_I,
uart_rx_data_out_stb =>uart_rx_data_out_stb,
data_in=> DATA_OUT,
rd => rd,
enable=>enable,
send_data=>send_data,
queue_empty=>queue_empty,
next_instructie=>next_instructie,
opcode => opcode,
adress => adress,
data => data
);
 
Inst_burst_uart: burst_uart PORT MAP(
CLOCK => CLK_I,
DBIN => db_out,
write_strobe => write_strobe,
ack => queue_ack,
RESET => RST_I,
DATA_STREAM_OUT_ACK => rd,
DATA_OUT => DATA_OUT,
DATA_STREAM_OUT_STB => uart_rx_data_out_stb,
send_data=>send_data,
queue_empty=>queue_empty,
RX => RX,
TX => TX
);
Inst_IOALU: IOALU PORT MAP(
ACK_I => ACK_I,
ADR_O => ADR_O,
CLK_I => CLK_I,
CYC_O => CYC_O,
DAT_I => DAT_I,
DAT_O => DAT_O,
RST_I => RST_I,
STB_O => STB_O,
WE_O => WE_O,
enable =>enable ,
adress => adress,
db_in => data,
db_out => db_out,
rs232_we =>write_strobe,
queue_ack => queue_ack,
opcode => opcode,
error => error,
next_instructie => next_instructie
);
 
end Behavioral;
 
/branches/uartcontroller/testbench/testprocessor.vhd
0,0 → 1,256
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:07:53 05/23/2013
-- Design Name:
-- Module Name: C:/Users/boris/Documents/projects/usb_io_processor/test_IOprocessor.vhd
-- Project Name: usb_io_processor
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: processor
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_IOprocessor IS
END test_IOprocessor;
ARCHITECTURE behavior OF test_IOprocessor IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT processor
PORT(
ACK_I : IN std_logic;
CLK_I : IN std_logic;
DAT_I : IN std_logic_vector(7 downto 0);
RST_I : IN std_logic;
ADR_O : OUT std_logic_vector(7 downto 0);
CYC_O : OUT std_logic;
DAT_O : OUT std_logic_vector(7 downto 0);
STB_O : OUT std_logic;
WE_O : OUT std_logic;
RX : IN std_logic;
TX : OUT std_logic
);
END COMPONENT;
 
--Inputs
signal ACK_I : std_logic := '0';
signal CLK_I : std_logic := '0';
signal DAT_I : std_logic_vector(7 downto 0) := (others => '0');
signal RST_I : std_logic := '0';
signal RX : std_logic := '0';
 
--Outputs
signal ADR_O : std_logic_vector(7 downto 0);
signal CYC_O : std_logic;
signal DAT_O : std_logic_vector(7 downto 0);
signal STB_O : std_logic;
signal WE_O : std_logic;
signal TX : std_logic;
 
-- Clock period definitions
constant CLK_I_period : time := 20 ns;
constant response : time := 21 ns;
constant datatime : time := CLK_I_period*217 ;
signal input : std_logic_vector(7 downto 0);
signal resievedata : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: processor PORT MAP (
ACK_I => ACK_I,
CLK_I => CLK_I,
DAT_I => DAT_I,
RST_I => RST_I,
ADR_O => ADR_O,
CYC_O => CYC_O,
DAT_O => DAT_O,
STB_O => STB_O,
WE_O => WE_O,
RX => RX,
TX => TX
);
 
-- Clock process definitions
CLK_I_process :process
begin
CLK_I <= '0';
wait for CLK_I_period/2;
CLK_I <= '1';
wait for CLK_I_period/2;
end process;
 
-- Stimulus process
-- Stimulus process
stim_proc: process
begin
RX<='1';
RST_I<='1';
wait for 101 ns;
RST_I<='0';
wait for datatime ;
RX<='0';
input<="0000"&"0010";--opcode + const & reg
wait for datatime ;
for i in 0 to 7 loop
RX<=input(i);
wait for datatime;
end loop;
RX<='1';
wait for datatime;
RX<='0';
input<="0000"&"0010";--opcode + const & reg
wait for datatime ;
for i in 0 to 7 loop
RX<=input(i);
wait for datatime;
end loop;
RX<='1';
wait for datatime;
RX<='0';
input<="0000"&"0000";--opcode + const & reg
wait for datatime ;
for i in 0 to 7 loop
RX<=input(i);
wait for datatime;
end loop;
RX<='1';
wait for datatime;
RX<='0';
input<="1000"&"0000";--opcode + const & reg
wait for datatime ;
for i in 0 to 7 loop
RX<=input(i);
wait for datatime;
end loop;
RX<='1';
wait for datatime;
wait for datatime;
RX<='0';
input<="1001"&"1100";--opcode + const & reg
wait for datatime ;
for i in 0 to 7 loop
RX<=input(i);
wait for datatime;
end loop;
RX<='1';
wait for datatime;
wait;
 
wait;
end process;
respons: process
begin
wait until STB_O='1';
wait for response;
ack_i<='1';
DAT_I<="11001101";
wait until STB_O='0';
wait for 2 ns ;
ack_i<='0';
DAT_I<=x"00";
wait until STB_O='1';
wait for response ;
ack_i<='1';
DAT_I<=x"ee";
wait until STB_O='0';
wait for 2 ns ;
ack_i<='0';
DAT_I<=x"00";
wait until STB_O='1';
wait for response ;
ack_i<='1';
DAT_I<=x"15";
wait until STB_O='0';
wait for 2 ns ;
ack_i<='0';
DAT_I<=x"00";
wait until STB_O='1';
wait for response ;
ack_i<='1';
DAT_I<=x"28";
wait until STB_O='0';
wait for 2 ns ;
ack_i<='0';
DAT_I<=x"00";
end process;
recieve: process
begin
---eerste byte
-- wait until tx ='0';
-- wait for datatime ;
-- wait for 1 ns;
-- wait for datatime ;
-- for i in 0 to 7 loop
-- resievedata(i)<=TX;
-- wait for datatime ;
-- end loop;
-- wait for 1 ns;
-- assert resievedata="11001101"
-- report "foute output";
-- --- 2de byte
wait until tx ='0';
wait for datatime ;
wait for datatime;
wait for 1 ns;
for i in 0 to 7 loop
resievedata(i)<=TX;
wait for datatime;
end loop;
wait for 1 ns;
assert resievedata=x"ee"
report "foute output";
---3de byte
wait until tx ='0';
wait for datatime ;
wait for datatime;
wait for 1 ns;
for i in 0 to 7 loop
resievedata(i)<=TX;
wait for datatime ;
end loop;
wait for 1 ns;
assert resievedata=x"15"
report "foute output";
--4de byte
wait until tx ='0';
wait for datatime ;
wait for datatime;
 
wait for 1 ns;
for i in 0 to 7 loop
resievedata(i)<=TX;
wait for datatime ;
end loop;
wait for 1 ns;
assert resievedata=x"28"
report "foute output";
end process;
END;
/branches/uartcontroller/burst_queue_rev1.vhd
0,0 → 1,76
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity burst_queue_rev1 is
Port (clk : IN std_logic;
DBIN : IN std_logic_vector(7 downto 0);
write_strobe : IN std_logic;
read_strobe : IN std_logic;
DBOUT : OUT std_logic_vector(7 downto 0);
ack: OUT std_logic:='0';
WR : OUT std_logic:='0');
end burst_queue_rev1;
 
architecture Behavioral of burst_queue_rev1 is
type shiftreg is array(0 to 3) of std_logic_vector(7 downto 0);
 
signal data_buf : shiftreg;
 
constant width : integer :=3;
signal WR_int : std_logic:='0';
signal writecount : integer range 0 to 3:=0;
signal readcount : integer range 0 to 4:=0;
signal ack_int : std_logic:='0';
begin
process(clk,write_strobe)
 
begin
if rising_edge(clk) then
if write_strobe='1' and ack_int='0' then
if(readcount< 4 )then
data_buf(writecount)<=DBIN;
writecount<=(writecount+1) mod 4;
ack_int<='1';
readcount<=readcount+1;
else
ack_int<='0';
end if;
end if;
if WR_int='0' or read_strobe='1' then
if(readcount>0) then
DBOUT<=data_buf((writecount-readcount) mod 4);
if write_strobe = '0' then
readcount<=readcount-1;-- laagste teld
else
if(readcount< 4 and ack_int='0')then
readcount<=readcount;
else
readcount<=readcount-1;
end if;
end if;
WR_int<='1';
else
WR_int<='0';
end if;
end if;
end if;
if write_strobe ='0' then
ack_int<='0';
end if;
end process;
WR<=WR_int;
ack<=ack_int;
end Behavioral;
 
/branches/uartcontroller/IOALU.vhd
0,0 → 1,146
--deze modulle/testbench is gemaakt door boris smidt.
--voor deze modulles kan je geen punten verdienen
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity IOALU is
Port (
ACK_I: in std_logic; --The acknowledge input
ADR_O: out std_logic_vector( 7 downto 0 ):=X"00"; --adres output
CLK_I: in std_logic;--clock input
CYC_O: out std_logic;-- The cycle output dient voor block doorvoer
DAT_I: in std_logic_vector( 7 downto 0 );--data in
DAT_O: out std_logic_vector( 7 downto 0 );--data out
RST_I: in std_logic;--reset in
--SEL_O: out std_logic;--deze input dient voor het selecteren van de poort word echter niet gebruikt als er maar met 8 bit word gewerkt
STB_O: out std_logic;--The strobe output
WE_O : out std_logic;--write enable output 0 is read 1 is write
enable : in std_logic;
adress : in STD_LOGIC_VECTOR (7 downto 0);
db_in : in STD_LOGIC_VECTOR (7 downto 0);
db_out : out STD_LOGIC_VECTOR (7 downto 0);
rs232_we: out STD_LOGIC;
queue_ack: in STD_LOGIC;
opcode : in STD_LOGIC;
error : out STD_LOGIC;
next_instructie: out std_logic:='1');
end IOALU;
 
architecture Behavioral of IOALU is
type state is(AdressOut, readwrite,toqueue);
signal currentstate :state :=AdressOut;
signal timeout :integer range 0 to 7 := 0;
signal enable_int: std_logic := '0';
begin
process(CLK_I)
 
begin
if rising_edge(CLK_I) then
if RST_I='1' then
null;
else
if enable ='1' then
enable_int<='1';
end if;
if enable_int='1' then
if opcode='0' then
if AdressOut = currentstate then
next_instructie<='0';
ADR_O<=adress;
CYC_O<='1';
WE_O <='0';
STB_O<='1';
currentstate<=readwrite;
timeout<=0;
elsif currentstate=readwrite then
if ACK_I='1' then
CYC_O<='0';
WE_O <='0';
STB_O<='0';
ADR_O<="00000000";
currentstate<=toqueue;
db_out<=DAT_I;
rs232_we<='1';
timeout<=0;
elsif timeout=7 then
CYC_O<='0';
WE_O <='0';
STB_O<='0';
ADR_O<="00000000";
next_instructie<='1';
currentstate<=AdressOut;
error<='1';
timeout<=0;
else
timeout<=timeout+1;
end if;
elsif currentstate=toqueue then
if queue_ack='1' then
rs232_we<='0';
next_instructie<='1';
currentstate<=AdressOut;
enable_int<='0';
end if;
end if;
--------------------------------write
else
if AdressOut =currentstate then
next_instructie<='0';
ADR_O<=adress;
DAT_O<=db_in;
CYC_O<='1';
WE_O <='1';
STB_O<='1';
currentstate<=readwrite;
timeout<=0;
elsif currentstate=readwrite then
if ACK_I='1' then
CYC_O<='0';
WE_O <='0';
STB_O<='0';
currentstate<=AdressOut;
ADR_O<="00000000";
next_instructie<='1';
timeout<=0;
enable_int<='0';
elsif timeout=7 then
CYC_O<='0';
WE_O <='0';
STB_O<='0';
ADR_O<="00000000";
currentstate<=AdressOut;
error<='1';
timeout<=0;
enable_int<='0';
next_instructie<='1';
else
timeout<=timeout+1;
end if ;
end if;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
 
/branches/uartcontroller/burst_uart.vhd
0,0 → 1,131
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:50:17 04/16/2013
-- Design Name:
-- Module Name: burst_uart - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity burst_uart is
Port ( CLOCK : in STD_LOGIC;
DBIN : in std_logic_vector(7 downto 0);
write_strobe: in STD_LOGIC;
ack: out std_logic;
RESET: in STD_LOGIC;
DATA_STREAM_OUT_ACK : IN std_logic;
DATA_OUT : OUT std_logic_vector(7 downto 0);
DATA_STREAM_OUT_STB : OUT std_logic;
RX : IN std_logic;
TX : OUT std_logic
);
end burst_uart;
 
architecture Behavioral of burst_uart is
COMPONENT uart_queue
PORT(
clk : IN std_logic;
DBIN : IN std_logic_vector(7 downto 0);
write_strobe : IN std_logic;
read_strobe : IN std_logic;
DBOUT : OUT std_logic_vector(7 downto 0);
ack: OUT std_logic:='0';
WR : OUT std_logic:='0');
END COMPONENT;
 
COMPONENT UART
Generic (
BAUD_RATE : positive:=230400;-- 9600;-- tijdelijke laage snelheid zal
--later opgetrokken worden naar 19200 of
--115200
CLOCK_FREQUENCY : positive:= 50000000
);
PORT(
CLOCK : IN std_logic;
RESET : IN std_logic;
DATA_STREAM_IN : IN std_logic_vector(7 downto 0);
DATA_STREAM_IN_STB : IN std_logic;
DATA_STREAM_OUT_ACK : IN std_logic;
DATA_STREAM_IN_TBE : out std_logic;
RX : IN std_logic;
DATA_STREAM_IN_ACK : OUT std_logic;
DATA_STREAM_OUT : OUT std_logic_vector(7 downto 0);
DATA_STREAM_OUT_STB : OUT std_logic;
TX : OUT std_logic
);
END COMPONENT;
 
--
-- COMPONENT Rs232RefComp
-- PORT(
-- RXD : IN std_logic;
-- CLK : IN std_logic;
-- DBIN : IN std_logic_vector(7 downto 0);
-- RD : IN std_logic;
-- WR : IN std_logic;
-- RST : IN std_logic;
-- TXD : OUT std_logic;
-- DBOUT : OUT std_logic_vector(7 downto 0);
-- RDA : OUT std_logic;
-- TBE : OUT std_logic;
-- OE : OUT std_logic
-- );
-- END COMPONENT;
 
signal wr_i :std_logic:='0';
signal DBOUT : std_logic_vector(7 downto 0);
signal read_strobe :std_logic;
begin
 
 
Inst_uart_sync: uart_queue PORT MAP(
clk =>CLOCK ,
write_strobe => write_strobe,
read_strobe=>read_strobe,
DBOUT => DBOUT,
DBIN => DBIN,
ack=>ack,
WR => wr_i
);
 
Inst_UART: UART PORT MAP(
CLOCK => CLOCK,
RESET => RESET,
DATA_STREAM_IN => DBOUT,
DATA_STREAM_IN_STB => wr_i,
DATA_STREAM_IN_ACK => read_strobe,
DATA_STREAM_IN_TBE=> open,
DATA_STREAM_OUT => DATA_OUT,
DATA_STREAM_OUT_STB => DATA_STREAM_OUT_STB,
DATA_STREAM_OUT_ACK => DATA_STREAM_OUT_ACK,
TX => TX,
RX => RX
);
 
end Behavioral;
 
/branches/uartcontroller/slave/queue.vhd
0,0 → 1,110
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:32:29 04/17/2013
-- Design Name:
-- Module Name: burst_slave - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity queue is
generic(adress : integer :=5;
depth : integer :=3);
Port (
ACK_O: out std_logic; --The acknowledge input
ADR_I: in std_logic_vector (7 downto 0 ); --adres output
CLK_I: in std_logic;
DAT_I: in std_logic_vector( 7 downto 0 );--data in
DAT_O: out std_logic_vector( 7 downto 0 ):=X"00";--data out
RST_I: in std_logic;--reset in
--SEL_O: out std_logic;--deze input dient voor het selecteren van de poort word echter niet gebruikt als er maar met 8 bit word gewerkt
STB_I: in std_logic;--The strobe
WE_I : in std_logic;--write enable
--- non wishbone
input: in STD_LOGIC_VECTOR (7 downto 0);
OutputReady:in std_logic;
busfull: out std_logic;--- is er nog plaats in de bus? '1' is nee '0' is ja.
--als er toch geschreven word zal dit een data overwrite geven
read_ack : out std_logic
);
end queue;
 
architecture Behavioral of queue is
 
type shiftreg is array(0 to depth) of std_logic_vector(7 downto 0);
 
signal read_buf : shiftreg;
 
 
signal writecount : integer range 0 to depth:=0;
signal readcount : integer range 0 to depth:=0;
signal ACK_O_int : std_logic:='0';
signal read_ack_int :std_logic:='0';
begin
 
process(CLK_I,STB_I,OutputReady)
begin
if rising_edge(CLK_I) then
if RST_I='1' then
readcount<=0;
else
-------------write
if OutputReady='1' and read_ack_int='0' then
read_buf(writecount)<=input;
read_ack_int<='1';
if writecount= depth then
writecount<=0;
else
writecount<=writecount+1;
end if;
end if;
if WE_I='0' and STB_I ='1' and adress=to_integer(unsigned(ADR_I))and ACK_O_int='0' then
ACK_O_int<='1';
DAT_O<=read_buf(readcount);-- zet data klaar
if readcount= depth then
readcount<=0;
else
readcount<=readcount+1;
end if;
end if;
------check is de queue vol ? code moet nog bedacht worden
--if writecount=readcount then
end if;
end if;
 
if STB_I= '0' then
ACK_O_int<='0';
end if;
if OutputReady='0' then
read_ack_int<='0';
end if;
end process;
ACK_O<=ACK_O_int;
read_ack<=read_ack_int;
end Behavioral;
 
/branches/uartcontroller/uart.vhd
0,0 → 1,296
--------------------------------------------------------------------------------
-- UART
-- Implements a universal asynchronous receiver transmitter with parameterisable
-- BAUD rate. Tested on a Spartan 6 LX9 connected to a Silicon Labs Cp210
-- USB-UART Bridge.
--
-- @author Peter A Bennett
-- @copyright (c) 2012 Peter A Bennett
-- @license LGPL
-- @email pab850@googlemail.com
-- @contact www.bytebash.com
--
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity UART is
Generic (
BAUD_RATE : positive:= 115200;
CLOCK_FREQUENCY : positive:= 50000000
);
Port ( -- General
CLOCK : in std_logic;
RESET : in std_logic;
DATA_STREAM_IN : in std_logic_vector(7 downto 0);
DATA_STREAM_IN_STB : in std_logic;
DATA_STREAM_IN_ACK : out std_logic;
DATA_STREAM_OUT : out std_logic_vector(7 downto 0);
DATA_STREAM_OUT_STB : out std_logic;
DATA_STREAM_OUT_ACK : in std_logic;
TX : out std_logic;
RX : in std_logic
);
end UART;
 
architecture Behavioral of UART is
----------------------------------------------------------------------------
-- BAUD Generation
----------------------------------------------------------------------------
constant c_tx_divider_val : positive := CLOCK_FREQUENCY / BAUD_RATE;
constant c_rx_divider_val : positive := CLOCK_FREQUENCY / (BAUD_RATE * 16);
 
signal baud_counter : integer range 0 to c_tx_divider_val;
signal baud_tick : std_logic := '0';
signal oversample_baud_counter : integer range 0 to c_rx_divider_val;
signal oversample_baud_tick : std_logic := '0';
 
----------------------------------------------------------------------------
-- Transmitter Signals
----------------------------------------------------------------------------
type uart_tx_states is ( idle,
wait_for_tick,
send_start_bit,
transmit_data,
send_stop_bit);
signal uart_tx_state : uart_tx_states := idle;
signal uart_tx_data_block : std_logic_vector(7 downto 0) := (others => '0');
signal uart_tx_data : std_logic := '1';
signal uart_tx_count : integer range 0 to 7 := 0;
signal uart_rx_data_in_ack : std_logic := '0';
----------------------------------------------------------------------------
-- Receiver Signals
----------------------------------------------------------------------------
type uart_rx_states is ( rx_wait_start_synchronise,
rx_get_start_bit,
rx_get_data,
rx_get_stop_bit,
rx_send_block);
signal uart_rx_state : uart_rx_states := rx_get_start_bit;
signal uart_rx_bit : std_logic := '0';
signal uart_rx_data_block : std_logic_vector(7 downto 0) := (others => '0');
signal uart_rx_data_vec : std_logic_vector(1 downto 0) := (others => '0');
signal uart_rx_filter : unsigned(1 downto 0) := (others => '0');
signal uart_rx_count : integer range 0 to 7 := 0;
signal uart_rx_data_out_stb: std_logic := '0';
signal uart_rx_bit_spacing : unsigned (3 downto 0) := (others => '0');
signal uart_rx_bit_tick : std_logic := '0';
begin
 
DATA_STREAM_IN_ACK <= uart_rx_data_in_ack;
DATA_STREAM_OUT <= uart_rx_data_block;
DATA_STREAM_OUT_STB <= uart_rx_data_out_stb;
TX <= uart_tx_data;
 
-- The input clock is 100Mhz, this needs to be divided down to the
-- rate dictated by the BAUD_RATE. For example, if 115200 baud is selected
-- (115200 baud = 115200 bps - 115.2kbps) a tick must be generated once
-- every 1/115200
TX_CLOCK_DIVIDER : process (CLOCK)
begin
if rising_edge (CLOCK) then
if RESET = '1' then
baud_counter <= 0;
baud_tick <= '0';
else
if baud_counter = c_tx_divider_val then
baud_counter <= 0;
baud_tick <= '1';
else
baud_counter <= baud_counter + 1;
baud_tick <= '0';
end if;
end if;
end if;
end process TX_CLOCK_DIVIDER;
-- Get data from DATA_STREAM_IN and send it one bit at a time
-- upon each BAUD tick. LSB first.
-- Wait 1 tick, Send Start Bit (0), Send Data 0-7, Send Stop Bit (1)
UART_SEND_DATA : process(CLOCK)
begin
if rising_edge(CLOCK) then
if RESET = '1' then
uart_tx_data <= '1';
--uart_tx_data_block <= (others => '0');
uart_tx_count <= 0;
uart_tx_state <= idle;
uart_rx_data_in_ack <= '0';
else
case uart_tx_state is
when idle =>
if DATA_STREAM_IN_STB = '1' then
uart_tx_data_block <= DATA_STREAM_IN;
uart_rx_data_in_ack <= '1';
uart_tx_state <= wait_for_tick;
end if;
when wait_for_tick =>
uart_rx_data_in_ack<= '0';
if baud_tick = '1' then
uart_tx_state <= send_start_bit;
end if;
when send_start_bit =>
if baud_tick = '1' then
uart_tx_data <= '0';
uart_tx_state <= transmit_data;
uart_tx_count <= 0;
end if;
when transmit_data =>
if baud_tick = '1' then
if uart_tx_count < 7 then
uart_tx_data <=
uart_tx_data_block(uart_tx_count);
uart_tx_count <= uart_tx_count + 1;
else
uart_tx_data <= uart_tx_data_block(uart_tx_count);
uart_tx_count <= 0;
uart_tx_state <= send_stop_bit;
end if;
end if;
when send_stop_bit =>
if baud_tick = '1' then
uart_tx_data <= '1';
uart_tx_state <= idle;
end if;
when others =>
uart_tx_data <= '1';
uart_tx_state <= idle;
end case;
end if;
end if;
end process UART_SEND_DATA;
-- Generate an oversampled tick (BAUD * 16)
OVERSAMPLE_CLOCK_DIVIDER : process (CLOCK)
begin
if rising_edge (CLOCK) then
if RESET = '1' then
oversample_baud_counter <= 0;
oversample_baud_tick <= '0';
else
if oversample_baud_counter = c_rx_divider_val then
oversample_baud_counter <= 0;
oversample_baud_tick <= '1';
else
oversample_baud_counter <= oversample_baud_counter + 1;
oversample_baud_tick <= '0';
end if;
end if;
end if;
end process OVERSAMPLE_CLOCK_DIVIDER;
-- Synchronise RXD to the oversampled BAUD
RXD_SYNCHRONISE : process(CLOCK)
begin
if rising_edge(CLOCK) then
if RESET = '1' then
uart_rx_data_vec <= (others => '1');
else
if oversample_baud_tick = '1' then
uart_rx_data_vec(0) <= RX;
uart_rx_data_vec(1) <= uart_rx_data_vec(0);
end if;
end if;
end if;
end process RXD_SYNCHRONISE;
-- Filter RXD with a 2 bit counter.
RXD_FILTER : process(CLOCK)
begin
if rising_edge(CLOCK) then
if RESET = '1' then
uart_rx_filter <= (others => '1');
uart_rx_bit <= '1';
else
if oversample_baud_tick = '1' then
-- Filter RXD.
if uart_rx_data_vec(1) = '1' and uart_rx_filter < 3 then
uart_rx_filter <= uart_rx_filter + 1;
elsif uart_rx_data_vec(1) = '0' and uart_rx_filter > 0 then
uart_rx_filter <= uart_rx_filter - 1;
end if;
-- Set the RX bit.
if uart_rx_filter = 3 then
uart_rx_bit <= '1';
elsif uart_rx_filter = 0 then
uart_rx_bit <= '0';
end if;
end if;
end if;
end if;
end process RXD_FILTER;
RX_BIT_SPACING : process (CLOCK)
begin
if rising_edge(CLOCK) then
uart_rx_bit_tick <= '0';
if oversample_baud_tick = '1' then
if uart_rx_bit_spacing = 15 then
uart_rx_bit_tick <= '1';
uart_rx_bit_spacing <= (others => '0');
else
uart_rx_bit_spacing <= uart_rx_bit_spacing + 1;
end if;
if uart_rx_state = rx_get_start_bit then
uart_rx_bit_spacing <= (others => '0');
end if;
end if;
end if;
end process RX_BIT_SPACING;
UART_RECEIVE_DATA : process(DATA_STREAM_OUT_ACK,CLOCK)
begin
if rising_edge(CLOCK) then
if RESET = '1' then
uart_rx_state <= rx_get_start_bit;
uart_rx_data_block <= (others => '0');
uart_rx_count <= 0;
uart_rx_data_out_stb <= '0';
else
case uart_rx_state is
when rx_get_start_bit =>
if oversample_baud_tick = '1' and uart_rx_bit = '0' then
uart_rx_state <= rx_get_data;
end if;
when rx_get_data =>
if uart_rx_bit_tick = '1' then
 
if uart_rx_count < 7 then
uart_rx_data_block(uart_rx_count)
<= uart_rx_bit;
uart_rx_count <= uart_rx_count + 1;
else
uart_rx_data_block(uart_rx_count) <= uart_rx_bit;
uart_rx_count <= 0;
uart_rx_state <= rx_get_stop_bit;
end if;
end if;
when rx_get_stop_bit =>
if uart_rx_bit_tick = '1' then
if uart_rx_bit = '1' then
uart_rx_state <= rx_send_block;
uart_rx_data_out_stb <= '1';
end if;
end if;
when rx_send_block =>
if DATA_STREAM_OUT_ACK = '1' then
uart_rx_state <= rx_get_start_bit;
uart_rx_data_out_stb <= '0';
end if;
when others =>
uart_rx_state <= rx_get_start_bit;
end case;
end if;
end if;
if DATA_STREAM_OUT_ACK ='1' then
uart_rx_data_out_stb<='0';
end if;
end process UART_RECEIVE_DATA;
end Behavioral;
/branches/uartcontroller/uart_to_instruction.vhd
0,0 → 1,97
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:03:15 04/17/2013
-- Design Name:
-- Module Name: uart_to_instruction - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity uart_to_instruction is
Port ( uart_rx_data_out_stb : in STD_LOGIC;
rd:out STD_LOGIC;
data_in: IN std_logic_vector(7 downto 0);
next_instructie:in std_logic;
enable:out std_logic;
clock:in STD_LOGIC;
send_data: out std_logic;
queue_empty:in std_logic;
opcode:out std_logic;
adress:out std_logic_vector(7 downto 0);
data:out std_logic_vector(7 downto 0)
);
end uart_to_instruction;
 
architecture Behavioral of uart_to_instruction is
signal count : integer range 0 to 3:=0;
signal send_data_int: std_logic:='0';
signal instructie_i:std_logic_vector(15 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
if uart_rx_data_out_stb ='1' then
if count=0 then
instructie_i(15 downto 8) <=data_in;
if data_in(7)='0' then
if data_in = x"00" then
count<=3;-- to pc
else
count <= 2;
end if;
else
count<=1;--write instructie wacht tot volgende byte.
end if;
rd<='1';
elsif count=1 then
count<=2;
instructie_i(7 downto 0) <=data_in;
rd<='1';
end if;
elsif uart_rx_data_out_stb ='0' then
rd<='0';
end if;
if next_instructie ='1' then
if count=2 then
opcode<=instructie_i(15);
adress<='0'&instructie_i(14 downto 8);
data<=instructie_i(7 downto 0);
enable<='1';
count<=0;
elsif count=3 then
send_data_int<='1';
end if;
else
enable<='0';
end if;
if count=3 and send_data_int='1' and queue_empty='1' then
count<=0;
send_data_int<='0';
end if;
end if;
end process;
send_data<=send_data_int;
end Behavioral;
 

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