URL
https://opencores.org/ocsvn/wrimm/wrimm/trunk
Subversion Repositories wrimm
Compare Revisions
- This comparison shows the changes necessary to convert path
/wrimm
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/trunk/LatticeProj/WrimmTestProj1.sty
File deleted
/trunk/LatticeProj/WrimmTestProj.lpf
File deleted
/trunk/LatticeProj/WrimmTestProj.ldf
File deleted
/trunk/WrimmPackage.vhd
6,7 → 6,6
|
------------------------------------------------------------ |
--********************************************************** |
--********************************************************** |
--!!!!!!!!!!!!!!!!!! EDIT THIS FILE !!!!!!!!!!!!!!!!! |
--Save a copy of this file in a project specific directory. |
--Each project may have a different WrimmPackage.vhd file. |
19,38 → 18,37
-- Hopefully the code ouside those marked sections |
-- will not require modification. |
--********************************************************** |
--********************************************************** |
------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
package WrimmPackage is |
library ieee; |
use ieee.std_logic_1164.all; |
|
package WrimmPackage is |
-->>>>>>>>>>>>>>>>>>>>>>>Start of Wishbone Bus Parameters >>>>>>>>>>>>>>>>>>>>>> |
constant WbAddrBits : Integer := 4; |
constant WbDataBits : Integer := 8; |
constant WbAddrBits : integer := 4; |
constant WbDataBits : integer := 8; |
--<<<<<<<<<<<<<<<<<<<<<<<End of Wishbone Bus Parameters <<<<<<<<<<<<<<<<<<<<<<<< |
|
subtype WbAddrType is std_logic_vector(0 to WbAddrBits-1); |
subtype WbDataType is std_logic_vector(0 to WbDataBits-1); |
|
type WbMasterOutType is record |
Strobe : std_logic; --Required |
WrEn : std_logic; --Required |
Addr : WbAddrType; --Required |
Data : WbDataType; |
--DataTag : std_logic_vector(0 to 1); --Write,Set,Clear,Toggle |
Cyc : std_logic; --Required |
--CycType : std_logic_vector(0 to 2); --For Burst Cycles |
end record WbMasterOutType; |
|
type WbSlaveOutType is record |
Ack : std_logic; --Required |
Err : std_logic; |
Rty : std_logic; |
Data : WbDataType; |
end record WbSlaveOutType; |
|
|
subtype WbAddrType is std_logic_vector(0 to WbAddrBits-1); |
subtype WbDataType is std_logic_vector(0 to WbDataBits-1); |
|
type WbMasterOutType is record |
Strobe : std_logic; --Required |
WrEn : std_logic; --Required |
Addr : WbAddrType; --Required |
Data : WbDataType; |
--DataTag : std_logic_vector(0 to 1); --Write,Set,Clear,Toggle |
Cyc : std_logic; --Required |
--CycType : std_logic_vector(0 to 2); --For Burst Cycles |
end record WbMasterOutType; |
|
type WbSlaveOutType is record |
Ack : std_logic; --Required |
Err : std_logic; |
Rty : std_logic; |
Data : WbDataType; |
end record WbSlaveOutType; |
|
--========================================================== |
------------------------------------------------------------ |
-- Master Interfaces: provides interfaces for 1-n Masters |
62,94 → 60,94
--<<<<<<<<<<<<<<<<<<<<<<<End of Wishbone Master List <<<<<<<<<<<<<<<<<<<<<<<<<<< |
|
type WbMasterOutArray is array (WbMasterType) of WbMasterOutType; |
type WbSlaveOutArray is array (WbMasterType) of WbSlaveOutType; |
type WbSlaveOutArray is array (WbMasterType) of WbSlaveOutType; |
|
type WbMasterGrantType is Array (WbMasterType'left to WbMasterType'right) of std_logic; |
--========================================================== |
------------------------------------------------------------ |
-- Status Registers: Report results from other modules |
------------------------------------------------------------ |
type StatusFieldParams is record |
BitWidth : integer; |
MSBLoc : integer; |
Address : WbAddrType; |
end record StatusFieldParams; |
|
type StatusFieldType is ( |
type WbMasterGrantType is array (WbMasterType'left to WbMasterType'right) of std_logic; |
--========================================================== |
------------------------------------------------------------ |
-- Status Registers: Report results from other modules |
------------------------------------------------------------ |
type StatusFieldParams is record |
BitWidth : integer; |
MSBLoc : integer; |
Address : WbAddrType; |
end record StatusFieldParams; |
|
type StatusFieldType is ( |
-->>>>>>>>>>>>>>>>>>>>>>>Start of Status Field List >>>>>>>>>>>>>>>>>>>>>>>>>>>> |
StatusA, |
StatusB, |
StatusC); |
StatusA, |
StatusB, |
StatusC); |
--<<<<<<<<<<<<<<<<<<<<<<<End of Status Field List <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|
type StatusArrayType is Array (StatusFieldType'left to StatusFieldType'right) of WbDataType; |
type StatusArrayBitType is Array (StatusFieldType'left to StatusFieldType'right) of std_logic; |
type StatusFieldDefType is Array (StatusFieldType'left to StatusFieldType'right) of StatusFieldParams; |
|
constant StatusParams : StatusFieldDefType :=( |
|
type StatusArrayType is array (StatusFieldType'left to StatusFieldType'right) of WbDataType; |
type StatusArrayBitType is array (StatusFieldType'left to StatusFieldType'right) of std_logic; |
type StatusFieldDefType is array (StatusFieldType'left to StatusFieldType'right) of StatusFieldParams; |
|
constant StatusParams : StatusFieldDefType := ( |
-->>>>>>>>>>>>>>>>>>>>>>>Start of Status Field Parameters >>>>>>>>>>>>>>>>>>>>>> |
StatusA => (BitWidth => 8, MSBLoc => 0, Address => x"0"), |
StatusB => (BitWidth => 8, MSBLoc => 0, Address => x"1"), |
StatusC => (BitWidth => 8, MSBLoc => 0, Address => x"2")); |
StatusA => (BitWidth => 8, MSBLoc => 0, Address => x"0"), |
StatusB => (BitWidth => 8, MSBLoc => 0, Address => x"1"), |
StatusC => (BitWidth => 8, MSBLoc => 0, Address => x"2")); |
--<<<<<<<<<<<<<<<<<<<<<<<End of Status Field Parameters <<<<<<<<<<<<<<<<<<<<<<<< |
--========================================================== |
------------------------------------------------------------ |
-- Setting Registers: Provide config bits to other modules |
------------------------------------------------------------ |
type SettingFieldParams is record |
BitWidth : integer; |
MSBLoc : integer; |
Address : WbAddrType; |
Default : WbDataType; |
end record SettingFieldParams; |
|
type SettingFieldType is ( |
------------------------------------------------------------ |
-- Setting Registers: Provide config bits to other modules |
------------------------------------------------------------ |
type SettingFieldParams is record |
BitWidth : integer; |
MSBLoc : integer; |
Address : WbAddrType; |
Default : WbDataType; |
end record SettingFieldParams; |
|
type SettingFieldType is ( |
-->>>>>>>>>>>>>>>>>>>>>>>Start of Setting Field List >>>>>>>>>>>>>>>>>>>>>>>>>>> |
SettingX, |
SettingY, |
SettingZ); |
SettingX, |
SettingY, |
SettingZ); |
--<<<<<<<<<<<<<<<<<<<<<<<End of Setting Field List <<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|
type SettingArrayType is Array (SettingFieldType'Left to SettingFieldType'Right) of WbDataType; |
type SettingArrayBitType is Array (SettingFieldType'Left to SettingFieldType'Right) of std_logic; |
type SettingFieldDefType is Array (SettingFieldType'Left to SettingFieldType'Right) of SettingFieldParams; |
|
constant SettingParams : SettingFieldDefType :=( |
|
type SettingArrayType is array (SettingFieldType'left to SettingFieldType'right) of WbDataType; |
type SettingArrayBitType is array (SettingFieldType'left to SettingFieldType'right) of std_logic; |
type SettingFieldDefType is array (SettingFieldType'left to SettingFieldType'right) of SettingFieldParams; |
|
constant SettingParams : SettingFieldDefType := ( |
-->>>>>>>>>>>>>>>>>>>>>>>Start of Setting Field Parameters >>>>>>>>>>>>>>>>>>>>> |
SettingX => (BitWidth => 8, MSBLoc => 0, Address => x"6", Default => x"05"), |
SettingY => (BitWidth => 8, MSBLoc => 0, Address => x"7", Default => x"3C"), |
SettingZ => (BitWidth => 8, MSBLoc => 0, Address => x"8", Default => x"AA")); |
SettingX => (BitWidth => 8, MSBLoc => 0, Address => x"6", Default => x"05"), |
SettingY => (BitWidth => 8, MSBLoc => 0, Address => x"7", Default => x"3C"), |
SettingZ => (BitWidth => 8, MSBLoc => 0, Address => x"8", Default => x"AA")); |
--<<<<<<<<<<<<<<<<<<<<<<<End of Setting Field Parameters<<<<<<<<<<<<<<<<<<<<<<<< |
--========================================================== |
------------------------------------------------------------ |
-- Trigger Registers, Launch other processes, cleared by those processes |
------------------------------------------------------------ |
type TriggerFieldParams is record |
BitLoc : integer; |
Address : WbAddrType; |
end record TriggerFieldParams; |
|
type TriggerFieldType is ( |
--========================================================== |
------------------------------------------------------------ |
-- Trigger Registers, Launch other processes, cleared by those processes |
------------------------------------------------------------ |
type TriggerFieldParams is record |
BitLoc : integer; |
Address : WbAddrType; |
end record TriggerFieldParams; |
|
type TriggerFieldType is ( |
-->>>>>>>>>>>>>>>>>>>>>>>Start of Trigger List >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> |
TriggerR, |
TriggerS, |
TriggerT); |
TriggerR, |
TriggerS, |
TriggerT); |
--<<<<<<<<<<<<<<<<<<<<<<<End of Trigger List <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|
type TriggerArrayType is Array (TriggerFieldType'Left to TriggerFieldType'Right) of std_logic; |
type TriggerFieldDefType is Array (TriggerFieldType'Left to TriggerFieldType'Right) of TriggerFieldParams; |
|
constant TriggerParams : TriggerFieldDefType :=( |
|
type TriggerArrayType is array (TriggerFieldType'left to TriggerFieldType'right) of std_logic; |
type TriggerFieldDefType is array (TriggerFieldType'left to TriggerFieldType'right) of TriggerFieldParams; |
|
constant TriggerParams : TriggerFieldDefType := ( |
-->>>>>>>>>>>>>>>>>>>>>>>Start of Trigger Parameters >>>>>>>>>>>>>>>>>>>>>>>>>>> |
TriggerR => (BitLoc => 7, Address => x"A"), |
TriggerS => (BitLoc => 7, Address => x"B"), |
TriggerT => (BitLoc => 7, Address => x"C")); |
TriggerR => (BitLoc => 7, Address => x"A"), |
TriggerS => (BitLoc => 7, Address => x"B"), |
TriggerT => (BitLoc => 7, Address => x"C")); |
--<<<<<<<<<<<<<<<<<<<<<<<End of Trigger Parameters <<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
|
end package WrimmPackage; |
|
--package body WishBonePackage is |
-- |
-- No package functions (yet) |
-- |
--end package body WishBonePackage; |
|
end package WrimmPackage; |
|
--package body WishBonePackage is |
-- |
-- No package functions (yet) |
-- |
--end package body WishBonePackage; |
/trunk/Example/LatticeProj/WrimmTestProj1.sty
0,0 → 1,192
<?xml version="1.0" encoding="UTF-8"?> |
<!DOCTYPE strategy> |
<Strategy version="1.0" predefined="0" description="" label="Strategy1"> |
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/> |
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/> |
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/> |
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/> |
<Property name="PROP_BD_EdfMemPath" value="" time="0"/> |
<Property name="PROP_BD_ParSearchPath" value="" time="0"/> |
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/> |
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/> |
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/> |
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/> |
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/> |
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/> |
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/> |
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/> |
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/> |
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/> |
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/> |
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/> |
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/> |
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/> |
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/> |
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/> |
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/> |
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/> |
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/> |
<Property name="PROP_BIT_NoHeader" value="False" time="0"/> |
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/> |
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/> |
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/> |
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/> |
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/> |
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/> |
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/> |
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/> |
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/> |
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/> |
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/> |
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/> |
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/> |
<Property name="PROP_LST_CarryChain" value="True" time="0"/> |
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/> |
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/> |
<Property name="PROP_LST_EBRUtil" value="100" time="0"/> |
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/> |
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/> |
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/> |
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/> |
<Property name="PROP_LST_EdfMemPath" value="" time="0"/> |
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/> |
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/> |
<Property name="PROP_LST_IOInsertion" value="True" time="0"/> |
<Property name="PROP_LST_InterFileDump" value="False" time="0"/> |
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/> |
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/> |
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/> |
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/> |
<Property name="PROP_LST_PrfOutput" value="False" time="0"/> |
<Property name="PROP_LST_PropagatConst" value="True" time="0"/> |
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/> |
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/> |
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/> |
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/> |
<Property name="PROP_LST_ResourceShare" value="True" time="0"/> |
<Property name="PROP_LST_UseIOReg" value="True" time="0"/> |
<Property name="PROP_LST_VHDL2008" value="False" time="0"/> |
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/> |
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/> |
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/> |
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/> |
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/> |
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/> |
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/> |
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/> |
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/> |
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/> |
<Property name="PROP_MAP_GuideFileMapDes" value="" time="0"/> |
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/> |
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/> |
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/> |
<Property name="PROP_MAP_MapModArgs" value="" time="0"/> |
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/> |
<Property name="PROP_MAP_PackLogMapDes" value="" time="0"/> |
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/> |
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/> |
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/> |
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/> |
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/> |
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/> |
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/> |
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/> |
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/> |
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/> |
<Property name="PROP_PARSTA_FullName" value="False" time="0"/> |
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/> |
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/> |
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/> |
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/> |
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/> |
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/> |
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/> |
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/> |
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/> |
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/> |
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/> |
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/> |
<Property name="PROP_PAR_PARModArgs" value="" time="0"/> |
<Property name="PROP_PAR_ParGuideRepMatch" value="False" time="0"/> |
<Property name="PROP_PAR_ParMatchFact" value="" time="0"/> |
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/> |
<Property name="PROP_PAR_ParNCDGuideFile" value="" time="0"/> |
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/> |
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/> |
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/> |
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/> |
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/> |
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/> |
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/> |
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/> |
<Property name="PROP_PAR_RoutingCDP" value="Auto" time="0"/> |
<Property name="PROP_PAR_RoutingCDR" value="1" time="0"/> |
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/> |
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/> |
<Property name="PROP_PAR_StopZero" value="False" time="0"/> |
<Property name="PROP_PAR_parHold" value="On" time="0"/> |
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/> |
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/> |
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/> |
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/> |
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/> |
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/> |
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/> |
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/> |
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/> |
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/> |
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/> |
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/> |
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/> |
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/> |
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/> |
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/> |
<Property name="PROP_PRE_VSynComArea" value="False" time="0"/> |
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/> |
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/> |
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/> |
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/> |
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/> |
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/> |
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/> |
<Property name="PROP_PRE_VSynOutPref" value="False" time="0"/> |
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/> |
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/> |
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/> |
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/> |
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/> |
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/> |
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/> |
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/> |
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/> |
<Property name="PROP_SYN_EdfArea" value="False" time="0"/> |
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/> |
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/> |
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/> |
<Property name="PROP_SYN_EdfFrequency" value="" time="0"/> |
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/> |
<Property name="PROP_SYN_EdfInPrfWrite" value="True" time="0"/> |
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/> |
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/> |
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/> |
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/> |
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/> |
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/> |
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/> |
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/> |
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/> |
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/> |
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/> |
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/> |
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/> |
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/> |
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/> |
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/> |
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/> |
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/> |
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/> |
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/> |
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/> |
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/> |
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/> |
</Strategy> |
/trunk/Example/LatticeProj/WrimmTestProj.lpf
0,0 → 1,2
BLOCK RESETPATHS; |
BLOCK ASYNCPATHS; |
/trunk/Example/LatticeProj/WrimmTestProj.ldf
0,0 → 1,20
<?xml version="1.0" encoding="UTF-8"?> |
<BaliProject version="3.0" title="WrimmTestProj" device="LFE3-17EA-6FTN256C" default_implementation="Example"> |
<Options/> |
<Implementation title="Example" dir="Example" description="Example" synthesis="synplify" default_strategy="Strategy1"> |
<Options def_top="Wrimm_Top"/> |
<Source name="../WrimmPackage.vhd" type="VHDL" type_short="VHDL"> |
<Options lib="wrimm"/> |
</Source> |
<Source name="../WrimmExample_Top.vhd" type="VHDL" type_short="VHDL"> |
<Options top_module="Wrimm_Top"/> |
</Source> |
<Source name="../Wrimm.vhd" type="VHDL" type_short="VHDL"> |
<Options/> |
</Source> |
<Source name="WrimmTestProj.lpf" type="Logic Preference" type_short="LPF"> |
<Options/> |
</Source> |
</Implementation> |
<Strategy name="Strategy1" file="WrimmTestProj1.sty"/> |
</BaliProject> |
/trunk/Wrimm.vhd
1,213 → 1,213
--Propery of Tecphos Inc. See WrimmLicense.txt for license details |
--Latest version of all Wrimm project files available at http://opencores.org/project,wrimm |
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details. |
--See wrimm subversion project for version history |
|
library ieee; |
use ieee.std_logic_1164.all; |
--Latest version of all Wrimm project files available at http://opencores.org/project,wrimm |
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details. |
--See wrimm subversion project for version history |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.WrimmPackage.all; |
|
entity Wrimm is |
port ( |
WbClk : in std_logic; |
WbRst : out std_logic; |
|
WbMasterIn : in WbMasterOutArray; --Signals from Masters |
|
use work.WrimmPackage.all; |
|
entity Wrimm is |
port ( |
WbClk : in std_logic; |
WbRst : out std_logic; |
|
WbMasterIn : in WbMasterOutArray; --Signals from Masters |
WbMasterOut : out WbSlaveOutArray; --Signals to Masters |
|
--WbSlaveIn : out WbMasterOutArray; |
--WbSlaveOut : in WbSlaveOutArray; |
|
StatusRegs : in StatusArrayType; |
|
SettingRegs : out SettingArrayType; |
SettingRsts : in SettingArrayBitType; |
|
Triggers : out TriggerArrayType; |
TriggerClr : in TriggerArrayType; |
|
rstZ : in std_logic); --Asynchronous reset |
end entity Wrimm; |
|
architecture behavior of Wrimm is |
signal wbStrobe : std_logic; --Internal Wishbone signals |
signal validAddress : std_logic; |
signal wbAddr : WbAddrType; |
signal wbSData,wbMData : WbDataType; |
signal wbWrEn,wbCyc : std_logic; |
signal wbAck,wbRty,wbErr : std_logic; |
--signal wbMDataTag : std_logic_vector(0 to 1); |
--signal wbCycType : std_logic_vector(0 to 2); |
|
signal iSettingRegs : SettingArrayType; |
signal iTriggers : TriggerArrayType; |
signal statusEnable : StatusArrayBitType; |
signal settingEnable : SettingArrayBitType; |
signal triggerEnable : TriggerArrayType; |
signal grant : WbMasterGrantType; |
|
begin |
SettingRegs <= iSettingRegs; |
Triggers <= iTriggers; |
|
--============================================================================= |
------------------------------------------------------------------------------- |
-- Master Round Robin Arbitration |
------------------------------------------------------------------------------- |
procArb: process(WbClk,rstZ) is --Round robin arbitration (descending) |
variable vGrant : WbMasterGrantType; |
begin |
if (rstZ='0') then |
vGrant := (Others=>'0'); |
vGrant(vGrant'left) := '1'; |
elsif rising_edge(WbClk) then |
loopGrant: for i in WbMasterType loop |
if vGrant(i)='1' and WbMasterIn(i).Cyc='0' then --else maintain grant |
loopNewGrantA: for j in i to WbMasterType'right loop --last master with cyc=1 will be selected |
if WbMasterIn(j).Cyc='1' then |
vGrant := (Others=>'0'); |
vGrant(j) := '1'; |
end if; |
end loop loopNewGrantA; |
if i/=WbMasterType'left then |
loopNewGrantB: for j in WbMasterType'left to WbMasterType'pred(i) loop |
if WbMasterIn(j).Cyc='1' then |
vGrant := (Others=>'0'); |
vGrant(j) := '1'; |
end if; |
end loop loopNewGrantB; --grant only moves after new requester |
end if; |
end if; |
end loop loopGrant; |
end if; --Clk |
grant <= vGrant; |
end process procArb; |
--============================================================================= |
------------------------------------------------------------------------------- |
-- Master Multiplexers |
------------------------------------------------------------------------------- |
procWbMasterIn: process(grant,WbMasterIn) is |
variable vSlaveOut : WbMasterOutType; |
begin |
loopGrantInMux: for i in WbMasterType loop |
vSlaveOut := WbMasterIn(i); |
exit when grant(i)='1'; |
end loop loopGrantInMux; |
wbStrobe <= vSlaveOut.Strobe; |
wbWrEn <= vSlaveOut.WrEn; |
wbAddr <= vSlaveOut.Addr; |
wbMData <= vSlaveOut.Data; |
--wbMDataTag <= vSlaveOut.DataTag; |
wbCyc <= vSlaveOut.Cyc; |
--wbCycType <= vSlaveOut.CycType; |
end process procWbMasterIn; |
procWbMasterOut: process(grant,wbSData,wbAck,wbErr,wbRty) is |
begin |
loopGrantOutMux: for i in grant'range loop |
WbMasterOut(i).Ack <= grant(i) and wbAck; |
WbMasterOut(i).Err <= grant(i) and wbErr; |
WbMasterOut(i).Rty <= grant(i) and wbRty; |
WbMasterOut(i).Data <= wbSData; --Data out can always be active. |
end loop loopGrantOutMux; |
end process procWbMasterOut; |
|
wbAck <= wbStrobe and validAddress; |
wbErr <= wbStrobe and not(validAddress); |
wbRty <= '0'; |
WbRst <= '0'; |
--============================================================================= |
------------------------------------------------------------------------------- |
-- Address Decode, Asynchronous |
------------------------------------------------------------------------------- |
procAddrDecode: process(wbAddr) is |
variable vValidAddress : std_logic; |
begin |
vValidAddress := '0'; |
loopStatusEn: for f in StatusFieldType loop |
if StatusParams(f).Address=wbAddr then |
statusEnable(f) <= '1'; |
vValidAddress := '1'; |
else |
statusEnable(f) <= '0'; |
end if; |
end loop loopStatusEn; |
loopSettingEn: for f in SettingFieldType loop |
if SettingParams(f).Address=wbAddr then |
settingEnable(f) <= '1'; |
vValidAddress := '1'; |
else |
settingEnable(f) <= '0'; |
end if; |
end loop loopSettingEn; |
loopTriggerEn: for f in TriggerFieldType loop |
if TriggerParams(f).Address=wbAddr then |
triggerEnable(f) <= '1'; |
vValidAddress := '1'; |
else |
triggerEnable(f) <= '0'; |
end if; |
end loop loopTriggerEn; |
validAddress <= vValidAddress; |
end process procAddrDecode; |
--============================================================================= |
------------------------------------------------------------------------------- |
-- Read |
------------------------------------------------------------------------------- |
procRegRead: process(StatusRegs,iSettingRegs,iTriggers,statusEnable,settingEnable,triggerEnable) is |
variable vWbSData : WbDataType; |
begin |
vWbSData := (Others=>'0'); |
loopStatusRegs : for f in StatusFieldType loop |
if statusEnable(f)='1' then |
vWbSData(StatusParams(f).MSBLoc to (StatusParams(f).MSBLoc + StatusParams(f).BitWidth - 1)) := StatusRegs(f)((WbDataBits-StatusParams(f).BitWidth) to WbDataBits-1); |
end if; --Address |
end loop loopStatusRegs; |
loopSettingRegs : for f in SettingFieldType loop |
if settingEnable(f)='1' then |
vWbSData(SettingParams(f).MSBLoc to (SettingParams(f).MSBLoc + SettingParams(f).BitWidth - 1)) := iSettingRegs(f)((WbDataBits-SettingParams(f).BitWidth) to WbDataBits-1); |
end if; --Address |
end loop loopSettingRegs; |
loopTriggerRegs : for f in TriggerFieldType loop |
if triggerEnable(f)='1' then |
vWbSData(TriggerParams(f).BitLoc) := iTriggers(f); |
end if; --Address |
end loop loopTriggerRegs; |
wbSData <= vWbSData; |
end process procRegRead; |
--============================================================================= |
------------------------------------------------------------------------------- |
-- Write, Reset, Clear |
------------------------------------------------------------------------------- |
procRegWrite: process(WbClk,rstZ) is |
begin |
if (rstZ='0') then |
loopSettingRegDefault : for f in SettingFieldType loop |
iSettingRegs(f) <= SettingParams(f).Default; |
end loop loopSettingRegDefault; |
loopTriggerRegDefault : for f in TriggerFieldType loop |
iTriggers(f) <= '0'; |
end loop loopTriggerRegDefault; |
elsif rising_edge(WbClk) then |
loopSettingRegWr : for f in SettingFieldType loop |
if settingEnable(f)='1' and wbStrobe='1' and wbWrEn='1' then |
iSettingRegs(f)((WbDataBits-SettingParams(f).BitWidth) to WbDataBits-1) <= wbMData(SettingParams(f).MSBLoc to (SettingParams(f).MSBLoc + SettingParams(f).BitWidth-1)); |
end if; |
end loop loopSettingRegWr; |
loopSettingRegRst : for f in SettingFieldType loop |
if SettingRsts(f)='1' then |
iSettingRegs(f) <= SettingParams(f).Default; |
end if; |
end loop loopSettingRegRst; |
loopTriggerRegWr : for f in TriggerFieldType loop |
if triggerEnable(f)='1' and wbStrobe='1' and wbWrEn='1' then |
iTriggers(f) <= wbMData(TriggerParams(f).BitLoc); |
elsif TriggerClr(f)='1' then |
iTriggers(f) <= '0'; |
end if; --Address or clear |
end loop loopTriggerRegWr; |
end if; --Clk |
end process procRegWrite; |
|
--WbSlaveOut : in WbSlaveOutArray; |
|
StatusRegs : in StatusArrayType; |
|
SettingRegs : out SettingArrayType; |
SettingRsts : in SettingArrayBitType; |
|
Triggers : out TriggerArrayType; |
TriggerClr : in TriggerArrayType; |
|
rstZ : in std_logic); --Asynchronous reset |
end entity Wrimm; |
|
architecture behavior of Wrimm is |
signal wbStrobe : std_logic; --Internal Wishbone signals |
signal validAddress : std_logic; |
signal wbAddr : WbAddrType; |
signal wbSData,wbMData : WbDataType; |
signal wbWrEn,wbCyc : std_logic; |
signal wbAck,wbRty,wbErr : std_logic; |
--signal wbMDataTag : std_logic_vector(0 to 1); |
--signal wbCycType : std_logic_vector(0 to 2); |
|
signal iSettingRegs : SettingArrayType; |
signal iTriggers : TriggerArrayType; |
signal statusEnable : StatusArrayBitType; |
signal settingEnable : SettingArrayBitType; |
signal triggerEnable : TriggerArrayType; |
signal grant : WbMasterGrantType; |
|
begin |
SettingRegs <= iSettingRegs; |
Triggers <= iTriggers; |
|
--============================================================================= |
------------------------------------------------------------------------------- |
-- Master Round Robin Arbitration |
------------------------------------------------------------------------------- |
procArb: process(WbClk,rstZ) is --Round robin arbitration (descending) |
variable vGrant : WbMasterGrantType; |
begin |
if (rstZ='0') then |
vGrant := (Others=>'0'); |
vGrant(vGrant'left) := '1'; |
elsif rising_edge(WbClk) then |
loopGrant: for i in WbMasterType loop |
if vGrant(i)='1' and WbMasterIn(i).Cyc='0' then --else maintain grant |
loopNewGrantA: for j in i to WbMasterType'right loop --last master with cyc=1 will be selected |
if WbMasterIn(j).Cyc='1' then |
vGrant := (Others=>'0'); |
vGrant(j) := '1'; |
end if; |
end loop loopNewGrantA; |
if i/=WbMasterType'left then |
loopNewGrantB: for j in WbMasterType'left to WbMasterType'pred(i) loop |
if WbMasterIn(j).Cyc='1' then |
vGrant := (Others=>'0'); |
vGrant(j) := '1'; |
end if; |
end loop loopNewGrantB; --grant only moves after new requester |
end if; |
end if; |
end loop loopGrant; |
end if; --Clk |
grant <= vGrant; |
end process procArb; |
--============================================================================= |
------------------------------------------------------------------------------- |
-- Master Multiplexers |
------------------------------------------------------------------------------- |
procWbMasterIn: process(grant,WbMasterIn) is |
variable vSlaveOut : WbMasterOutType; |
begin |
loopGrantInMux: for i in WbMasterType loop |
vSlaveOut := WbMasterIn(i); |
exit when grant(i)='1'; |
end loop loopGrantInMux; |
wbStrobe <= vSlaveOut.Strobe; |
wbWrEn <= vSlaveOut.WrEn; |
wbAddr <= vSlaveOut.Addr; |
wbMData <= vSlaveOut.Data; |
--wbMDataTag <= vSlaveOut.DataTag; |
wbCyc <= vSlaveOut.Cyc; |
--wbCycType <= vSlaveOut.CycType; |
end process procWbMasterIn; |
procWbMasterOut: process(grant,wbSData,wbAck,wbErr,wbRty) is |
begin |
loopGrantOutMux: for i in grant'range loop |
WbMasterOut(i).Ack <= grant(i) and wbAck; |
WbMasterOut(i).Err <= grant(i) and wbErr; |
WbMasterOut(i).Rty <= grant(i) and wbRty; |
WbMasterOut(i).Data <= wbSData; --Data out can always be active. |
end loop loopGrantOutMux; |
end process procWbMasterOut; |
|
wbAck <= wbStrobe and validAddress; |
wbErr <= wbStrobe and not(validAddress); |
wbRty <= '0'; |
WbRst <= '0'; |
--============================================================================= |
------------------------------------------------------------------------------- |
-- Address Decode, Asynchronous |
------------------------------------------------------------------------------- |
procAddrDecode: process(wbAddr) is |
variable vValidAddress : std_logic; |
begin |
vValidAddress := '0'; |
loopStatusEn: for f in StatusFieldType loop |
if StatusParams(f).Address=wbAddr then |
statusEnable(f) <= '1'; |
vValidAddress := '1'; |
else |
statusEnable(f) <= '0'; |
end if; |
end loop loopStatusEn; |
loopSettingEn: for f in SettingFieldType loop |
if SettingParams(f).Address=wbAddr then |
settingEnable(f) <= '1'; |
vValidAddress := '1'; |
else |
settingEnable(f) <= '0'; |
end if; |
end loop loopSettingEn; |
loopTriggerEn: for f in TriggerFieldType loop |
if TriggerParams(f).Address=wbAddr then |
triggerEnable(f) <= '1'; |
vValidAddress := '1'; |
else |
triggerEnable(f) <= '0'; |
end if; |
end loop loopTriggerEn; |
validAddress <= vValidAddress; |
end process procAddrDecode; |
--============================================================================= |
------------------------------------------------------------------------------- |
-- Read |
------------------------------------------------------------------------------- |
procRegRead: process(StatusRegs,iSettingRegs,iTriggers,statusEnable,settingEnable,triggerEnable) is |
variable vWbSData : WbDataType; |
begin |
vWbSData := (Others=>'0'); |
loopStatusRegs : for f in StatusFieldType loop |
if statusEnable(f)='1' then |
vWbSData(StatusParams(f).MSBLoc to (StatusParams(f).MSBLoc + StatusParams(f).BitWidth - 1)) := StatusRegs(f)((WbDataBits-StatusParams(f).BitWidth) to WbDataBits-1); |
end if; --Address |
end loop loopStatusRegs; |
loopSettingRegs : for f in SettingFieldType loop |
if settingEnable(f)='1' then |
vWbSData(SettingParams(f).MSBLoc to (SettingParams(f).MSBLoc + SettingParams(f).BitWidth - 1)) := iSettingRegs(f)((WbDataBits-SettingParams(f).BitWidth) to WbDataBits-1); |
end if; --Address |
end loop loopSettingRegs; |
loopTriggerRegs : for f in TriggerFieldType loop |
if triggerEnable(f)='1' then |
vWbSData(TriggerParams(f).BitLoc) := iTriggers(f); |
end if; --Address |
end loop loopTriggerRegs; |
wbSData <= vWbSData; |
end process procRegRead; |
--============================================================================= |
------------------------------------------------------------------------------- |
-- Write, Reset, Clear |
------------------------------------------------------------------------------- |
procRegWrite: process(WbClk,rstZ) is |
begin |
if (rstZ='0') then |
loopSettingRegDefault : for f in SettingFieldType loop |
iSettingRegs(f) <= SettingParams(f).Default; |
end loop loopSettingRegDefault; |
loopTriggerRegDefault : for f in TriggerFieldType loop |
iTriggers(f) <= '0'; |
end loop loopTriggerRegDefault; |
elsif rising_edge(WbClk) then |
loopSettingRegWr : for f in SettingFieldType loop |
if settingEnable(f)='1' and wbStrobe='1' and wbWrEn='1' then |
iSettingRegs(f)((WbDataBits-SettingParams(f).BitWidth) to WbDataBits-1) <= wbMData(SettingParams(f).MSBLoc to (SettingParams(f).MSBLoc + SettingParams(f).BitWidth-1)); |
end if; |
end loop loopSettingRegWr; |
loopSettingRegRst : for f in SettingFieldType loop |
if SettingRsts(f)='1' then |
iSettingRegs(f) <= SettingParams(f).Default; |
end if; |
end loop loopSettingRegRst; |
loopTriggerRegWr : for f in TriggerFieldType loop |
if triggerEnable(f)='1' and wbStrobe='1' and wbWrEn='1' then |
iTriggers(f) <= wbMData(TriggerParams(f).BitLoc); |
elsif TriggerClr(f)='1' then |
iTriggers(f) <= '0'; |
end if; --Address or clear |
end loop loopTriggerRegWr; |
end if; --Clk |
end process procRegWrite; |
|
end architecture behavior; |