OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /xulalx25soc/trunk/rtl
    from Rev 45 to Rev 46
    ↔ Reverse comparison
  •

Rev 45 → Rev 46

/cpu/cpudefs.v
1,3 → 1,4
`define XULA25
///////////////////////////////////////////////////////////////////////////////
//
// Filename: cpudefs.v
/cpu/cpuops.v
96,6 → 96,7
// the Xilinx multiplexer fabric that follows.
// Given that we wish to apply this multiplexer approach to 33-bits,
// this will cost a minimum of 132 6-LUTs.
wire w_illegal;
generate
if (IMPLEMENT_MPY == 0)
begin
126,9 → 127,10
 
assign o_busy = 1'b0;
 
assign w_illegal = (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4));
reg r_illegal;
always @(posedge i_clk)
r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4));
r_illegal <= w_illegal;
assign o_illegal = r_illegal;
end else begin
//
181,6 → 183,7
 
assign o_busy = r_busy;
 
assign w_illegal = 1'b0;
assign o_illegal = 1'b0;
end endgenerate
 
195,6 → 198,6
if (i_rst)
o_valid <= 1'b0;
else
o_valid <= (i_ce)&&(i_valid)&&(i_op[3:1] != 3'h5)
o_valid <= (i_ce)&&(i_valid)&&(i_op[3:1] != 3'h5)&&(~w_illegal)
||(o_busy);
endmodule
/cpu/zipcpu.v
1045,8 → 1045,20
alu_wr <= 1'b0;
alF_wr <= 1'b0;
end else if (alu_ce)
`ifdef OPT_ILLEGAL_INSTRUCTION
begin
// alu_reg <= opR;
alu_wr <= (opR_wr)&&(set_cond)&&(~op_illegal);
alF_wr <= (opF_wr)&&(set_cond);
end else if (~alu_busy) begin
// These are strobe signals, so clear them if not
// set for any particular clock
alu_wr <= (i_halt)&&(i_dbg_we);
alF_wr <= 1'b0;
end
`else
begin
// alu_reg <= opR;
alu_wr <= (opR_wr)&&(set_cond);
alF_wr <= (opF_wr)&&(set_cond);
end else if (~alu_busy) begin
1055,6 → 1067,7
alu_wr <= (i_halt)&&(i_dbg_we);
alF_wr <= 1'b0;
end
`endif
 
`ifdef OPT_VLIW
reg r_alu_phase;
1091,6 → 1104,7
alu_pc <= op_pc;
 
`ifdef OPT_ILLEGAL_INSTRUCTION
/*
reg r_alu_illegal;
initial r_alu_illegal = 0;
always @(posedge i_clk)
1098,7 → 1112,9
r_alu_illegal <= 1'b0;
else if ((alu_ce)||(mem_ce))
r_alu_illegal <= op_illegal;
assign alu_illegal = (alu_illegal_op)||(r_alu_illegal);
||(r_alu_illegal);
*/
assign alu_illegal = (alu_illegal_op);
`endif
 
// This _almost_ is equal to (alu_ce)||(mem_ce). The only
1187,8 → 1203,7
// Further, alu_wr includes (set_cond), so we don't need to
// check for that here either.
`ifdef OPT_ILLEGAL_INSTRUCTION
assign wr_reg_ce = (~alu_illegal)&&
(((alu_wr)&&(~clear_pipeline)
assign wr_reg_ce = (((alu_wr)&&(~clear_pipeline)
&&((alu_valid)||(div_valid)||(fpu_valid)))
||(mem_valid));
`else
/wbubus.v
40,9 → 40,7
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
i_interrupt,
o_tx_stb, o_tx_data, i_tx_busy,
// o_dbg
);
o_tx_stb, o_tx_data, i_tx_busy);
parameter LGWATCHDOG=19;
input i_clk;
input i_rx_stb;
/wbpwmaudio.v
116,6 → 116,7
 
reg [31:0] reload_value, timer;
initial reload_value = DEFAULT_RELOAD;
initial timer = DEFAULT_RELOAD;
always @(posedge i_clk)
if (timer == 0)
timer <= reload_value;
/wbsdram.v
99,6 → 99,12
// 84 MHz 656
// 80 MHz 625
//
// However, since we do two refresh cycles everytime we need a refresh,
// this standard is close to overkill--but we'll use it anyway. At
// some later time we should address this, once we are entirely
// convinced that the memory is otherwise working without failure. Of
// course, at that time, it may no longer be a priority ...
//
reg need_refresh;
reg [9:0] refresh_clk;
wire refresh_cmd;
142,7 → 148,20
//
// Keep in mind, the number of clocks to wait has to be reduced by
// the amount of time it may take us to go into a precharge state.
// You may also notice that the precharge requirement is tighter
// than this one, so ... perhaps this isn't as required?
//
`ifdef PRECHARGE_COUNTERS
/*
*
* I'm commenting this out. As long as we are doing one refresh
* cycle every 625 (or even 1250) clocks, and as long as that refresh
* cycle requires that all banks be precharged, then we will never run
* out of the maximum active to precharge command period.
*
* If the logic isn't needed, then, let's get rid of it.
*
*/
reg [3:0] need_precharge;
genvar k;
generate
159,6 → 178,9
always @(posedge i_clk)
begin
if ((precharge_cmd)||(bank_active[k] == 0))
// This needs to be 100_000 ns, or 10_000
// clocks. A value of 1000 is *highly*
// conservative.
precharge_clk <= 10'd1000;
else if (|precharge_clk)
precharge_clk <= precharge_clk - 10'h1;
168,6 → 190,10
need_precharge[k] <= ~(|precharge_clk);
end // precharge_genvar_loop
endgenerate
`else
wire [3:0] need_precharge;
assign need_precharge = 4'h0;
`endif
 
 
 
244,6 → 270,12
o_ram_dmod <= nxt_dmod;
 
//
// We assume that, whatever state the bank is in, that it
// continues in that state and set up a series of shift
// registers to contain that information. If it will not
// continue in that state, all that therefore needs to be
// done is to set bank_active[?][2] below.
//
bank_active[0] <= { bank_active[0][2], bank_active[0][2:1] };
bank_active[1] <= { bank_active[1][2], bank_active[1][2:1] };
bank_active[2] <= { bank_active[2][2], bank_active[2][2:1] };
263,10 → 295,11
o_ram_cas_n <= 1'b1;
o_ram_we_n <= 1'b1;
 
// Don't drive the bus normally, let it float unless we wish
// to give it a command
o_ram_data <= r_data[15:0];
// o_ram_data <= r_data[15:0];
 
if (nxt_dmod)
;
else
if ((~i_wb_cyc)||(|need_precharge)||(need_refresh))
begin // Issue a precharge all command (if any banks are open),
// otherwise an autorefresh command
273,7 → 306,8
if ((bank_active[0][2:1]==2'b10)
||(bank_active[1][2:1]==2'b10)
||(bank_active[2][2:1]==2'b10)
||(bank_active[3][2:1]==2'b10))
||(bank_active[3][2:1]==2'b10)
||(|clocks_til_idle[2:0]))
begin
// Do nothing this clock
// Can't precharge a bank immediately after
304,10 → 338,21
o_ram_cas_n <= 1'b0;
o_ram_we_n <= 1'b1;
end // Else just send NOOP's, the default command
end else if (nxt_dmod)
begin
// end else if (nxt_dmod)
// begin
// Last half of a two cycle write
o_ram_data <= r_data[15:0];
// o_ram_data <= r_data[15:0];
//
// While this does need to take precedence over all
// other commands, it doesn't need to take precedence
// over the the deactivate/precharge commands from
// above.
//
// We could probably even speed ourselves up a touch
// by moving this condition down below activating
// and closing active banks. ... only problem is when I
// last tried that I broke everything so ... that's not
// my problem.
end else if (in_refresh)
begin
// NOOPS only here, until we are out of refresh
366,7 → 411,7
 
o_wb_stall <= 1'b0;
r_barrell_ack[1] <= 1'b1;
o_ram_data <= r_data[31:16];
// o_ram_data <= r_data[31:16];
//
o_ram_dmod <= `DMOD_PUTOUTPUT;
nxt_dmod <= `DMOD_PUTOUTPUT;
458,6 → 503,12
r_barrell_ack[(RDLY-1):0] <= 0;
end
 
always @(posedge i_clk)
if (nxt_dmod)
o_ram_data <= r_data[15:0];
else
o_ram_data <= r_data[31:16];
 
`ifdef VERILATOR
// While I hate to build something that works one way under Verilator
// and another way in practice, this really isn't that. The problem
491,12 → 542,18
// The first value "written" to the device can be caught in the next
// interaction after that.
//
assign o_debug = { i_wb_cyc, i_wb_stb, i_wb_we, o_wb_ack, o_wb_stall,
o_ram_cs_n, o_ram_ras_n, o_ram_cas_n, o_ram_we_n, o_ram_bs,
o_ram_dmod, r_pending,
// 13 of 32
o_ram_addr[10:0], // 11 more
(r_we) ? { i_wb_data[23:20], i_wb_data[3:0] }
reg trigger;
always @(posedge i_clk)
trigger <= ((o_wb_data[15:0]==o_wb_data[31:16])
&&(o_wb_ack)&&(~i_wb_we));
 
 
assign o_debug = { i_wb_cyc, i_wb_stb, i_wb_we, o_wb_ack, o_wb_stall, // 5
o_ram_cs_n, o_ram_ras_n, o_ram_cas_n, o_ram_we_n, o_ram_bs,//6
o_ram_dmod, r_pending, // 2
trigger, // 1
o_ram_addr[9:0], // 10 more
(r_we) ? { o_ram_data[7:0] } // 8 values
: { o_wb_data[23:20], o_wb_data[3:0] }
// i_ram_data[7:0]
};
/busmaster.v
1,3 → 1,4
`define XULA25
///////////////////////////////////////////////////////////////////////////
//
// Filename: busmaster.v
39,8 → 40,12
//
///////////////////////////////////////////////////////////////////////////
//
// `define XULA25
 
//
// Configuration question #1
//
// What innate capabilities are built into the board?
//
`define INCLUDE_ZIPCPU
// `define NO_ZIP_WBU_DELAY
`define IMPLEMENT_ONCHIP_RAM
52,14 → 57,36
`define FLASH_ACCESS
// `define SDCARD_ACCESS // Not built yet ...
//
 
 
//
// Configuration question #2
//
// Are any scopes built in to the board?
//
 
//
// Position #1: The flash scope, or perhaps the wishbone bus/uart/jtag scope
//
// `define FLASH_SCOPE
`ifndef FLASH_SCOPE
// `define WBUS_SCOPE // Occupies the FLASH_SCOPE location, so both cannot be active
`endif
//
// Position #2: The ICAP configuration scope
//
`ifdef FANCY_ICAP_ACCESS
`define CFG_SCOPE
`define CFG_SCOPE // Only defined if we have the access ...
`endif
// `define SDRAM_SCOPE
//
// Position #3: The SDRAM scope
//
`define SDRAM_SCOPE
//
// Position #4: The Zip CPU scope
//
`ifdef XULA25
`define ZIP_SCOPE
// `define ZIP_SCOPE
`endif
 
module busmaster(i_clk, i_rst,
328,8 → 355,6
// 1xxx xxxx Up-sampler taps
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
 
`ifndef SPEEDY_IO
 
wire pre_io, pre_pwm, pre_uart, pre_flctl, pre_scop;
assign io_bank = (wb_cyc)&&(wb_addr[31:5] == 27'h8);
assign pre_io = (~pre_flctl)&&(~pre_pwm)&&(~pre_uart)&&(~pre_scop);
348,25 → 373,7
assign flash_sel=((wb_cyc)&&(wb_addr[31:18]== 14'h01));
assign sdcard_sel=1'b0;
assign sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
`else
assign iovec = { wb_addr[23],wb_addr[18],wb_addr[15:13] }
 
assign sdram_sel =((wb_cyc)&&(io_vec[4]));
assign flash_sel =((wb_cyc)&&(io_vec[4:3]==2'b01));
assign mem_sel =((wb_cyc)&&(io_vec[4:0]==5'h07));
assign cfg_sel =((wb_cyc)&&(io_vec[4:0]==5'h06));
assign sdcard_sel=((wb_cyc)&&(io_vec[4:0]==5'h05));
assign scop_sel =((wb_cyc)&&(io_vec[4:0]==5'h04));
assign rtc_sel =((wb_cyc)&&(io_vec[4:0]==5'h03));
assign rtc_sel =((wb_cyc)&&(io_vec[4:0]==5'h03));
assign puf_sel =((wb_cyc)&&(io_vec[4:0]==5'h02));
assign io_sel =((wb_cyc)&&(io_vec[4:0]==5'h01));
assign wb_err =((wb_cyc)&&(io_vec[4:0]==5'h00));
assign flctl_sel = (puf_sel)&&(wb_addr[2]);
assign pwm_sel = (puf_sel)&&(wb_addr[2:1]==2'b01);
assign sdcard_sel=1'b0;//((wb_cyc)&&({wb_addr[23],wb_addr[18]}==2'b01));
`endif
 
assign none_sel =((wb_cyc)&&(wb_stb)&&(~
(io_sel
||uart_sel
442,9 → 449,21
//
// PWM (audio) device
//
wbpwmaudio pwmdev(i_clk,
// The audio rate is given by the number of clock ticks between
// samples. If we are running at 80 MHz, then divide that by the
// sample rate to get the first parameter for the PWM device. The
// second parameter is zero or one, indicating whether or not the
// audio rate can be adjusted (1), or whether it is fixed within the
// build (0).
`ifdef XULA25
wbpwmaudio #(32'd1814,1) // 44.1 kHz, user adjustable
`else
wbpwmaudio #(32'h10000,0) // 8 kHz, fixed audio rate
`endif
pwmdev(i_clk,
wb_cyc, (wb_stb)&&(pwm_sel), wb_we, wb_addr[0],
wb_data, pwm_ack, pwm_stall, pwm_data, o_pwm, pwm_int);
 
 
//
581,10 → 600,17
//
//
//
wire [31:0] scop_flash_data;
wire scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
 
`ifndef FLASH_ACCESS
`ifdef FLASH_SCOPE
`undef FLASH_SCOPE // FLASH_SCOPE only makes sense if you have flash access
`endif
`endif
 
`ifdef FLASH_SCOPE
reg [31:0] r_flash_debug, last_flash_debug;
wire [31:0] scop_flash_data;
wire scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
always @(posedge i_clk)
r_flash_debug <= flash_debug;
always @(posedge i_clk)
596,13 → 622,20
scop_flash_ack, scop_flash_stall, scop_flash_data,
scop_flash_interrupt);
`else
wire [31:0] scop_flash_data;
wire scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
`ifdef WBUS_SCOPE
wbscopc #(5'ha) wbuscope(i_clk, 1'b1, wbus_debug[31], wbus_debug[30:0],
// Wishbone interface
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
wb_data,
scop_flash_ack, scop_flash_stall, scop_flash_data,
scop_flash_interrupt);
`else
assign scop_flash_data = 32'h00;
assign scop_flash_ack = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00);
assign scop_flash_stall = 1'b0;
assign scop_flash_interrupt = 1'b0;
`endif
`endif
 
 
wire [31:0] scop_cfg_data;
627,27 → 660,11
wire scop_ram_ack, scop_ram_stall, scop_ram_interrupt;
`ifdef SDRAM_SCOPE
wire sdram_trigger;
assign sdram_trigger = sdram_sel;
// assign sdram_trigger = ((wbu_cyc)&&(wbu_zip_sel)&&(wbu_stb)&&(~wbu_addr[0])),
wire sdram_write;
assign sdram_write = ((wb_cyc)&&(sdram_sel)&&(wb_stb)&&(wb_we)&&(~sdram_stall));
/*
reg r_trigger;
reg [31:0] last_data;
always @(posedge i_clk)
if (sdram_write)
last_data <= wb_data;
initial r_trigger = 1'b0;
always @(posedge i_clk)
if ((sdram_write)&&(last_data == wb_data))
r_trigger <= 1'b1;
else
r_trigger <= 1'b0;
*/
assign sdram_trigger = sdram_debug[18]; // sdram_sel;
wbscope #(5'ha) sdramscope(i_clk, 1'b1, sdram_trigger,
wbscope #(5'hb) sdramscope(i_clk, 1'b1, sdram_trigger,
sdram_debug,
// zip_debug,
//{ sdram_trigger, wb_data[30:0] },
// Wishbone interface
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
wb_data,

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.